msim_setup.tcl 11 KB

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  1. # (C) 2001-2023 Altera Corporation. All rights reserved.
  2. # Your use of Altera Corporation's design tools, logic functions and
  3. # other software and tools, and its AMPP partner logic functions, and
  4. # any output files any of the foregoing (including device programming
  5. # or simulation files), and any associated documentation or information
  6. # are expressly subject to the terms and conditions of the Altera
  7. # Program License Subscription Agreement, Altera MegaCore Function
  8. # License Agreement, or other applicable license agreement, including,
  9. # without limitation, that your use is for the sole purpose of
  10. # programming logic devices manufactured by Altera and sold by Altera
  11. # or its authorized distributors. Please refer to the applicable
  12. # agreement for further details.
  13. # ----------------------------------------
  14. # Auto-generated simulation script msim_setup.tcl
  15. # ----------------------------------------
  16. # This script provides commands to simulate the following IP detected in
  17. # your Quartus project:
  18. # int_osc
  19. #
  20. # Altera recommends that you source this Quartus-generated IP simulation
  21. # script from your own customized top-level script, and avoid editing this
  22. # generated script.
  23. #
  24. # To write a top-level script that compiles Altera simulation libraries and
  25. # the Quartus-generated IP in your project, along with your design and
  26. # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
  27. # into a new file, e.g. named "mentor.do", and modify the text as directed.
  28. #
  29. # ----------------------------------------
  30. # # TOP-LEVEL TEMPLATE - BEGIN
  31. # #
  32. # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
  33. # # construct paths to the files required to simulate the IP in your Quartus
  34. # # project. By default, the IP script assumes that you are launching the
  35. # # simulator from the IP script location. If launching from another
  36. # # location, set QSYS_SIMDIR to the output directory you specified when you
  37. # # generated the IP script, relative to the directory from which you launch
  38. # # the simulator.
  39. # #
  40. # set QSYS_SIMDIR <script generation output directory>
  41. # #
  42. # # Source the generated IP simulation script.
  43. # source $QSYS_SIMDIR/mentor/msim_setup.tcl
  44. # #
  45. # # Set any compilation options you require (this is unusual).
  46. # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
  47. # set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
  48. # set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
  49. # #
  50. # # Call command to compile the Quartus EDA simulation library.
  51. # dev_com
  52. # #
  53. # # Call command to compile the Quartus-generated IP simulation files.
  54. # com
  55. # #
  56. # # Add commands to compile all design files and testbench files, including
  57. # # the top level. (These are all the files required for simulation other
  58. # # than the files compiled by the Quartus-generated IP simulation script)
  59. # #
  60. # vlog <compilation options> <design and testbench files>
  61. # #
  62. # # Set the top-level simulation or testbench module/entity name, which is
  63. # # used by the elab command to elaborate the top level.
  64. # #
  65. # set TOP_LEVEL_NAME <simulation top>
  66. # #
  67. # # Set any elaboration options you require.
  68. # set USER_DEFINED_ELAB_OPTIONS <elaboration options>
  69. # #
  70. # # Call command to elaborate your design and testbench.
  71. # elab
  72. # #
  73. # # Run the simulation.
  74. # run -a
  75. # #
  76. # # Report success to the shell.
  77. # exit -code 0
  78. # #
  79. # # TOP-LEVEL TEMPLATE - END
  80. # ----------------------------------------
  81. #
  82. # IP SIMULATION SCRIPT
  83. # ----------------------------------------
  84. # If int_osc is one of several IP cores in your
  85. # Quartus project, you can generate a simulation script
  86. # suitable for inclusion in your top-level simulation
  87. # script by running the following command line:
  88. #
  89. # ip-setup-simulation --quartus-project=<quartus project>
  90. #
  91. # ip-setup-simulation will discover the Altera IP
  92. # within the Quartus project, and generate a unified
  93. # script which supports all the Altera IP within the design.
  94. # ----------------------------------------
  95. # ACDS 22.1 915 linux 2023.01.23.17:46:00
  96. # ----------------------------------------
  97. # Initialize variables
  98. if ![info exists SYSTEM_INSTANCE_NAME] {
  99. set SYSTEM_INSTANCE_NAME ""
  100. } elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
  101. set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
  102. }
  103. if ![info exists TOP_LEVEL_NAME] {
  104. set TOP_LEVEL_NAME "int_osc"
  105. }
  106. if ![info exists QSYS_SIMDIR] {
  107. set QSYS_SIMDIR "./../"
  108. }
  109. if ![info exists QUARTUS_INSTALL_DIR] {
  110. set QUARTUS_INSTALL_DIR "/opt/altera/22.1/quartus/"
  111. }
  112. if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
  113. set USER_DEFINED_COMPILE_OPTIONS ""
  114. }
  115. if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
  116. set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
  117. }
  118. if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
  119. set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
  120. }
  121. if ![info exists USER_DEFINED_ELAB_OPTIONS] {
  122. set USER_DEFINED_ELAB_OPTIONS ""
  123. }
  124. # ----------------------------------------
  125. # Initialize simulation properties - DO NOT MODIFY!
  126. set ELAB_OPTIONS ""
  127. set SIM_OPTIONS ""
  128. if ![ string match "*-64 vsim*" [ vsim -version ] ] {
  129. } else {
  130. }
  131. # ----------------------------------------
  132. # Copy ROM/RAM files to simulation directory
  133. alias file_copy {
  134. echo "\[exec\] file_copy"
  135. }
  136. # ----------------------------------------
  137. # Create compilation libraries
  138. proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
  139. ensure_lib ./libraries/
  140. ensure_lib ./libraries/work/
  141. vmap work ./libraries/work/
  142. vmap work_lib ./libraries/work/
  143. if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
  144. ensure_lib ./libraries/altera_ver/
  145. vmap altera_ver ./libraries/altera_ver/
  146. ensure_lib ./libraries/lpm_ver/
  147. vmap lpm_ver ./libraries/lpm_ver/
  148. ensure_lib ./libraries/sgate_ver/
  149. vmap sgate_ver ./libraries/sgate_ver/
  150. ensure_lib ./libraries/altera_mf_ver/
  151. vmap altera_mf_ver ./libraries/altera_mf_ver/
  152. ensure_lib ./libraries/altera_lnsim_ver/
  153. vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
  154. ensure_lib ./libraries/cycloneive_ver/
  155. vmap cycloneive_ver ./libraries/cycloneive_ver/
  156. }
  157. ensure_lib ./libraries/int_osc_0/
  158. vmap int_osc_0 ./libraries/int_osc_0/
  159. # ----------------------------------------
  160. # Compile device library files
  161. alias dev_com {
  162. echo "\[exec\] dev_com"
  163. if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
  164. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
  165. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
  166. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
  167. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
  168. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
  169. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
  170. }
  171. }
  172. # ----------------------------------------
  173. # Compile the design files in correct order
  174. alias com {
  175. echo "\[exec\] com"
  176. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_int_osc.v" -work int_osc_0
  177. eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/int_osc.v"
  178. }
  179. # ----------------------------------------
  180. # Elaborate top level design
  181. alias elab {
  182. echo "\[exec\] elab"
  183. eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
  184. }
  185. # ----------------------------------------
  186. # Elaborate the top level design with -voptargs=+acc option
  187. alias elab_debug {
  188. echo "\[exec\] elab_debug"
  189. eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
  190. }
  191. # ----------------------------------------
  192. # Compile all the design files and elaborate the top level design
  193. alias ld "
  194. dev_com
  195. com
  196. elab
  197. "
  198. # ----------------------------------------
  199. # Compile all the design files and elaborate the top level design with -voptargs=+acc
  200. alias ld_debug "
  201. dev_com
  202. com
  203. elab_debug
  204. "
  205. # ----------------------------------------
  206. # Print out user commmand line aliases
  207. alias h {
  208. echo "List Of Command Line Aliases"
  209. echo
  210. echo "file_copy -- Copy ROM/RAM files to simulation directory"
  211. echo
  212. echo "dev_com -- Compile device library files"
  213. echo
  214. echo "com -- Compile the design files in correct order"
  215. echo
  216. echo "elab -- Elaborate top level design"
  217. echo
  218. echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
  219. echo
  220. echo "ld -- Compile all the design files and elaborate the top level design"
  221. echo
  222. echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
  223. echo
  224. echo
  225. echo
  226. echo "List Of Variables"
  227. echo
  228. echo "TOP_LEVEL_NAME -- Top level module name."
  229. echo " For most designs, this should be overridden"
  230. echo " to enable the elab/elab_debug aliases."
  231. echo
  232. echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
  233. echo
  234. echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
  235. echo
  236. echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
  237. echo
  238. echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
  239. echo
  240. echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
  241. echo
  242. echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
  243. echo
  244. echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
  245. }
  246. file_copy
  247. h