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- module sdram
- #( parameter
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- t_cl = 3,
- t_rcd = 3,
- t_rfc = 10,
- t_rp = 3,
- t_ras = 7,
- t_rc = 10,
- t_rrd = 2,
- t_wr = 2,
- t_mrd = 2,
- t_refi_lg2 = 10,
- t_p_lg2 = 15,
- burst_lg2 = 1
- )
- (
-
- input rst_n,
- input clk,
- input out_clk,
-
- output sr_clk,
- output sr_cke,
- output sr_cs_n,
- output sr_ras_n,
- output sr_cas_n,
- output sr_we_n,
- output [1:0] sr_dqm,
- output [1:0] sr_ba,
- output [12:0] sr_a,
- inout [15:0] sr_dq,
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- input [24:0] a0,
- output reg [7:0] rd0,
- input rrq0,
- output reg rack0,
- output reg rready0,
- input [7:0] wd0,
- input wrq0,
- output reg wack0,
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- input [24:2] a1,
- output reg [31:0] rd1,
- input rrq1,
- output reg rack1,
- output reg rready1,
- input [31:0] wd1,
- input [3:0] wstrb1,
- output reg wack1,
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- input [24:1] a2,
- input [15:0] wd2,
- input [1:0] wrq2,
- output reg wacc2
- );
- `include "functions.sv" // For modelsim
- wire wrq1 = |wstrb1;
-
-
- wire mrd_wburst = 1'b1;
- wire [2:0] mrd_cl = t_cl;
- wire [2:0] mrd_burst = burst_lg2;
- wire mrd_interleave = 1'b0;
- wire [12:0] mrd_val = { 3'b000,
- ~mrd_wburst,
- 2'b00,
- mrd_cl,
- mrd_interleave,
- mrd_burst };
-
-
- localparam t_pre_rd_when = max(t_ras, t_rcd + 1);
-
-
- localparam t_pre_wr_when = max(t_ras, t_rcd + t_wr);
-
- localparam burst_n = 1 << burst_lg2;
-
- localparam cmd_desl = 5'b0_1111;
- localparam cmd_nop = 5'b0_0111;
- localparam cmd_bst = 5'b0_0110;
- localparam cmd_rd = 5'b0_0101;
- localparam cmd_wr = 5'b0_0100;
- localparam cmd_act = 5'b0_0011;
- localparam cmd_pre = 5'b0_0010;
- localparam cmd_ref = 5'b1_0001;
- localparam cmd_mrd = 5'b0_0000;
- reg [4:0] dram_cmd;
- wire is_rfsh = dram_cmd[4];
- assign sr_cs_n = dram_cmd[3];
- assign sr_ras_n = dram_cmd[2];
- assign sr_cas_n = dram_cmd[1];
- assign sr_we_n = dram_cmd[0];
- assign sr_cke = 1'b1;
- `ifdef SD_CLK_USE_DDIO
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- ddio_out sr_clk_out (
- .aclr ( 1'b0 ),
- .datain_h ( 1'b1 ),
- .datain_l ( 1'b0 ),
- .outclock ( out_clk ),
- .dataout ( sr_clk )
- );
- `else // !`ifdef SD_CLK_USE_DDIO
-
- assign sr_clk = out_clk;
- `endif
-
- reg [12:0] dram_a;
- assign sr_a = dram_a;
- reg [1:0] dram_ba;
- assign sr_ba = dram_ba;
- reg [1:0] dram_dqm;
- assign sr_dqm = dram_dqm;
- reg [15:0] dram_d;
- reg dram_d_en;
- assign sr_dq = dram_d_en ? dram_d : 16'hzzzz;
-
- reg [t_refi_lg2-2:0] rfsh_ctr;
- wire rfsh_ctr_msb = rfsh_ctr[t_refi_lg2-2];
- reg rfsh_ctr_last_msb;
- wire rfsh_tick = rfsh_ctr_last_msb & ~rfsh_ctr_msb;
- reg [t_p_lg2:t_refi_lg2-1] init_ctr;
- reg [1:0] rfsh_prio;
-
-
-
-
- typedef enum logic [2:0] {
- st_reset,
- st_init_rfsh,
- st_init_mrd,
- st_idle,
- st_rfsh,
- st_rd_wr,
- st_pre_idle,
- st_wr2
- } state_t;
- state_t state = st_reset;
- reg is_write;
-
- always @(posedge clk or negedge rst_n)
- if (~rst_n)
- begin
- rfsh_ctr <= 1'b0;
- rfsh_prio <= 2'b00;
- init_ctr <= 1'b0;
- end
- else
- begin
- rfsh_ctr <= rfsh_ctr + 1'b1;
- rfsh_ctr_last_msb <= rfsh_ctr_msb;
-
- if (is_rfsh)
- rfsh_prio <= 2'b00;
- else if (rfsh_tick)
- rfsh_prio <= { rfsh_prio[0], 1'b1 };
-
-
-
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- init_ctr <= init_ctr + rfsh_tick;
- end
- reg [5:0] op_ctr;
- wire [3:0] op_cycle = op_ctr[3:0];
- wire [1:0] init_op_ctr = op_ctr[5:4];
- reg op_zero;
-
- reg [31:0] wdata_q;
- reg [ 3:0] be_q;
- reg [ 9:0] col_addr;
- reg wrq2_more;
-
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-
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- always @(posedge clk or negedge rst_n)
- if (~rst_n)
- begin
- dram_cmd <= cmd_desl;
- dram_a <= 13'hxxxx;
- dram_ba <= 2'bxx;
- dram_dqm <= 2'b00;
- dram_d <= 16'hxxxx;
- dram_d_en <= 1'b1;
- op_ctr <= 6'h0;
- op_zero <= 1'b0;
- state <= st_reset;
- is_write <= 1'bx;
- rack0 <= 1'b0;
- rready0 <= 1'b1;
- wack0 <= 1'b0;
- rack1 <= 1'b0;
- rready1 <= 1'b1;
- wack1 <= 1'b0;
- wacc2 <= 1'b0;
- wrq2_more <= 1'bx;
- wdata_q <= 32'hxxxx_xxxx;
- be_q <= 4'bxxxx;
- col_addr <= 10'hxxx;
- end
- else
- begin
-
-
- dram_a <= 13'hxxxx;
- dram_dqm <= 2'b00;
- dram_d <= 16'haaaa;
- dram_cmd <= cmd_nop;
- dram_d_en <= 1'b1;
- if (state != st_rd_wr)
- begin
- rack0 <= 1'b0;
- wack0 <= 1'b0;
- rack1 <= 1'b0;
- wack1 <= 1'b0;
- end
- wacc2 <= 1'b0;
- if (state == st_reset || state == st_idle)
- begin
- op_ctr <= 6'b0;
- op_zero <= 1'b0;
- end
- else
- begin
- op_ctr <= op_ctr + 1'b1;
- op_zero <= &op_cycle;
- end
-
- case (state)
- st_reset:
- begin
- dram_a[10] <= 1'b1;
- dram_cmd <= cmd_nop;
- if (init_ctr[t_p_lg2])
- begin
- dram_cmd <= cmd_pre;
- state <= st_init_rfsh;
- end
- end
- st_init_rfsh:
- begin
- if (op_zero)
- begin
- dram_cmd <= cmd_ref;
- if (init_op_ctr == 2'b11)
- state <= st_init_mrd;
- end
- end
- st_init_mrd:
- begin
- dram_a <= mrd_val;
- dram_ba <= 2'b00;
- if (op_zero)
- if (init_op_ctr[0])
- state <= st_idle;
- else
- dram_cmd <= cmd_mrd;
- end
- st_idle:
- begin
- is_write <= 1'bx;
- be_q <= 4'bxxxx;
- wdata_q <= 32'hxxxx_xxxx;
-
-
-
-
-
-
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- dram_a <= 13'h1bb;
- dram_ba <= 2'bxx;
- dram_d <= 16'hbbbb;
-
- casez ( {rrq0|wrq0, rrq1|wrq1, wrq2[0], rfsh_prio} )
- 5'b1????:
- begin
-
- dram_cmd <= cmd_act;
- dram_a <= a0[24:12];
- dram_ba <= a0[11:10];
- col_addr <= a0[9:0];
- if ( wrq0 )
- begin
- state <= st_rd_wr;
- wack0 <= 1'b1;
- wdata_q <= {16'hxxxx, wd0, wd0};
- be_q <= {2'b00, a0[0], ~a0[0]};
- is_write <= 1'b1;
- end
- else
- begin
- state <= st_rd_wr;
- rack0 <= 1'b1;
- rready0 <= 1'b0;
- is_write <= 1'b0;
- end
- end
- 5'b01?0?:
- begin
-
- dram_cmd <= cmd_act;
- dram_a <= a1[24:12];
- dram_ba <= a1[11:10];
- col_addr <= { a1[9:2], 2'b00 };
- if ( wrq1 )
- begin
- state <= st_rd_wr;
- wack1 <= 1'b1;
- wdata_q <= wd1;
- be_q <= wstrb1;
- is_write <= 1'b1;
- end
- else
- begin
- state <= st_rd_wr;
- rack1 <= 1'b1;
- rready1 <= 1'b0;
- is_write <= 1'b0;
- end
- end
- 5'b0??1?, 5'b00?01:
- begin
-
- dram_cmd <= cmd_ref;
- state <= st_rfsh;
- end
- 5'b00100:
- begin
-
- dram_cmd <= cmd_act;
- dram_a <= a2[24:12];
- dram_ba <= a2[11:10];
- state <= st_wr2;
- end
- default:
- begin
- dram_cmd <= cmd_desl;
- state <= st_idle;
- end
- endcase
- end
- st_rfsh:
- begin
- if (op_cycle == t_rfc-2)
- state <= st_idle;
- end
- st_rd_wr:
- begin
- dram_d_en <= is_write;
- dram_dqm <= {2{is_write}};
- dram_d <= 16'hcccc;
-
-
-
-
-
-
-
-
-
-
-
- case (op_cycle)
- 2: begin
- dram_a[10] <= 1'b0;
- dram_a[8:0] <= col_addr[9:1];
- dram_cmd <= is_write ? cmd_wr : cmd_rd;
- dram_d <= wdata_q[15:0];
- dram_dqm <= {2{is_write}} & ~be_q[1:0];
- wdata_q <= { 16'hdddd, wdata_q[31:16] };
- be_q <= { 2'hxx, be_q[3:2] };
- end
- 3: begin
- dram_d <= wdata_q[15:0];
- dram_dqm <= {2{is_write}} & ~be_q[1:0];
- wdata_q <= { 16'heeee, wdata_q[31:16] };
- be_q <= 4'bxxxx;
- end
- 6: begin
-
-
-
- dram_a[10] <= 1'b1;
- dram_cmd <= cmd_pre;
- end
-
-
- 7: begin
- if (rack0)
- rd0 <= col_addr[0] ? sr_dq[15:8] : sr_dq[7:0];
- rready0 <= rready0 | rack0;
- if (rack1)
- rd1[15:0] <= sr_dq;
- end
- 8: begin
- if (rack1)
- rd1[31:16] <= sr_dq;
- rready1 <= rready1 | rack1;
- state <= st_pre_idle;
- end
- endcase
- end
- st_pre_idle:
- begin
-
-
- dram_d_en <= is_write;
- dram_dqm <= {2{is_write}};
- state <= st_idle;
- end
-
- st_wr2:
- begin
-
- dram_d <= wd2;
- dram_a[10] <= 1'b0;
- dram_a[8:0] <= a2[9:1];
- case (op_cycle)
- 0: begin
- wacc2 <= 1'b1;
- end
- 1: begin
- wacc2 <= 1'b1;
- end
- 2: begin
- dram_cmd <= cmd_wr;
- wacc2 <= 1'b1;
- wrq2_more <= wrq2[1];
- end
- 3: begin
- wacc2 <= 1'b1;
- end
- 4: begin
- dram_cmd <= cmd_wr;
- if (wrq2_more &
- ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&dram_a[8:2])))
- begin
-
- wacc2 <= 1'b1;
- op_ctr[3:0] <= 4'd1;
- end
- end
- 6: begin
- dram_dqm <= 2'b11;
- end
- 7: begin
-
- dram_cmd <= cmd_pre;
- dram_dqm <= 2'b11;
- end
- 8: begin
- dram_dqm <= 2'b11;
- end
- 9: begin
-
- dram_dqm <= 2'b11;
- state <= st_idle;
- end
- endcase
- end
- endcase
- end
- endmodule
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