| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298 | # -------------------------------------------------------------------------- ### Copyright (C) 2019  Intel Corporation. All rights reserved.# Your use of Intel Corporation's design tools, logic functions# and other software and tools, and any partner logic# functions, and any output files from any of the foregoing# (including device programming or simulation files), and any# associated documentation or information are expressly subject# to the terms and conditions of the Intel Program License# Subscription Agreement, the Intel Quartus Prime License Agreement,# the Intel FPGA IP License Agreement, or other applicable license# agreement, including, without limitation, that your use is for# the sole purpose of programming logic devices manufactured by# Intel and sold by Intel or its authorized distributors.  Please# refer to the applicable agreement for further details, at# https://fpgasoftware.intel.com/eula.## -------------------------------------------------------------------------- ### Quartus Prime# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition# Date created = 13:01:33  February 22, 2021## -------------------------------------------------------------------------- ### Notes:## 1) The default values for assignments are stored in the file:#		max80_assignment_defaults.qdf#    If this file doesn't exist, see file:#		assignment_defaults.qdf## 2) Altera recommends that you do not modify this file. This#    file is updated automatically by the Quartus Prime software#    and any changes you make may be lost or overwritten.## -------------------------------------------------------------------------- #set_global_assignment -name FAMILY "Cyclone IV E"set_global_assignment -name DEVICE EP4CE15F17C8set_global_assignment -name TOP_LEVEL_ENTITY max80set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:33  FEBRUARY 22, 2021"set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_filesset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85set_global_assignment -name DEVICE_FILTER_PACKAGE EQFPset_global_assignment -name DEVICE_FILTER_PIN_COUNT 144set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"set_global_assignment -name EDA_TIME_SCALE "100 ps" -section_id eda_simulationset_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulationset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timingset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbolset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrityset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scanset_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Topset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Topset_global_assignment -name PARTITION_COLOR 16764057 -section_id Topset_global_assignment -name VCCA_USER_VOLTAGE 2.5Vset_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ONset_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFFset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFFset_global_assignment -name SAFE_STATE_MACHINE OFFset_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ONset_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ONset_global_assignment -name SYNTH_MESSAGE_LEVEL HIGHset_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"set_global_assignment -name WEAK_PULL_UP_RESISTOR ONset_global_assignment -name ENABLE_OCT_DONE OFFset_global_assignment -name ENABLE_CONFIGURATION_PINS OFFset_global_assignment -name ENABLE_BOOT_SEL_PIN OFFset_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0set_global_assignment -name USE_CONFIGURATION_DEVICE ONset_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFFset_global_assignment -name GENERATE_JBC_FILE ONset_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -riseset_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fallset_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -riseset_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fallset_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_48set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_nset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_misoset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_mosiset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_idset_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulationset_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulationset_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulationset_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulationset_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128Aset_global_assignment -name GENERATE_JAM_FILE OFFset_global_assignment -name FORCE_CONFIGURATION_VCCIO ONset_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3Vset_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ONset_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ONset_global_assignment -name PRE_MAPPING_RESYNTHESIS ONset_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ONset_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"set_global_assignment -name SAVE_DISK_SPACE OFFset_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ONset_global_assignment -name SMART_RECOMPILE ONset_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulationset_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testclk -section_id eda_simulationset_global_assignment -name EDA_TEST_BENCH_NAME testclk -section_id eda_simulationset_global_assignment -name EDA_DESIGN_INSTANCE_NAME max80 -section_id testclkset_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testclkset_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclkset_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclkset_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulationset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_dtrset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_rtsset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to tty_txdset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_rxdset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_ctsset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_sclset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_sdaset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c_sclset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c_sdaset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khzset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rtc_int_nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_haset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hbset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hcset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hdset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_heset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hfset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hgset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hhset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to esp_intset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to esp_io0set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[3]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[2]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[0]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_datset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_esp_nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_flash_nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_misoset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_mosiset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[0]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[2]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[4]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[3]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[5]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_clkset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_inp_n[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[13]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[2]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[6]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[0]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdoset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tckset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to abc_xinpstb_nset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdiset_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tmsset_global_assignment -name OCP_HW_EVAL DISABLEset_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ONset_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ONset_global_assignment -name POWER_REPORT_POWER_DISSIPATION ONset_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUMset_global_assignment -name POWER_USE_TA_VALUE 35set_location_assignment PLL_3 -to "pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"set_location_assignment PLL_4 -to "pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"set_location_assignment PLL_2 -to "pll2:pll2|altpll:altpll_component|pll2_altpll:auto_generated|pll1"set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[12]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[11]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[10]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[9]set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[8]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[7]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[6]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[5]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[4]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[3]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[2]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[0]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[0]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[1]set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[2]set_global_assignment -name SYSTEMVERILOG_FILE rng.svset_global_assignment -name VERILOG_FILE ip/int_osc/synthesis/int_osc.vset_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qipset_global_assignment -name VERILOG_FILE ip/int_osc/synthesis/submodules/altera_int_osc.vset_global_assignment -name VERILOG_FILE ip/pll4.vset_global_assignment -name VERILOG_FILE ip/pll3.vset_global_assignment -name VERILOG_FILE ip/pll2.vset_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_device_core.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_desc_rom.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_cdc_top.vset_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.vset_global_assignment -name SYSTEMVERILOG_FILE usb/usb.svset_global_assignment -name VERILOG_FILE ip/statusram.vset_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vhset_global_assignment -name SYSTEMVERILOG_FILE tty.svset_global_assignment -name SYSTEMVERILOG_FILE sdcard.svset_global_assignment -name SYSTEMVERILOG_FILE sysclock.svset_global_assignment -name SYSTEMVERILOG_FILE i2c.svset_global_assignment -name SYSTEMVERILOG_FILE abcbus.svset_global_assignment -name VERILOG_FILE ip/abcmapram.vset_global_assignment -name VERILOG_FILE ip/fastmem_ip.vset_global_assignment -name SYSTEMVERILOG_FILE fast_mem.svset_global_assignment -name MIF_FILE ../rv32/boot.mifset_global_assignment -name VERILOG_FILE picorv32.vset_global_assignment -name SYSTEMVERILOG_FILE functions.svset_global_assignment -name SYSTEMVERILOG_FILE spi_master.svset_global_assignment -name SYSTEMVERILOG_FILE sdram.svset_global_assignment -name SYSTEMVERILOG_FILE spirom.svset_global_assignment -name VERILOG_FILE ip/ddio_out.vset_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tclset_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tclset_global_assignment -name SOURCE_FILE max80jic.cofset_global_assignment -name VERILOG_FILE ip/hdmitx.vset_global_assignment -name SYSTEMVERILOG_FILE transpose.svset_global_assignment -name SYSTEMVERILOG_FILE synchro.svset_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.svset_global_assignment -name SDC_FILE max80.sdcset_global_assignment -name SYSTEMVERILOG_FILE max80.svset_global_assignment -name SOURCE_FILE max80.pinsset_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tclset_global_assignment -name VERILOG_FILE ip/fifo.vset_global_assignment -name VERILOG_FILE ip/ddufifo.vset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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