max80_fw/output_files/max80.pow.rpt

Power Analyzer report for max80
Wed Jul 28 12:56:12 2021
Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Parallel Compilation
  3. Power Analyzer Summary
  4. Power Analyzer Settings
  5. Indeterminate Toggle Rates
  6. Operating Conditions Used
  7. Thermal Power Dissipation by Block
  8. Thermal Power Dissipation by Block Type
  9. Thermal Power Dissipation by Hierarchy
 10. Core Dynamic Thermal Power Dissipation by Clock Domain
 11. Current Drawn from Voltage Supplies Summary
 12. VCCIO Supply Current Drawn by I/O Bank
 13. VCCIO Supply Current Drawn by Voltage
 14. Confidence Metric Details
 15. Signal Activities
 16. Power Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2019  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.01        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   1.4%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------+
; Power Analyzer Summary                                                                    ;
+----------------------------------------+--------------------------------------------------+
; Power Analyzer Status                  ; Successful - Wed Jul 28 12:56:12 2021            ;
; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
; Revision Name                          ; max80                                            ;
; Top-level Entity Name                  ; max80                                            ;
; Family                                 ; Cyclone IV E                                     ;
; Device                                 ; EP4CE15F17C8                                     ;
; Power Models                           ; Final                                            ;
; Total Thermal Power Dissipation        ; 170.95 mW                                        ;
; Core Dynamic Thermal Power Dissipation ; 0.00 mW                                          ;
; Core Static Thermal Power Dissipation  ; 59.93 mW                                         ;
; I/O Thermal Power Dissipation          ; 111.02 mW                                        ;
; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
+----------------------------------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Power Analyzer Settings                                                                                        ;
+------------------------------------------------------------------+-----------------------------+---------------+
; Option                                                           ; Setting                     ; Default Value ;
+------------------------------------------------------------------+-----------------------------+---------------+
; Use smart compilation                                            ; Off                         ; Off           ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                          ; On            ;
; Enable compact report table                                      ; Off                         ; Off           ;
; Default Power Input I/O Toggle Rate                              ; 12.5%                       ; 12.5%         ;
; Preset Cooling Solution                                          ; No Heat Sink With Still Air ;               ;
; Board thermal model                                              ; None (CONSERVATIVE)         ;               ;
; VCCA voltage                                                     ; 2.5V                        ;               ;
; Default Power Toggle Rate                                        ; 12.5%                       ; 12.5%         ;
; Use vectorless estimation                                        ; On                          ; On            ;
; Use Input Files                                                  ; Off                         ; Off           ;
; Filter Glitches in VCD File Reader                               ; On                          ; On            ;
; Power Analyzer Report Signal Activity                            ; Off                         ; Off           ;
; Power Analyzer Report Power Dissipation                          ; Off                         ; Off           ;
; Device Power Characteristics                                     ; TYPICAL                     ; TYPICAL       ;
; Automatically Compute Junction Temperature                       ; On                          ; On            ;
; Specified Junction Temperature                                   ; 25                          ; 25            ;
; Ambient Temperature                                              ; 25                          ; 25            ;
; Use Custom Cooling Solution                                      ; Off                         ; Off           ;
; Board Temperature                                                ; 25                          ; 25            ;
+------------------------------------------------------------------+-----------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Indeterminate Toggle Rates                                                                                                        ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+
; Node                                                                                                ; Reason                      ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; No valid clock domain found ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; No valid clock domain found ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; No valid clock domain found ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; No valid clock domain found ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; No valid clock domain found ;
; abc_clk                                                                                             ; No valid clock domain found ;
; abc_a[0]                                                                                            ; No valid clock domain found ;
; abc_a[1]                                                                                            ; No valid clock domain found ;
; abc_a[2]                                                                                            ; No valid clock domain found ;
; abc_a[3]                                                                                            ; No valid clock domain found ;
; abc_a[4]                                                                                            ; No valid clock domain found ;
; abc_a[5]                                                                                            ; No valid clock domain found ;
; abc_a[6]                                                                                            ; No valid clock domain found ;
; abc_a[7]                                                                                            ; No valid clock domain found ;
; abc_a[8]                                                                                            ; No valid clock domain found ;
; abc_a[9]                                                                                            ; No valid clock domain found ;
; abc_a[10]                                                                                           ; No valid clock domain found ;
; abc_a[11]                                                                                           ; No valid clock domain found ;
; abc_a[12]                                                                                           ; No valid clock domain found ;
; abc_a[13]                                                                                           ; No valid clock domain found ;
; abc_a[14]                                                                                           ; No valid clock domain found ;
; abc_a[15]                                                                                           ; No valid clock domain found ;
; abc_rst_n                                                                                           ; No valid clock domain found ;
; abc_cs_n                                                                                            ; No valid clock domain found ;
; abc_out_n[0]                                                                                        ; No valid clock domain found ;
; abc_out_n[1]                                                                                        ; No valid clock domain found ;
; abc_out_n[2]                                                                                        ; No valid clock domain found ;
; abc_out_n[3]                                                                                        ; No valid clock domain found ;
; abc_out_n[4]                                                                                        ; No valid clock domain found ;
; abc_inp_n[0]                                                                                        ; No valid clock domain found ;
; abc_inp_n[1]                                                                                        ; No valid clock domain found ;
; abc_xmemfl_n                                                                                        ; No valid clock domain found ;
; abc_xmemw800_n                                                                                      ; No valid clock domain found ;
; abc_xmemw80_n                                                                                       ; No valid clock domain found ;
; abc_xinpstb_n                                                                                       ; No valid clock domain found ;
; abc_xoutpstb_n                                                                                      ; No valid clock domain found ;
; tty_txd                                                                                             ; No valid clock domain found ;
; tty_rts                                                                                             ; No valid clock domain found ;
; tty_dtr                                                                                             ; No valid clock domain found ;
; flash_miso                                                                                          ; No valid clock domain found ;
; rtc_32khz                                                                                           ; No valid clock domain found ;
; rtc_int_n                                                                                           ; No valid clock domain found ;
; abc_d[0]                                                                                            ; No valid clock domain found ;
; abc_d[1]                                                                                            ; No valid clock domain found ;
; abc_d[2]                                                                                            ; No valid clock domain found ;
; abc_d[3]                                                                                            ; No valid clock domain found ;
; abc_d[4]                                                                                            ; No valid clock domain found ;
; abc_d[5]                                                                                            ; No valid clock domain found ;
; abc_d[6]                                                                                            ; No valid clock domain found ;
; abc_d[7]                                                                                            ; No valid clock domain found ;
; hdmi_sda                                                                                            ; No valid clock domain found ;
; sr_dq[0]                                                                                            ; No valid clock domain found ;
; sr_dq[1]                                                                                            ; No valid clock domain found ;
; sr_dq[2]                                                                                            ; No valid clock domain found ;
; sr_dq[3]                                                                                            ; No valid clock domain found ;
; sr_dq[4]                                                                                            ; No valid clock domain found ;
; sr_dq[5]                                                                                            ; No valid clock domain found ;
; sr_dq[6]                                                                                            ; No valid clock domain found ;
; sr_dq[7]                                                                                            ; No valid clock domain found ;
; sr_dq[8]                                                                                            ; No valid clock domain found ;
; sr_dq[9]                                                                                            ; No valid clock domain found ;
; sr_dq[10]                                                                                           ; No valid clock domain found ;
; sr_dq[11]                                                                                           ; No valid clock domain found ;
; sr_dq[12]                                                                                           ; No valid clock domain found ;
; sr_dq[13]                                                                                           ; No valid clock domain found ;
; sr_dq[14]                                                                                           ; No valid clock domain found ;
; sr_dq[15]                                                                                           ; No valid clock domain found ;
; sd_dat[0]                                                                                           ; No valid clock domain found ;
; sd_dat[1]                                                                                           ; No valid clock domain found ;
; sd_dat[2]                                                                                           ; No valid clock domain found ;
; sd_dat[3]                                                                                           ; No valid clock domain found ;
; spi_clk                                                                                             ; No valid clock domain found ;
; spi_miso                                                                                            ; No valid clock domain found ;
; spi_mosi                                                                                            ; No valid clock domain found ;
; spi_cs_esp_n                                                                                        ; No valid clock domain found ;
; esp_io0                                                                                             ; No valid clock domain found ;
; esp_int                                                                                             ; No valid clock domain found ;
; i2c_scl                                                                                             ; No valid clock domain found ;
; i2c_sda                                                                                             ; No valid clock domain found ;
; gpio[0]                                                                                             ; No valid clock domain found ;
; gpio[1]                                                                                             ; No valid clock domain found ;
; gpio[2]                                                                                             ; No valid clock domain found ;
; gpio[3]                                                                                             ; No valid clock domain found ;
; gpio[4]                                                                                             ; No valid clock domain found ;
; gpio[5]                                                                                             ; No valid clock domain found ;
; hdmi_scl                                                                                            ; No valid clock domain found ;
; hdmi_hpd                                                                                            ; No valid clock domain found ;
; clock_48                                                                                            ; No valid clock domain found ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+


+----------------------------------------------------------------------+
; Operating Conditions Used                                            ;
+-----------------------------------------+----------------------------+
; Setting                                 ; Value                      ;
+-----------------------------------------+----------------------------+
; Device power characteristics            ; Typical                    ;
;                                         ;                            ;
; Voltages                                ;                            ;
;     VCCINT                              ; 1.20 V                     ;
;     VCCA                                ; 2.50 V                     ;
;     VCCD                                ; 1.20 V                     ;
;     3.3-V LVTTL I/O Standard            ; 3.3 V                      ;
;     2.5 V I/O Standard                  ; 2.5 V                      ;
;     LVDS I/O Standard                   ; 2.5 V                      ;
;                                         ;                            ;
; Auto computed junction temperature      ; 30.1 degrees Celsius       ;
;     Ambient temperature                 ; 25.0 degrees Celsius       ;
;     Junction-to-Case thermal resistance ; 7.30 degrees Celsius/Watt  ;
;     Case-to-Ambient thermal resistance  ; 22.30 degrees Celsius/Watt ;
;                                         ;                            ;
; Board model used                        ; Typical                    ;
+-----------------------------------------+----------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block                                                                                                           ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block Type                                                                                                                                                                                              ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Block Type                            ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Combinational cell                    ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
; Register cell                         ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
; Double Data Rate I/O Output Circuitry ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
; I/O register                          ; 0.00 mW                           ; 0.00 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
; I/O                                   ; 84.65 mW                          ; 0.00 mW                     ; 84.65 mW                       ; 0.00 mW                       ;    0.000                                                  ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Hierarchy                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
; |max80                                                          ; 84.65 mW (84.65 mW)                  ; 0.00 mW (0.00 mW)               ; 84.65 mW (84.65 mW)               ; 0.00 mW (0.00 mW)                 ; |max80                                                                                                             ;
;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
;     |tmdsenc:hdmitmds[0].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
;     |tmdsenc:hdmitmds[1].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
;     |tmdsenc:hdmitmds[2].enc                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ;
;     |transpose:hdmitranspose                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|transpose:hdmitranspose                                                                                     ;
;     |hdmitx:hdmitx                                              ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
;         |altlvds_tx:ALTLVDS_TX_component                        ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
;             |hdmitx_lvds_tx:auto_generated                      ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
;                 |hdmitx_cntr:cntr2                              ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
;                 |hdmitx_cntr:cntr13                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
;                 |hdmitx_ddio_out:ddio_out                       ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ;
;                 |hdmitx_shift_reg:outclk_shift_h                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ;
;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
;                 |hdmitx_ddio_out1:outclock_ddio                 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ;
;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
;     |pll:pll                                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
;         |altpll:altpll_component                                ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
;             |pll_altpll:auto_generated                          ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
;                 |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2   ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ;
;                 |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ;
;                 |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ;
;                 |pll_cntr:phasestep_counter                     ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter                        ;
;                 |pll_cntr1:pll_internal_phasestep               ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep                  ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.

(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.


+--------------------------------------------------------------------+
; Core Dynamic Thermal Power Dissipation by Clock Domain             ;
+-----------------+-----------------------+--------------------------+
; Clock Domain    ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
+-----------------+-----------------------+--------------------------+
; No clock domain ; 0.00                  ; 0.00                     ;
+-----------------+-----------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Current Drawn from Voltage Supplies Summary                                                                                        ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCINT         ; 39.95 mA                ; 0.00 mA                   ; 39.95 mA                 ; 39.95 mA                         ;
; VCCIO          ; 27.11 mA                ; 0.00 mA                   ; 27.11 mA                 ; 27.11 mA                         ;
; VCCA           ; 18.22 mA                ; 0.00 mA                   ; 18.22 mA                 ; 18.22 mA                         ;
; VCCD           ; 7.76 mA                 ; 0.00 mA                   ; 7.76 mA                  ; 7.76 mA                          ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.


+-----------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by I/O Bank                                                        ;
+----------+---------------+---------------------+-----------------------+----------------------+
; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
+----------+---------------+---------------------+-----------------------+----------------------+
; 1        ; 3.3V          ; 1.27 mA             ; 0.00 mA               ; 1.27 mA              ;
; 2        ; 3.3V          ; 1.31 mA             ; 0.00 mA               ; 1.31 mA              ;
; 3        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
; 4        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
; 5        ; 2.5V          ; 17.74 mA            ; 0.00 mA               ; 17.74 mA             ;
; 6        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
; 7        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
; 8        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
+----------+---------------+---------------------+-----------------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by Voltage                                                                                             ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; 2.5V          ; 17.74 mA                ; 0.00 mA                   ; 17.74 mA                 ; 17.74 mA                         ;
; 3.3V          ; 9.37 mA                 ; 0.00 mA                   ; 9.37 mA                  ; 9.37 mA                          ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Confidence Metric Details                                                                                                                        ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
; Data Source                                                                            ; Total       ; Pin        ; Registered   ; Combinational ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
; Simulation (from file)                                                                 ;             ;            ;              ;               ;
;     -- Number of signals with Toggle Rate from Simulation                              ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
;     -- Number of signals with Static Probability from Simulation                       ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
;                                                                                        ;             ;            ;              ;               ;
; Node, entity or clock assignment                                                       ;             ;            ;              ;               ;
;     -- Number of signals with Toggle Rate from Node, entity or clock assignment        ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
;                                                                                        ;             ;            ;              ;               ;
; Vectorless estimation                                                                  ;             ;            ;              ;               ;
;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 806 (90.2%) ; 96 (53.6%) ; 221 (100.0%) ; 489 (99.0%)   ;
;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 187 (20.9%) ; 85 (47.5%) ; 0 (0.0%)     ; 102 (20.6%)   ;
;     -- Number of signals with Static Probability from Vectorless estimation            ; 806 (90.2%) ; 96 (53.6%) ; 221 (100.0%) ; 489 (99.0%)   ;
;                                                                                        ;             ;            ;              ;               ;
; Default assignment                                                                     ;             ;            ;              ;               ;
;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)     ; 0 (0.0%)      ;
;     -- Number of signals with Static Probability from Default assignment               ; 88 (9.8%)   ; 83 (46.4%) ; 0 (0.0%)     ; 5 (1.0%)      ;
;                                                                                        ;             ;            ;              ;               ;
; Assumed 0                                                                              ;             ;            ;              ;               ;
;     -- Number of signals with Toggle Rate assumed 0                                    ; 88 (9.8%)   ; 83 (46.4%) ; 0 (0.0%)     ; 5 (1.0%)      ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Activities                                                                                                                           ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".


+-------------------------+
; Power Analyzer Messages ;
+-------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Power Analyzer
    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
    Info: Processing started: Wed Jul 28 12:56:10 2021
Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity pll_altpll
        Info (332166): set_false_path -from ** -to *phasedone_state* 
        Info (332166): set_false_path -from ** -to *internal_phasestep* 
Warning (332173): Ignored filter: *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
Warning (332173): Ignored filter: *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
Critical Warning (332012): Synopsys Design Constraints File file not found: 'max80.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332060): Node: clock_48 was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register led_ctr[26]~_Duplicate_1 is being clocked by clock_48
Warning (332068): No clocks defined in design.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
    Warning (332056): Node: pll|altpll_component|auto_generated|pll1|clk[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.833
    Warning (332056): Node: hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 27.778
    Warning (332056): Node: hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 27.778
Info (223000): Starting Vectorless Power Activity Estimation
Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
Info (223001): Completed Vectorless Power Activity Estimation
Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec
Info (215031): Total thermal power estimate for the design is 170.95 mW
Info: Quartus Prime Power Analyzer was successful. 0 errors, 15 warnings
    Info: Peak virtual memory: 1262 megabytes
    Info: Processing ended: Wed Jul 28 12:56:12 2021
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02