spi_master.sv 5.2 KB

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  1. //
  2. // spi_master.sv
  3. //
  4. // Simple byte-oriented SPI master unit with optional multiwidth support
  5. // (1, 2, 4, 8).
  6. //
  7. // The output SPI clock equals the system clock /2 unless clk_en is used
  8. // to throttle the output clock.
  9. //
  10. // spi_io[0] = DI, spi_io[1] = DO in single bit mode.
  11. //
  12. // By default the output is latched; if not, it is only valid in
  13. // the cycle that eack is asserted (useful for FIFOs etc.)
  14. //
  15. //
  16. // XXX: CHPA option (mode 1/3)
  17. //
  18. `define IO_MAX max(ilog2c(width)-1, 1)
  19. module spi_master
  20. #(
  21. parameter width = 1, // Max width of SPI bus (1, 2, 4, or 8)
  22. parameter n_cs = 1, // Number of CS# outputs
  23. parameter cs_delay = 1, // Time from CS# low to first data
  24. parameter latch_q = 1 // Latch output
  25. )
  26. (
  27. input rst_n, // Unit reset
  28. input clk, // System clock
  29. input clk_en, // SPI clock enable
  30. input [7:0] d, // System data in
  31. output [7:0] q, // System data out
  32. input req, // Session request
  33. input dir, // Session is write (for multibit)
  34. input [1:0] iowidth, // Session width (lg2)
  35. output reg sack, // Session started
  36. output reg eack, // Session ended
  37. input idle_io, // Signal level for I/Os at idle
  38. input cpol, // Clock polarity (usually constant)
  39. input lsb, // Littleendian mode (usually constant)
  40. input [n_cs-1:0] cs, // Device select (active high)
  41. output reg spi_sck, // SPI clock
  42. inout [`IO_MAX:0] spi_io, // SPI data
  43. output [n_cs-1:0] spi_cs_n // SPI CS# lines
  44. );
  45. localparam io_max = `IO_MAX;
  46. localparam iowidth_max = ilog2c(width);
  47. localparam ctr_max = max(ilog2c(cs_delay)-1,2);
  48. reg spi_active;
  49. reg [((width > 2) ? 1 : 0):0] spi_width;
  50. reg [ctr_max:0] spi_ctr;
  51. reg [n_cs-1:0] spi_cs_q;
  52. reg [io_max:0] spi_out_q;
  53. reg [1:0] spi_oe_q;
  54. reg d_dir;
  55. reg [7:0] d_out; // Output shift register
  56. reg [7:0] d_in; // Input shift register
  57. reg [7:0] q_q; // Latched output data
  58. assign spi_cs_n = ~spi_cs_q;
  59. assign q = latch_q ? q_q : d_in;
  60. wire spi_cs_changed = |(spi_cs_q ^ cs);
  61. // Always 2'b10 for single-bit SPI
  62. wire [1:0] spi_oe = (width > 1) ? spi_oe_q : 2'b10;
  63. assign spi_io[0] = spi_oe[0] ? spi_out_q[0] : 1'bz;
  64. assign spi_io[io_max:1] = spi_oe[1] ? spi_out_q[io_max:1] : {io_max{1'bz}};
  65. // Make it clear to the compiler that iowidth is undefined if
  66. // it is too large
  67. wire [1:0] iowidth_in = (iowidth > iowidth_max) ? 2'bxx : iowidth;
  68. // Just for convenience...
  69. wire [3:0] spi_width_n = 1'b1 << spi_width;
  70. wire [io_max:0] idle_allio = {(io_max+1){idle_io}};
  71. always @(negedge rst_n or posedge clk)
  72. if (~rst_n)
  73. begin
  74. spi_sck <= 1'b0;
  75. spi_active <= 1'b0;
  76. spi_width <= 4'b0001;
  77. spi_ctr <= 1'b0;
  78. spi_cs_q <= 1'b0;
  79. spi_out_q <= idle_allio;
  80. spi_oe_q <= 2'b10;
  81. sack <= 1'b0;
  82. eack <= 1'b0;
  83. d_out <= idle_allio;
  84. d_in <= 8'hxx;
  85. q_q <= 8'hxx;
  86. end
  87. else
  88. begin
  89. // These are always single system clock pulses
  90. sack <= 1'b0;
  91. eack <= 1'b0;
  92. if (clk_en)
  93. begin
  94. spi_ctr <= spi_ctr - 1'b1;
  95. spi_sck <= (spi_ctr[0] & spi_active) ^ cpol;
  96. if (~spi_ctr[0])
  97. if (lsb)
  98. d_in <= (spi_io[spi_width_n-1:0] << (8-spi_width_n)) |
  99. (d_in >> spi_width_n);
  100. else
  101. d_in <= (d_in << spi_width_n) | spi_io[spi_width_n-1:0];
  102. else
  103. begin
  104. spi_out_q <= idle_allio;
  105. if (spi_active)
  106. begin
  107. if (~|spi_ctr[ctr_max:1])
  108. begin
  109. eack <= 1'b1;
  110. q_q <= d_in;
  111. spi_active <= 1'b0;
  112. end
  113. if (spi_width > iowidth_max)
  114. begin
  115. // Invalid width, let the compiler do whatever
  116. d_out <= 8'hxx;
  117. spi_out_q <= {(io_max+1){1'bx}};
  118. end
  119. else
  120. begin
  121. if (lsb)
  122. d_out <= {spi_width_n{io_idle}} |
  123. (d_out >> spi_width_n);
  124. else
  125. d_out <= (d_out << spi_width_n) |
  126. {spi_width_n{io_idle}};
  127. // 1-byte SPI uses IO1 as output (DO)
  128. if (spi_width == 2'd0)
  129. spi_out_q[1] <= d_out[lsb ? 0 : 7];
  130. else
  131. spi_out_q[spi_width_n-1:0]
  132. <= d_out >> (lsb ? 0 : 8-spi_width_n);
  133. end
  134. end // if (spi_active)
  135. else
  136. begin
  137. spi_cs_q <= cs;
  138. d_out <= d;
  139. if (cs_delay != 0 &&
  140. (spi_cs_changed | ~|spi_ctr[ctr_max:1]))
  141. begin
  142. if (spi_cs_changed)
  143. spi_ctr[ctr_max:1] <= cs_delay;
  144. spi_oe_q <= 2'b10; // As for 1-bit mode
  145. end
  146. else if (req &&
  147. (cs_delay == 0 || ~|spi_ctr[ctr_max:1]))
  148. begin
  149. if (iowidth <= iowidth_max)
  150. begin
  151. spi_width <= iowidth;
  152. spi_ctr[ctr_max:1] <= 3'd8 >> iowidth;
  153. spi_oe_q <=
  154. |iowidth ? {2{dir}} : 2'b10;
  155. spi_active <= 1'b1;
  156. sack <= 1'b1;
  157. end
  158. else
  159. begin
  160. // Invalid width, let the compiler
  161. // do whatever it wants...
  162. spi_width <= 2'bxx;
  163. spi_ctr[ctr_max:1] <= {ctr_max{1'bx}};
  164. spi_oe_q <= 2'bxx;
  165. spi_active <= 1'bx;
  166. sack <= 1'bx;
  167. end
  168. end // if (req &&...
  169. end // else: !if(spi_active)
  170. end // else: !if(~spi_ctr[0])
  171. end // if (clk_en)
  172. end // else: !if(~rst_n)
  173. endmodule // spi_master