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- module i2c (
- input rst_n,
- input clk,
- input valid,
- input [1:0] addr,
- input [31:0] wdata,
- input [3:0] wstrb,
- output reg [31:0] rdata,
- output irq,
- inout i2c_scl,
- inout i2c_sda
- );
- reg [7:0] divisor;
- reg [7:0] baudctr;
- reg [3:0] bitctr;
- reg [1:0] phase;
- reg [8:0] wreg;
- reg [8:0] rreg;
- reg do_read;
- reg busy;
- reg end_s, end_p;
- reg started;
- reg [1:0] outsymb;
-
- reg scl_out = 1'b1;
- reg sda_out = 1'b1;
- assign i2c_scl = scl_out ? 1'bz : 1'b0;
- assign i2c_sda = sda_out ? 1'bz : 1'b0;
- always @(negedge rst_n or posedge clk)
- if (~rst_n)
- begin
- bitctr <= 4'd14;
- busy <= 1'b0;
- outsymb <= 2'b11;
- baudctr <= 8'd0;
- divisor <= 8'd209;
- scl_out <= 1'b1;
- sda_out <= 1'b1;
- phase <= 2'b00;
- do_read <= 1'b0;
- end_s <= 1'b0;
- end_p <= 1'b0;
- started <= 1'b0;
- end
- else
- begin
-
-
-
- if (|baudctr)
- begin
- baudctr <= baudctr - 1'b1;
- end
- else
- begin
-
- baudctr <= divisor;
- phase <= phase + 1'b1;
- if ((phase == 2'b10) & ~i2c_scl)
- phase <= 2'b10;
-
-
-
-
-
- if (phase[0])
- scl_out <= outsymb[1] | ~phase[1];
- sda_out <= outsymb[0];
- if (phase == 2'b11)
- begin
-
- if (do_read)
- rreg <= { rreg[7:0], i2c_sda };
- do_read <= 1'b0;
-
-
- if (~busy)
- begin
- started <= started & ~end_p;
- bitctr <= started & ~end_p ? 4'd0 : 4'd14;
- outsymb <= { 1'b1, ~(started & ~end_p) };
- end
- else
- begin
- bitctr <= bitctr + 1'b1;
- started <= 1'b1;
- case (bitctr)
- 4'd0, 4'd1, 4'd2, 4'd3, 4'd4,
- 4'd5, 4'd6, 4'd7, 4'd8:
- begin
- outsymb <= { 1'b0, wreg[8] };
- wreg <= { wreg[7:0], 1'b1 };
- do_read <= 1'b1;
- if (bitctr[3])
- begin
- bitctr <= end_s ? 4'd14 :
- end_p ? 4'd12 : 4'b0;
- busy <= end_p & ~end_s;
-
-
-
- started <= ~(end_s | end_p);
- end
- end
-
- 4'd12: begin
- started <= 1'b0;
- outsymb <= 2'b10;
- end
- 4'd13: begin
- started <= 1'b0;
- outsymb <= 2'b11;
- busy <= 1'b0;
- end
-
- 4'd14: begin
- started <= ~(end_s & end_p);
- outsymb <= 2'b11;
- end
- 4'd15: begin
-
- outsymb <= { 1'b0, ~started };
- end
- default: begin
- outsymb <= 2'bxx;
- end
- endcase
- end
- end
- end
-
-
-
- if (valid)
- case (addr)
- 2'b00:
- if (~busy)
- begin
- if (wstrb[1])
- wreg[8:1] <= wdata[15:8];
- if (wstrb[0])
- begin
- wreg[0] <= wdata[7];
- end_p <= wdata[2];
- end_s <= wdata[1];
- busy <= 1'b1;
- end
- end
- 2'b10: begin
- if (wstrb[0])
- divisor <= wdata[7:0];
- end
- 2'b11: begin
- if (wstrb[0])
- begin
- if (wdata[0])
- begin
- end_p <= 1'b1;
- end_s <= 1'b0;
- end
- end
- end
- default: begin
-
- end
- endcase
- end
-
-
-
- always_comb
- case (addr)
- 2'b00: rdata = { 16'b0, wreg, i2c_sda, i2c_scl, started, 1'b0,
- end_p, end_s, busy | do_read };
- 2'b01: rdata = { 16'b0, rreg, i2c_sda, i2c_scl, started, 1'b0,
- end_p, end_s, busy | do_read };
- 2'b10: rdata = { 24'b0, divisor };
- default: rdata = 32'b0;
- endcase
-
-
-
- assign irq = ~(busy | do_read | unstart);
- endmodule
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