1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768 |
- module synchronizer #(parameter width = 1, parameter stages = 2)
- (
- input rst_n,
- input clk,
- input [width-1:0] d,
- output [width-1:0] q
- );
-
-
-
-
-
- (*
- syn_preserve = 1,
- altera_attribute =
- {"-name SYNCHRONIZER_IDENTIFICATION FORCED ; ",
- "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ", tostr(stages-1)}
- *)
- reg [width-1:0] qreg0;
- (*
- syn_preserve = 1,
- altera_attribute =
- {"-name SYNCHRONIZER_IDENTIFICATION AUTO ; ",
- "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ", tostr(stages-1)}
- *)
- reg [width-1:0] qreg[stages-1:1];
- always @(posedge clk or negedge rst_n)
- if (~rst_n)
- qreg0 <= {width{1'b0}};
- else
- qreg0 <= d;
- always @(posedge clk or negedge rst_n)
- if (~rst_n)
- qreg[1] <= {width{1'b0}};
- else
- qreg[1] <= qreg0;
- generate
- genvar i;
- for (i = 2; i < stages; i = i + 1)
- begin : stage
- always @(posedge clk or negedge rst_n)
- if (~rst_n)
- qreg[i] <= {width{1'b0}};
- else
- qreg[i] <= qreg[i-1];
- end
- endgenerate
- assign q = qreg[stages-1];
- endmodule
|