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- PAL16R8
- PAT8003 **-Luxor X37 CPU board-** mk,85-05-29
- SCC decoder and clock multiplexor control
- clk ba2 zwr d07 scc ba5 ba4 ba3 rst GND
- OE ce0 c0a c1b ce1 c1a c2b ce2 c2a VCC
- ;equations:
- /ce0 := rst*/scc*/ba5*/ba4*/ba3
- /ce1 := rst*/scc*/ba5* ba4*/ba3
- /ce2 := rst*/scc* ba5*/ba4*/ba3
-
- /c0a := /rst
- + /scc*/ba5*/ba4* ba3* ba2*/zwr*/d07
- + /c0a* scc
- + /c0a* zwr
- + /c0a* ba5
- + /c0a* ba4
- + /c0a*/ba3
- + /c0a*/ba2
-
- /c1b := /rst
- + /scc*/ba5* ba4* ba3*/ba2*/zwr*/d07
- + /c1b* scc
- + /c1b* zwr
- + /c1b* ba5
- + /c1b*/ba4
- + /c1b*/ba3
- + /c1b* ba2
- /c1a := /rst
- + /scc*/ba5* ba4* ba3* ba2*/zwr*/d07
- + /c1a* scc
- + /c1a* zwr
- + /c1a* ba5
- + /c1a*/ba4
- + /c1a*/ba3
- + /c1a*/ba2
-
- /c2b := /rst
- + /scc* ba5*/ba4* ba3*/ba2*/zwr*/d07
- + /c2b* scc
- + /c2b* zwr
- + /c2b*/ba5
- + /c2b* ba4
- + /c2b*/ba3
- + /c2b* ba2
-
- /c2a := /rst
- + /scc* ba5*/ba4* ba3* ba2*/zwr*/d07
- + /c2a* scc
- + /c2a* zwr
- + /c2a*/ba5
- + /c2a* ba4
- + /c2a*/ba3
- + /c2a*/ba2
- FUNCTION TABLE
- clk OE rst scc zwr d07 ba3 ba5 ba4 ba2
- ce2 ce1 ce0 c2a c2b c1a c1b c0a
- ;c r sz d b bbb ccc ccccc
- ;lOs cw 0 a aaa eee 22110
- ;kEt cr 7 3 542 210 ababa
- ---------------------------
- CHX XX X X XXX ZZZ ZZZZZ
- CLL XX X X XXX HHH LLLLL
- CLH HX X X XXX HHH LLLLL
- CLH LX X L LLX HHL LLLLL
- CLH LX X L LHX HLH LLLLL
- CLH LX X L HLX LHH LLLLL
- CLH LX X L HHX HHH LLLLL
- CLH LL X H LLL HHH LLLLL
- CLH LL H H LLH HHH LLLLH
- CLH LL H H LHL HHH LLLHH
- CLH LL H H LHH HHH LLHHH
- CLH LL H H HLL HHH LHHHH
- CLH LL H H HLH HHH HHHHH
- CLH LL X H HHX HHH HHHHH
- CLH HX X X XXX HHH HHHHH
- CLH XH X X XXX XXX HHHHH
- CLH XX X H XXX HHH HHHHH
- CLH LL L H HLH HHH LHHHH
- CLH LL L H HLL HHH LLHHH
- CLH LL L H LHH HHH LLLHH
- CLH LL L H LHL HHH LLLLH
- CLH LL L H LLH HHH LLLLL
- ---------------------------
- DESCRIPTION:
- This device generates three decoded CE signals for SCC circuits on
- X37 CPU board and five latched clock multiplexor controls for serial
- adapters.
- Inputs: rst - reset
- ba(n) - bufffered address line n
- d07 - data bit 7
- scc - access to the SCC device group
- zwr - write pulse
- Outputs:ce(n) - SCC(n) chip enable
- c(n)a - mux control corr. to SCC(n) port a
- c(n)b - " " " " " b
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