fmrx: add a timeout for no more clock edge (last bit?)

USBCAS/fmrx.c

@@ -4,8 +4,6 @@
 
 #include "usbcas.h"
 
-static uint16_t one_bit_lo, one_bit_hi; /* Range for an edge being a "1" */
-
 static inline void fmrx_led_on(void)
 {
 	PORTB &= ~(1 << 0);
@@ -35,10 +33,7 @@ void fmrx_init(void)
 	TCCR1A = 0;
 
 	/* Enable interrupts on input capture */
-	TIMSK1 = (1 << ICIE1);
-
-	/* Clear interrupt flag if set */
-	TIFR1 = (1 << ICF1);
+	TIFR1 = TIMSK1 = (1 << ICIE1);
 
 	/* Clear timer counter */
 	TCNT1 = 0;
@@ -52,7 +47,27 @@ void fmrx_init(void)
 	TCCR1B = tccr1b;
 }
 
+/* Timing constants: start and end of data bit interval, and timeout */
+static uint16_t one_bit_lo, one_bit_hi, one_bit_timeout;
+
 static uint16_t bytes;
+static uint16_t last_edge;
+static uint16_t data;		/* 16 bit for sync pattern detect */
+static uint8_t  bits;
+static uint16_t bytes;
+static bool started;
+
+/* Bit receive timeout on/off */
+static inline void enable_timeout(uint16_t when)
+{
+	OCR1A = when;
+	TIFR1 = TIMSK1 = (1 << ICIE1) | (1 << OCIE1A);
+}
+
+static inline void disable_timeout(void)
+{
+	TIMSK1 = (1 << ICIE1);
+}
 
 void fmrx_set_speed(uint32_t baudrate)
 {
@@ -64,10 +79,14 @@ void fmrx_set_speed(uint32_t baudrate)
 		prescale++;	/* Prescale by 8 */
 	}
 
-	one_bit_lo = F_CPU / (4 * baudrate);
-	one_bit_hi = 3 * one_bit_lo;
+	one_bit_lo      = F_CPU / (4 * baudrate);
+	one_bit_hi      =  3 * one_bit_lo;
+	one_bit_timeout = 16 * one_bit_lo; /* 4 total bit times... */
 
-	bytes = 0;
+	disable_timeout();
+	started = false;
+	bits = bytes = 0;
+	last_edge = TCNT1;
 
 	TCCR1B = (TCCR1B & ~7) | prescale;
 }
@@ -76,13 +95,31 @@ void fmrx_set_speed(uint32_t baudrate)
 #define CAS_SYNC_PATTERN 0x0216 /* SYNC + STX */
 #define CAS_BLOCK_LEN    (1+2+253+1+2) /* type+num+data+ETX+checksum */
 
+/* Finish a bit due to clock edge or timeout */
+static void finish_bit(void)
+{
+	if (!started)
+		return;
+
+	if (bytes) {
+		if (--bits == 0) {
+			uint8_t outbyte = data >> 8;
+			fmrx_recv_byte(outbyte);
+			data = 0; /* To avoid false sync */
+			bits = 8;
+			if (--bytes == 0)
+				fmrx_led_off();
+		}
+	} else if (data == CAS_SYNC_PATTERN) {
+		bits = 8;
+		bytes = CAS_BLOCK_LEN;
+		fmrx_led_on();
+	}
+}
+
 /* Interrupt routine for edge capture */
 ISR(TIMER1_CAPT_vect)
 {
-	static uint16_t last_edge;
-	static uint16_t data;
-	static uint8_t  bits;
-
 	uint16_t edge, delta;
 
 	TCCR1B ^= (1 << ICES1);	/* Next edge -> opposite polarity */
@@ -99,20 +136,17 @@ ISR(TIMER1_CAPT_vect)
 	} else {
 		/* Clock edge */
 		last_edge = edge;
-		if (bytes) {
-			if (--bits == 0) {
-				uint8_t outbyte = data >> 8;
-				fmrx_recv_byte(outbyte);
-				data = 0; /* To avoid false sync */
-				bits = 8;
-				if (--bytes == 0)
-					fmrx_led_off();
-			}
-		} else if (data == CAS_SYNC_PATTERN) {
-			bits = 8;
-			bytes = CAS_BLOCK_LEN;
-			fmrx_led_on();
-		}
+		enable_timeout(edge + one_bit_timeout);
+		finish_bit();
+		started = true;
 		data >>= 1;
 	}
 }
+
+/* Interrupt routine for bit timeout */
+ISR(TIMER1_COMPA_vect)
+{
+	disable_timeout();
+	finish_bit();
+	started = false;
+}