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+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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+//
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+// Licensed under the Apache License, Version 2.0 (the "License");
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+// you may not use this file except in compliance with the License.
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+// You may obtain a copy of the License at
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+//
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+// http://www.apache.org/licenses/LICENSE-2.0
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+//
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+// Unless required by applicable law or agreed to in writing, software
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+// distributed under the License is distributed on an "AS IS" BASIS,
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+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+// See the License for the specific language governing permissions and
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+// limitations under the License.
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+
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+/*
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+Architecture:
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+
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+We can initialize a SPI driver, but we don't talk to the SPI driver itself, we address a device. A device essentially
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+is a combination of SPI port and CS pin, plus some information about the specifics of communication to the device
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+(timing, command/address length etc). The arbitration between tasks is also in conception of devices.
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+
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+A device can work in interrupt mode and polling mode, and a third but
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+complicated mode which combines the two modes above:
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+
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+1. Work in the ISR with a set of queues; one per device.
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+
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+ The idea is that to send something to a SPI device, you allocate a
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+ transaction descriptor. It contains some information about the transfer
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+ like the lenghth, address, command etc, plus pointers to transmit and
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+ receive buffer. The address of this block gets pushed into the transmit
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+ queue. The SPI driver does its magic, and sends and retrieves the data
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+ eventually. The data gets written to the receive buffers, if needed the
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+ transaction descriptor is modified to indicate returned parameters and
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+ the entire thing goes into the return queue, where whatever software
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+ initiated the transaction can retrieve it.
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+
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+ The entire thing is run from the SPI interrupt handler. If SPI is done
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+ transmitting/receiving but nothing is in the queue, it will not clear the
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+ SPI interrupt but just disable it by esp_intr_disable. This way, when a
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+ new thing is sent, pushing the packet into the send queue and re-enabling
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+ the interrupt (by esp_intr_enable) will trigger the interrupt again, which
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+ can then take care of the sending.
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+
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+2. Work in the polling mode in the task.
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+
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+ In this mode we get rid of the ISR, FreeRTOS queue and task switching, the
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+ task is no longer blocked during a transaction. This increase the cpu
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+ load, but decrease the interval of SPI transactions. Each time only one
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+ device (in one task) can send polling transactions, transactions to
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+ other devices are blocked until the polling transaction of current device
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+ is done.
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+
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+ In the polling mode, the queue is not used, all the operations are done
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+ in the task. The task calls ``spi_device_polling_start`` to setup and start
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+ a new transaction, then call ``spi_device_polling_end`` to handle the
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+ return value of the transaction.
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+
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+ To handle the arbitration among devices, the device "temporarily" acquire
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+ a bus by the ``device_acquire_bus_internal`` function, which writes
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+ dev_request by CAS operation. Other devices which wants to send polling
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+ transactions but don't own the bus will block and wait until given the
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+ semaphore which indicates the ownership of bus.
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+
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+ In case of the ISR is still sending transactions to other devices, the ISR
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+ should maintain an ``random_idle`` flag indicating that it's not doing
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+ transactions. When the bus is locked, the ISR can only send new
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+ transactions to the acquiring device. The ISR will automatically disable
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+ itself and send semaphore to the device if the ISR is free. If the device
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+ sees the random_idle flag, it can directly start its polling transaction.
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+ Otherwise it should block and wait for the semaphore from the ISR.
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+
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+ After the polling transaction, the driver will release the bus. During the
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+ release of the bus, the driver search all other devices to see whether
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+ there is any device waiting to acquire the bus, if so, acquire for it and
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+ send it a semaphore if the device queue is empty, or invoke the ISR for
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+ it. If all other devices don't need to acquire the bus, but there are
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+ still transactions in the queues, the ISR will also be invoked.
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+
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+ To get better polling efficiency, user can call ``spi_device_acquire_bus``
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+ function, which also calls the ``spi_bus_lock_acquire_core`` function,
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+ before a series of polling transactions to a device. The bus acquiring and
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+ task switching before and after the polling transaction will be escaped.
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+
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+3. Mixed mode
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+
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+ The driver is written under the assumption that polling and interrupt
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+ transactions are not happening simultaneously. When sending polling
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+ transactions, it will check whether the ISR is active, which includes the
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+ case the ISR is sending the interrupt transactions of the acquiring
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+ device. If the ISR is still working, the routine sending a polling
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+ transaction will get blocked and wait until the semaphore from the ISR
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+ which indicates the ISR is free now.
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+
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+ A fatal case is, a polling transaction is in flight, but the ISR received
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+ an interrupt transaction. The behavior of the driver is unpredictable,
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+ which should be strictly forbidden.
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+
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+We have two bits to control the interrupt:
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+
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+1. The slave->trans_done bit, which is automatically asserted when a transaction is done.
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+
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+ This bit is cleared during an interrupt transaction, so that the interrupt
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+ will be triggered when the transaction is done, or the SW can check the
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+ bit to see if the transaction is done for polling transactions.
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+
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+ When no transaction is in-flight, the bit is kept active, so that the SW
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+ can easily invoke the ISR by enable the interrupt.
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+
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+2. The system interrupt enable/disable, controlled by esp_intr_enable and esp_intr_disable.
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+
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+ The interrupt is disabled (by the ISR itself) when no interrupt transaction
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+ is queued. When the bus is not occupied, any task, which queues a
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+ transaction into the queue, will enable the interrupt to invoke the ISR.
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+ When the bus is occupied by a device, other device will put off the
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+ invoking of ISR to the moment when the bus is released. The device
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+ acquiring the bus can still send interrupt transactions by enable the
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+ interrupt.
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+
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+*/
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+
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+#include <string.h>
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+#include "driver/spi_common_internal.h"
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+#include "driver/spi_master.h"
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+
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+#include "esp_log.h"
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+#include "freertos/task.h"
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+#include "freertos/queue.h"
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+#include "freertos/semphr.h"
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+#include "soc/soc_memory_layout.h"
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+#include "driver/gpio.h"
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+#include "hal/spi_hal.h"
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+#include "esp_heap_caps.h"
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+
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+
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+typedef struct spi_device_t spi_device_t;
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+
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+/// struct to hold private transaction data (like tx and rx buffer for DMA).
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+typedef struct {
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+ spi_transaction_t *trans;
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+ const uint32_t *buffer_to_send; //equals to tx_data, if SPI_TRANS_USE_RXDATA is applied; otherwise if original buffer wasn't in DMA-capable memory, this gets the address of a temporary buffer that is;
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+ //otherwise sets to the original buffer or NULL if no buffer is assigned.
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+ uint32_t *buffer_to_rcv; // similar to buffer_to_send
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+} spi_trans_priv_t;
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+
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+typedef struct {
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+ int id;
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+ spi_device_t* device[DEV_NUM_MAX];
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+ intr_handle_t intr;
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+ spi_hal_context_t hal;
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+ spi_trans_priv_t cur_trans_buf;
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+ int cur_cs; //current device doing transaction
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+ const spi_bus_attr_t* bus_attr;
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+
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+ /**
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+ * the bus is permanently controlled by a device until `spi_bus_release_bus`` is called. Otherwise
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+ * the acquiring of SPI bus will be freed when `spi_device_polling_end` is called.
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+ */
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+ spi_device_t* device_acquiring_lock;
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+
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+//debug information
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+ bool polling; //in process of a polling, avoid of queue new transactions into ISR
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+
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+// PATCH
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+ SemaphoreHandle_t mutex;
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+ int count;
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+} spi_host_t;
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+
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+struct spi_device_t {
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+ int id;
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+ QueueHandle_t trans_queue;
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+ QueueHandle_t ret_queue;
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+ spi_device_interface_config_t cfg;
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+ spi_hal_dev_config_t hal_dev;
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+ spi_host_t *host;
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+ spi_bus_lock_dev_handle_t dev_lock;
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+};
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+
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+static spi_host_t* bus_driver_ctx[SOC_SPI_PERIPH_NUM] = {};
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+
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+static const char *SPI_TAG = "spi_master";
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+#define SPI_CHECK(a, str, ret_val, ...) \
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+ if (unlikely(!(a))) { \
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+ ESP_LOGE(SPI_TAG,"%s(%d): "str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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+ return (ret_val); \
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+ }
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+
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+
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+static void spi_intr(void *arg);
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+static void spi_bus_intr_enable(void *host);
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+static void spi_bus_intr_disable(void *host);
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+
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+static esp_err_t spi_master_deinit_driver(void* arg);
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+
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+static inline bool is_valid_host(spi_host_device_t host)
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+{
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+//SPI1 can be used as GPSPI only on ESP32
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+#if CONFIG_IDF_TARGET_ESP32
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+ return host >= SPI1_HOST && host <= SPI3_HOST;
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+#elif (SOC_SPI_PERIPH_NUM == 2)
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+ return host == SPI2_HOST;
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+#elif (SOC_SPI_PERIPH_NUM == 3)
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+ return host >= SPI2_HOST && host <= SPI3_HOST;
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+#endif
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+}
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+
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+// Should be called before any devices are actually registered or used.
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+// Currently automatically called after `spi_bus_initialize()` and when first device is registered.
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+static esp_err_t spi_master_init_driver(spi_host_device_t host_id)
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+{
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+ esp_err_t err = ESP_OK;
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+
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+ const spi_bus_attr_t* bus_attr = spi_bus_get_attr(host_id);
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+ SPI_CHECK(bus_attr != NULL, "host_id not initialized", ESP_ERR_INVALID_STATE);
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+ SPI_CHECK(bus_attr->lock != NULL, "SPI Master cannot attach to bus. (Check CONFIG_SPI_FLASH_SHARE_SPI1_BUS)", ESP_ERR_INVALID_ARG);
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+ // spihost contains atomic variables, which should not be put in PSRAM
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+ spi_host_t* host = heap_caps_malloc(sizeof(spi_host_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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+ if (host == NULL) {
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+ err = ESP_ERR_NO_MEM;
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+ goto cleanup;
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+ }
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+
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+ *host = (spi_host_t) {
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+ .id = host_id,
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+ .cur_cs = DEV_NUM_MAX,
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+ .polling = false,
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+ .device_acquiring_lock = NULL,
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+ .bus_attr = bus_attr,
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+ };
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+
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+ if (host_id != SPI1_HOST) {
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+ // interrupts are not allowed on SPI1 bus
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+ err = esp_intr_alloc(spicommon_irqsource_for_host(host_id),
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+ bus_attr->bus_cfg.intr_flags | ESP_INTR_FLAG_INTRDISABLED,
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+ spi_intr, host, &host->intr);
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+ if (err != ESP_OK) {
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+ goto cleanup;
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+ }
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+ }
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+
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+ //assign the SPI, RX DMA and TX DMA peripheral registers beginning address
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+ spi_hal_config_t hal_config = {
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+ //On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. Pass the registers of SPI peripheral to control it.
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+ .dma_in = SPI_LL_GET_HW(host_id),
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+ .dma_out = SPI_LL_GET_HW(host_id),
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+ .dma_enabled = bus_attr->dma_enabled,
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+ .dmadesc_tx = bus_attr->dmadesc_tx,
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+ .dmadesc_rx = bus_attr->dmadesc_rx,
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+ .tx_dma_chan = bus_attr->tx_dma_chan,
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+ .rx_dma_chan = bus_attr->rx_dma_chan,
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+ .dmadesc_n = bus_attr->dma_desc_num,
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+ };
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+ spi_hal_init(&host->hal, host_id, &hal_config);
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+
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+ if (host_id != SPI1_HOST) {
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+ //SPI1 attributes are already initialized at start up.
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+ spi_bus_lock_handle_t lock = spi_bus_lock_get_by_id(host_id);
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+ spi_bus_lock_set_bg_control(lock, spi_bus_intr_enable, spi_bus_intr_disable, host);
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+ spi_bus_register_destroy_func(host_id, spi_master_deinit_driver, host);
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+ }
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+
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+ bus_driver_ctx[host_id] = host;
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+ return ESP_OK;
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+
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+cleanup:
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+ if (host) {
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+ spi_hal_deinit(&host->hal);
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+ if (host->intr) {
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+ esp_intr_free(host->intr);
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+ }
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+ }
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+ free(host);
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+ return err;
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+}
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+
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+static esp_err_t spi_master_deinit_driver(void* arg)
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+{
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+ spi_host_t *host = (spi_host_t*)arg;
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+ SPI_CHECK(host != NULL, "host_id not in use", ESP_ERR_INVALID_STATE);
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+
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+ int host_id = host->id;
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+ SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG);
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+
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+ int x;
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+ for (x=0; x<DEV_NUM_MAX; x++) {
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+ SPI_CHECK(host->device[x] == NULL, "not all CSses freed", ESP_ERR_INVALID_STATE);
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+ }
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+
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+ spi_hal_deinit(&host->hal);
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+
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+ if (host->intr) {
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+ esp_intr_free(host->intr);
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+ }
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+ free(host);
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+ bus_driver_ctx[host_id] = NULL;
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+ return ESP_OK;
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+}
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+
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+void spi_get_timing(bool gpio_is_used, int input_delay_ns, int eff_clk, int* dummy_o, int* cycles_remain_o)
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+{
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+ int timing_dummy;
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+ int timing_miso_delay;
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+
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+ spi_hal_cal_timing(eff_clk, gpio_is_used, input_delay_ns, &timing_dummy, &timing_miso_delay);
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+ if (dummy_o) *dummy_o = timing_dummy;
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+ if (cycles_remain_o) *cycles_remain_o = timing_miso_delay;
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+}
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+
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+int spi_get_freq_limit(bool gpio_is_used, int input_delay_ns)
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+{
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+ return spi_hal_get_freq_limit(gpio_is_used, input_delay_ns);
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+}
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+
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+/*
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+ Add a device. This allocates a CS line for the device, allocates memory for the device structure and hooks
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+ up the CS pin to whatever is specified.
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+*/
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+esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interface_config_t *dev_config, spi_device_handle_t *handle)
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+{
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+ spi_device_t *dev = NULL;
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+ esp_err_t err = ESP_OK;
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+
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+ SPI_CHECK(is_valid_host(host_id), "invalid host", ESP_ERR_INVALID_ARG);
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+ if (bus_driver_ctx[host_id] == NULL) {
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+ //lazy initialization the driver, get deinitialized by the bus is freed
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+ err = spi_master_init_driver(host_id);
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+ if (err != ESP_OK) {
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+ return err;
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+ }
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+ }
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+
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+ spi_host_t *host = bus_driver_ctx[host_id];
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+ const spi_bus_attr_t* bus_attr = host->bus_attr;
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+ SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
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+ SPI_CHECK(dev_config->clock_speed_hz > 0, "invalid sclk speed", ESP_ERR_INVALID_ARG);
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+#ifdef CONFIG_IDF_TARGET_ESP32
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+ //The hardware looks like it would support this, but actually setting cs_ena_pretrans when transferring in full
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+ //duplex mode does absolutely nothing on the ESP32.
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+ SPI_CHECK(dev_config->cs_ena_pretrans <= 1 || (dev_config->address_bits == 0 && dev_config->command_bits == 0) ||
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+ (dev_config->flags & SPI_DEVICE_HALFDUPLEX), "In full-duplex mode, only support cs pretrans delay = 1 and without address_bits and command_bits", ESP_ERR_INVALID_ARG);
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+#endif
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+ uint32_t lock_flag = ((dev_config->spics_io_num != -1)? SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED: 0);
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+
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+ spi_bus_lock_dev_config_t lock_config = {
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+ .flags = lock_flag,
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+ };
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+ spi_bus_lock_dev_handle_t dev_handle;
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+ err = spi_bus_lock_register_dev(bus_attr->lock, &lock_config, &dev_handle);
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+ if (err != ESP_OK) {
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+ goto nomem;
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+ }
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+
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+ int freecs = spi_bus_lock_get_dev_id(dev_handle);
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+ SPI_CHECK(freecs != -1, "no free cs pins for the host", ESP_ERR_NOT_FOUND);
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+
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+ //input parameters to calculate timing configuration
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|
|
+ int half_duplex = dev_config->flags & SPI_DEVICE_HALFDUPLEX ? 1 : 0;
|
|
|
+ int no_compensate = dev_config->flags & SPI_DEVICE_NO_DUMMY ? 1 : 0;
|
|
|
+ int duty_cycle = (dev_config->duty_cycle_pos==0) ? 128 : dev_config->duty_cycle_pos;
|
|
|
+ int use_gpio = !(bus_attr->flags & SPICOMMON_BUSFLAG_IOMUX_PINS);
|
|
|
+ spi_hal_timing_param_t timing_param = {
|
|
|
+ .half_duplex = half_duplex,
|
|
|
+ .no_compensate = no_compensate,
|
|
|
+ .clock_speed_hz = dev_config->clock_speed_hz,
|
|
|
+ .duty_cycle = duty_cycle,
|
|
|
+ .input_delay_ns = dev_config->input_delay_ns,
|
|
|
+ .use_gpio = use_gpio
|
|
|
+ };
|
|
|
+
|
|
|
+ //output values of timing configuration
|
|
|
+ spi_hal_timing_conf_t temp_timing_conf;
|
|
|
+ int freq;
|
|
|
+ esp_err_t ret = spi_hal_cal_clock_conf(&timing_param, &freq, &temp_timing_conf);
|
|
|
+ SPI_CHECK(ret==ESP_OK, "assigned clock speed not supported", ret);
|
|
|
+
|
|
|
+ //Allocate memory for device
|
|
|
+ dev = malloc(sizeof(spi_device_t));
|
|
|
+ if (dev == NULL) goto nomem;
|
|
|
+ memset(dev, 0, sizeof(spi_device_t));
|
|
|
+
|
|
|
+ dev->id = freecs;
|
|
|
+ dev->dev_lock = dev_handle;
|
|
|
+
|
|
|
+ //Allocate queues, set defaults
|
|
|
+ dev->trans_queue = xQueueCreate(dev_config->queue_size, sizeof(spi_trans_priv_t));
|
|
|
+ dev->ret_queue = xQueueCreate(dev_config->queue_size, sizeof(spi_trans_priv_t));
|
|
|
+ if (!dev->trans_queue || !dev->ret_queue) {
|
|
|
+ goto nomem;
|
|
|
+ }
|
|
|
+
|
|
|
+ //We want to save a copy of the dev config in the dev struct.
|
|
|
+ memcpy(&dev->cfg, dev_config, sizeof(spi_device_interface_config_t));
|
|
|
+ dev->cfg.duty_cycle_pos = duty_cycle;
|
|
|
+ // TODO: if we have to change the apb clock among transactions, re-calculate this each time the apb clock lock is locked.
|
|
|
+
|
|
|
+ //Set CS pin, CS options
|
|
|
+ if (dev_config->spics_io_num >= 0) {
|
|
|
+ spicommon_cs_initialize(host_id, dev_config->spics_io_num, freecs, use_gpio);
|
|
|
+ }
|
|
|
+
|
|
|
+ // create a mutex if we have more than one client
|
|
|
+ if (host->count++) {
|
|
|
+ ESP_LOGI(SPI_TAG, "More than one device on SPI %d => creating mutex", host_id);
|
|
|
+ //host->mutex = xSemaphoreCreateMutex();
|
|
|
+ }
|
|
|
+
|
|
|
+ //save a pointer to device in spi_host_t
|
|
|
+ host->device[freecs] = dev;
|
|
|
+ //save a pointer to host in spi_device_t
|
|
|
+ dev->host= host;
|
|
|
+
|
|
|
+ //initialise the device specific configuration
|
|
|
+ spi_hal_dev_config_t *hal_dev = &(dev->hal_dev);
|
|
|
+ hal_dev->mode = dev_config->mode;
|
|
|
+ hal_dev->cs_setup = dev_config->cs_ena_pretrans;
|
|
|
+ hal_dev->cs_hold = dev_config->cs_ena_posttrans;
|
|
|
+ //set hold_time to 0 will not actually append delay to CS
|
|
|
+ //set it to 1 since we do need at least one clock of hold time in most cases
|
|
|
+ if (hal_dev->cs_hold == 0) {
|
|
|
+ hal_dev->cs_hold = 1;
|
|
|
+ }
|
|
|
+ hal_dev->cs_pin_id = dev->id;
|
|
|
+ hal_dev->timing_conf = temp_timing_conf;
|
|
|
+ hal_dev->sio = (dev_config->flags) & SPI_DEVICE_3WIRE ? 1 : 0;
|
|
|
+ hal_dev->half_duplex = dev_config->flags & SPI_DEVICE_HALFDUPLEX ? 1 : 0;
|
|
|
+ hal_dev->tx_lsbfirst = dev_config->flags & SPI_DEVICE_TXBIT_LSBFIRST ? 1 : 0;
|
|
|
+ hal_dev->rx_lsbfirst = dev_config->flags & SPI_DEVICE_RXBIT_LSBFIRST ? 1 : 0;
|
|
|
+ hal_dev->no_compensate = dev_config->flags & SPI_DEVICE_NO_DUMMY ? 1 : 0;
|
|
|
+#if SOC_SPI_SUPPORT_AS_CS
|
|
|
+ hal_dev->as_cs = dev_config->flags& SPI_DEVICE_CLK_AS_CS ? 1 : 0;
|
|
|
+#endif
|
|
|
+ hal_dev->positive_cs = dev_config->flags & SPI_DEVICE_POSITIVE_CS ? 1 : 0;
|
|
|
+
|
|
|
+ *handle = dev;
|
|
|
+ ESP_LOGD(SPI_TAG, "SPI%d: New device added to CS%d, effective clock: %dkHz", host_id+1, freecs, freq/1000);
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+
|
|
|
+nomem:
|
|
|
+ if (dev) {
|
|
|
+ if (dev->trans_queue) vQueueDelete(dev->trans_queue);
|
|
|
+ if (dev->ret_queue) vQueueDelete(dev->ret_queue);
|
|
|
+ spi_bus_lock_unregister_dev(dev->dev_lock);
|
|
|
+ }
|
|
|
+ free(dev);
|
|
|
+ return ESP_ERR_NO_MEM;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
|
|
|
+{
|
|
|
+ SPI_CHECK(handle!=NULL, "invalid handle", ESP_ERR_INVALID_ARG);
|
|
|
+ //These checks aren't exhaustive; another thread could sneak in a transaction inbetween. These are only here to
|
|
|
+ //catch design errors and aren't meant to be triggered during normal operation.
|
|
|
+ SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
|
+ SPI_CHECK(handle->host->cur_cs == DEV_NUM_MAX || handle->host->device[handle->host->cur_cs] != handle, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
|
+ SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
|
+
|
|
|
+ //return
|
|
|
+ int spics_io_num = handle->cfg.spics_io_num;
|
|
|
+ if (spics_io_num >= 0) spicommon_cs_free_io(spics_io_num);
|
|
|
+
|
|
|
+ //Kill queues
|
|
|
+ vQueueDelete(handle->trans_queue);
|
|
|
+ vQueueDelete(handle->ret_queue);
|
|
|
+ spi_bus_lock_unregister_dev(handle->dev_lock);
|
|
|
+
|
|
|
+ assert(handle->host->device[handle->id] == handle);
|
|
|
+ handle->host->device[handle->id] = NULL;
|
|
|
+ free(handle);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+int spi_cal_clock(int fapb, int hz, int duty_cycle, uint32_t *reg_o)
|
|
|
+{
|
|
|
+ return spi_ll_master_cal_clock(fapb, hz, duty_cycle, reg_o);
|
|
|
+}
|
|
|
+
|
|
|
+int spi_get_actual_clock(int fapb, int hz, int duty_cycle)
|
|
|
+{
|
|
|
+ return spi_hal_master_cal_clock(fapb, hz, duty_cycle);
|
|
|
+}
|
|
|
+
|
|
|
+// Setup the device-specified configuration registers. Called every time a new
|
|
|
+// transaction is to be sent, but only apply new configurations when the device
|
|
|
+// changes.
|
|
|
+static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev)
|
|
|
+{
|
|
|
+ spi_bus_lock_dev_handle_t dev_lock = dev->dev_lock;
|
|
|
+
|
|
|
+ if (!spi_bus_lock_touch(dev_lock)) {
|
|
|
+ //if the configuration is already applied, skip the following.
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ spi_hal_context_t *hal = &dev->host->hal;
|
|
|
+ spi_hal_dev_config_t *hal_dev = &(dev->hal_dev);
|
|
|
+ spi_hal_setup_device(hal, hal_dev);
|
|
|
+}
|
|
|
+
|
|
|
+static SPI_MASTER_ISR_ATTR spi_device_t *get_acquiring_dev(spi_host_t *host)
|
|
|
+{
|
|
|
+ spi_bus_lock_dev_handle_t dev_lock = spi_bus_lock_get_acquiring_dev(host->bus_attr->lock);
|
|
|
+if (!dev_lock) {
|
|
|
+ESP_LOGW(SPI_TAG, "NOBODY HERE");
|
|
|
+return NULL;
|
|
|
+}
|
|
|
+
|
|
|
+ return host->device[spi_bus_lock_get_dev_id(dev_lock)];
|
|
|
+}
|
|
|
+
|
|
|
+// Debug only
|
|
|
+// NOTE if the acquiring is not fully completed, `spi_bus_lock_get_acquiring_dev`
|
|
|
+// may return a false `NULL` cause the function returning false `false`.
|
|
|
+static inline SPI_MASTER_ISR_ATTR bool spi_bus_device_is_polling(spi_device_t *dev)
|
|
|
+{
|
|
|
+spi_device_t *toto = NULL;
|
|
|
+spi_bus_lock_dev_handle_t dev_lock = spi_bus_lock_get_acquiring_dev(dev->host->bus_attr->lock);
|
|
|
+if (dev_lock) toto = dev->host->device[spi_bus_lock_get_dev_id(dev_lock)];
|
|
|
+return toto == dev && dev->host->polling;
|
|
|
+
|
|
|
+ //return get_acquiring_dev(dev->host) == dev && dev->host->polling;
|
|
|
+}
|
|
|
+
|
|
|
+/*-----------------------------------------------------------------------------
|
|
|
+ Working Functions
|
|
|
+-----------------------------------------------------------------------------*/
|
|
|
+
|
|
|
+// The interrupt may get invoked by the bus lock.
|
|
|
+static void SPI_MASTER_ISR_ATTR spi_bus_intr_enable(void *host)
|
|
|
+{
|
|
|
+ esp_intr_enable(((spi_host_t*)host)->intr);
|
|
|
+}
|
|
|
+
|
|
|
+// The interrupt is always disabled by the ISR itself, not exposed
|
|
|
+static void SPI_MASTER_ISR_ATTR spi_bus_intr_disable(void *host)
|
|
|
+{
|
|
|
+ esp_intr_disable(((spi_host_t*)host)->intr);
|
|
|
+}
|
|
|
+
|
|
|
+// The function is called to send a new transaction, in ISR or in the task.
|
|
|
+// Setup the transaction-specified registers and linked-list used by the DMA (or FIFO if DMA is not used)
|
|
|
+static void SPI_MASTER_ISR_ATTR spi_new_trans(spi_device_t *dev, spi_trans_priv_t *trans_buf)
|
|
|
+{
|
|
|
+ spi_transaction_t *trans = NULL;
|
|
|
+ spi_host_t *host = dev->host;
|
|
|
+ spi_hal_context_t *hal = &(host->hal);
|
|
|
+ spi_hal_dev_config_t *hal_dev = &(dev->hal_dev);
|
|
|
+
|
|
|
+ trans = trans_buf->trans;
|
|
|
+ host->cur_cs = dev->id;
|
|
|
+
|
|
|
+ //Reconfigure according to device settings, the function only has effect when the dev_id is changed.
|
|
|
+ spi_setup_device(dev);
|
|
|
+
|
|
|
+ //set the transaction specific configuration each time before a transaction setup
|
|
|
+ spi_hal_trans_config_t hal_trans = {};
|
|
|
+ hal_trans.tx_bitlen = trans->length;
|
|
|
+ hal_trans.rx_bitlen = trans->rxlength;
|
|
|
+ hal_trans.rcv_buffer = (uint8_t*)host->cur_trans_buf.buffer_to_rcv;
|
|
|
+ hal_trans.send_buffer = (uint8_t*)host->cur_trans_buf.buffer_to_send;
|
|
|
+ hal_trans.cmd = trans->cmd;
|
|
|
+ hal_trans.addr = trans->addr;
|
|
|
+ //Set up QIO/DIO if needed
|
|
|
+ hal_trans.io_mode = (trans->flags & SPI_TRANS_MODE_DIO ?
|
|
|
+ (trans->flags & SPI_TRANS_MODE_DIOQIO_ADDR ? SPI_LL_IO_MODE_DIO : SPI_LL_IO_MODE_DUAL) :
|
|
|
+ (trans->flags & SPI_TRANS_MODE_QIO ?
|
|
|
+ (trans->flags & SPI_TRANS_MODE_DIOQIO_ADDR ? SPI_LL_IO_MODE_QIO : SPI_LL_IO_MODE_QUAD) :
|
|
|
+ SPI_LL_IO_MODE_NORMAL
|
|
|
+ ));
|
|
|
+
|
|
|
+ if (trans->flags & SPI_TRANS_VARIABLE_CMD) {
|
|
|
+ hal_trans.cmd_bits = ((spi_transaction_ext_t *)trans)->command_bits;
|
|
|
+ } else {
|
|
|
+ hal_trans.cmd_bits = dev->cfg.command_bits;
|
|
|
+ }
|
|
|
+ if (trans->flags & SPI_TRANS_VARIABLE_ADDR) {
|
|
|
+ hal_trans.addr_bits = ((spi_transaction_ext_t *)trans)->address_bits;
|
|
|
+ } else {
|
|
|
+ hal_trans.addr_bits = dev->cfg.address_bits;
|
|
|
+ }
|
|
|
+ if (trans->flags & SPI_TRANS_VARIABLE_DUMMY) {
|
|
|
+ hal_trans.dummy_bits = ((spi_transaction_ext_t *)trans)->dummy_bits;
|
|
|
+ } else {
|
|
|
+ hal_trans.dummy_bits = dev->cfg.dummy_bits;
|
|
|
+ }
|
|
|
+
|
|
|
+ spi_hal_setup_trans(hal, hal_dev, &hal_trans);
|
|
|
+ spi_hal_prepare_data(hal, hal_dev, &hal_trans);
|
|
|
+
|
|
|
+ //Call pre-transmission callback, if any
|
|
|
+ if (dev->cfg.pre_cb) dev->cfg.pre_cb(trans);
|
|
|
+ //Kick off transfer
|
|
|
+ spi_hal_user_start(hal);
|
|
|
+}
|
|
|
+
|
|
|
+// The function is called when a transaction is done, in ISR or in the task.
|
|
|
+// Fetch the data from FIFO and call the ``post_cb``.
|
|
|
+static void SPI_MASTER_ISR_ATTR spi_post_trans(spi_host_t *host)
|
|
|
+{
|
|
|
+ spi_transaction_t *cur_trans = host->cur_trans_buf.trans;
|
|
|
+
|
|
|
+ spi_hal_fetch_result(&host->hal);
|
|
|
+ //Call post-transaction callback, if any
|
|
|
+ spi_device_t* dev = host->device[host->cur_cs];
|
|
|
+ if (dev->cfg.post_cb) dev->cfg.post_cb(cur_trans);
|
|
|
+
|
|
|
+ host->cur_cs = DEV_NUM_MAX;
|
|
|
+}
|
|
|
+
|
|
|
+// This is run in interrupt context.
|
|
|
+static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
|
|
|
+{
|
|
|
+ BaseType_t do_yield = pdFALSE;
|
|
|
+ spi_host_t *host = (spi_host_t *)arg;
|
|
|
+ const spi_bus_attr_t* bus_attr = host->bus_attr;
|
|
|
+
|
|
|
+ assert(spi_hal_usr_is_done(&host->hal));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Help to skip the handling of in-flight transaction, and disable of the interrupt.
|
|
|
+ * The esp_intr_enable will be called (b) after new BG request is queued (a) in the task;
|
|
|
+ * while esp_intr_disable should be called (c) if we check and found the sending queue is empty (d).
|
|
|
+ * If (c) is called after (d), then there is a risk that things happens in this sequence:
|
|
|
+ * (d) -> (a) -> (b) -> (c), and in this case the interrupt is disabled while there's pending BG request in the queue.
|
|
|
+ * To avoid this, interrupt is disabled here, and re-enabled later if required.
|
|
|
+ */
|
|
|
+ if (!spi_bus_lock_bg_entry(bus_attr->lock)) {
|
|
|
+ /*------------ deal with the in-flight transaction -----------------*/
|
|
|
+ assert(host->cur_cs != DEV_NUM_MAX);
|
|
|
+ //Okay, transaction is done.
|
|
|
+ const int cs = host->cur_cs;
|
|
|
+ //Tell common code DMA workaround that our DMA channel is idle. If needed, the code will do a DMA reset.
|
|
|
+ if (bus_attr->dma_enabled) {
|
|
|
+ //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same
|
|
|
+ spicommon_dmaworkaround_idle(bus_attr->tx_dma_chan);
|
|
|
+ }
|
|
|
+
|
|
|
+ //cur_cs is changed to DEV_NUM_MAX here
|
|
|
+ spi_post_trans(host);
|
|
|
+ // spi_bus_lock_bg_pause(bus_attr->lock);
|
|
|
+ //Return transaction descriptor.
|
|
|
+ xQueueSendFromISR(host->device[cs]->ret_queue, &host->cur_trans_buf, &do_yield);
|
|
|
+#ifdef CONFIG_PM_ENABLE
|
|
|
+ //Release APB frequency lock
|
|
|
+ esp_pm_lock_release(bus_attr->pm_lock);
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ /*------------ new transaction starts here ------------------*/
|
|
|
+ assert(host->cur_cs == DEV_NUM_MAX);
|
|
|
+
|
|
|
+ spi_bus_lock_handle_t lock = host->bus_attr->lock;
|
|
|
+ BaseType_t trans_found = pdFALSE;
|
|
|
+
|
|
|
+
|
|
|
+ // There should be remaining requests
|
|
|
+ BUS_LOCK_DEBUG_EXECUTE_CHECK(spi_bus_lock_bg_req_exist(lock));
|
|
|
+
|
|
|
+ do {
|
|
|
+ spi_bus_lock_dev_handle_t acq_dev_lock = spi_bus_lock_get_acquiring_dev(lock);
|
|
|
+ spi_bus_lock_dev_handle_t desired_dev = acq_dev_lock;
|
|
|
+ bool resume_task = false;
|
|
|
+ spi_device_t* device_to_send = NULL;
|
|
|
+
|
|
|
+ if (!acq_dev_lock) {
|
|
|
+ // This function may assign a new acquiring device, otherwise it will suggest a desired device with BG active
|
|
|
+ // We use either of them without further searching in the devices.
|
|
|
+ // If the return value is true, it means either there's no acquiring device, or the acquiring device's BG is active,
|
|
|
+ // We stay in the ISR to deal with those transactions of desired device, otherwise nothing will be done, check whether we need to resume some other tasks, or just quit the ISR
|
|
|
+ resume_task = spi_bus_lock_bg_check_dev_acq(lock, &desired_dev);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!resume_task) {
|
|
|
+ bool dev_has_req = spi_bus_lock_bg_check_dev_req(desired_dev);
|
|
|
+ if (dev_has_req) {
|
|
|
+ device_to_send = host->device[spi_bus_lock_get_dev_id(desired_dev)];
|
|
|
+ trans_found = xQueueReceiveFromISR(device_to_send->trans_queue, &host->cur_trans_buf, &do_yield);
|
|
|
+ if (!trans_found) {
|
|
|
+ spi_bus_lock_bg_clear_req(desired_dev);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (trans_found) {
|
|
|
+ spi_trans_priv_t *const cur_trans_buf = &host->cur_trans_buf;
|
|
|
+ if (bus_attr->dma_enabled && (cur_trans_buf->buffer_to_rcv || cur_trans_buf->buffer_to_send)) {
|
|
|
+ //mark channel as active, so that the DMA will not be reset by the slave
|
|
|
+ //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same
|
|
|
+ spicommon_dmaworkaround_transfer_active(bus_attr->tx_dma_chan);
|
|
|
+ }
|
|
|
+ spi_new_trans(device_to_send, cur_trans_buf);
|
|
|
+ }
|
|
|
+ // Exit of the ISR, handle interrupt re-enable (if sending transaction), retry (if there's coming BG),
|
|
|
+ // or resume acquiring device task (if quit due to bus acquiring).
|
|
|
+ } while (!spi_bus_lock_bg_exit(lock, trans_found, &do_yield));
|
|
|
+
|
|
|
+ if (do_yield) portYIELD_FROM_ISR();
|
|
|
+}
|
|
|
+
|
|
|
+static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handle, spi_transaction_t *trans_desc)
|
|
|
+{
|
|
|
+ SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG);
|
|
|
+ spi_host_t *host = handle->host;
|
|
|
+ const spi_bus_attr_t* bus_attr = host->bus_attr;
|
|
|
+ bool tx_enabled = (trans_desc->flags & SPI_TRANS_USE_TXDATA) || (trans_desc->tx_buffer);
|
|
|
+ bool rx_enabled = (trans_desc->flags & SPI_TRANS_USE_RXDATA) || (trans_desc->rx_buffer);
|
|
|
+ spi_transaction_ext_t *t_ext = (spi_transaction_ext_t *)trans_desc;
|
|
|
+ bool dummy_enabled = (((trans_desc->flags & SPI_TRANS_VARIABLE_DUMMY)? t_ext->dummy_bits: handle->cfg.dummy_bits) != 0);
|
|
|
+ bool extra_dummy_enabled = handle->hal_dev.timing_conf.timing_dummy;
|
|
|
+ bool is_half_duplex = ((handle->cfg.flags & SPI_DEVICE_HALFDUPLEX) != 0);
|
|
|
+
|
|
|
+ //check transmission length
|
|
|
+ SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_RXDATA)==0 || trans_desc->rxlength <= 32, "SPI_TRANS_USE_RXDATA only available for rxdata transfer <= 32 bits", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_TXDATA)==0 || trans_desc->length <= 32, "SPI_TRANS_USE_TXDATA only available for txdata transfer <= 32 bits", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK(trans_desc->length <= bus_attr->max_transfer_sz*8, "txdata transfer > host maximum", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK(trans_desc->rxlength <= bus_attr->max_transfer_sz*8, "rxdata transfer > host maximum", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK(is_half_duplex || trans_desc->rxlength <= trans_desc->length, "rx length > tx length in full duplex mode", ESP_ERR_INVALID_ARG);
|
|
|
+ //check working mode
|
|
|
+ SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "incompatible iface params", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && !is_half_duplex), "incompatible iface params", ESP_ERR_INVALID_ARG);
|
|
|
+#ifdef CONFIG_IDF_TARGET_ESP32
|
|
|
+ SPI_CHECK(!is_half_duplex || !bus_attr->dma_enabled || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG );
|
|
|
+#elif CONFIG_IDF_TARGET_ESP32S3
|
|
|
+ SPI_CHECK(!is_half_duplex || !tx_enabled || !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG);
|
|
|
+#endif
|
|
|
+ //MOSI phase is skipped only when both tx_buffer and SPI_TRANS_USE_TXDATA are not set.
|
|
|
+ SPI_CHECK(trans_desc->length != 0 || !tx_enabled, "trans tx_buffer should be NULL and SPI_TRANS_USE_TXDATA should be cleared to skip MOSI phase.", ESP_ERR_INVALID_ARG);
|
|
|
+ //MISO phase is skipped only when both rx_buffer and SPI_TRANS_USE_RXDATA are not set.
|
|
|
+ //If set rxlength=0 in full_duplex mode, it will be automatically set to length
|
|
|
+ SPI_CHECK(!is_half_duplex || trans_desc->rxlength != 0 || !rx_enabled, "trans rx_buffer should be NULL and SPI_TRANS_USE_RXDATA should be cleared to skip MISO phase.", ESP_ERR_INVALID_ARG);
|
|
|
+ //In Full duplex mode, default rxlength to be the same as length, if not filled in.
|
|
|
+ // set rxlength to length is ok, even when rx buffer=NULL
|
|
|
+ if (trans_desc->rxlength==0 && !is_half_duplex) {
|
|
|
+ trans_desc->rxlength=trans_desc->length;
|
|
|
+ }
|
|
|
+ //Dummy phase is not available when both data out and in are enabled, regardless of FD or HD mode.
|
|
|
+ SPI_CHECK(!tx_enabled || !rx_enabled || !dummy_enabled || !extra_dummy_enabled, "Dummy phase is not available when both data out and in are enabled", ESP_ERR_INVALID_ARG);
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+static SPI_MASTER_ISR_ATTR void uninstall_priv_desc(spi_trans_priv_t* trans_buf)
|
|
|
+{
|
|
|
+ spi_transaction_t *trans_desc = trans_buf->trans;
|
|
|
+ if ((void *)trans_buf->buffer_to_send != &trans_desc->tx_data[0] &&
|
|
|
+ trans_buf->buffer_to_send != trans_desc->tx_buffer) {
|
|
|
+ free((void *)trans_buf->buffer_to_send); //force free, ignore const
|
|
|
+ }
|
|
|
+ // copy data from temporary DMA-capable buffer back to IRAM buffer and free the temporary one.
|
|
|
+ if ((void *)trans_buf->buffer_to_rcv != &trans_desc->rx_data[0] &&
|
|
|
+ trans_buf->buffer_to_rcv != trans_desc->rx_buffer) { // NOLINT(clang-analyzer-unix.Malloc)
|
|
|
+ if (trans_desc->flags & SPI_TRANS_USE_RXDATA) {
|
|
|
+ memcpy((uint8_t *) & trans_desc->rx_data[0], trans_buf->buffer_to_rcv, (trans_desc->rxlength + 7) / 8);
|
|
|
+ } else {
|
|
|
+ memcpy(trans_desc->rx_buffer, trans_buf->buffer_to_rcv, (trans_desc->rxlength + 7) / 8);
|
|
|
+ }
|
|
|
+ free(trans_buf->buffer_to_rcv);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_transaction_t *trans_desc, spi_trans_priv_t* new_desc, bool isdma)
|
|
|
+{
|
|
|
+ *new_desc = (spi_trans_priv_t) { .trans = trans_desc, };
|
|
|
+
|
|
|
+ // rx memory assign
|
|
|
+ uint32_t* rcv_ptr;
|
|
|
+ if ( trans_desc->flags & SPI_TRANS_USE_RXDATA ) {
|
|
|
+ rcv_ptr = (uint32_t *)&trans_desc->rx_data[0];
|
|
|
+ } else {
|
|
|
+ //if not use RXDATA neither rx_buffer, buffer_to_rcv assigned to NULL
|
|
|
+ rcv_ptr = trans_desc->rx_buffer;
|
|
|
+ }
|
|
|
+ if (rcv_ptr && isdma && (!esp_ptr_dma_capable(rcv_ptr) || ((int)rcv_ptr % 4 != 0))) {
|
|
|
+ //if rxbuf in the desc not DMA-capable, malloc a new one. The rx buffer need to be length of multiples of 32 bits to avoid heap corruption.
|
|
|
+ ESP_LOGD(SPI_TAG, "Allocate RX buffer for DMA" );
|
|
|
+ rcv_ptr = heap_caps_malloc((trans_desc->rxlength + 31) / 8, MALLOC_CAP_DMA);
|
|
|
+ if (rcv_ptr == NULL) goto clean_up;
|
|
|
+ }
|
|
|
+ new_desc->buffer_to_rcv = rcv_ptr;
|
|
|
+
|
|
|
+ // tx memory assign
|
|
|
+ const uint32_t *send_ptr;
|
|
|
+ if ( trans_desc->flags & SPI_TRANS_USE_TXDATA ) {
|
|
|
+ send_ptr = (uint32_t *)&trans_desc->tx_data[0];
|
|
|
+ } else {
|
|
|
+ //if not use TXDATA neither tx_buffer, tx data assigned to NULL
|
|
|
+ send_ptr = trans_desc->tx_buffer ;
|
|
|
+ }
|
|
|
+ if (send_ptr && isdma && !esp_ptr_dma_capable( send_ptr )) {
|
|
|
+ //if txbuf in the desc not DMA-capable, malloc a new one
|
|
|
+ ESP_LOGD(SPI_TAG, "Allocate TX buffer for DMA" );
|
|
|
+ uint32_t *temp = heap_caps_malloc((trans_desc->length + 7) / 8, MALLOC_CAP_DMA);
|
|
|
+ if (temp == NULL) goto clean_up;
|
|
|
+
|
|
|
+ memcpy( temp, send_ptr, (trans_desc->length + 7) / 8 );
|
|
|
+ send_ptr = temp;
|
|
|
+ }
|
|
|
+ new_desc->buffer_to_send = send_ptr;
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+
|
|
|
+clean_up:
|
|
|
+ uninstall_priv_desc(new_desc);
|
|
|
+ return ESP_ERR_NO_MEM;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
|
|
+{
|
|
|
+ esp_err_t ret = check_trans_valid(handle, trans_desc);
|
|
|
+ if (ret != ESP_OK) return ret;
|
|
|
+
|
|
|
+ spi_host_t *host = handle->host;
|
|
|
+
|
|
|
+ SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE );
|
|
|
+
|
|
|
+ spi_trans_priv_t trans_buf;
|
|
|
+ ret = setup_priv_desc(trans_desc, &trans_buf, (host->bus_attr->dma_enabled));
|
|
|
+ if (ret != ESP_OK) return ret;
|
|
|
+
|
|
|
+#ifdef CONFIG_PM_ENABLE
|
|
|
+ esp_pm_lock_acquire(host->bus_attr->pm_lock);
|
|
|
+#endif
|
|
|
+ //Send to queue and invoke the ISR.
|
|
|
+
|
|
|
+ BaseType_t r = xQueueSend(handle->trans_queue, (void *)&trans_buf, ticks_to_wait);
|
|
|
+ if (!r) {
|
|
|
+ ret = ESP_ERR_TIMEOUT;
|
|
|
+#ifdef CONFIG_PM_ENABLE
|
|
|
+ //Release APB frequency lock
|
|
|
+ esp_pm_lock_release(host->bus_attr->pm_lock);
|
|
|
+#endif
|
|
|
+ goto clean_up;
|
|
|
+ }
|
|
|
+
|
|
|
+ // The ISR will be invoked at correct time by the lock with `spi_bus_intr_enable`.
|
|
|
+ ret = spi_bus_lock_bg_request(handle->dev_lock);
|
|
|
+ if (ret != ESP_OK) {
|
|
|
+ goto clean_up;
|
|
|
+ }
|
|
|
+ return ESP_OK;
|
|
|
+
|
|
|
+clean_up:
|
|
|
+ uninstall_priv_desc(&trans_buf);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ATTR spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait)
|
|
|
+{
|
|
|
+ BaseType_t r;
|
|
|
+ spi_trans_priv_t trans_buf;
|
|
|
+ SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG);
|
|
|
+
|
|
|
+ //use the interrupt, block until return
|
|
|
+ r=xQueueReceive(handle->ret_queue, (void*)&trans_buf, ticks_to_wait);
|
|
|
+ if (!r) {
|
|
|
+ // The memory occupied by rx and tx DMA buffer destroyed only when receiving from the queue (transaction finished).
|
|
|
+ // If timeout, wait and retry.
|
|
|
+ // Every in-flight transaction request occupies internal memory as DMA buffer if needed.
|
|
|
+ return ESP_ERR_TIMEOUT;
|
|
|
+ }
|
|
|
+ //release temporary buffers
|
|
|
+ uninstall_priv_desc(&trans_buf);
|
|
|
+ (*trans_desc) = trans_buf.trans;
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+//Porcelain to do one blocking transmission.
|
|
|
+esp_err_t SPI_MASTER_ATTR spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc)
|
|
|
+{
|
|
|
+ esp_err_t ret;
|
|
|
+ spi_transaction_t *ret_trans;
|
|
|
+ //ToDo: check if any spi transfers in flight
|
|
|
+ ret = spi_device_queue_trans(handle, trans_desc, portMAX_DELAY);
|
|
|
+ if (ret != ESP_OK) return ret;
|
|
|
+
|
|
|
+ ret = spi_device_get_trans_result(handle, &ret_trans, portMAX_DELAY);
|
|
|
+ if (ret != ESP_OK) return ret;
|
|
|
+
|
|
|
+ assert(ret_trans == trans_desc);
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ISR_ATTR spi_device_acquire_bus(spi_device_t *device, TickType_t wait)
|
|
|
+{
|
|
|
+ spi_host_t *const host = device->host;
|
|
|
+ SPI_CHECK(wait==portMAX_DELAY, "acquire finite time not supported now.", ESP_ERR_INVALID_ARG);
|
|
|
+ SPI_CHECK(!spi_bus_device_is_polling(device), "Cannot acquire bus when a polling transaction is in progress.", ESP_ERR_INVALID_STATE );
|
|
|
+
|
|
|
+ esp_err_t ret = spi_bus_lock_acquire_start(device->dev_lock, wait);
|
|
|
+ if (ret != ESP_OK) {
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ host->device_acquiring_lock = device;
|
|
|
+
|
|
|
+ ESP_LOGD(SPI_TAG, "device%d locked the bus", device->id);
|
|
|
+
|
|
|
+#ifdef CONFIG_PM_ENABLE
|
|
|
+ // though we don't suggest to block the task before ``release_bus``, still allow doing so.
|
|
|
+ // this keeps the spi clock at 80MHz even if all tasks are blocked
|
|
|
+ esp_pm_lock_acquire(host->bus_attr->pm_lock);
|
|
|
+#endif
|
|
|
+ //configure the device ahead so that we don't need to do it again in the following transactions
|
|
|
+ spi_setup_device(host->device[device->id]);
|
|
|
+ //the DMA is also occupied by the device, all the slave devices that using DMA should wait until bus released.
|
|
|
+ if (host->bus_attr->dma_enabled) {
|
|
|
+ //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same
|
|
|
+ spicommon_dmaworkaround_transfer_active(host->bus_attr->tx_dma_chan);
|
|
|
+ }
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+// This function restore configurations required in the non-polling mode
|
|
|
+void SPI_MASTER_ISR_ATTR spi_device_release_bus(spi_device_t *dev)
|
|
|
+{
|
|
|
+ spi_host_t *host = dev->host;
|
|
|
+
|
|
|
+ if (spi_bus_device_is_polling(dev)){
|
|
|
+ ESP_EARLY_LOGE(SPI_TAG, "Cannot release bus when a polling transaction is in progress.");
|
|
|
+ assert(0);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (host->bus_attr->dma_enabled) {
|
|
|
+ //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same
|
|
|
+ spicommon_dmaworkaround_idle(host->bus_attr->tx_dma_chan);
|
|
|
+ }
|
|
|
+ //Tell common code DMA workaround that our DMA channel is idle. If needed, the code will do a DMA reset.
|
|
|
+
|
|
|
+ //allow clock to be lower than 80MHz when all tasks blocked
|
|
|
+#ifdef CONFIG_PM_ENABLE
|
|
|
+ //Release APB frequency lock
|
|
|
+ esp_pm_lock_release(host->bus_attr->pm_lock);
|
|
|
+#endif
|
|
|
+ ESP_LOGD(SPI_TAG, "device%d release bus", dev->id);
|
|
|
+
|
|
|
+ host->device_acquiring_lock = NULL;
|
|
|
+ esp_err_t ret = spi_bus_lock_acquire_end(dev->dev_lock);
|
|
|
+ assert(ret == ESP_OK);
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_start(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
|
|
+{
|
|
|
+ esp_err_t ret;
|
|
|
+ SPI_CHECK(ticks_to_wait == portMAX_DELAY, "currently timeout is not available for polling transactions", ESP_ERR_INVALID_ARG);
|
|
|
+ ret = check_trans_valid(handle, trans_desc);
|
|
|
+ if (ret!=ESP_OK) return ret;
|
|
|
+ SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot send polling transaction while the previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE );
|
|
|
+
|
|
|
+ /* If device_acquiring_lock is set to handle, it means that the user has already
|
|
|
+ * acquired the bus thanks to the function `spi_device_acquire_bus()`.
|
|
|
+ * In that case, we don't need to take the lock again. */
|
|
|
+ spi_host_t *host = handle->host;
|
|
|
+try_again:
|
|
|
+ if (host->device_acquiring_lock != handle) {
|
|
|
+ ret = spi_bus_lock_acquire_start(handle->dev_lock, ticks_to_wait);
|
|
|
+ } else {
|
|
|
+ESP_LOGW(SPI_TAG, "ALREADYA CQUIRED %d", handle->id);
|
|
|
+ ret = spi_bus_lock_wait_bg_done(handle->dev_lock, ticks_to_wait);
|
|
|
+ }
|
|
|
+ if (ret != ESP_OK) return ret;
|
|
|
+
|
|
|
+if (handle != get_acquiring_dev(host)) {
|
|
|
+ESP_LOGW(SPI_TAG, "WE THOUGHT WE ACQUIRED THE BUS %d %p", handle->id, host);
|
|
|
+goto try_again;
|
|
|
+}
|
|
|
+
|
|
|
+ ret = setup_priv_desc(trans_desc, &host->cur_trans_buf, (host->bus_attr->dma_enabled));
|
|
|
+ if (ret!=ESP_OK) return ret;
|
|
|
+
|
|
|
+ //Polling, no interrupt is used.
|
|
|
+ host->polling = true;
|
|
|
+
|
|
|
+ ESP_LOGV(SPI_TAG, "polling trans");
|
|
|
+ spi_new_trans(handle, &host->cur_trans_buf);
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_end(spi_device_handle_t handle, TickType_t ticks_to_wait)
|
|
|
+{
|
|
|
+ SPI_CHECK(handle != NULL, "invalid dev handle", ESP_ERR_INVALID_ARG);
|
|
|
+ spi_host_t *host = handle->host;
|
|
|
+
|
|
|
+ assert(host->cur_cs == handle->id);
|
|
|
+if (handle != get_acquiring_dev(host)) {
|
|
|
+spi_device_handle_t toto = get_acquiring_dev(host);
|
|
|
+ESP_LOGW(SPI_TAG, "SPIDEVICEHANDLE id %d (%d) , host %p (%p)", handle->id, toto ? toto->id : -1, handle->host, toto ? toto->host : NULL);
|
|
|
+}
|
|
|
+ assert(handle == get_acquiring_dev(host));
|
|
|
+
|
|
|
+ TickType_t start = xTaskGetTickCount();
|
|
|
+ while (!spi_hal_usr_is_done(&host->hal)) {
|
|
|
+ TickType_t end = xTaskGetTickCount();
|
|
|
+ if (end - start > ticks_to_wait) {
|
|
|
+ return ESP_ERR_TIMEOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ESP_LOGV(SPI_TAG, "polling trans done");
|
|
|
+ //deal with the in-flight transaction
|
|
|
+ spi_post_trans(host);
|
|
|
+ //release temporary buffers
|
|
|
+ uninstall_priv_desc(&host->cur_trans_buf);
|
|
|
+
|
|
|
+ host->polling = false;
|
|
|
+ if (host->device_acquiring_lock != handle) {
|
|
|
+ assert(host->device_acquiring_lock == NULL);
|
|
|
+ spi_bus_lock_acquire_end(handle->dev_lock);
|
|
|
+ }
|
|
|
+
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
+esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_transmit(spi_device_handle_t handle, spi_transaction_t* trans_desc)
|
|
|
+{
|
|
|
+ esp_err_t ret;
|
|
|
+static struct {
|
|
|
+int count;
|
|
|
+SemaphoreHandle_t mutex;
|
|
|
+} ctx[4];
|
|
|
+int id = handle->id;
|
|
|
+ctx[id].count++;
|
|
|
+//if (!ctx[id].mutex) ctx[id].mutex = xSemaphoreCreateMutex();
|
|
|
+//xSemaphoreTake(ctx[id].mutex, portMAX_DELAY);
|
|
|
+if (handle->host->mutex) xSemaphoreTake(handle->host->mutex, portMAX_DELAY);
|
|
|
+if (ctx[id].count > 1) {
|
|
|
+ESP_LOGW(SPI_TAG, "COUNTER of %d is %d %p", id, ctx[id].count, handle->host);
|
|
|
+}
|
|
|
+
|
|
|
+ ret = spi_device_polling_start(handle, trans_desc, portMAX_DELAY);
|
|
|
+if (ctx[id].count > 1) {
|
|
|
+ESP_LOGW(SPI_TAG, "COUNTER of %d REALLY %d %p", id, ctx[id].count, handle->host);
|
|
|
+}
|
|
|
+ //if (ret != ESP_OK) return ret;
|
|
|
+if (ret != ESP_OK) {
|
|
|
+ctx[id].count--;
|
|
|
+ESP_LOGE(SPI_TAG, "CAN'T START SPI POLLING %d", id);
|
|
|
+// xSemaphoreGive(ctx[id].mutex);
|
|
|
+if (handle->host->mutex) xSemaphoreGive(handle->host->mutex);
|
|
|
+return ret;
|
|
|
+}
|
|
|
+
|
|
|
+ret = spi_device_polling_end(handle, portMAX_DELAY);
|
|
|
+ctx[id].count--;
|
|
|
+//xSemaphoreGive(ctx[id].mutex);
|
|
|
+if (handle->host->mutex) xSemaphoreGive(handle->host->mutex);
|
|
|
+return ret;
|
|
|
+// return spi_device_polling_end(handle, portMAX_DELAY);
|
|
|
+}
|
philippe44