|  | @@ -27,7 +27,9 @@
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				|  |  |  #include "soc/efuse_periph.h"
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				|  |  |  #include "driver/gpio.h"
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				|  |  |  #include "driver/spi_common_internal.h"
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				|  |  | +#if CONFIG_IDF_TARGET_ESP32   
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				|  |  |  #include "esp32/rom/efuse.h"
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				|  |  | +#endif
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				|  |  |  #include "tools.h"
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				|  |  |  #include "monitor.h"
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				|  |  |  #include "messaging.h"
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				|  | @@ -1088,6 +1090,9 @@ gpio_entry_t * get_gpio_by_name(char * name,char * group, bool refresh){
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				|  |  |  
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				|  |  |  
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				|  |  |  cJSON * get_psram_gpio_list(cJSON * list){
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				|  |  | +	cJSON * llist=list;
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				|  |  | +	
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				|  |  | +#if CONFIG_IDF_TARGET_ESP32    
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				|  |  |  	const char * psram_dev = "psram";
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				|  |  |  	const char * flash_dev = "flash";
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				|  |  |  	const char * clk = "clk";
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				|  | @@ -1096,7 +1101,6 @@ cJSON * get_psram_gpio_list(cJSON * list){
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				|  |  |  	const char * spid_sd1_io = "spid_sd1_io";
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				|  |  |  	const char * spiwp_sd3_io = "spiwp_sd3_io";
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				|  |  |  	const char * spihd_sd2_io = "spihd_sd2_io";
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				|  |  | -	cJSON * llist=list;
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				|  |  |  	
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				|  |  |      uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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				|  |  |      uint32_t pkg_ver = chip_ver & 0x7;
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				|  | @@ -1156,6 +1160,9 @@ cJSON * get_psram_gpio_list(cJSON * list){
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				|  |  |  		cJSON_AddItemToArray(list,get_gpio_entry(clk,flash_dev,EFUSE_SPICONFIG_RET_SPICLK(spiconfig),true));
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				|  |  |  		cJSON_AddItemToArray(list,get_gpio_entry(cs,flash_dev,EFUSE_SPICONFIG_RET_SPICS0(spiconfig),true));
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				|  |  |  	}
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				|  |  | +#else
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				|  |  | +#pragma message("need to add esp32-s3 specific SPIRAM GPIO config code")
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				|  |  | +#endif    
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				|  |  |      return llist;	
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				|  |  |  }
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