ac101.h 4.7 KB

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  1. /*
  2. * ESPRESSIF MIT License
  3. *
  4. * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
  5. *
  6. * Permission is hereby granted for use on all ESPRESSIF SYSTEMS products, in which case,
  7. * it is free of charge, to any person obtaining a copy of this software and associated
  8. * documentation files (the "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
  11. * to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in all copies or
  14. * substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  18. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  19. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  20. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. */
  24. #ifndef __AC101_H__
  25. #define __AC101_H__
  26. #include "esp_types.h"
  27. #define AC101_ADDR 0x1a /*!< Device address*/
  28. #define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
  29. #define READ_BIT I2C_MASTER_READ /*!< I2C master read */
  30. #define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
  31. #define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
  32. #define ACK_VAL 0x0 /*!< I2C ack value */
  33. #define NACK_VAL 0x1 /*!< I2C nack value */
  34. #define CHIP_AUDIO_RS 0x00
  35. #define PLL_CTRL1 0x01
  36. #define PLL_CTRL2 0x02
  37. #define SYSCLK_CTRL 0x03
  38. #define MOD_CLK_ENA 0x04
  39. #define MOD_RST_CTRL 0x05
  40. #define I2S_SR_CTRL 0x06
  41. #define I2S1LCK_CTRL 0x10
  42. #define I2S1_SDOUT_CTRL 0x11
  43. #define I2S1_SDIN_CTRL 0x12
  44. #define I2S1_MXR_SRC 0x13
  45. #define I2S1_VOL_CTRL1 0x14
  46. #define I2S1_VOL_CTRL2 0x15
  47. #define I2S1_VOL_CTRL3 0x16
  48. #define I2S1_VOL_CTRL4 0x17
  49. #define I2S1_MXR_GAIN 0x18
  50. #define ADC_DIG_CTRL 0x40
  51. #define ADC_VOL_CTRL 0x41
  52. #define HMIC_CTRL1 0x44
  53. #define HMIC_CTRL2 0x45
  54. #define HMIC_STATUS 0x46
  55. #define DAC_DIG_CTRL 0x48
  56. #define DAC_VOL_CTRL 0x49
  57. #define DAC_MXR_SRC 0x4c
  58. #define DAC_MXR_GAIN 0x4d
  59. #define ADC_ANA_CTRL 0x50
  60. #define ADC_SRC 0x51
  61. #define ADC_SRCBST_CTRL 0x52
  62. #define OMIXER_DACA_CTRL 0x53
  63. #define OMIXER_SR 0x54
  64. #define OMIXER_BST1_CTRL 0x55
  65. #define HPOUT_CTRL 0x56
  66. #define SPKOUT_CTRL 0x58
  67. #define AC_DAC_DAPCTRL 0xa0
  68. #define AC_DAC_DAPHHPFC 0xa1
  69. #define AC_DAC_DAPLHPFC 0xa2
  70. #define AC_DAC_DAPLHAVC 0xa3
  71. #define AC_DAC_DAPLLAVC 0xa4
  72. #define AC_DAC_DAPRHAVC 0xa5
  73. #define AC_DAC_DAPRLAVC 0xa6
  74. #define AC_DAC_DAPHGDEC 0xa7
  75. #define AC_DAC_DAPLGDEC 0xa8
  76. #define AC_DAC_DAPHGATC 0xa9
  77. #define AC_DAC_DAPLGATC 0xaa
  78. #define AC_DAC_DAPHETHD 0xab
  79. #define AC_DAC_DAPLETHD 0xac
  80. #define AC_DAC_DAPHGKPA 0xad
  81. #define AC_DAC_DAPLGKPA 0xae
  82. #define AC_DAC_DAPHGOPA 0xaf
  83. #define AC_DAC_DAPLGOPA 0xb0
  84. #define AC_DAC_DAPOPT 0xb1
  85. #define DAC_DAP_ENA 0xb5
  86. typedef enum {
  87. SAMPLE_RATE_8000 = 0x0000,
  88. SAMPLE_RATE_11052 = 0x1000,
  89. SAMPLE_RATE_12000 = 0x2000,
  90. SAMPLE_RATE_16000 = 0x3000,
  91. SAMPLE_RATE_22050 = 0x4000,
  92. SAMPLE_RATE_24000 = 0x5000,
  93. SAMPLE_RATE_32000 = 0x6000,
  94. SAMPLE_RATE_44100 = 0x7000,
  95. SAMPLE_RATE_48000 = 0x8000,
  96. SAMPLE_RATE_96000 = 0x9000,
  97. SAMPLE_RATE_192000 = 0xa000,
  98. } ac_adda_fs_i2s1_t;
  99. typedef enum {
  100. BCLK_DIV_1 = 0x0,
  101. BCLK_DIV_2 = 0x1,
  102. BCLK_DIV_4 = 0x2,
  103. BCLK_DIV_6 = 0x3,
  104. BCLK_DIV_8 = 0x4,
  105. BCLK_DIV_12 = 0x5,
  106. BCLK_DIV_16 = 0x6,
  107. BCLK_DIV_24 = 0x7,
  108. BCLK_DIV_32 = 0x8,
  109. BCLK_DIV_48 = 0x9,
  110. BCLK_DIV_64 = 0xa,
  111. BCLK_DIV_96 = 0xb,
  112. BCLK_DIV_128 = 0xc,
  113. BCLK_DIV_192 = 0xd,
  114. } ac_i2s1_bclk_div_t;
  115. typedef enum {
  116. LRCK_DIV_16 = 0x0,
  117. LRCK_DIV_32 = 0x1,
  118. LRCK_DIV_64 = 0x2,
  119. LRCK_DIV_128 = 0x3,
  120. LRCK_DIV_256 = 0x4,
  121. } ac_i2s1_lrck_div_t;
  122. typedef enum {
  123. BIT_LENGTH_8_BITS = 0x00,
  124. BIT_LENGTH_16_BITS = 0x01,
  125. BIT_LENGTH_20_BITS = 0x02,
  126. BIT_LENGTH_24_BITS = 0x03,
  127. } ac_bits_length_t;
  128. typedef enum {
  129. AC_MODE_MIN = -1,
  130. AC_MODE_SLAVE = 0x00,
  131. AC_MODE_MASTER = 0x01,
  132. AC_MODE_MAX,
  133. } ac_mode_sm_t;
  134. typedef enum {
  135. AC_MODULE_MIN = -1,
  136. AC_MODULE_ADC = 0x01,
  137. AC_MODULE_DAC = 0x02,
  138. AC_MODULE_ADC_DAC = 0x03,
  139. AC_MODULE_LINE = 0x04,
  140. AC_MODULE_MAX
  141. } ac_module_t;
  142. typedef enum {
  143. SRC_MIC1 = 1,
  144. SRC_MIC2 = 2,
  145. SRC_LINEIN = 3,
  146. } ac_output_mixer_source_t;
  147. typedef enum {
  148. GAIN_N45DB = 0,
  149. GAIN_N30DB = 1,
  150. GAIN_N15DB = 2,
  151. GAIN_0DB = 3,
  152. GAIN_15DB = 4,
  153. GAIN_30DB = 5,
  154. GAIN_45DB = 6,
  155. GAIN_60DB = 7,
  156. } ac_output_mixer_gain_t;
  157. typedef struct {
  158. ac_i2s1_bclk_div_t bclk_div; /*!< bits clock divide */
  159. ac_i2s1_lrck_div_t lclk_div; /*!< WS clock divide */
  160. } ac_i2s_clock_t;
  161. #endif