Merge pull request #573 from ZuluSCSI/dev_blaster_sync5_timings

Blaster: Fix SYNC-5 synchronous mode timings

lib/ZuluSCSI_platform_RP2MCU/scsi_accel_target.cpp

@@ -1243,6 +1243,7 @@ bool scsi_accel_rp2040_setSyncMode(int syncOffset, int syncPeriod)
             // This is the period in clock cycles rounded up
             int totalPeriod = (delay_in_ps + up_rounder) / g_zuluscsi_timings->scsi.clk_period_ps;
             int rtotalPeriod = totalPeriod;
+            int clkdiv = 0;
             if (syncPeriod < 25)
             {
                 // Fast-20 SCSI timing: 15 ns assertion period
@@ -1274,6 +1275,8 @@ bool scsi_accel_rp2040_setSyncMode(int syncOffset, int syncPeriod)
             {
                 // Slow SCSI timing: 90 ns assertion period, 55 ns skew delay
                 // Delay2 must be at least 2 to keep negation period well above the 90 ns minimum
+                clkdiv = g_zuluscsi_timings->scsi_5.clkdiv;
+                if (clkdiv > 0) { totalPeriod /= clkdiv; rtotalPeriod /= clkdiv; }
                 totalPeriod += g_zuluscsi_timings->scsi_5.total_period_adjust;
                 delay0 = g_zuluscsi_timings->scsi_5.delay0;
                 delay1 = g_zuluscsi_timings->scsi_5.delay1;
@@ -1310,6 +1313,20 @@ bool scsi_accel_rp2040_setSyncMode(int syncOffset, int syncPeriod)
             uint16_t rinstr1 = (scsi_sync_read_pacer_program_instructions[1] + g_scsi_dma.pio_offset_sync_read_pacer) | pio_encode_delay(rdelay1);
             SCSI_DMA_PIO->instr_mem[g_scsi_dma.pio_offset_sync_read_pacer + 0] = rinstr0;
             SCSI_DMA_PIO->instr_mem[g_scsi_dma.pio_offset_sync_read_pacer + 1] = rinstr1;
+
+            if (clkdiv > 0)
+            {
+                // Add divider to REQ controlling programs in order to satisfy slowest
+                // SCSI-5 timing requirements.
+                sm_config_set_clkdiv_int_frac(&g_scsi_dma.pio_cfg_sync_read_pacer, clkdiv, 0);
+                sm_config_set_clkdiv_int_frac(&g_scsi_dma.pio_cfg_sync_write, clkdiv, 0);
+            }
+            else
+            {
+                // No clock divider
+                sm_config_set_clkdiv_int_frac(&g_scsi_dma.pio_cfg_sync_read_pacer, 1, 0);
+                sm_config_set_clkdiv_int_frac(&g_scsi_dma.pio_cfg_sync_write, 1, 0);
+            }
         }
     }
 

lib/ZuluSCSI_platform_RP2MCU/timings_RP2MCU.c

@@ -256,13 +256,13 @@ static zuluscsi_timings_t  predefined_timings[]  = {
 
         .scsi_5 =
         {
-            .delay0 = 10 - 1,
-            .delay1 = 15, // should be 18 - 1 but max currently is 15
+            .delay0 = 5 - 1,
+            .delay1 = 8 - 1,
             .total_period_adjust = 0,
-            .rdelay1 = 15,
+            .rdelay1 = 8 - 1,
             .rtotal_period_adjust = 0,
             .max_sync = 50,
-
+            .clkdiv = 2,
         },
 
         .sdio =
@@ -320,12 +320,13 @@ static zuluscsi_timings_t  predefined_timings[]  = {
 
         .scsi_5 =
         {
-            .delay0 = 15, // maxed out should be 16
-            .delay1 = 15, // maxed out should be 30
+            .delay0 = 8 - 1,
+            .delay1 = 12 - 1,
             .total_period_adjust = 1,
-            .rdelay1 = 15,
+            .rdelay1 = 12 - 1,
             .rtotal_period_adjust = 1,
             .max_sync = 50,
+            .clkdiv = 2,
         },
         .sdio =
         {
@@ -384,13 +385,13 @@ static zuluscsi_timings_t  predefined_timings[]  = {
 
         .scsi_5 =
         {
-            .delay0 = 10 - 1,
-            .delay1 = 15, // should be 18 - 1 but max currently is 15
+            .delay0 = 5 - 1,
+            .delay1 = 8 - 1,
             .total_period_adjust = 0,
-            .rdelay1 = 15,
+            .rdelay1 = 8 - 1,
             .rtotal_period_adjust = 0,
             .max_sync = 50,
-
+            .clkdiv = 2,
         },
 
         .sdio =
@@ -451,12 +452,12 @@ static zuluscsi_timings_t  predefined_timings[]  = {
         .scsi_5 =
         {
             .delay0 = 4 - 1,
-            .delay1 = 10 - 1,
+            .delay1 = 8 - 1,
             .total_period_adjust = 0,
-            .rdelay1 = 10 - 1,
+            .rdelay1 = 8 - 1,
             .rtotal_period_adjust = 0,
             .max_sync = 50,
-
+            .clkdiv = 2,
         },
 
         .sdio =
@@ -518,12 +519,12 @@ static zuluscsi_timings_t  predefined_timings[]  = {
         .scsi_5 =
         {
             .delay0 = 5 - 1,
-            .delay1 = 11 - 1,
+            .delay1 = 10 - 1,
             .total_period_adjust = 0,
-            .rdelay1 = 11 - 1,
+            .rdelay1 = 10 - 1,
             .rtotal_period_adjust = 0,
             .max_sync = 50,
-
+            .clkdiv = 2,
         },
 
         .sdio =
@@ -583,12 +584,13 @@ static zuluscsi_timings_t  predefined_timings[]  = {
 
         .scsi_5 =
         {
-            .delay0 = 15, // maxed out should be 16
-            .delay1 = 15, // maxed out should be 30
+            .delay0 = 8 - 1,
+            .delay1 = 12 - 1,
             .total_period_adjust = 1,
-            .rdelay1 = 15,
+            .rdelay1 = 12 -1,
             .rtotal_period_adjust = 1,
             .max_sync = 50,
+            .clkdiv = 2,
         },
         .sdio =
         {

lib/ZuluSCSI_platform_RP2MCU/timings_RP2MCU.h

@@ -98,6 +98,7 @@ typedef struct
         uint8_t rdelay1;
         int16_t total_period_adjust;
         uint8_t max_sync;
+        uint8_t clkdiv;
     } scsi_5;