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@@ -8,6 +8,36 @@
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#include "hardware/pio.h"
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#include "hardware/pio.h"
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#endif
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#endif
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+// ----------- //
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+// scsi_parity //
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+// ----------- //
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+
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+#define scsi_parity_wrap_target 0
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+#define scsi_parity_wrap 3
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+
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+static const uint16_t scsi_parity_program_instructions[] = {
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+ // .wrap_target
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+ 0x80a0, // 0: pull block
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+ 0x4061, // 1: in null, 1
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+ 0x40e8, // 2: in osr, 8
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+ 0x4037, // 3: in x, 23
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+ // .wrap
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+};
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+
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+#if !PICO_NO_HARDWARE
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+static const struct pio_program scsi_parity_program = {
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+ .instructions = scsi_parity_program_instructions,
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+ .length = 4,
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+ .origin = -1,
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+};
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+
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+static inline pio_sm_config scsi_parity_program_get_default_config(uint offset) {
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+ pio_sm_config c = pio_get_default_sm_config();
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+ sm_config_set_wrap(&c, offset + scsi_parity_wrap_target, offset + scsi_parity_wrap);
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+ return c;
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+}
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+#endif
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+
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// ---------------------- //
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// ---------------------- //
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// scsi_accel_async_write //
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// scsi_accel_async_write //
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// ---------------------- //
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// ---------------------- //
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@@ -19,7 +49,7 @@ static const uint16_t scsi_accel_async_write_program_instructions[] = {
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// .wrap_target
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// .wrap_target
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0x90e0, // 0: pull ifempty block side 1
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0x90e0, // 0: pull ifempty block side 1
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0x7009, // 1: out pins, 9 side 1
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0x7009, // 1: out pins, 9 side 1
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- 0x7567, // 2: out null, 7 side 1 [5]
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+ 0x7577, // 2: out null, 23 side 1 [5]
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0x309a, // 3: wait 1 gpio, 26 side 1
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0x309a, // 3: wait 1 gpio, 26 side 1
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0x201a, // 4: wait 0 gpio, 26 side 0
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0x201a, // 4: wait 0 gpio, 26 side 0
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// .wrap
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// .wrap
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@@ -40,35 +70,34 @@ static inline pio_sm_config scsi_accel_async_write_program_get_default_config(ui
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}
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}
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#endif
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#endif
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-// --------------------- //
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-// scsi_accel_async_read //
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-// --------------------- //
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+// --------------- //
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+// scsi_accel_read //
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+// --------------- //
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-#define scsi_accel_async_read_wrap_target 0
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-#define scsi_accel_async_read_wrap 6
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+#define scsi_accel_read_wrap_target 0
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+#define scsi_accel_read_wrap 5
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-static const uint16_t scsi_accel_async_read_program_instructions[] = {
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+static const uint16_t scsi_accel_read_program_instructions[] = {
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// .wrap_target
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// .wrap_target
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0x90a0, // 0: pull block side 1
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0x90a0, // 0: pull block side 1
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- 0xb027, // 1: mov x, osr side 1
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- 0x309a, // 2: wait 1 gpio, 26 side 1
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+ 0x309a, // 1: wait 1 gpio, 26 side 1
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+ 0x4061, // 2: in null, 1 side 0
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0x201a, // 3: wait 0 gpio, 26 side 0
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0x201a, // 3: wait 0 gpio, 26 side 0
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0x5009, // 4: in pins, 9 side 1
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0x5009, // 4: in pins, 9 side 1
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- 0x5067, // 5: in null, 7 side 1
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- 0x1042, // 6: jmp x--, 2 side 1
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+ 0x5056, // 5: in y, 22 side 1
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// .wrap
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// .wrap
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};
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};
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#if !PICO_NO_HARDWARE
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#if !PICO_NO_HARDWARE
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-static const struct pio_program scsi_accel_async_read_program = {
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- .instructions = scsi_accel_async_read_program_instructions,
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- .length = 7,
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+static const struct pio_program scsi_accel_read_program = {
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+ .instructions = scsi_accel_read_program_instructions,
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+ .length = 6,
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.origin = -1,
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.origin = -1,
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};
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};
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-static inline pio_sm_config scsi_accel_async_read_program_get_default_config(uint offset) {
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+static inline pio_sm_config scsi_accel_read_program_get_default_config(uint offset) {
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pio_sm_config c = pio_get_default_sm_config();
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pio_sm_config c = pio_get_default_sm_config();
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- sm_config_set_wrap(&c, offset + scsi_accel_async_read_wrap_target, offset + scsi_accel_async_read_wrap);
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+ sm_config_set_wrap(&c, offset + scsi_accel_read_wrap_target, offset + scsi_accel_read_wrap);
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sm_config_set_sideset(&c, 1, false, false);
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sm_config_set_sideset(&c, 1, false, false);
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return c;
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return c;
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}
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}
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@@ -84,7 +113,7 @@ static inline pio_sm_config scsi_accel_async_read_program_get_default_config(uin
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static const uint16_t scsi_sync_write_program_instructions[] = {
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static const uint16_t scsi_sync_write_program_instructions[] = {
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// .wrap_target
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// .wrap_target
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0x7009, // 0: out pins, 9 side 1
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0x7009, // 0: out pins, 9 side 1
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- 0x6067, // 1: out null, 7 side 0
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+ 0x6077, // 1: out null, 23 side 0
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0x5061, // 2: in null, 1 side 1
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0x5061, // 2: in null, 1 side 1
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// .wrap
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// .wrap
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};
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};
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@@ -132,3 +161,65 @@ static inline pio_sm_config scsi_sync_write_pacer_program_get_default_config(uin
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return c;
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return c;
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}
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}
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#endif
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#endif
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+
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+// -------------------- //
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+// scsi_sync_read_pacer //
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+// -------------------- //
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+
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+#define scsi_sync_read_pacer_wrap_target 0
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+#define scsi_sync_read_pacer_wrap 2
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+
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+static const uint16_t scsi_sync_read_pacer_program_instructions[] = {
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+ // .wrap_target
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+ 0x9020, // 0: push block side 1
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+ 0x0040, // 1: jmp x--, 0 side 0
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+ 0x1002, // 2: jmp 2 side 1
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+ // .wrap
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+};
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+
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+#if !PICO_NO_HARDWARE
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+static const struct pio_program scsi_sync_read_pacer_program = {
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+ .instructions = scsi_sync_read_pacer_program_instructions,
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+ .length = 3,
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+ .origin = -1,
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+};
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+
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+static inline pio_sm_config scsi_sync_read_pacer_program_get_default_config(uint offset) {
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+ pio_sm_config c = pio_get_default_sm_config();
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+ sm_config_set_wrap(&c, offset + scsi_sync_read_pacer_wrap_target, offset + scsi_sync_read_pacer_wrap);
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+ sm_config_set_sideset(&c, 1, false, false);
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+ return c;
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+}
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+#endif
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+
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+// ---------------- //
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+// scsi_read_parity //
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+// ---------------- //
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+
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+#define scsi_read_parity_wrap_target 0
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+#define scsi_read_parity_wrap 4
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+
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+static const uint16_t scsi_read_parity_program_instructions[] = {
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+ // .wrap_target
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+ 0x60c8, // 0: out isr, 8
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+ 0x8020, // 1: push block
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+ 0x6038, // 2: out x, 24
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+ 0x0040, // 3: jmp x--, 0
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+ 0xc000, // 4: irq nowait 0
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+ // .wrap
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+};
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+
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+#if !PICO_NO_HARDWARE
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+static const struct pio_program scsi_read_parity_program = {
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+ .instructions = scsi_read_parity_program_instructions,
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+ .length = 5,
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+ .origin = -1,
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+};
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+
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+static inline pio_sm_config scsi_read_parity_program_get_default_config(uint offset) {
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+ pio_sm_config c = pio_get_default_sm_config();
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+ sm_config_set_wrap(&c, offset + scsi_read_parity_wrap_target, offset + scsi_read_parity_wrap);
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+ return c;
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+}
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+#endif
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+
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