Init the FS USB device in STM32CUBEMX generated code

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx.h
   * @author  MCD Application Team
+  * @version V2.1.0
+  * @date    09-October-2015
   * @brief   CMSIS STM32F2xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -16,13 +18,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -81,17 +99,17 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.2.2
-  */
-#define __STM32F2xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F2xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
-#define __STM32F2xx_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
-#define __STM32F2xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32F2xx_CMSIS_VERSION        ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
-                                         |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
-                                         |(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 )\
-                                         |(__STM32F2xx_CMSIS_VERSION))
-
+  * @brief CMSIS Device version number V2.1.0
+  */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32F2xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+                                             
 /**
   * @}
   */
@@ -121,21 +139,21 @@
   */ 
 typedef enum 
 {
-  RESET = 0U, 
+  RESET = 0, 
   SET = !RESET
 } FlagStatus, ITStatus;
 
 typedef enum 
 {
-  DISABLE = 0U, 
+  DISABLE = 0, 
   ENABLE = !DISABLE
 } FunctionalState;
 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
 typedef enum 
 {
-  SUCCESS = 0U,
-  ERROR = !SUCCESS
+  ERROR = 0, 
+  SUCCESS = !ERROR
 } ErrorStatus;
 
 /**

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    system_stm32f2xx.h
   * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
-  ****************************************************************************
+  * @version V2.1.0
+  * @date    09-October-2015
+  * @brief   CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.       
+******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  ******************************************************************************
-  */
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
 
 /** @addtogroup CMSIS
   * @{
@@ -57,8 +75,6 @@
   */
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
 
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s

@@ -1,6 +1,8 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f205xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F205xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,18 +13,31 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
-;******************************************************************************
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s

@@ -1,6 +1,8 @@
-******************* (C) COPYRIGHT 2017 STMicroelectronics ********************
+******************* (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f207xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F207xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,18 +13,31 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
-;******************************************************************************
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f215xx.s

@@ -1,6 +1,8 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f215xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F215xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,18 +13,31 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
-;******************************************************************************
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f217xx.s

@@ -1,6 +1,8 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f217xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F217xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,18 +13,31 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
-;******************************************************************************
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f205xx.s

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f205xx.s
   * @author    MCD Application Team
+  * @version   V2.1.0
+  * @date      09-October-2015
   * @brief     STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -14,13 +16,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f207xx.s
   * @author    MCD Application Team
+  * @version   V2.1.0
+  * @date      09-October-2015
   * @brief     STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -14,13 +16,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f215xx.s
   * @author    MCD Application Team
+  * @version   V2.1.0
+  * @date      09-October-2015
   * @brief     STM32F215xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -14,13 +16,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f217xx.s
   * @author    MCD Application Team
+  * @version   V2.1.0
+  * @date      09-October-2015
   * @brief     STM32F217xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -14,13 +16,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s

@@ -1,6 +1,8 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f205xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,17 +13,30 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
 ;*******************************************************************************
 ;
 ;

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s

@@ -1,6 +1,8 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f207xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,17 +13,30 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
 ;*******************************************************************************
 ;
 ;

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s

@@ -1,6 +1,8 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f215xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,17 +13,30 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
 ;*******************************************************************************
 ;
 ;

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s

@@ -1,6 +1,8 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
 ;* File Name          : startup_stm32f217xx.s
 ;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -11,17 +13,30 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
 ;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
 ;*******************************************************************************
 ;
 ;

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f2xx.c
   * @author  MCD Application Team
+  * @version V2.1.0
+  * @date    09-October-2015
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *             
   *   This file provides two functions and one global variable to be called from 
@@ -21,13 +23,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -47,7 +65,7 @@
 #include "stm32f2xx.h"
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
@@ -105,9 +123,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 16000000;
+  uint32_t SystemCoreClock = 12000000;
   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
 /**
   * @}
   */
@@ -193,10 +211,10 @@ void SystemInit(void)
   *             16 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.   
   *    
-  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
-  *              depends on the application requirements), user has to ensure that HSE_VALUE
-  *              is same as the real frequency of the crystal used. Otherwise, this function
-  *              may have wrong result.
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
   *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0.h

@@ -1,44 +1,52 @@
 /**************************************************************************//**
  * @file     core_cm0.h
  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.5
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * @version  V4.10
+ * @date     18. March 2015
  *
- * www.apache.org/licenses/LICENSE-2.0
+ * @note
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifndef __CORE_CM0_H_GENERIC
 #define __CORE_CM0_H_GENERIC
 
-#include <stdint.h>
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.<br>
@@ -55,49 +63,74 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/**
-  \ingroup Cortex_M0
+/** \ingroup Cortex_M0
   @{
  */
 
-#include "cmsis_version.h"
- 
 /*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
 
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+#endif
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0U
+#define __FPU_USED       0
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -105,15 +138,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
-
 #endif
 
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #ifdef __cplusplus
 }
@@ -133,17 +166,17 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
+    #define __CM0_REV               0x0000
     #warning "__CM0_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
+    #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
+    #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -157,17 +190,12 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
 /*@} end of group Cortex_M0 */
 
@@ -181,364 +209,325 @@
   - Core SCB Register
   - Core SysTick Register
  ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
+/** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
+/** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the System Control Block (SCB).
+/** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
-/**
-  \brief  Structure type to access the System Timer (SysTick).
+/** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/* Memory mapping of Core Hardware */
+/* Memory mapping of Cortex-M0 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 
 
 /*@} */
@@ -552,377 +541,179 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
 
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
+/** \brief  Enable External Interrupt
 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
+/** \brief  Disable External Interrupt
 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
+/** \brief  Get Pending Interrupt
 
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
+    \param [in]      IRQn  Interrupt number.
 
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
 
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
+/** \brief  Set Pending Interrupt
 
+    The function sets the pending bit of an external interrupt.
 
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
 
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
+/** \brief  Clear Pending Interrupt
 
+    The function clears the pending bit of an external interrupt.
 
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
 
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
+/** \brief  Set Interrupt Priority
 
+    The function sets the priority of an interrupt.
 
+    \note The priority cannot be set for every core interrupt.
 
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  uint32_t *vectors = (uint32_t *)0x0U;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
 }
 
 
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
-  uint32_t *vectors = (uint32_t *)0x0U;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
 }
 
 
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
  */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
 {
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
 
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
  */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
 
+#if (__Vendor_SysTickConfig == 0)
 
-/*@} end of CMSIS_Core_FpuFunctions */
+/** \brief  System Tick Configuration
 
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
 
+    \param [in]  ticks  Number of ticks between two interrupts.
 
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
+    \return          0  Function succeeded.
+    \return          1  Function failed.
 
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
 
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0plus.h

@@ -1,44 +1,52 @@
 /**************************************************************************//**
  * @file     core_cm0plus.h
  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.6
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * @version  V4.10
+ * @date     18. March 2015
  *
- * www.apache.org/licenses/LICENSE-2.0
+ * @note
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifndef __CORE_CM0PLUS_H_GENERIC
 #define __CORE_CM0PLUS_H_GENERIC
 
-#include <stdint.h>
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.<br>
@@ -55,49 +63,74 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
+/** \ingroup Cortex-M0+
   @{
  */
 
-#include "cmsis_version.h"
- 
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
 
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0U
+#define __FPU_USED       0
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -105,15 +138,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
-
 #endif
 
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #ifdef __cplusplus
 }
@@ -133,27 +166,27 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
+    #define __CM0PLUS_REV             0x0000
     #warning "__CM0PLUS_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
+    #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
+    #define __VTOR_PRESENT            0
     #warning "__VTOR_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
+    #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
+    #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -167,17 +200,12 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
 /*@} end of group Cortex-M0+ */
 
@@ -192,471 +220,428 @@
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
+/** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
+/** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the System Control Block (SCB).
+/** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
 #else
-        uint32_t RESERVED0;
+       uint32_t RESERVED0;
 #endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if (__VTOR_PRESENT == 1)
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 #endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
-/**
-  \brief  Structure type to access the System Timer (SysTick).
+/** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
 } MPU_Type;
 
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
+/* Memory mapping of Cortex-M0+ Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -670,393 +655,179 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
 
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
+/** \brief  Enable External Interrupt
 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
+/** \brief  Disable External Interrupt
 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
+/** \brief  Get Pending Interrupt
 
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
 
+    \param [in]      IRQn  Interrupt number.
 
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
 
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
+/** \brief  Set Pending Interrupt
 
+    The function sets the pending bit of an external interrupt.
 
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
 
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
+/** \brief  Clear Pending Interrupt
 
+    The function clears the pending bit of an external interrupt.
 
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
 
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
+/** \brief  Set Interrupt Priority
 
+    The function sets the priority of an interrupt.
 
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-    uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
 }
 
 
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
 }
 
 
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
  */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
 {
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 
-#include "mpu_armv7.h"
 
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
+#if (__Vendor_SysTickConfig == 0)
 
-/*@} end of CMSIS_Core_FpuFunctions */
+/** \brief  System Tick Configuration
 
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
 
+    \param [in]  ticks  Number of ticks between two interrupts.
 
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
+    \return          0  Function succeeded.
+    \return          1  Function failed.
 
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
 
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc000.h

@@ -1,44 +1,52 @@
 /**************************************************************************//**
  * @file     core_sc000.h
  * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.5
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
+ * @version  V4.10
+ * @date     18. March 2015
  *
- * www.apache.org/licenses/LICENSE-2.0
+ * @note
  *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
 #endif
 
 #ifndef __CORE_SC000_H_GENERIC
 #define __CORE_SC000_H_GENERIC
 
-#include <stdint.h>
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.<br>
@@ -55,49 +63,74 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/**
-  \ingroup SC000
+/** \ingroup SC000
   @{
  */
 
-#include "cmsis_version.h"
-
 /*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
 
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0U
+#define __FPU_USED       0
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -105,15 +138,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
-
 #endif
 
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
 
 #ifdef __cplusplus
 }
@@ -133,22 +166,22 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __SC000_REV
-    #define __SC000_REV             0x0000U
+    #define __SC000_REV             0x0000
     #warning "__SC000_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
+    #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
+    #define __NVIC_PRIO_BITS          2
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
+    #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -162,17 +195,12 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
 /*@} end of group SC000 */
 
@@ -187,486 +215,443 @@
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
   @{
  */
 
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
+/** \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
+/** \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
   @{
  */
 
-/**
-  \brief  Structure type to access the System Control Block (SCB).
+/** \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-        uint32_t RESERVED1[154U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
 } SCnSCB_Type;
 
 /* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
   @{
  */
 
-/**
-  \brief  Structure type to access the System Timer (SysTick).
+/** \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
 } MPU_Type;
 
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
+/* Memory mapping of SC000 Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
 
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
 #endif
 
 /*@} */
@@ -680,322 +665,179 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
  */
 
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
 
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
+/** \brief  Enable External Interrupt
 
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
+/** \brief  Disable External Interrupt
 
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
 
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
 
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 }
 
 
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
 
 
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
+/** \brief  Get Interrupt Priority
 
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
 
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
 }
 
 
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
  */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
 {
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
   @{
  */
 
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
+#if (__Vendor_SysTickConfig == 0)
 
+/** \brief  System Tick Configuration
 
-/*@} end of CMSIS_Core_FpuFunctions */
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
 
+    \param [in]  ticks  Number of ticks between two interrupts.
 
+    \return          0  Function succeeded.
+    \return          1  Function failed.
 
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
 
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/CMSIS/RTOS/Template/cmsis_os.h

@@ -24,21 +24,30 @@
  *    Removed: osSignalGet 
  *----------------------------------------------------------------------------
  *
- * Copyright (c) 2013-2017 ARM LIMITED
+ * Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
  *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  *---------------------------------------------------------------------------*/
  
  
@@ -327,14 +336,14 @@ osPriority osThreadGetPriority (osThreadId thread_id);
 //  ==== Generic Wait Functions ====
  
 /// Wait for Timeout (Time Delay).
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \param[in]     millisec      time delay value
 /// \return status code that indicates the execution status of the function.
 osStatus osDelay (uint32_t millisec);
  
 #if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
  
 /// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \param[in] millisec          timeout value or 0 in case of no time-out
 /// \return event that contains signal, message, or mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
 osEvent osWait (uint32_t millisec);
@@ -374,7 +383,7 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void
  
 /// Start or restart a timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \param[in]     millisec      time delay value of the timer.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
@@ -410,7 +419,7 @@ int32_t osSignalClear (osThreadId thread_id, int32_t signals);
  
 /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
 /// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return event flag information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
 osEvent osSignalWait (int32_t signals, uint32_t millisec);
@@ -445,7 +454,7 @@ osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
  
 /// Wait until a Mutex becomes available.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
 osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
@@ -495,7 +504,7 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t
  
 /// Wait until a Semaphore token becomes available.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return number of available tokens, or -1 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
 int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
@@ -605,14 +614,14 @@ osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId threa
 /// Put a Message to a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     info          message information.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
 osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
  
 /// Get a Message or Wait for a Message from a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
 /// \return event information that includes status code.
 /// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
 osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
@@ -655,14 +664,14 @@ osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
  
 /// Allocate a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
  
 /// Allocate a memory block from a mail and set memory block to zero.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
@@ -676,7 +685,7 @@ osStatus osMailPut (osMailQId queue_id, void *mail);
  
 /// Get a mail from a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
 /// \return event that contains mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
 osEvent osMailGet (osMailQId queue_id, uint32_t millisec);

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h

@@ -2,21 +2,39 @@
   ******************************************************************************
   * @file    stm32f2xx_hal.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_H
@@ -39,29 +57,6 @@
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
-  * @{
-  */
-typedef enum
-{
-  HAL_TICK_FREQ_10HZ         = 100U,
-  HAL_TICK_FREQ_100HZ        = 10U,
-  HAL_TICK_FREQ_1KHZ         = 1U,
-  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup HAL_Exported_Macros HAL Exported Macros
   * @{
@@ -142,16 +137,6 @@ typedef enum
   * @}
   */
 
-/** @defgroup HAL_Private_Macros HAL Private Macros
-  * @{
-  */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
-                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
-                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
-  * @}
-  */
-
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup HAL_Exported_Functions
   * @{
@@ -165,17 +150,6 @@ HAL_StatusTypeDef HAL_DeInit(void);
 void HAL_MspInit(void);
 void HAL_MspDeInit(void);
 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
-  * @}
-  */
-
- /* Exported variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
-  * @{
-  */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
 /**
   * @}
   */
@@ -187,9 +161,6 @@ extern HAL_TickFreqTypeDef uwTickFreq;
 void HAL_IncTick(void);
 void HAL_Delay(__IO uint32_t Delay);
 uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
 void HAL_SuspendTick(void);
 void HAL_ResumeTick(void);
 uint32_t HAL_GetHalVersion(void);
@@ -203,9 +174,6 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
 void HAL_DBGMCU_DisableDBGStandbyMode(void);
 void HAL_EnableCompensationCell(void);
 void HAL_DisableCompensationCell(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
 /**
   * @}
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h

@@ -2,17 +2,35 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -154,38 +172,34 @@ typedef struct
   * @brief  HAL ADC state machine: ADC states definition (bitfields)
   */ 
 /* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             0x00000000U    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             0x00000001U    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     0x00000002U    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           0x00000004U    /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
 
 /* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    0x00000010U    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      0x00000020U    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         0x00000040U    /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
 
 /* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           0x00000200U    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           0x00000400U    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
 
 /* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           0x00002000U    /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
 
 /* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              0x00010000U    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
 
 /** 
   * @brief  ADC handle Structure definition
   */ 
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-typedef struct __ADC_HandleTypeDef
-#else
 typedef struct
-#endif
 {
   ADC_TypeDef                   *Instance;                   /*!< Register base address */
 
@@ -200,39 +214,7 @@ typedef struct
   __IO uint32_t                 State;                       /*!< ADC communication state */
 
   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
-  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
-  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
-  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
-  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
-  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
-  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 }ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL ADC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
-  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
-  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
-  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
-  HAL_ADC_MSPINIT_CB_ID                 = 0x05U,  /*!< ADC Msp Init callback ID          */
-  HAL_ADC_MSPDEINIT_CB_ID               = 0x06U   /*!< ADC Msp DeInit callback ID        */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL ADC Callback pointer definition
-  */
-typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
@@ -245,14 +227,11 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_Error_Code ADC Error Code
   * @{
   */
-#define HAL_ADC_ERROR_NONE        0x00U   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    0x01U   /*!< ADC IP internal error: if problem of clocking, 
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
                                                           enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         0x02U   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         0x04U   /*!< DMA transfer error                                    */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
 /**
   * @}
   */
@@ -261,7 +240,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
   * @{
   */ 
-#define ADC_CLOCK_SYNC_PCLK_DIV2    0x00000000U
+#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000)
 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
@@ -272,7 +251,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
   * @{
   */ 
-#define ADC_TWOSAMPLINGDELAY_5CYCLES    0x00000000U
+#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000)
 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@@ -295,7 +274,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_Resolution ADC Resolution
   * @{
   */ 
-#define ADC_RESOLUTION_12B  0x00000000U
+#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000)
 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
@@ -306,7 +285,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
   * @{
   */ 
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           0x00000000U
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
@@ -319,7 +298,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
 /*       compatibility with other STM32 devices.                              */
-#define ADC_EXTERNALTRIGCONV_T1_CC1    0x00000000U
+#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -335,7 +314,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 #define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)
+#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
 /**
   * @}
   */ 
@@ -343,7 +322,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_Data_align ADC Data Align
   * @{
   */ 
-#define ADC_DATAALIGN_RIGHT      0x00000000U
+#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
 /**
   * @}
@@ -352,7 +331,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_channels  ADC Common Channels
   * @{
   */ 
-#define ADC_CHANNEL_0           0x00000000U
+#define ADC_CHANNEL_0           ((uint32_t)0x00000000)
 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@@ -381,7 +360,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_sampling_times  ADC Sampling Times
   * @{
   */ 
-#define ADC_SAMPLETIME_3CYCLES    0x00000000U
+#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000)
 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@@ -396,9 +375,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   /** @defgroup ADC_EOCSelection ADC EOC Selection
   * @{
   */ 
-#define ADC_EOC_SEQ_CONV              0x00000000U
-#define ADC_EOC_SINGLE_CONV           0x00000001U
-#define ADC_EOC_SINGLE_SEQ_CONV       0x00000002U  /*!< reserved for future use */
+#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000)
+#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001)
+#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002)  /*!< reserved for future use */
 /**
   * @}
   */ 
@@ -421,7 +400,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_NONE               0x00000000U
+#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000)
 /**
   * @}
   */ 
@@ -453,9 +432,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_channels_type ADC Channels Type
   * @{
   */ 
-#define ADC_ALL_CHANNELS      0x00000001U
-#define ADC_REGULAR_CHANNELS  0x00000002U /*!< reserved for future use */
-#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
+#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001)
+#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002) /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
 /**
   * @}
   */
@@ -470,70 +449,60 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 
 /** @brief Reset ADC handle state
-  * @param  __HANDLE__ ADC handle
+  * @param  __HANDLE__: ADC handle
   * @retval None
   */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  do{                                                                          \
-     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
-     (__HANDLE__)->MspInitCallback = NULL;                                     \
-     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
-    } while(0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
 
 /**
   * @brief  Enable the ADC peripheral.
-  * @param  __HANDLE__ ADC handle
+  * @param  __HANDLE__: ADC handle
   * @retval None
   */
 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
 
 /**
   * @brief  Disable the ADC peripheral.
-  * @param  __HANDLE__ ADC handle
+  * @param  __HANDLE__: ADC handle
   * @retval None
   */
 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
 
 /**
   * @brief  Enable the ADC end of conversion interrupt.
-  * @param  __HANDLE__ specifies the ADC Handle.
-  * @param  __INTERRUPT__ ADC Interrupt.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: ADC Interrupt.
   * @retval None
   */
 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the ADC end of conversion interrupt.
-  * @param  __HANDLE__ specifies the ADC Handle.
-  * @param  __INTERRUPT__ ADC interrupt.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: ADC interrupt.
   * @retval None
   */
 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
 
 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the ADC Handle.
-  * @param  __INTERRUPT__ specifies the ADC interrupt source to check.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Clear the ADC's pending flags.
-  * @param  __HANDLE__ specifies the ADC Handle.
-  * @param  __FLAG__ ADC flag.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __FLAG__: ADC flag.
   * @retval None
   */
 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
 
 /**
   * @brief  Get the selected ADC's flag status.
-  * @param  __HANDLE__ specifies the ADC Handle.
-  * @param  __FLAG__ ADC flag.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __FLAG__: ADC flag.
   * @retval None
   */
 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
@@ -558,12 +527,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -628,11 +591,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /* Delay for ADC stabilization time.                                        */
 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
 /* Unit: us                                                                 */
-#define ADC_STAB_DELAY_US               3U
+#define ADC_STAB_DELAY_US               ((uint32_t) 3)
 /* Delay for temperature sensor stabilization time.                         */
 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
 /* Unit: us                                                                 */
-#define ADC_TEMPSENSOR_DELAY_US        10U
+#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
 /**
   * @}
   */
@@ -647,7 +610,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
   * @brief Verification of ADC state: enabled or disabled
-  * @param  __HANDLE__ ADC handle
+  * @param __HANDLE__: ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
 #define ADC_IS_ENABLE(__HANDLE__)                                              \
@@ -657,7 +620,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /**
   * @brief Test if conversion trigger of regular group is software start
   *        or external trigger.
-  * @param  __HANDLE__ ADC handle
+  * @param __HANDLE__: ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
@@ -666,7 +629,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /**
   * @brief Test if conversion trigger of injected group is software start
   *        or external trigger.
-  * @param  __HANDLE__ ADC handle
+  * @param __HANDLE__: ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
@@ -683,7 +646,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
   * @brief Clear ADC error code (set it to error code: "no error")
-  * @param  __HANDLE__ ADC handle
+  * @param __HANDLE__: ADC handle
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
@@ -760,102 +723,102 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
 
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
-   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
-    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
-    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= 0x00FFU)) || \
-    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= 0x003FU)))
+   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003F))))
 
 /**
   * @brief  Set ADC Regular channel sequence length.
-  * @param  _NbrOfConversion_ Regular channel sequence length. 
+  * @param  _NbrOfConversion_: Regular channel sequence length. 
   * @retval None
   */
-#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U)
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
 
 /**
   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param  _SAMPLETIME_ Sample time parameter.
-  * @param  _CHANNELNB_ Channel number.  
+  * @param  _SAMPLETIME_: Sample time parameter.
+  * @param  _CHANNELNB_: Channel number.  
   * @retval None
   */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
 
 /**
   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param  _SAMPLETIME_ Sample time parameter.
-  * @param  _CHANNELNB_ Channel number.  
+  * @param  _SAMPLETIME_: Sample time parameter.
+  * @param  _CHANNELNB_: Channel number.  
   * @retval None
   */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 1 and 6.
-  * @param  _CHANNELNB_ Channel number.
-  * @param  _RANKNB_ Rank number.    
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
   * @retval None
   */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 7 and 12.
-  * @param  _CHANNELNB_ Channel number.
-  * @param  _RANKNB_ Rank number.    
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
   * @retval None
   */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 13 and 16.
-  * @param  _CHANNELNB_ Channel number.
-  * @param  _RANKNB_ Rank number.    
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
   * @retval None
   */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
 
 /**
   * @brief  Enable ADC continuous conversion mode.
-  * @param  _CONTINUOUS_MODE_ Continuous mode.
+  * @param  _CONTINUOUS_MODE_: Continuous mode.
   * @retval None
   */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
 
 /**
   * @brief  Configures the number of discontinuous conversions for the regular group channels.
-  * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
+  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
   * @retval None
   */
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
 
 /**
   * @brief  Enable ADC scan mode.
-  * @param  _SCANCONV_MODE_ Scan conversion mode.
+  * @param  _SCANCONV_MODE_: Scan conversion mode.
   * @retval None
   */
-#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
 
 /**
   * @brief  Enable the ADC end of conversion selection.
-  * @param  _EOCSelection_MODE_ End of conversion selection mode.
+  * @param  _EOCSelection_MODE_: End of conversion selection mode.
   * @retval None
   */
-#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
 
 /**
   * @brief  Enable the ADC DMA continuous request.
-  * @param  _DMAContReq_MODE_ DMA continuous request mode.
+  * @param  _DMAContReq_MODE_: DMA continuous request mode.
   * @retval None
   */
-#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
 
 /**
   * @brief Return resolution bits in CR1 register.
-  * @param  __HANDLE__ ADC handle
+  * @param __HANDLE__: ADC handle
   * @retval None
   */
 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h

@@ -1,18 +1,36 @@
 /**
   ******************************************************************************
-  * @file    stm32f2xx_hal_adc_ex.h
+  * @file    stm32f2xx_hal_adc.h
   * @author  MCD Application Team
-  * @brief   Header file of ADC HAL extension module.
+  * @version V1.1.0
+  * @date    09-October-2015
+  * @brief   Header file of ADC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -108,6 +126,9 @@ typedef struct
                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 }ADC_InjectionConfTypeDef; 
+/**
+  * @}
+  */
 
 /** 
   * @brief ADC Configuration multi-mode structure definition  
@@ -134,7 +155,7 @@ typedef struct
 /** @defgroup ADCEx_Common_mode ADC Common Mode
   * @{
   */ 
-#define ADC_MODE_INDEPENDENT                  0x00000000U      
+#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000)      
 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@@ -154,7 +175,7 @@ typedef struct
 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
   * @{
   */ 
-#define ADC_DMAACCESSMODE_DISABLED  0x00000000U     /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000)     /*!< DMA mode disabled */
 #define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
 #define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
 #define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@@ -165,7 +186,7 @@ typedef struct
 /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
   * @{
   */ 
-#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           0x00000000U
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000)
 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
@@ -176,7 +197,7 @@ typedef struct
 /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
   * @{
   */ 
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           0x00000000U
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00000000)
 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)
 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)
 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@@ -192,7 +213,7 @@ typedef struct
 #define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)
-#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1U)
+#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
 /**
   * @}
   */ 
@@ -200,10 +221,10 @@ typedef struct
 /** @defgroup ADCEx_injected_rank ADC Injected Rank
   * @{
   */ 
-#define ADC_INJECTED_RANK_1    0x00000001U
-#define ADC_INJECTED_RANK_2    0x00000002U
-#define ADC_INJECTED_RANK_3    0x00000003U
-#define ADC_INJECTED_RANK_4    0x00000004U
+#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
 /**
   * @}
   */
@@ -317,17 +338,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
                                         ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
 
 /**
   * @brief  Set the selected injected Channel rank.
-  * @param  _CHANNELNB_ Channel number.
-  * @param  _RANKNB_ Rank number. 
-  * @param  _JSQR_JL_ Sequence length.
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number. 
+  * @param  _JSQR_JL_: Sequence length.     
   * @retval None
   */
-#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
+#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
 
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h

@@ -2,22 +2,40 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_conf_template.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f2xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CONF_H
@@ -34,43 +52,41 @@
 /**
   * @brief This is the list of modules to be used in the HAL driver 
   */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DCMI_MODULE_ENABLED
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED  
+#define HAL_CAN_MODULE_ENABLED  
+#define HAL_CRC_MODULE_ENABLED  
+#define HAL_CRYP_MODULE_ENABLED  
+#define HAL_DAC_MODULE_ENABLED  
+#define HAL_DCMI_MODULE_ENABLED 
 #define HAL_DMA_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED 
 #define HAL_NAND_MODULE_ENABLED
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_PCCARD_MODULE_ENABLED
 #define HAL_SRAM_MODULE_ENABLED
-#define HAL_HASH_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED  
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED   
+#define HAL_IWDG_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED   
+#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RNG_MODULE_ENABLED   
 #define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED  
+#define HAL_SPI_MODULE_ENABLED   
+#define HAL_TIM_MODULE_ENABLED   
+#define HAL_UART_MODULE_ENABLED 
+#define HAL_USART_MODULE_ENABLED 
+#define HAL_IRDA_MODULE_ENABLED 
+#define HAL_SMARTCARD_MODULE_ENABLED 
+#define HAL_WWDG_MODULE_ENABLED  
 #define HAL_CORTEX_MODULE_ENABLED
 #define HAL_PCD_MODULE_ENABLED
 #define HAL_HCD_MODULE_ENABLED
-#define HAL_MMC_MODULE_ENABLED
+
 
 /* ########################## HSE/HSI Values adaptation ##################### */
 /**
@@ -79,11 +95,11 @@
   *        (when HSE is used as system clock source, directly or through the PLL).  
   */
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE                    25000000U       /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT               100U       /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -92,35 +108,31 @@
   *        (when HSI is used as system clock source, directly or through the PLL). 
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE                    16000000U       /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
 #if !defined  (LSI_VALUE) 
- #define LSI_VALUE                        32000U       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                                 /*!< Value of the Internal Low Speed oscillator in Hz
-                                                            The real value may vary depending on the variations
-                                                            in voltage and temperature.*/
+ #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
 /**
   * @brief External Low Speed oscillator (LSE) value.
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE                        32768U       /*!< Value of the External Low Speed oscillator in Hz */
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT              5000U       /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
 /**
   * @brief External clock source for I2S peripheral
   *        This value is used by the I2S HAL module to compute the I2S clock source 
   *        frequency, this source is inserted directly through I2S_CKIN pad. 
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE       12288000U        /*!< Value of the Internal oscillator in Hz*/
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -130,81 +142,54 @@
 /**
   * @brief This is the HAL system configuration section
   */     
-#define  VDD_VALUE                      3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY              0x0FU /*!< tick interrupt priority */
-#define  USE_RTOS                          0U
-#define  PREFETCH_ENABLE                   1U
-#define  INSTRUCTION_CACHE_ENABLE          1U
-#define  DATA_CACHE_ENABLE                 1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
 
 /* ########################## Assert Selection ############################## */
 /**
   * @brief Uncomment the line below to expanse the "assert_param" macro in the 
   *        HAL drivers code
   */
-/* #define USE_FULL_ASSERT    1U */
+/* #define USE_FULL_ASSERT    1 */
 
 /* ################## Ethernet peripheral configuration ##################### */
 
 /* Section 1 : Ethernet peripheral configuration */
 
 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0                         2U
-#define MAC_ADDR1                         0U
-#define MAC_ADDR2                         0U
-#define MAC_ADDR3                         0U
-#define MAC_ADDR4                         0U
-#define MAC_ADDR5                         0U
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
 
 /* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                       4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                       4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
 
 /* Section 2: PHY configuration section */
 
 /* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01U
+#define DP83848_PHY_ADDRESS             0x01
 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 0x000000FFU
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
 /* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
 
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
  
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
@@ -223,9 +208,9 @@
   
 /* Section 4: Extended PHY Registers */
 
-#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
  
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
@@ -237,15 +222,6 @@
 #define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
 #define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
 
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
 /* Includes ------------------------------------------------------------------*/
 /**
   * @brief Include module's header file 
@@ -259,10 +235,6 @@
   #include "stm32f2xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
 
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f2xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f2xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
@@ -279,10 +251,6 @@
   #include "stm32f2xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
 
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f2xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
 #ifdef HAL_CRC_MODULE_ENABLED
   #include "stm32f2xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
@@ -390,25 +358,22 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f2xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f2xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
+   
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
+  * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
   *         line number of the call that failed. 
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
 #else
-  #define assert_param(expr) ((void)0U)
+  #define assert_param(expr) ((void)0)
 #endif /* USE_FULL_ASSERT */
 
 

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cortex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CORTEX_H
@@ -40,7 +58,7 @@
   * @{
   */
 
-#if (__MPU_PRESENT == 1U)
+#if (__MPU_PRESENT == 1)
 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
   * @brief  MPU Region initialization structure 
   * @{
@@ -87,25 +105,25 @@ typedef struct
 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
   * @{
   */
-#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
-                                                      4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
-                                                      3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
-                                                      2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
-                                                      1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
-                                                      0 bits for subpriority */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
 /**
   * @}
   */
 
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
   * @{
   */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
 
 /**
   * @}
@@ -115,11 +133,10 @@ typedef struct
 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
   * @{
   */
-#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
-#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
-#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
-#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
 /**
   * @}
   */
@@ -184,44 +201,44 @@ typedef struct
   */
 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-/**
+/**                                
   * @}
   */
    
 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
   * @{
   */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
 /**
   * @}
@@ -230,11 +247,11 @@ typedef struct
 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
   * @{
   */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
@@ -249,6 +266,29 @@ typedef struct
 
 
 /* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/** @brief Configures the SysTick clock source.
+  * @param __CLKSRC__: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__)                             \
+                            do {                                               \
+                                 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK)   \
+                                  {                                            \
+                                    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;   \
+                                  }                                            \
+                                 else                                          \
+                                    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;  \
+                                } while(0)
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup CORTEX_Exported_Functions
@@ -256,8 +296,8 @@ typedef struct
   */
   
 /** @addtogroup CORTEX_Exported_Functions_Group1
-  * @{
-  */
+ * @{
+ */
 /* Initialization and de-initialization functions *****************************/
 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@@ -270,9 +310,12 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
   */
 
 /** @addtogroup CORTEX_Exported_Functions_Group2
-  * @{
-  */
+ * @{
+ */
 /* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
 uint32_t HAL_NVIC_GetPriorityGrouping(void);
 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -282,12 +325,6 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
 void HAL_SYSTICK_IRQHandler(void);
 void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
 /**
   * @}
   */
@@ -296,7 +333,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/ 
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
@@ -309,16 +346,16 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
 
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
 
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
 
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
 
 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
 
-#if (__MPU_PRESENT == 1U)
+#if (__MPU_PRESENT == 1)
 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
                                      ((STATE) == MPU_REGION_DISABLE))
 
@@ -388,9 +425,52 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 
 /**                                                                          
   * @}                                                                  
+  */                                                                            
+                                                                                   
+/* Private functions ---------------------------------------------------------*/   
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+  * @brief    CORTEX private  functions 
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
   */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU */
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged access to the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
 
-/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */
 
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_crc.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_CRC_H
-#define STM32F2xx_HAL_CRC_H
+#ifndef __STM32F2xx_HAL_CRC_H
+#define __STM32F2xx_HAL_CRC_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -32,7 +50,8 @@ extern "C" {
   * @{
   */
 
-/** @addtogroup CRC
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver
   * @{
   */
 
@@ -41,110 +60,95 @@ extern "C" {
   * @{
   */
 
-/**
-  * @brief  CRC HAL State Structure definition
+/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition 
+  * @{
   */
 typedef enum
 {
-  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
-} HAL_CRC_StateTypeDef;
-
-
-/**
-  * @brief  CRC Handle Structure definition
+  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
+
+}HAL_CRC_StateTypeDef;
+/** 
+  * @}
   */
+
+/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition   
+  * @{
+  */ 
 typedef struct
 {
-  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+  CRC_TypeDef                 *Instance;  /*!< Register base address   */
 
-  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+  HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
 
-  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+  __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
 
-} CRC_HandleTypeDef;
-/**
+}CRC_HandleTypeDef;
+/** 
   * @}
   */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
 /**
   * @}
-  */
+  */ 
 
-/* Exported macros -----------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup CRC_Exported_Macros CRC Exported Macros
   * @{
   */
 
-/** @brief Reset CRC handle state.
-  * @param  __HANDLE__ CRC handle.
+/** @brief Resets CRC handle state
+  * @param  __HANDLE__: CRC handle
   * @retval None
   */
 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
 
 /**
-  * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__ CRC handle
+  * @brief  Resets CRC Data Register.
+  * @param  __HANDLE__: CRC handle
   * @retval None
   */
 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
 
 /**
-  * @brief Store data in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @param __VALUE__  Value to be stored in the ID register
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @brief Stores a 8-bit data in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @param __VALUE__: 8-bit value to be stored in the ID register
   * @retval None
   */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) 
 
 /**
-  * @brief Return the data stored in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval Value of the ID register
+  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @retval 8-bit value of the ID register 
   */
 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
 /**
   * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup  CRC_Private_Macros CRC Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
+  */ 
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup CRC_Exported_Functions CRC Exported Functions
   * @{
   */
 
-/* Initialization and de-initialization functions  ****************************/
 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
 /**
   * @}
-  */
+  */ 
 
-/* Peripheral Control functions ***********************************************/
 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
@@ -152,33 +156,94 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
 /**
   * @}
-  */
+  */ 
 
-/* Peripheral State and Error functions ***************************************/
 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
 /**
   * @}
+  */ 
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRC_Private_Types CRC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRC_Private_Defines CRC Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Variables CRC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Constants CRC Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+  * @{
   */
 
 /**
   * @}
   */
 
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
+  * @{
+  */
+
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+  * @{
+  */
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_CRC_H */
+#endif /* __STM32F2xx_HAL_CRC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h

@@ -2,17 +2,35 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cryp.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */ 
@@ -22,11 +40,10 @@
 #define __STM32F2xx_HAL_CRYP_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-#if defined(CRYP)
-
+#if defined(STM32F215xx) || defined(STM32F217xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
@@ -34,8 +51,7 @@ extern "C" {
   * @{
   */
 
-/** @defgroup CRYP CRYP
-  * @brief CRYP HAL module driver.
+/** @addtogroup CRYP
   * @{
   */
 
@@ -45,315 +61,281 @@ extern "C" {
   * @{
   */
 
-/**
-  * @brief CRYP Init Structure definition
+/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
+  * @{
   */
 
 typedef struct
 {
-  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                                        This parameter can be a value of @ref CRYP_Data_Type */
-  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
-                                            This parameter can be a value of @ref CRYP_Key_Size */
-  uint32_t* pKey;                      /*!< The key used for encryption/decryption */
-  uint32_t* pInitVect;                 /*!< The initialization vector used also as initialization
-                                         counter in CTR mode */
-  uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC*/
- 
-  uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
-}CRYP_ConfigTypeDef;
-
-
-/**
-  * @brief  CRYP State Structure definition
-  */
-
-typedef enum
-{
-  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02U  /*!< CRYP BUSY, internal processing is ongoing  */
-}HAL_CRYP_STATETypeDef;
-
-
-/**
-  * @brief  CRYP handle Structure definition
-  */
-
-typedef struct __CRYP_HandleTypeDef
-{
-
-      CRYP_TypeDef                      *Instance;            /*!< CRYP registers base address */
-
-      CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
-
-      uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-      uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-      
-      __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP CRYP_Data_Type */
 
-      __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
+  uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length. 
+                             This parameter can be a value of @ref CRYP CRYP_Key_Size */
 
-      uint16_t                          Size;           /*!< length of input data in word */
+  uint8_t* pKey;        /*!< The key used for encryption/decryption */
 
-      uint32_t                          Phase;            /*!< CRYP peripheral phase */
+  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
+                             counter in CTR mode */
 
-      DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
+  uint8_t IVSize;       /*!< The size of initialization vector. 
+                             This parameter (called nonce size in CCM) is used only 
+                             in AES-128/192/256 encryption/decryption CCM mode */
 
-      DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
+  uint8_t TagSize;      /*!< The size of returned authentication TAG. 
+                             This parameter is used only in AES-128/192/256 
+                             encryption/decryption CCM mode */
 
-      HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
+  uint8_t* Header;      /*!< The header used in GCM and CCM modes */
 
-      __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
+  uint32_t HeaderSize;  /*!< The size of header buffer in bytes */
 
-      __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
+  uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
+                             This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
+}CRYP_InitTypeDef;
 
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback)    (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback  */
- void (*OutCpltCallback)   (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback)     (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback)  (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback  */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback  */
-
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-
-}CRYP_HandleTypeDef;
-
-
-/**
+/** 
   * @}
   */
 
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
-  * @brief  HAL CRYP Callback ID enumeration definition
+/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
   * @{
   */
+    
+
 typedef enum
 {
-  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x01U,    /*!< CRYP Input FIFO transfer completed callback ID */
-  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x02U,    /*!< CRYP Output FIFO transfer completed callback ID */
-  HAL_CRYP_ERROR_CB_ID             = 0x03U,    /*!< CRYP Error callback ID           */
-
-  HAL_CRYP_MSPINIT_CB_ID        = 0x04U,    /*!< CRYP MspInit callback ID         */
-  HAL_CRYP_MSPDEINIT_CB_ID      = 0x05U     /*!< CRYP MspDeInit callback ID       */
+  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */
+}HAL_CRYP_STATETypeDef;
 
-}HAL_CRYP_CallbackIDTypeDef;
-/**
+/** 
   * @}
   */
-
-/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
-  * @brief  HAL CRYP Callback pointer definition
+  
+/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
   * @{
   */
+    
 
-typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp);   /*!< pointer to a common CRYP callback function */
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
+  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
+  HAL_CRYP_PHASE_FINAL             = 0x03     /*!< CRYP peripheral is in final phase
+                                                   This is relevant only with CCM and GCM modes */
+}HAL_PhaseTypeDef;
 
-/**
+/** 
   * @}
   */
-
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  
+/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
   * @{
   */
+  
+typedef struct
+{
+      CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */
 
-/** @defgroup CRYP_Error_Definition   CRYP Error Definition
-  * @{
-  */
-#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
-#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
-#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
-#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
-#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
-#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
-#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
-#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
 
-/**
-  * @}
-  */
+      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
 
+      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
 
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
-  * @{
-  */
+      __IO uint16_t            CrypInCount;      /*!< Counter of input data */
 
-#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is word */
+      __IO uint16_t            CrypOutCount;     /*!< Counter of outputted data */
 
-/**
-  * @}
-  */
+      HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */
 
-/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
-  * @{
-  */
+      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */
 
-#define CRYP_DES_ECB     CRYP_CR_ALGOMODE_DES_ECB
-#define CRYP_DES_CBC     CRYP_CR_ALGOMODE_DES_CBC
-#define CRYP_TDES_ECB    CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC    CRYP_CR_ALGOMODE_TDES_CBC
-#define CRYP_AES_ECB     CRYP_CR_ALGOMODE_AES_ECB
-#define CRYP_AES_CBC     CRYP_CR_ALGOMODE_AES_CBC
-#define CRYP_AES_CTR     CRYP_CR_ALGOMODE_AES_CTR
+      DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */
 
-/**
+      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */
+
+      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+
+   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+}CRYP_HandleTypeDef;
+
+/** 
   * @}
   */
 
-/** @defgroup CRYP_Key_Size CRYP Key Size
+/** 
+  * @}
+  */
+    
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
   * @{
   */
 
-#define CRYP_KEYSIZE_128B         0x00000000U
+/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
+  * @{
+  */
+#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)
 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
-
-/**
+/**                                
   * @}
   */
 
-/** @defgroup CRYP_Data_Type CRYP Data Type
+/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
   * @{
   */
-
-#define CRYP_DATATYPE_32B         0x00000000U
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
+/**                                
+  * @}
+  */
 
+/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
+  * @{
+  */
+#define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003C)
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004)
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000C)
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014)
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001C)
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002C)
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034)
 /**
   * @}
   */
-
-/** @defgroup CRYP_Interrupt  CRYP Interrupt
+  
+/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
   * @{
   */
-
-#define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< Output FIFO Interrupt */
-
+#define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */
 /**
   * @}
   */
 
-/** @defgroup CRYP_Flags CRYP Flags
+/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
   * @{
   */
-
-/* Flags in the SR register */
-#define CRYP_FLAG_IFEM    CRYP_SR_IFEM  /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF    CRYP_SR_IFNF  /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE    CRYP_SR_OFNE  /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU    CRYP_SR_OFFU  /*!< Output FIFO is Full */
-#define CRYP_FLAG_BUSY    CRYP_SR_BUSY  /*!< The CRYP core is currently processing a block of data
-                                             or a key preparation (for AES decryption). */
-/* Flags in the RISR register */
-#define CRYP_FLAG_OUTRIS  0x01000002U  /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS   0x01000001U  /*!< Input FIFO service raw interrupt status*/
-
+#define CRYP_FLAG_BUSY   ((uint32_t)0x00000010)  /*!< The CRYP core is currently 
+                                                     processing a block of data 
+                                                     or a key preparation (for 
+                                                     AES decryption). */
+#define CRYP_FLAG_IFEM   ((uint32_t)0x00000001)  /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF   ((uint32_t)0x00000002)  /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE   ((uint32_t)0x00000004)  /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU   ((uint32_t)0x00000008)  /*!< Output FIFO is Full */
+#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002)  /*!< Output FIFO service raw 
+                                                      interrupt status */
+#define CRYP_FLAG_INRIS  ((uint32_t)0x01000001)  /*!< Input FIFO service raw 
+                                                      interrupt status */
 /**
   * @}
   */
 
-
 /**
   * @}
   */
 
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
   * @{
   */
-
+  
 /** @brief Reset CRYP handle state
-  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @retval None
   */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0)
-#else
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
 
 /**
   * @brief  Enable/Disable the CRYP peripheral.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @retval None
   */
-
 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
 
-/** @brief  Check whether the specified CRYP status flag is set or not.
+/**
+  * @brief  Flush the data FIFO.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
+
+/**
+  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  MODE: The algorithm mode.
+  * @retval None
+  */
+#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
+
+/** @brief  Check whether the specified CRYP flag is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values for CRYP:
-  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
-  *                                 or a key preparation (for AES decryption).
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data 
+  *                                 or a key preparation (for AES decryption). 
   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define CRYP_FLAG_MASK  0x0000001FU
 
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
                                                  ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
 
 /** @brief  Check whether the specified CRYP interrupt is set or not.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: specifies the interrupt to check.
-  *         This parameter can be one of the following values for CRYP:
-  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
-  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
-  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
+  *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
   */
-
 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Enable the CRYP interrupt.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: CRYP Interrupt.
-  *         This parameter can be one of the following values for CRYP:
-  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
-  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
   * @retval None
   */
-
 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the CRYP interrupt.
   * @param  __HANDLE__: specifies the CRYP handle.
-  * @param  __INTERRUPT__: CRYP Interrupt.
-  *         This parameter can be one of the following values for CRYP:
-  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
-  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+  * @param  __INTERRUPT__: CRYP interrupt.
   * @retval None
   */
-
 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
 
 /**
   * @}
-  */
+  */ 
+  
+
+
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
@@ -362,108 +344,131 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp);   /*!< point
 
 /** @addtogroup CRYP_Exported_Functions_Group1
   * @{
-  */
+  */    
 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 /**
   * @}
-  */
+  */ 
 
 /** @addtogroup CRYP_Exported_Functions_Group2
   * @{
-  */
-
-/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-
+  */  
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
 /**
   * @}
-  */
-
+  */ 
 
 /** @addtogroup CRYP_Exported_Functions_Group3
   * @{
-  */
-/* Interrupt Handler functions  **********************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
+  */  
+/* DES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+
+/* DES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
 /**
   * @}
-  */
+  */ 
 
+/** @addtogroup CRYP_Exported_Functions_Group4
+  * @{
+  */  
+/* TDES encryption/decryption using polling  **********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* TDES encryption/decryption using interrupt  ********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using DMA  **************************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
 /**
   * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros   CRYP Private Macros
-  * @{
-  */
+  */ 
 
-/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
+/** @addtogroup CRYP_Exported_Functions_Group5
   * @{
-  */
-
-#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB)   || \
-                                   ((ALGORITHM)  == CRYP_DES_CBC)   || \
-                                   ((ALGORITHM)  == CRYP_TDES_ECB)  || \
-                                   ((ALGORITHM)  == CRYP_TDES_CBC)  || \
-                                   ((ALGORITHM)  == CRYP_AES_ECB)   || \
-                                   ((ALGORITHM)  == CRYP_AES_CBC)   || \
-                                   ((ALGORITHM)  == CRYP_AES_CTR))
-
-#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
-                                 ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
-                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))
-
-#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \
-                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_1B))
-
+  */  
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
 /**
   * @}
-  */
+  */ 
 
+/** @addtogroup CRYP_Exported_Functions_Group6
+  * @{
+  */  
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
 /**
   * @}
-  */
-
+  */ 
 
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
+/** @addtogroup CRYP_Exported_Functions_Group7
   * @{
-  */
-
+  */  
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+/**
+  * @}
+  */ 
+  
 /**
   * @}
   */
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Types CRYP Private Types
   * @{
   */
 
 /**
   * @}
-  */
+  */ 
 
 /* Private variables ---------------------------------------------------------*/
 /** @defgroup CRYP_Private_Variables CRYP Private Variables
@@ -472,16 +477,37 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
 
 /**
   * @}
-  */
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
   * @{
   */
-
+#define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)
 /**
   * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+  * @{
   */
 
+#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
+                                       ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \
+                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
+
+
+#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
+                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))  
+
+
+ /**
+  * @}
+  */ 
+  
 /* Private functions ---------------------------------------------------------*/
 /** @defgroup CRYP_Private_Functions CRYP Private Functions
   * @{
@@ -490,18 +516,17 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
 /**
   * @}
   */
-
+     
+#endif /* STM32F215xx || STM32F217xx */
 
 /**
   * @}
-  */
-
+  */ 
 
-#endif /* CRYP */
 /**
   * @}
-  */
-
+  */ 
+  
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h

@@ -2,69 +2,79 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dac.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DAC_H
-#define STM32F2xx_HAL_DAC_H
+#ifndef __STM32F2xx_HAL_DAC_H
+#define __STM32F2xx_HAL_DAC_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-/** @addtogroup STM32F2xx_HAL_Driver
-  * @{
-  */
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
-#if defined(DAC)
+/** @addtogroup STM32F2xx_HAL_Driver
+  * @{
+  */
 
 /** @addtogroup DAC
   * @{
   */
 
 /* Exported types ------------------------------------------------------------*/
-
 /** @defgroup DAC_Exported_Types DAC Exported Types
   * @{
   */
 
-/**
-  * @brief  HAL State structures definition
+/** 
+  * @brief HAL State structures definition
   */
 typedef enum
 {
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
-
-} HAL_DAC_StateTypeDef;
-
-/**
-  * @brief  DAC handle Structure definition
+  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
+}HAL_DAC_StateTypeDef;
+ 
+/** 
+  * @brief DAC handle Structure definition
   */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
 typedef struct
-#endif
 {
   DAC_TypeDef                 *Instance;     /*!< Register base address             */
 
@@ -78,67 +88,24 @@ typedef struct
 
   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
 
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
-
-  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}DAC_HandleTypeDef;
 
-} DAC_HandleTypeDef;
-
-
-/**
-  * @brief   DAC Configuration regular Channel structure definition
+/** 
+  * @brief DAC Configuration regular Channel structure definition
   */
 typedef struct
 {
-  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
-                                              This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                               This parameter can be a value of @ref DAC_output_buffer */
-
-} DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL DAC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
-  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
-  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
-  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
-  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
-  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
-  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
-  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
-  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
-  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
-  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
-} HAL_DAC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL DAC Callback pointer definition
-  */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
+                                   This parameter can be a value of @ref DAC_trigger_selection */
 
+  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                   This parameter can be a value of @ref DAC_output_buffer */
+}DAC_ChannelConfTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-
 /** @defgroup DAC_Exported_Constants DAC Exported Constants
   * @{
   */
@@ -146,82 +113,75 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 /** @defgroup DAC_Error_Code DAC Error Code
   * @{
   */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
+#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DAM underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DAM underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
 /**
   * @}
   */
 
-/** @defgroup DAC_trigger_selection DAC trigger selection
+/** @defgroup DAC_trigger_selection DAC Trigger Selection
   * @{
   */
-#define DAC_TRIGGER_NONE                0x00000000U                                                      /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO             (DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO             (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO             (                                                   DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO             (                                  DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE            (DAC_CR_TSEL1                                     | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
 
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
 /**
   * @}
   */
 
-/** @defgroup DAC_output_buffer DAC output buffer
+/** @defgroup DAC_output_buffer  DAC Output Buffer
   * @{
   */
-#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE           (DAC_CR_BOFF1)
-
+#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
 /**
   * @}
   */
 
-/** @defgroup DAC_Channel_selection DAC Channel selection
+/** @defgroup DAC_Channel_selection DAC Channel Selection
   * @{
   */
-#define DAC_CHANNEL_1                      0x00000000U
-#define DAC_CHANNEL_2                      0x00000010U
+#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
 /**
   * @}
   */
 
-/** @defgroup DAC_data_alignment DAC data alignment
+/** @defgroup DAC_data_alignment DAC Data Alignment
   * @{
   */
-#define DAC_ALIGN_12B_R                    0x00000000U
-#define DAC_ALIGN_12B_L                    0x00000004U
-#define DAC_ALIGN_8B_R                     0x00000008U
-
+#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
 /**
   * @}
   */
 
-/** @defgroup DAC_flags_definition DAC flags definition
+/** @defgroup DAC_flags_definition DAC Flags Definition
   * @{
-  */
-#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
-
+  */ 
+#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
 /**
   * @}
   */
 
-/** @defgroup DAC_IT_definition  DAC IT definition
+/** @defgroup DAC_IT_definition DAC IT Definition
   * @{
-  */
-#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
-
+  */ 
+#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
 /**
   * @}
   */
@@ -231,82 +191,47 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   */
 
 /* Exported macro ------------------------------------------------------------*/
-
 /** @defgroup DAC_Exported_Macros DAC Exported Macros
   * @{
   */
 
-/** @brief Reset DAC handle state.
-  * @param  __HANDLE__ specifies the DAC handle.
+/** @brief Reset DAC handle state
+  * @param  __HANDLE__: specifies the DAC handle.
   * @retval None
   */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
-                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
-                                                     } while(0)
-#else
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __DAC_Channel__ specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Disable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __DAC_Channel__ specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Set DHR12R1 alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
 
-/** @brief  Set DHR12R2 alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
+/** @brief Enable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __DAC_Channel__: specifies the DAC channel
   * @retval None
   */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
 
-/** @brief  Set DHR12RD alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
+/** @brief Disable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __DAC_Channel__: specifies the DAC channel.
   * @retval None
   */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
 
-/** @brief Enable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+/** @brief Enable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
   * @retval None
   */
 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
 
-/** @brief Disable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+/** @brief Disable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
   * @retval None
   */
 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
 
-/** @brief  Check whether the specified DAC interrupt source is enabled or not.
-  * @param __HANDLE__ DAC handle
-  * @param __INTERRUPT__ DAC interrupt source to check
+/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
+  * @param __HANDLE__: DAC handle
+  * @param __INTERRUPT__: DAC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -315,134 +240,150 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to get.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
   * @retval None
   */
 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
+  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
   * @retval None
   */
 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
 /**
   * @}
   */
 
-/* Private macro -------------------------------------------------------------*/
+/* Include DAC HAL Extension module */
+#include "stm32f2xx_hal_dac_ex.h"   
 
-/** @defgroup DAC_Private_Macros DAC Private Macros
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_Exported_Functions
   * @{
   */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
 
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
 /**
   * @}
   */
 
-/* Include DAC HAL Extended module */
-#include "stm32f2xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
+/** @addtogroup DAC_Exported_Functions_Group2
   * @{
   */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+/**
+  * @}
+  */
 
-/** @addtogroup DAC_Exported_Functions_Group1
+/** @addtogroup DAC_Exported_Functions_Group3
   * @{
   */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
-
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
 /**
   * @}
   */
 
-/** @addtogroup DAC_Exported_Functions_Group2
+/** @addtogroup DAC_Exported_Functions_Group4
   * @{
   */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                    uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/* Peripheral State functions *************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
 
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
-                                               pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
 
-/** @addtogroup DAC_Exported_Functions_Group3
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_Private_Constants DAC Private Constants
   * @{
   */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
 
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
 /**
   * @}
   */
 
-/** @addtogroup DAC_Exported_Functions_Group4
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
   * @{
   */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                 ((CHANNEL) == DAC_CHANNEL_2))
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
 
-/**
-  * @}
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+/** @brief Set DHR12R1 alignment
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12R2 alignment
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
   */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12RD alignment
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
 
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
 /** @defgroup DAC_Private_Functions DAC Private Functions
   * @{
   */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
@@ -451,18 +392,14 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
   * @}
   */
 
-#endif /* DAC */
-
 /**
   * @}
   */
-
+  
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /*STM32F2xx_HAL_DAC_H */
+#endif /*__STM32F2xx_HAL_DAC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h

@@ -1,83 +1,92 @@
 /**
   ******************************************************************************
-  * @file    stm32f2xx_hal_dac_ex.h
+  * @file    stm32f2xx_hal_dac.h
   * @author  MCD Application Team
-  * @brief   Header file of DAC HAL Extended module.
+  * @version V1.1.0
+  * @date    09-October-2015
+  * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DAC_EX_H
-#define STM32F2xx_HAL_DAC_EX_H
+#ifndef __STM32F2xx_HAL_DAC_EX_H
+#define __STM32F2xx_HAL_DAC_EX_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-/** @addtogroup STM32F2xx_HAL_Driver
-  * @{
-  */
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
-#if defined(DAC)
+/** @addtogroup STM32F2xx_HAL_Driver
+  * @{
+  */
 
 /** @addtogroup DACEx
   * @{
   */
 
 /* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL State structures definition
-  */
-
 /* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+/** @defgroup DACEx_Exported_Constants DAC Exported Constants
   * @{
   */
 
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
   * @{
   */
-#define DAC_LFSRUNMASK_BIT0                0x00000000U                                                         /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            0x00000000U                                                         /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
+#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
 /**
   * @}
   */
@@ -87,24 +96,46 @@ extern "C" {
   */
 
 /* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
 
+/** @addtogroup DACEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
 
-/* Private macro -------------------------------------------------------------*/
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+/**
+  * @}
+  */
 
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Constants DAC Private Constants
   * @{
   */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
 
+/**
+  * @}
+  */
 
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DACEx_Private_Macros DAC Private Macros
+  * @{
+  */
 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -129,52 +160,18 @@ extern "C" {
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
-
 
 /**
   * @}
   */
 
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Private_Functions
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DAC Private Functions
   * @{
   */
-
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
 /**
   * @}
   */
@@ -186,17 +183,11 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
-
-#endif /* DAC */
-
-/**
-  * @}
-  */
-
+  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /*STM32F2xx_HAL_DAC_EX_H */
+#endif /*__STM32F2xx_HAL_DAC_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h

@@ -2,33 +2,51 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dcmi.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DCMI_H
-#define STM32F2xx_HAL_DCMI_H
+#ifndef __STM32F2xx_HAL_DCMI_H
+#define __STM32F2xx_HAL_DCMI_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
+#if defined(STM32F207xx) || defined(STM32F217xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
-#if defined (DCMI)
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -37,49 +55,35 @@ extern "C" {
 /** @addtogroup DCMI DCMI
   * @brief DCMI HAL module driver
   * @{
-  */
+  */  
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Types DCMI Exported Types
   * @{
   */
-/**
-  * @brief  HAL DCMI State structures definition
+/** 
+  * @brief DCMI Error source
   */
 typedef enum
-{
-  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
-  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
-  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
-  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
-  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
-  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
-} HAL_DCMI_StateTypeDef;
+{ 
+  DCMI_ERROR_SYNC = 1,     /*!< Synchronisation error */
+  DCMI_OVERRUN   = 2,      /*!< DCMI Overrun */
+}DCMI_ErrorTypeDef;
 
-/**
-  * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition
-  */
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */ 
 typedef struct
 {
   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
-} DCMI_CodesInitTypeDef;
+}DCMI_CodesInitTypeDef;
 
-/**
-  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
-  */
-typedef struct
-{
-  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
-  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
-  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
-  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
-} DCMI_SyncUnmaskTypeDef;
-/**
+/** 
   * @brief   DCMI Init structure definition
-  */
+  */ 
 typedef struct
 {
   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
@@ -100,17 +104,29 @@ typedef struct
   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
 
-  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the
-                                             line/frame end delimiter */
+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
 
-  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                
                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
-} DCMI_InitTypeDef;
 
-/**
+}DCMI_InitTypeDef;
+
+/** 
+  * @brief  HAL DCMI State structures definition
+  */ 
+typedef enum
+{
+  HAL_DCMI_STATE_RESET             = 0x00,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04   /*!< DCMI error state                      */
+}HAL_DCMI_StateTypeDef;
+
+/** 
   * @brief  DCMI handle Structure definition
   */
-typedef struct __DCMI_HandleTypeDef
+typedef struct
 {
   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
 
@@ -131,37 +147,13 @@ typedef struct __DCMI_HandleTypeDef
   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
 
   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-  void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Frame Event Callback */
-  void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Vsync Event Callback */
-  void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Line Event Callback  */
-  void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi);            /*!< DCMI Error Callback       */
-  void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);          /*!< DCMI Msp Init callback    */
-  void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Msp DeInit callback  */
-#endif  /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-} DCMI_HandleTypeDef;
-
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-typedef enum
-{
-  HAL_DCMI_FRAME_EVENT_CB_ID    = 0x00U,    /*!< DCMI Frame Event Callback ID */
-  HAL_DCMI_VSYNC_EVENT_CB_ID    = 0x01U,    /*!< DCMI Vsync Event Callback ID */
-  HAL_DCMI_LINE_EVENT_CB_ID     = 0x02U,    /*!< DCMI Line Event Callback ID  */
-  HAL_DCMI_ERROR_CB_ID          = 0x03U,    /*!< DCMI Error Callback ID       */
-  HAL_DCMI_MSPINIT_CB_ID        = 0x04U,    /*!< DCMI MspInit callback ID     */
-  HAL_DCMI_MSPDEINIT_CB_ID      = 0x05U     /*!< DCMI MspDeInit callback ID   */
-
-} HAL_DCMI_CallbackIDTypeDef;
-
-typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-
 
+}DCMI_HandleTypeDef;
 /**
   * @}
   */
-/* Exported constants --------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
   * @{
   */
@@ -169,22 +161,18 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_Error_Code DCMI Error Code
   * @{
   */
-#define HAL_DCMI_ERROR_NONE             ((uint32_t)0x00000000U)  /*!< No error              */
-#define HAL_DCMI_ERROR_OVR              ((uint32_t)0x00000001U)  /*!< Overrun error         */
-#define HAL_DCMI_ERROR_SYNC             ((uint32_t)0x00000002U)  /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT          ((uint32_t)0x00000020U)  /*!< Timeout error         */
-#define HAL_DCMI_ERROR_DMA              ((uint32_t)0x00000040U)  /*!< DMA error             */
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)  /*!< Invalid callback error */
-#endif
+#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
+#define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001)    /*!< Overflow error        */
+#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
 /**
   * @}
   */
 
 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
   * @{
-  */
-#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously 
+  */ 
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously 
                                                                     into the destination memory through the DMA             */
 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of 
                                                                     frame and then transfers a single frame through the DMA */
@@ -194,8 +182,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
   * @{
-  */
-#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
+  */ 
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
                                                                    is synchronized with the HSYNC/VSYNC signals                  */
 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with 
                                                                    synchronization codes embedded in the data flow               */
@@ -207,17 +195,17 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
   * @{
   */
-#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
 
 /**
   * @}
   */
-
+ 
 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
   * @{
   */
-#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
 
 /**
@@ -226,8 +214,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
   * @{
-  */
-#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */
+  */ 
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
 
 /**
@@ -237,7 +225,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
   * @{
   */
-#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< Mode JPEG Disabled  */
 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
 
 /**
@@ -247,7 +235,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
   * @{
   */
-#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
 
@@ -258,7 +246,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
   * @{
   */
-#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
@@ -270,7 +258,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
   * @{
   */
-#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFFU)  /*!< Window coordinate */
+#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
 
 /**
   * @}
@@ -278,8 +266,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /** @defgroup DCMI_Window_Height DCMI Window Height
   * @{
-  */
-#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */
+  */ 
+#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
 
 /**
   * @}
@@ -288,11 +276,11 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
   * @{
   */
-#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
-#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
-#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
-#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
-#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
+#define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
 /**
   * @}
   */
@@ -301,94 +289,82 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
   * @{
   */
 
-/**
+/** 
   * @brief   DCMI SR register
-  */
-#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
-#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
-#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
-/**
-  * @brief   DCMI RIS register
-  */
-#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
-#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */
-#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */
-#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
-#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */
-/**
-  * @brief   DCMI MIS register
-  */
-#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */
-#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
-#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
-#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
-#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint32_t)0x2001)
+#define DCMI_FLAG_VSYNC     ((uint32_t)0x2002)
+#define DCMI_FLAG_FNE       ((uint32_t)0x2004)
+/** 
+  * @brief   DCMI RISR register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
+#define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
+/** 
+  * @brief   DCMI MISR register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001)
+#define DCMI_FLAG_OVFMI      ((uint32_t)0x1002)
+#define DCMI_FLAG_ERRMI      ((uint32_t)0x1004)
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008)
+#define DCMI_FLAG_LINEMI     ((uint32_t)0x1010)
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
+ 
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
   * @{
   */
-
+  
 /** @brief Reset DCMI handle state
-  * @param  __HANDLE__ specifies the DCMI handle.
+  * @param  __HANDLE__: specifies the DCMI handle.
   * @retval None
   */
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
-                                                     (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
-                                                     (__HANDLE__)->MspInitCallback = NULL;      \
-                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
-                                                   } while(0)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
 
 /**
   * @brief  Enable the DCMI.
-  * @param  __HANDLE__ DCMI handle
+  * @param  __HANDLE__: DCMI handle
   * @retval None
   */
 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
 
 /**
   * @brief  Disable the DCMI.
-  * @param  __HANDLE__ DCMI handle
+  * @param  __HANDLE__: DCMI handle
   * @retval None
   */
 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
 
 /* Interrupt & Flag management */
 /**
-  * @brief  Get the DCMI pending flag.
-  * @param  __HANDLE__ DCMI handle
-  * @param  __FLAG__ Get the specified flag.
-  *         This parameter can be one of the following values (no combination allowed)
-  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
-  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
-  *            @arg DCMI_FLAG_FNE: FIFO empty flag
+  * @brief  Get the DCMI pending flags.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: Get the specified flag.
+  *         This parameter can be any combination of the following values:
   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
-  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
   *            @arg DCMI_FLAG_LINERI: Line flag mask
-  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
-  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
-  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
-  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
-  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
   * @retval The state of FLAG.
   */
 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
-((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
- (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
 
 /**
   * @brief  Clear the DCMI pending flags.
-  * @param  __HANDLE__ DCMI handle
-  * @param  __FLAG__ specifies the flag to clear.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: specifies the flag to clear.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
@@ -401,8 +377,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /**
   * @brief  Enable the specified DCMI interrupts.
-  * @param  __HANDLE__    DCMI handle
-  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+  * @param  __HANDLE__:    DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -415,8 +391,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /**
   * @brief  Disable the specified DCMI interrupts.
-  * @param  __HANDLE__ DCMI handle
-  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -429,8 +405,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 
 /**
   * @brief  Check whether the specified DCMI interrupt has occurred or not.
-  * @param  __HANDLE__ DCMI handle
-  * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -444,38 +420,32 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
-
+      
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
+/** @addtogroup DCMI_Exported_Functions
   * @{
   */
 
-/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+/** @addtogroup DCMI_Exported_Functions_Group1 
  * @{
  */
+ 
 /* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
 /**
   * @}
   */
-
-/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
+  
+/** @addtogroup DCMI_Exported_Functions_Group2 
  * @{
  */
+ 
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
@@ -484,21 +454,19 @@ void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
-
-/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+  
+/** @addtogroup DCMI_Exported_Functions_Group3 
  * @{
  */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
-HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
-
+HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
-
-/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
+  
+/** @addtogroup DCMI_Exported_Functions_Group4 
  * @{
  */
 /* Peripheral State functions *************************************************/
@@ -514,46 +482,38 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DCMI_Private_Constants DCMI Private Constants
-  * @{
-  */
-#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */
-#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */
-/**
-  * @}
-  */
+/* Private constants ---------------------------------------------------------*/   
 /* Private macro -------------------------------------------------------------*/
 /** @defgroup DCMI_Private_Macros DCMI Private Macros
   * @{
   */
 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
                                    ((MODE) == DCMI_MODE_SNAPSHOT))
-
+                                                                                                
 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
-
+                              
 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
-
+                                      
 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
-
+                                     
 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
-
+                                     
 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
-
+                                     
 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
-
+                                    
 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
                                     ((DATA) == DCMI_EXTEND_DATA_14B))
-
+                                    
 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
 
 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
@@ -566,23 +526,26 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
   * @{
   */
-
+  
 /**
   * @}
   */
+      
+#endif /* STM32F207xx || STM32F217xx */
+
 
 /**
   * @}
   */
+    
 /**
   * @}
-  */
-#endif /* DCMI */
+  */ 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_DCMI_H */
+#endif /* __STM32F2xx_HAL_DCMI_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h

@@ -2,18 +2,36 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_def.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -29,7 +47,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx.h"
 #include "Legacy/stm32_hal_legacy.h"
-#include <stddef.h>
+#include <stdio.h>
 
 /* Exported types ------------------------------------------------------------*/
 
@@ -38,10 +56,10 @@
   */  
 typedef enum 
 {
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
 } HAL_StatusTypeDef;
 
 /** 
@@ -49,27 +67,26 @@ typedef enum
   */
 typedef enum 
 {
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U  
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01  
 } HAL_LockTypeDef;
 
 /* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY      0xFFFFFFFF
 
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY      0xFFFFFFFFU
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
 
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)               \
                         do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0U)
+                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \
+                          } while(0)
 
+#define UNUSED(x) ((void)(x))
+							  
 /** @brief Reset the Handle's State field.
-  * @param  __HANDLE__ specifies the Peripheral Handle.
+  * @param __HANDLE__: specifies the Peripheral Handle.
   * @note  This macro can be used for the following purpose: 
   *          - When the Handle is declared as local variable; before passing it as parameter
   *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
@@ -83,11 +100,11 @@ typedef enum
   *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
   * @retval None
   */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
 
-#if (USE_RTOS == 1U)
+#if (USE_RTOS == 1)
   /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
+  #error " USE_RTOS should be 0 in the current HAL release "
 #else
   #define __HAL_LOCK(__HANDLE__)                                           \
                                 do{                                        \
@@ -99,15 +116,15 @@ typedef enum
                                     {                                      \
                                        (__HANDLE__)->Lock = HAL_LOCKED;    \
                                     }                                      \
-                                  }while (0U)
+                                  }while (0)
 
   #define __HAL_UNLOCK(__HANDLE__)                                          \
                                   do{                                       \
                                       (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0U)
+                                    }while (0)
 #endif /* USE_RTOS */
 
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if  defined ( __GNUC__ )
   #ifndef __weak
     #define __weak   __attribute__((weak))
   #endif /* __weak */
@@ -116,11 +133,11 @@ typedef enum
   #endif /* __packed */
 #endif /* __GNUC__ */
 
-
+  
 /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined   (__GNUC__)        /* GNU Compiler */
   #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4U)))
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
   #endif /* __ALIGN_END */
   #ifndef __ALIGN_BEGIN  
     #define __ALIGN_BEGIN
@@ -131,7 +148,7 @@ typedef enum
   #endif /* __ALIGN_END */
   #ifndef __ALIGN_BEGIN      
     #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4U)
+      #define __ALIGN_BEGIN    __align(4)  
     #elif defined (__ICCARM__)    /* IAR Compiler */
       #define __ALIGN_BEGIN 
     #endif /* __CC_ARM */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_DMA_H
@@ -102,12 +120,17 @@ typedef struct
   */
 typedef enum
 {
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
-  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
+  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
+  HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
+  HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
+  HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
+  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
+  HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 }HAL_DMA_StateTypeDef;
 
 /** 
@@ -115,24 +138,10 @@ typedef enum
   */
 typedef enum
 {
-  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
+  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 }HAL_DMA_LevelCompleteTypeDef;
 
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
-  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
-  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
 /** 
   * @brief  DMA handle Structure definition
   */
@@ -146,26 +155,21 @@ typedef struct __DMA_HandleTypeDef
 
   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 
-  void                       *Parent;                                                      /*!< Parent object state                    */ 
+  void                       *Parent;                                                      /*!< Parent object state                    */  
 
   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 
   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 
   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
-  
-  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
-  
+
   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-  
-  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  
 
- __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
-  
+ __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                         */
+
  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
 
- uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
- 
+ uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */ 
 }DMA_HandleTypeDef;
 
 /**
@@ -183,14 +187,11 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA Error Code 
   * @{
   */ 
-#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
-#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
-#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
-#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
-#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
-#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
-#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */ 
-#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */     
+#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
+#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
+#define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
+#define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
+#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 /**
   * @}
   */
@@ -199,14 +200,14 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA channel selection 
   * @{
   */ 
-#define DMA_CHANNEL_0        0x00000000U  /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1        0x02000000U  /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2        0x04000000U  /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3        0x06000000U  /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4        0x08000000U  /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5        0x0A000000U  /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6        0x0C000000U  /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7        0x0E000000U  /*!< DMA Channel 7 */
+#define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
 /**
   * @}
   */
@@ -215,19 +216,19 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA data transfer direction 
   * @{
   */ 
-#define DMA_PERIPH_TO_MEMORY         0x00000000U      /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 /**
   * @}
-  */
+  */  
         
 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
   * @brief    DMA peripheral incremented mode 
   * @{
   */ 
 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
-#define DMA_PINC_DISABLE       0x00000000U     /*!< Peripheral increment mode disable */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
 /**
   * @}
   */ 
@@ -237,7 +238,7 @@ typedef struct __DMA_HandleTypeDef
   * @{
   */ 
 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
-#define DMA_MINC_DISABLE        0x00000000U     /*!< Memory increment mode disable */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
 /**
   * @}
   */
@@ -246,7 +247,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA peripheral data size 
   * @{
   */ 
-#define DMA_PDATAALIGN_BYTE          0x00000000U        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
 /**
@@ -257,7 +258,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA memory data size 
   * @{ 
   */
-#define DMA_MDATAALIGN_BYTE          0x00000000U        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 /**
@@ -268,7 +269,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA mode 
   * @{
   */ 
-#define DMA_NORMAL         0x00000000U       /*!< Normal mode                  */
+#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
 /**
@@ -279,7 +280,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA priority levels 
   * @{
   */
-#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level: Low       */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
@@ -291,7 +292,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA FIFO direct mode
   * @{
   */
-#define DMA_FIFOMODE_DISABLE        0x00000000U       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
 /**
   * @}
@@ -301,7 +302,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA FIFO level 
   * @{
   */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
@@ -313,7 +314,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA memory burst 
   * @{
   */ 
-#define DMA_MBURST_SINGLE       0x00000000U
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)  
 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  
 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  
 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  
@@ -325,10 +326,10 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA peripheral burst 
   * @{
   */ 
-#define DMA_PBURST_SINGLE       0x00000000U
-#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)  
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)  
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)  
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)  
 /**
   * @}
   */
@@ -341,7 +342,7 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE                         0x00000080U
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
 /**
   * @}
   */
@@ -350,26 +351,26 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA flag definitions 
   * @{
   */ 
-#define DMA_FLAG_FEIF0_4                    0x00000001U
-#define DMA_FLAG_DMEIF0_4                   0x00000004U
-#define DMA_FLAG_TEIF0_4                    0x00000008U
-#define DMA_FLAG_HTIF0_4                    0x00000010U
-#define DMA_FLAG_TCIF0_4                    0x00000020U
-#define DMA_FLAG_FEIF1_5                    0x00000040U
-#define DMA_FLAG_DMEIF1_5                   0x00000100U
-#define DMA_FLAG_TEIF1_5                    0x00000200U
-#define DMA_FLAG_HTIF1_5                    0x00000400U
-#define DMA_FLAG_TCIF1_5                    0x00000800U
-#define DMA_FLAG_FEIF2_6                    0x00010000U
-#define DMA_FLAG_DMEIF2_6                   0x00040000U
-#define DMA_FLAG_TEIF2_6                    0x00080000U
-#define DMA_FLAG_HTIF2_6                    0x00100000U
-#define DMA_FLAG_TCIF2_6                    0x00200000U
-#define DMA_FLAG_FEIF3_7                    0x00400000U
-#define DMA_FLAG_DMEIF3_7                   0x01000000U
-#define DMA_FLAG_TEIF3_7                    0x02000000U
-#define DMA_FLAG_HTIF3_7                    0x04000000U
-#define DMA_FLAG_TCIF3_7                    0x08000000U
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
 /**
   * @}
   */
@@ -381,14 +382,14 @@ typedef struct __DMA_HandleTypeDef
 /* Exported macro ------------------------------------------------------------*/
 
 /** @brief Reset DMA handle state
-  * @param  __HANDLE__ specifies the DMA handle.
+  * @param  __HANDLE__: specifies the DMA handle.
   * @retval None
   */
 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 
 /**
   * @brief  Return the current DMA Stream FIFO filled level.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The FIFO filling state.
   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
   *                                              and not empty.
@@ -402,14 +403,14 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Enable the specified DMA Stream.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval None
   */
 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 
 /**
   * @brief  Disable the specified DMA Stream.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval None
   */
 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
@@ -418,7 +419,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream transfer complete flag.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The specified transfer complete flag index.
   */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -438,7 +439,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream half transfer complete flag.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -458,7 +459,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream transfer error flag.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -478,7 +479,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream FIFO error flag.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The specified FIFO error flag index.
   */
 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
@@ -498,7 +499,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream direct mode error flag.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   * @retval The specified direct mode error flag index.
   */
 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
@@ -518,8 +519,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Get the DMA Stream pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -536,8 +537,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Clear the DMA Stream pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -554,8 +555,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Enable the specified DMA Stream interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
   *        This parameter can be any combination of the following values:
   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -569,8 +570,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Disable the specified DMA Stream interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
   *         This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -584,8 +585,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -600,8 +601,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Writes the number of data units to be transferred on the DMA Stream.
-  * @param  __HANDLE__ DMA handle
-  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) 
   *          Number of data items depends only on the Peripheral data format.
   *            
   * @note   If Peripheral data format is Bytes: number of data units is equal 
@@ -619,7 +620,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
-  * @param  __HANDLE__ DMA handle
+  * @param  __HANDLE__: DMA handle
   *   
   * @retval The number of remaining data units in the current DMA Stream transfer.
   */
@@ -653,13 +654,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
 /**
   * @}
   */ 
@@ -703,7 +699,7 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
 
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 
 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
                                             ((STATE) == DMA_PINC_DISABLE))

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h

@@ -2,17 +2,35 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -47,8 +65,9 @@
   */ 
 typedef enum
 {
-  MEMORY0      = 0x00U,    /*!< Memory 0     */
-  MEMORY1      = 0x01U     /*!< Memory 1     */
+  MEMORY0      = 0x00,    /*!< Memory 0     */
+  MEMORY1      = 0x01,    /*!< Memory 1     */
+
 }HAL_DMA_MemoryTypeDef;
 
 /**

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_FLASH_H
@@ -46,7 +64,7 @@
   */
 typedef enum 
 {
-  FLASH_PROC_NONE = 0U, 
+  FLASH_PROC_NONE = 0, 
   FLASH_PROC_SECTERASE,
   FLASH_PROC_MASSERASE,
   FLASH_PROC_PROGRAM
@@ -87,12 +105,12 @@ typedef struct
   * @brief    FLASH Error Code 
   * @{
   */ 
-#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */
-#define HAL_FLASH_ERROR_PGS          0x00000001U    /*!< Programming Sequence error    */
-#define HAL_FLASH_ERROR_PGP          0x00000002U    /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA          0x00000004U    /*!< Programming Alignment error   */
-#define HAL_FLASH_ERROR_WRP          0x00000008U    /*!< Write protection error        */
-#define HAL_FLASH_ERROR_OPERATION    0x00000010U    /*!< Operation Error               */
+#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000)    /*!< No error                      */
+#define HAL_FLASH_ERROR_PGS          ((uint32_t)0x00000001)    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000002)    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000004)    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000008)    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000010)    /*!< Operation Error               */
 /**
   * @}
   */
@@ -100,10 +118,10 @@ typedef struct
 /** @defgroup FLASH_Type_Program FLASH Type Program
   * @{
   */ 
-#define FLASH_TYPEPROGRAM_BYTE        0x00U  /*!< Program byte (8-bit) at a specified address           */
-#define FLASH_TYPEPROGRAM_HALFWORD    0x01U  /*!< Program a half-word (16-bit) at a specified address   */
-#define FLASH_TYPEPROGRAM_WORD        0x02U  /*!< Program a word (32-bit) at a specified address        */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x03U  /*!< Program a double word (64-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00)  /*!< Program byte (8-bit) at a specified address           */
+#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01)  /*!< Program a half-word (16-bit) at a specified address   */
+#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02)  /*!< Program a word (32-bit) at a specified address        */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03)  /*!< Program a double word (64-bit) at a specified address */
 /**
   * @}
   */
@@ -127,8 +145,8 @@ typedef struct
   * @brief FLASH Interrupt definition
   * @{
   */ 
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE           /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   0x02000000U  /*!< Error Interrupt source                  */
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source                  */
 /**
   * @}
   */  
@@ -136,11 +154,11 @@ typedef struct
 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
   * @{
   */
-#define FLASH_PSIZE_BYTE           0x00000000U
-#define FLASH_PSIZE_HALF_WORD      0x00000100U
-#define FLASH_PSIZE_WORD           0x00000200U
-#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U
-#define CR_PSIZE_MASK              0xFFFFFCFFU
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
 /**
   * @}
   */ 
@@ -149,10 +167,10 @@ typedef struct
   * @{
   */ 
 #define RDP_KEY                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               0x45670123U
-#define FLASH_KEY2               0xCDEF89ABU
-#define FLASH_OPT_KEY1           0x08192A3BU
-#define FLASH_OPT_KEY2           0x4C5D6E7FU
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
 /**
   * @}
   */ 
@@ -167,7 +185,7 @@ typedef struct
   */
 /**
   * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency                   
+  * @param  __LATENCY__: FLASH Latency                   
   *         The value of this parameter depend on device used within the same series
   * @retval none
   */ 
@@ -223,7 +241,7 @@ typedef struct
   */
 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
                                                   FLASH->ACR &= ~FLASH_ACR_ICRST; \
-                                                 }while(0U)
+                                                 }while(0)
 
 /**
   * @brief  Resets the FLASH data Cache.
@@ -232,10 +250,10 @@ typedef struct
   */
 #define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
                                            FLASH->ACR &= ~FLASH_ACR_DCRST; \
-                                          }while(0U)
+                                          }while(0)
 /**
   * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ FLASH interrupt 
+  * @param  __INTERRUPT__ : FLASH interrupt 
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
   *     @arg FLASH_IT_ERR: Error Interrupt    
@@ -245,7 +263,7 @@ typedef struct
 
 /**
   * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ FLASH interrupt 
+  * @param  __INTERRUPT__ : FLASH interrupt 
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
   *     @arg FLASH_IT_ERR: Error Interrupt    
@@ -255,8 +273,8 @@ typedef struct
 
 /**
   * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__ specifies the FLASH flags to check.
-  *          This parameter can be any combination of the following values:
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
@@ -266,11 +284,11 @@ typedef struct
   *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
   * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)) == (__FLAG__))
 
 /**
-  * @brief  Clear the specified FLASH flags.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
   *          This parameter can be any combination of the following values:
   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
@@ -351,23 +369,23 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
 /** 
   * @brief   ACR register byte 0 (Bits[7:0]) base address  
   */ 
-#define ACR_BYTE0_ADDRESS           0x40023C00U
+#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
 /** 
   * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
   */ 
-#define OPTCR_BYTE0_ADDRESS         0x40023C14U
+#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
 /** 
   * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
   */ 
-#define OPTCR_BYTE1_ADDRESS         0x40023C15U
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
 /** 
   * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
   */ 
-#define OPTCR_BYTE2_ADDRESS         0x40023C16U
+#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
 /** 
   * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
   */ 
-#define OPTCR_BYTE3_ADDRESS         0x40023C17U
+#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
 
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_FLASH_EX_H
@@ -50,17 +68,17 @@ typedef struct
                              This parameter can be a value of @ref FLASHEx_Type_Erase */
 
   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */
+                             This parameter must be a value of @ref FLASHEx_Banks */        
 
   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
-                             This parameter must be a value of @ref FLASHEx_Sectors */
-
+                             This parameter must be a value of @ref FLASHEx_Sectors */        
+  
   uint32_t NbSectors;   /*!< Number of sectors to be erased.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/           
+                                                          
   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
-                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */        
+  
 } FLASH_EraseInitTypeDef;
 
 /**
@@ -99,8 +117,8 @@ typedef struct
 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
   * @{
   */ 
-#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */
-#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */
+#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00)  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01)  /*!< Flash Mass erase activation */
 /**
   * @}
   */
@@ -108,10 +126,10 @@ typedef struct
 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
   * @{
   */ 
-#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */
-#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */
-#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */
-#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00)  /*!< Device operating range: 1.8V to 2.1V                */
+#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01)  /*!< Device operating range: 2.1V to 2.7V                */
+#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02)  /*!< Device operating range: 2.7V to 3.6V                */
+#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
 /**
   * @}
   */
@@ -119,8 +137,8 @@ typedef struct
 /** @defgroup FLASHEx_WRP_State FLASH WRP State
   * @{
   */ 
-#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00)  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01)  /*!< Enable the write protection of the desired bank 1 sectors  */
 /**
   * @}
   */
@@ -128,10 +146,10 @@ typedef struct
 /** @defgroup FLASHEx_Option_Type FLASH Option Type
   * @{
   */ 
-#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */
-#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */
-#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */
+#define OPTIONBYTE_WRP        ((uint32_t)0x01)  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP        ((uint32_t)0x02)  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER       ((uint32_t)0x04)  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR        ((uint32_t)0x08)  /*!< BOR option byte configuration  */
 /**
   * @}
   */
@@ -141,8 +159,8 @@ typedef struct
   */
 #define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
 #define OB_RDP_LEVEL_1   ((uint8_t)0x55)
-#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
-                                              it s no more possible to go back to level 1 or 0 */
+#define OB_RDP_LEVEL_2   ((uint8_t)0xCC)   /*!< Warning: When enabling read protection level 2 
+                                            it s no more possible to go back to level 1 or 0 */
 /**
   * @}
   */ 
@@ -211,7 +229,7 @@ typedef struct
 /** @defgroup FLASHEx_Banks FLASH Banks
   * @{
   */
-#define FLASH_BANK_1     1U /*!< Bank 1   */
+#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
 /**
   * @}
   */ 
@@ -219,7 +237,7 @@ typedef struct
 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
   * @{
   */
-#define FLASH_MER_BIT     FLASH_CR_MER /*!< only 1 MER Bit */
+#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
 /**
   * @}
   */ 
@@ -227,18 +245,18 @@ typedef struct
 /** @defgroup FLASHEx_Sectors FLASH Sectors
   * @{
   */
-#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#define FLASH_SECTOR_0     ((uint32_t)0)  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     ((uint32_t)1)  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     ((uint32_t)2)  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     ((uint32_t)3)  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     ((uint32_t)4)  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     ((uint32_t)5)  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     ((uint32_t)6)  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     ((uint32_t)7)  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     ((uint32_t)8)  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     ((uint32_t)9)  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    ((uint32_t)10) /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    ((uint32_t)11) /*!< Sector Number 11  */
 
 
 
@@ -249,19 +267,19 @@ typedef struct
 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
   * @{
   */
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0 */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1 */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2 */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3 */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4 */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5 */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6 */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7 */
-#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8 */
-#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9 */
-#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10 */
-#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11 */
-#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
 
 
 /**
@@ -297,19 +315,12 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
   */
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Variables FLASH Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup FLASHEx_Private_Constants FLASH Private Constants
   * @{
   */
 
-#define FLASH_SECTOR_TOTAL  12U
+#define FLASH_SECTOR_TOTAL  12
 
 /**
   * @}
@@ -369,10 +380,9 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
 
 
 
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
-                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_GPIO_H
@@ -67,7 +85,7 @@ typedef struct
   */
 typedef enum
 {
-  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_RESET = 0,
   GPIO_PIN_SET
 }GPIO_PinState;
 /**
@@ -101,7 +119,7 @@ typedef enum
 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
 
-#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
+#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
 /**
   * @}
   */
@@ -116,21 +134,21 @@ typedef enum
   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
   * @{
   */ 
-#define  GPIO_MODE_INPUT                        0x00000000U   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    0x00000001U   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    0x00000011U   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        0x00000002U   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        0x00000012U   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
 
-#define  GPIO_MODE_ANALOG                       0x00000003U   /*!< Analog Mode  */
+#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
     
-#define  GPIO_MODE_IT_RISING                    0x10110000U   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   0x10210000U   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            0x10310000U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
  
-#define  GPIO_MODE_EVT_RISING                   0x10120000U   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  0x10220000U   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           0x10320000U   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
 /**
   * @}
   */
@@ -138,11 +156,11 @@ typedef enum
 /** @defgroup GPIO_speed_define  GPIO speed define
   * @brief GPIO Output Maximum frequency
   * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
-#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
+  */  
+#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000)  /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001)  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002)  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003)  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
 /**
   * @}
   */
@@ -151,9 +169,9 @@ typedef enum
    * @brief GPIO Pull-Up or Pull-Down Activation
    * @{
    */  
-#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
+#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
 /**
   * @}
   */
@@ -169,7 +187,7 @@ typedef enum
 
 /**
   * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -177,7 +195,7 @@ typedef enum
 
 /**
   * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -185,7 +203,7 @@ typedef enum
 
 /**
   * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -193,7 +211,7 @@ typedef enum
 
 /**
   * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -201,7 +219,7 @@ typedef enum
 
 /**
   * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval None
   */
@@ -262,7 +280,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
   * @{
   */
 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_GPIO_EX_H
@@ -121,22 +139,22 @@
 /** 
   * @brief   AF 10 selection  
   */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
 
 /** 
   * @brief   AF 11 selection  
   */ 
 #if defined(STM32F207xx) || defined(STM32F217xx)
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+#define GPIO_AF11_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
 #endif /* STM32F207xx || STM32F217xx */
 
 /** 
   * @brief   AF 12 selection  
   */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+#define GPIO_AF12_FSMC          ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
 
 /** 
   * @brief   AF 13 selection  
@@ -246,7 +264,7 @@
                           ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
                           ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
 #endif /* STM32F207xx || STM32F217xx */
-
+                          
 /**
   * @}
   */ 

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h

@@ -2,209 +2,180 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hash.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_HASH_H
-#define STM32F2xx_HAL_HASH_H
+#ifndef __STM32F2xx_HAL_HASH_H
+#define __STM32F2xx_HAL_HASH_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#if defined(STM32F215xx) || defined(STM32F217xx)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
-#if defined (HASH)
-/** @addtogroup HASH
-  * @{
-  */
+
+/** @addtogroup HASH    
+  * @brief HASH HAL module driver 
+  *  @{
+  */ 
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup HASH_Exported_Types HASH Exported Types
   * @{
   */
 
-/**
-  * @brief  HASH Configuration Structure definition
+/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
+  * @{
   */
+
 typedef struct
 {
-  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
-                              This parameter can be a value of @ref HASH_Data_Type. */
-
-  uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
+  uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                           This parameter can be a value of @ref HASH_Data_Type */
 
-  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
+  uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */
 
-} HASH_InitTypeDef;
+  uint8_t* pKey;      /*!< The key is used only in HMAC operation               */
+}HASH_InitTypeDef;
 
-/**
-  * @brief HAL State structures definition
+/** 
+  * @}
   */
-typedef enum
-{
-  HAL_HASH_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized            */
-  HAL_HASH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
-  HAL_HASH_STATE_BUSY              = 0x02U,    /*!< Processing (hashing) is ongoing          */
-  HAL_HASH_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                            */
-  HAL_HASH_STATE_ERROR             = 0x07U,    /*!< Error state                              */
-  HAL_HASH_STATE_SUSPENDED         = 0x08U     /*!< Suspended state                          */
-}HAL_HASH_StateTypeDef;
 
-/**
-  * @brief HAL phase structures definition
+/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
+  * @{
   */
-typedef enum
-{
-  HAL_HASH_PHASE_READY             = 0x01U,    /*!< HASH peripheral is ready to start                    */
-  HAL_HASH_PHASE_PROCESS           = 0x02U,    /*!< HASH peripheral is in HASH processing phase          */
-  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03U,    /*!< HASH peripheral is in HMAC step 1 processing phase
-                                              (step 1 consists in entering the inner hash function key) */
-  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04U,    /*!< HASH peripheral is in HMAC step 2 processing phase
-                                              (step 2 consists in entering the message text) */
-  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase
-                                              (step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
 
-/**
-  * @brief HAL HASH mode suspend definitions
-  */
 typedef enum
 {
-  HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */
-  HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */
-}HAL_HASH_SuspendTypeDef;
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL HASH common Callback ID enumeration definition
+  HAL_HASH_STATE_RESET     = 0x00,  /*!< HASH not yet initialized or disabled */
+  HAL_HASH_STATE_READY     = 0x01,  /*!< HASH initialized and ready for use   */
+  HAL_HASH_STATE_BUSY      = 0x02,  /*!< HASH internal process is ongoing     */
+  HAL_HASH_STATE_TIMEOUT   = 0x03,  /*!< HASH timeout state                   */
+  HAL_HASH_STATE_ERROR     = 0x04   /*!< HASH error state                     */
+}HAL_HASH_STATETypeDef;
+
+/** 
+  * @}
+  */
+  
+/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
+  * @{
   */
+  
 typedef enum
 {
-  HAL_HASH_MSPINIT_CB_ID           = 0x00U,    /*!< HASH MspInit callback ID     */
-  HAL_HASH_MSPDEINIT_CB_ID         = 0x01U,    /*!< HASH MspDeInit callback ID   */
-  HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID */
-  HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */
-  HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID     */
-}HAL_HASH_CallbackIDTypeDef;
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+  HAL_HASH_PHASE_READY     = 0x01,  /*!< HASH peripheral is ready for initialization */
+  HAL_HASH_PHASE_PROCESS   = 0x02,  /*!< HASH peripheral is in processing phase      */
+}HAL_HASHPhaseTypeDef;
 
-/**
-  * @brief  HASH Handle Structure definition
+/** 
+  * @}
   */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-typedef struct __HASH_HandleTypeDef
-#else
+ 
+/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
+  * @{
+  */ 
+  
 typedef struct
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 {
-  HASH_InitTypeDef           Init;             /*!< HASH required parameters */
-
-  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
-
-  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
-
-  uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
-
-  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
-
-  uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
-
-  __IO uint32_t              HashInCount;      /*!< Counter of inputted data */
-
-  __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */
+      HASH_InitTypeDef           Init;              /*!< HASH required parameters       */
 
-  __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
+      uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */
 
-  HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
+      uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */
 
-  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */
+     __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */
 
-  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
+     __IO uint32_t               HashInCount;       /*!< Counter of input data        */
 
-  HAL_LockTypeDef            Lock;             /*!< Locking object */
+     __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */
 
-  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */
+      HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
 
-  HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */
+      HAL_HASHPhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
 
-  FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
+      DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
 
-  __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */
+      HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
 
-  __IO  uint32_t             ErrorCode;        /*!< HASH Error code */
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-  void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */
-
-  void    (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash);  /*!< HASH digest computation completion callback */
-
-  void    (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash);     /*!< HASH error callback */
-
-  void    (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash);   /*!< HASH Msp Init callback */
-
-  void    (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
-
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+     __IO HAL_HASH_STATETypeDef  State;             /*!< HASH peripheral state          */
 } HASH_HandleTypeDef;
 
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL HASH Callback pointer definition
+/** 
+  * @}
   */
-typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+  
 
 /**
   * @}
-  */
-
+  */ 
+  
 /* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants  HASH Exported Constants
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
   * @{
   */
 
-/** @defgroup HASH_Algo_Selection   HASH algorithm selection
+/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
   * @{
   */
-#define HASH_ALGOSELECTION_SHA1      0x00000000U /*!< HASH function is SHA1   */
-#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
+#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000)  /*!< HASH function is SHA1   */
+#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */
 /**
   * @}
   */
 
-/** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
+/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
   * @{
   */
-#define HASH_ALGOMODE_HASH         0x00000000U /*!< Algorithm is HASH */
-#define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
+#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000)  /*!< Algorithm is HASH */ 
+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */
 /**
   * @}
   */
 
-/** @defgroup HASH_Data_Type      HASH input data type
+/** @defgroup HASH_Data_Type HASH Data Type
   * @{
   */
-#define HASH_DATATYPE_32B          0x00000000U /*!< 32-bit data. No swapping                     */
+#define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
@@ -212,47 +183,33 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @}
   */
 
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
+/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key 
+  * @brief HASH HMAC Long key used only for HMAC mode
   * @{
   */
-#define HASH_HMAC_KEYTYPE_SHORTKEY      0x00000000U /*!< HMAC Key size is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
+#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000)  /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */
 /**
   * @}
   */
 
-/** @defgroup HASH_flags_definition  HASH flags definitions
+/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition 
   * @{
   */
-#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
-#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
-#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
-#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
-
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
 /**
   * @}
   */
 
-/** @defgroup HASH_interrupts_definition   HASH interrupts definitions
+/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition 
   * @{
   */
 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Error_Definition   HASH Error Definition
-  * @{
-  */
-#define  HAL_HASH_ERROR_NONE             0x00000000U   /*!< No error                */
-#define  HAL_HASH_ERROR_IT               0x00000001U   /*!< IT-based process error  */
-#define  HAL_HASH_ERROR_DMA              0x00000002U   /*!< DMA-based process error */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-#define  HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -261,313 +218,215 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @}
   */
 
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup HASH_Exported_Macros HASH Exported Macros
   * @{
   */
-
-/** @brief  Check whether or not the specified HASH flag is set.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
-  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
-  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
-  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
-  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
-                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
-                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
-
-
-/** @brief  Clear the specified HASH flag.
-  * @param  __FLAG__: specifies the flag to clear.
-  *        This parameter can be one of the following values:
-  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
-  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
-  * @retval None
-  */
-#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
-
-
-/** @brief  Enable the specified HASH interrupt.
-  * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
-  *            @arg @ref HASH_IT_DCI   Digest calculation complete
-  * @retval None
-  */
-#define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief  Disable the specified HASH interrupt.
-  * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
-  *            @arg @ref HASH_IT_DCI   Digest calculation complete
-  * @retval None
-  */
-#define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief Reset HASH handle state.
-  * @param  __HANDLE__: HASH handle.
+  
+/** @brief Reset HASH handle state
+  * @param  __HANDLE__: specifies the HASH handle.
   * @retval None
   */
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;      \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
-                                                     }while(0)
-#else
 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
 
-/** @brief Reset HASH handle status.
-  * @param  __HANDLE__: HASH handle.
-  * @retval None
+/** @brief  Check whether the specified HASH flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. 
+  *            @arg HASH_FLAG_DCIS: Digest calculation complete
+  *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
+  *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
+  *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
-
-
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+                                                           ((HASH->SR & (__FLAG__)) == (__FLAG__)))
 /**
-  * @brief Start the digest computation.
+  * @brief  Start the digest computation
   * @retval None
   */
-#define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
+#define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL
 
 /**
-  * @brief Set the number of valid bits in the last word written in data register DIN.
-  * @param  __SIZE__: size in bytes of last data written in Data register.
+  * @brief Set the number of valid bits in last word written in Data register
+  * @param  SIZE: size in byte of last data written in Data register.
   * @retval None
 */
-#define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
-
-/**
-  * @brief Reset the HASH core.
-  * @retval None
-  */
-#define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
+                                            HASH->STR |= 8 * ((SIZE) % 4);\
+                                           }while(0)
 
 /**
   * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros   HASH Private Macros
-  * @{
-  */
-#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : 16)
-/**
-  * @brief  Return number of words already pushed in the FIFO.
-  * @retval Number of words already pushed in the FIFO
-  */
-#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
-
-/**
-  * @brief Ensure that HASH input data type is valid.
-  * @param __DATATYPE__: HASH input data type.
-  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
-  */
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
-                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
-                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
-                                        ((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-
-/**
-  * @brief Ensure that input data buffer size is valid for multi-buffer HASH
-  *        processing in polling mode.
-  * @note  This check is valid only for multi-buffer HASH processing in polling mode.
-  * @param __SIZE__: input data buffer size.
-  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
-  */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4U) == 0U)
-/**
-  * @brief Ensure that handle phase is set to HASH processing.
-  * @param __HANDLE__: HASH handle.
-  * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
-  */
-#define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
+  */ 
 
-/**
-  * @brief Ensure that handle phase is set to HMAC processing.
-  * @param __HANDLE__: HASH handle.
-  * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
-  */
-#define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
-                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
-                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-
-/**
-  * @}
-  */
 
 /* Exported functions --------------------------------------------------------*/
 
-/** @addtogroup HASH_Exported_Functions HASH Exported Functions
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
   * @{
   */
 
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup HASH_Exported_Functions_Group1
   * @{
-  */
-
-/* Initialization/de-initialization methods  **********************************/
+  */  
 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+/** @addtogroup HASH_Exported_Functions_Group2
   * @{
-  */
-
-
-/* HASH processing using polling  *********************************************/
+  */  
 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
 /**
   * @}
-  */
-
-/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+  */ 
+  
+/** @addtogroup HASH_Exported_Functions_Group3
   * @{
-  */
+  */  
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+/**
+  * @}
+  */ 
 
-/* HASH processing using IT  **************************************************/
+/** @addtogroup HASH_Exported_Functions_Group4
+  * @{
+  */  
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+/** @addtogroup HASH_Exported_Functions_Group5
   * @{
-  */
-
-/* HASH processing using DMA  *************************************************/
+  */    
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+/** @addtogroup HASH_Exported_Functions_Group6
   * @{
-  */
-
-/* HASH-MAC processing using polling  *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+  */  
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+/**
+  * @}
+  */ 
 
+/** @addtogroup HASH_Exported_Functions_Group7
+  * @{
+  */  
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+/** @addtogroup HASH_Exported_Functions_Group8
   * @{
   */
-
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
 /**
   * @}
-  */
-
-/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+  */ 
+  
+ /**
+  * @}
+  */ 
+ 
+ /* Private types -------------------------------------------------------------*/
+/** @defgroup HASH_Private_Types HASH Private Types
   * @{
   */
 
-/* HASH-HMAC processing using DMA  ********************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Variables HASH Private Variables
   * @{
   */
 
-
-/* Peripheral State methods  **************************************************/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
-
 /**
   * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+  * @{
   */
 
 /**
   * @}
-  */
-
-/* Private functions -----------------------------------------------------------*/
+  */ 
 
-/** @addtogroup HASH_Private_Functions HASH Private Functions
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
   * @{
   */
+#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \
+                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
 
-/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
+#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
+                                        ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+
+
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+                                        ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
+                                           ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+
+#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
 
 /**
   * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
   */
 
 /**
   * @}
   */
-#endif /*  HASH*/
+ 
+#endif /* STM32F215xx || STM32F217xx */
 /**
   * @}
-  */
-
+  */ 
 
+/**
+  * @}
+  */
+  
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* STM32F2xx_HAL_HASH_H */
+#endif /* __STM32F2xx_HAL_HASH_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h

@@ -2,33 +2,50 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hcd.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_HCD_H
-#define STM32F2xx_HAL_HCD_H
+#ifndef __STM32F2xx_HAL_HCD_H
+#define __STM32F2xx_HAL_HCD_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_usb.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+   
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
@@ -37,15 +54,15 @@ extern "C" {
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup HCD_Exported_Types HCD Exported Types
   * @{
   */
 
-/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition 
   * @{
   */
-typedef enum
+typedef enum 
 {
   HAL_HCD_STATE_RESET    = 0x00,
   HAL_HCD_STATE_READY    = 0x01,
@@ -56,41 +73,24 @@ typedef enum
 
 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
-typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;   
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
 /**
   * @}
   */
 
 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
   * @{
-  */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-typedef struct __HCD_HandleTypeDef
-#else
+  */ 
 typedef struct
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
 {
   HCD_TypeDef               *Instance;  /*!< Register base address    */
   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
-  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
+  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
-  __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
   void                      *pData;     /*!< Pointer Stack Handler    */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-  void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
-  void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
-  void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
-  void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
-  void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
-  void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
-                                      HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
-
-  void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
-  void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
 } HCD_HandleTypeDef;
 /**
   * @}
@@ -98,7 +98,7 @@ typedef struct
 
 /**
   * @}
-  */
+  */ 
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup HCD_Exported_Constants HCD Exported Constants
@@ -108,10 +108,9 @@ typedef struct
 /** @defgroup HCD_Speed HCD Speed
   * @{
   */
-#define HCD_SPEED_HIGH               USBH_HS_SPEED
-#define HCD_SPEED_FULL               USBH_FS_SPEED
-#define HCD_SPEED_LOW                USBH_LS_SPEED
-
+#define HCD_SPEED_HIGH               0
+#define HCD_SPEED_LOW                2  
+#define HCD_SPEED_FULL               3
 /**
   * @}
   */
@@ -119,45 +118,33 @@ typedef struct
 /** @defgroup HCD_PHY_Module HCD PHY Module
   * @{
   */
-#define HCD_PHY_ULPI                 1U
-#define HCD_PHY_EMBEDDED             2U
-/**
-  * @}
-  */
-
-/** @defgroup HCD_Error_Code_definition HCD Error Code definition
-  * @brief  HCD Error Code definition
-  * @{
-  */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-#define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
+#define HCD_PHY_ULPI                 1
+#define HCD_PHY_EMBEDDED             2
 /**
   * @}
   */
 
 /**
   * @}
-  */
+  */ 
 
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup HCD_Exported_Macros HCD Exported Macros
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
-#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
+#define __HAL_HCD_ENABLE(__HANDLE__)               USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)              USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)    
+  
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 
 /**
   * @}
   */
@@ -167,63 +154,24 @@ typedef struct
   * @{
   */
 
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
-                                       uint8_t ch_num,
-                                       uint8_t epnum,
-                                       uint8_t dev_address,
-                                       uint8_t speed,
-                                       uint8_t ep_type,
-                                       uint16_t mps);
-
-HAL_StatusTypeDef     HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void                  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void                  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
-  * @brief  HAL USB OTG HCD Callback ID enumeration definition
-  * @{
-  */
-typedef enum
-{
-  HAL_HCD_SOF_CB_ID           = 0x01,       /*!< USB HCD SOF callback ID           */
-  HAL_HCD_CONNECT_CB_ID       = 0x02,       /*!< USB HCD Connect callback ID       */
-  HAL_HCD_DISCONNECT_CB_ID   = 0x03,       /*!< USB HCD Disconnect callback ID    */
-  HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,      /*!< USB HCD Port Enable callback ID   */
-  HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,      /*!< USB HCD Port Disable callback ID  */
-
-  HAL_HCD_MSPINIT_CB_ID       = 0x06,       /*!< USB HCD MspInit callback ID       */
-  HAL_HCD_MSPDEINIT_CB_ID     = 0x07        /*!< USB HCD MspDeInit callback ID     */
-
-} HAL_HCD_CallbackIDTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
-  * @brief  HAL USB OTG HCD Callback pointer definition
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
+HAL_StatusTypeDef   HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef   HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef   HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+                                    uint8_t ch_num,
+                                    uint8_t epnum,
+                                    uint8_t dev_address,
+                                    uint8_t speed,
+                                    uint8_t ep_type,
+                                    uint16_t mps);
 
-typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
-typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
-                                                       uint8_t epnum,
-                                                       HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
-/**
-  * @}
-  */
-
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
 
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+void                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
 /**
   * @}
   */
@@ -232,25 +180,23 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
-HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
-                                                 uint8_t ch_num,
-                                                 uint8_t direction,
-                                                 uint8_t ep_type,
-                                                 uint8_t token,
-                                                 uint8_t *pbuff,
-                                                 uint16_t length,
-                                                 uint8_t do_ping);
+HAL_StatusTypeDef   HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                             uint8_t pipe, 
+                                             uint8_t direction,
+                                             uint8_t ep_type,  
+                                             uint8_t token, 
+                                             uint8_t* pbuff, 
+                                             uint16_t length,
+                                             uint8_t do_ping);
 
 /* Non-Blocking mode: Interrupt */
-void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
-                                                     uint8_t chnum,
-                                                     HCD_URBStateTypeDef urb_state);
+void                HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void                HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void                HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void                HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void                HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, 
+                                                        uint8_t chnum, 
+                                                        HCD_URBStateTypeDef urb_state);
 /**
   * @}
   */
@@ -259,9 +205,9 @@ void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
-HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef   HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef   HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef   HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
 /**
   * @}
   */
@@ -270,12 +216,12 @@ HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
-HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+HCD_StateTypeDef    HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t            HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t            HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 /**
   * @}
   */
@@ -288,25 +234,15 @@ uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 /** @defgroup HCD_Private_Macros HCD Private Macros
  * @{
  */
-
-/**
-  * @}
-  */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
+/** @defgroup HCD_Instance_definition HCD Instance definition
   * @{
   */
-
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
-  * @{
-  */
-
 /**
   * @}
   */
@@ -317,13 +253,12 @@ uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 
 /**
   * @}
-  */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  */ 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_HCD_H */
+#endif /* __STM32F2xx_HAL_HCD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h

@@ -2,17 +2,35 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2c.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -22,7 +40,7 @@
 #define __STM32F2xx_HAL_I2C_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -40,10 +58,9 @@ extern "C" {
 /** @defgroup I2C_Exported_Types I2C Exported Types
   * @{
   */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+   
+/**
   * @brief  I2C Configuration Structure definition
-  * @{
   */
 typedef struct
 {
@@ -71,218 +88,79 @@ typedef struct
   uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
                                   This parameter can be a value of @ref I2C_nostretch_mode */
 
-} I2C_InitTypeDef;
+}I2C_InitTypeDef;
 
 /**
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : Abort (Abort user request on going)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initilisation status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
-  *          b4     (not used)
-  *             x  : Should be set to 0
-  *          b3
-  *             0  : Ready or Busy (No Listen mode ongoing)
-  *             1  : Listen (Peripheral in Address Listen Mode)
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  * @{
+  * @brief  HAL State structures definition
   */
 typedef enum
 {
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-} HAL_I2C_StateTypeDef;
+  HAL_I2C_STATE_RESET             = 0x00,  /*!< I2C not yet initialized or disabled         */
+  HAL_I2C_STATE_READY             = 0x01,  /*!< I2C initialized and ready for use           */
+  HAL_I2C_STATE_BUSY              = 0x02,  /*!< I2C internal process is ongoing             */
+  HAL_I2C_STATE_BUSY_TX           = 0x12,  /*!< Data Transmission process is ongoing        */
+  HAL_I2C_STATE_BUSY_RX           = 0x22,  /*!< Data Reception process is ongoing           */
+  HAL_I2C_STATE_MEM_BUSY_TX       = 0x32,  /*!< Memory Data Transmission process is ongoing */
+  HAL_I2C_STATE_MEM_BUSY_RX       = 0x42,  /*!< Memory Data Reception process is ongoing    */
+  HAL_I2C_STATE_TIMEOUT           = 0x03,  /*!< I2C timeout state                           */
+  HAL_I2C_STATE_ERROR             = 0x04   /*!< I2C error state                             */
 
-/**
-  * @}
-  */
+}HAL_I2C_StateTypeDef;
 
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :\n
-  *          b7     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b6\n
-  *             0  : None\n
-  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
-  *          b5\n
-  *             0  : None\n
-  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
-  *          b4\n
-  *             0  : None\n
-  *             1  : Master (HAL I2C communication is in Master Mode)\n
-  *          b3-b2-b1-b0  (not used)\n
-  *             xxxx : Should be set to 0000
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */
-#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */
-#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */
-#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 /**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
   * @brief  I2C handle Structure definition
-  * @{
   */
-typedef struct __I2C_HandleTypeDef
+typedef struct
 {
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
-
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
-
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
-
-  uint16_t                   XferSize;       /*!< I2C transfer size                        */
-
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
-
-  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
-
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
-                                                  context for internal usage               */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
-
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
+  I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
 
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
+  I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
 
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
+  uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
 
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
+  uint16_t                   XferSize;   /*!< I2C transfer size              */
 
-  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
+  __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
 
-  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
+  DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
 
-  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
+  DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
 
-  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
+  HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
 
+  __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
 
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
-
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
-
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL I2C Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
-  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
-  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
-  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
-  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
-  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
-  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
-  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
-  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
-
-  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
-  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
-
-} HAL_I2C_CallbackIDTypeDef;
+  __IO uint32_t              ErrorCode;  /*!<  I2C Error code                */
 
-/**
-  * @brief  HAL I2C Callback pointer definition
-  */
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}I2C_HandleTypeDef;
 /**
   * @}
   */
 
-/**
-  * @}
-  */
 /* Exported constants --------------------------------------------------------*/
-
 /** @defgroup I2C_Exported_Constants I2C Exported Constants
   * @{
   */
 
+/** @defgroup I2C_Error_Code I2C Error Code
+  * @brief    I2C Error Code 
+  * @{
+  */ 
+#define HAL_I2C_ERROR_NONE       ((uint32_t)0x00000000)    /*!< No error           */
+#define HAL_I2C_ERROR_BERR       ((uint32_t)0x00000001)    /*!< BERR error         */
+#define HAL_I2C_ERROR_ARLO       ((uint32_t)0x00000002)    /*!< ARLO error         */
+#define HAL_I2C_ERROR_AF         ((uint32_t)0x00000004)    /*!< AF error           */
+#define HAL_I2C_ERROR_OVR        ((uint32_t)0x00000008)    /*!< OVR error          */
+#define HAL_I2C_ERROR_DMA        ((uint32_t)0x00000010)    /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT    ((uint32_t)0x00000020)    /*!< Timeout Error      */
+/**
+  * @}
+  */
+
 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
   * @{
   */
-#define I2C_DUTYCYCLE_2                 0x00000000U
+#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000)
 #define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
 /**
   * @}
@@ -291,8 +169,8 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_addressing_mode I2C addressing mode
   * @{
   */
-#define I2C_ADDRESSINGMODE_7BIT         0x00004000U
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
+#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
 /**
   * @}
   */
@@ -300,7 +178,7 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
   * @{
   */
-#define I2C_DUALADDRESS_DISABLE        0x00000000U
+#define I2C_DUALADDRESS_DISABLE        ((uint32_t)0x00000000)
 #define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
 /**
   * @}
@@ -309,7 +187,7 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
   * @{
   */
-#define I2C_GENERALCALL_DISABLE        0x00000000U
+#define I2C_GENERALCALL_DISABLE        ((uint32_t)0x00000000)
 #define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
 /**
   * @}
@@ -318,7 +196,7 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_nostretch_mode I2C nostretch mode
   * @{
   */
-#define I2C_NOSTRETCH_DISABLE          0x00000000U
+#define I2C_NOSTRETCH_DISABLE          ((uint32_t)0x00000000)
 #define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
 /**
   * @}
@@ -327,44 +205,13 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
   * @{
   */
-#define I2C_MEMADD_SIZE_8BIT            0x00000001U
-#define I2C_MEMADD_SIZE_16BIT           0x00000010U
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
-  * @{
-  */
-#define I2C_DIRECTION_RECEIVE           0x00000000U
-#define I2C_DIRECTION_TRANSMIT          0x00000001U
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
-  * @{
-  */
-#define  I2C_FIRST_FRAME                0x00000001U
-#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U
-#define  I2C_NEXT_FRAME                 0x00000004U
-#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U
-#define  I2C_LAST_FRAME_NO_STOP         0x00000010U
-#define  I2C_LAST_FRAME                 0x00000020U
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  I2C_OTHER_FRAME                (0x00AA0000U)
-#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)
+#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010)
 /**
   * @}
   */
 
 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
   * @{
   */
 #define I2C_IT_BUF                      I2C_CR2_ITBUFEN
@@ -377,23 +224,27 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 /** @defgroup I2C_Flag_definition I2C Flag definition
   * @{
   */
-
-#define I2C_FLAG_OVR                    0x00010800U
-#define I2C_FLAG_AF                     0x00010400U
-#define I2C_FLAG_ARLO                   0x00010200U
-#define I2C_FLAG_BERR                   0x00010100U
-#define I2C_FLAG_TXE                    0x00010080U
-#define I2C_FLAG_RXNE                   0x00010040U
-#define I2C_FLAG_STOPF                  0x00010010U
-#define I2C_FLAG_ADD10                  0x00010008U
-#define I2C_FLAG_BTF                    0x00010004U
-#define I2C_FLAG_ADDR                   0x00010002U
-#define I2C_FLAG_SB                     0x00010001U
-#define I2C_FLAG_DUALF                  0x00100080U
-#define I2C_FLAG_GENCALL                0x00100010U
-#define I2C_FLAG_TRA                    0x00100004U
-#define I2C_FLAG_BUSY                   0x00100002U
-#define I2C_FLAG_MSL                    0x00100001U
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x00011000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x00010800)
+#define I2C_FLAG_AF                     ((uint32_t)0x00010400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x00010200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x00010100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x00010080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x00010040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x00010010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x00010008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x00010004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x00010002)
+#define I2C_FLAG_SB                     ((uint32_t)0x00010001)
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00100080)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100010)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00100004)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00100002)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00100001)
 /**
   * @}
   */
@@ -402,41 +253,35 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
   * @}
   */
 
-/* Exported macros -----------------------------------------------------------*/
-
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup I2C_Exported_Macros I2C Exported Macros
   * @{
   */
 
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
+/** @brief Reset I2C handle state
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
   * @retval None
   */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
 
 /** @brief  Enable or disable the specified I2C interrupts.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
   *         This parameter can be one of the following values:
   *            @arg I2C_IT_BUF: Buffer interrupt enable
   *            @arg I2C_IT_EVT: Event interrupt enable
   *            @arg I2C_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
 
 /** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2C_IT_BUF: Buffer interrupt enable
   *            @arg I2C_IT_EVT: Event interrupt enable
@@ -446,9 +291,13 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *         This parameter can be one of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
   *            @arg I2C_FLAG_AF: Acknowledge failure flag
   *            @arg I2C_FLAG_ARLO: Arbitration lost flag
@@ -462,20 +311,25 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
   *                                Address matched flag
   *            @arg I2C_FLAG_SB: Start bit flag
   *            @arg I2C_FLAG_DUALF: Dual flag
+  *            @arg I2C_FLAG_SMBHOST: SMBus host header
+  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
   *            @arg I2C_FLAG_GENCALL: General call header flag
   *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
   *            @arg I2C_FLAG_BUSY: Bus busy flag
   *            @arg I2C_FLAG_MSL: Master/Slave flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
-                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
-                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
 
 /** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __FLAG__: specifies the flag to clear.
   *         This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
   *            @arg I2C_FLAG_AF: Acknowledge failure flag
   *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
@@ -485,41 +339,33 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
 
 /** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __HANDLE__: specifies the I2C Handle.
   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
   * @retval None
   */
 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
   do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
+    __IO uint32_t tmpreg;                       \
     tmpreg = (__HANDLE__)->Instance->SR1;       \
     tmpreg = (__HANDLE__)->Instance->SR2;       \
     UNUSED(tmpreg);                             \
   } while(0)
 
 /** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
   * @retval None
   */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \
-  do{                                                  \
-    __IO uint32_t tmpreg = 0x00U;                      \
-    tmpreg = (__HANDLE__)->Instance->SR1;              \
-    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \
-    UNUSED(tmpreg);                                    \
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)    \
+  do{                                           \
+    __IO uint32_t tmpreg;                       \
+    tmpreg = (__HANDLE__)->Instance->SR1;       \
+    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
+    UNUSED(tmpreg);                             \
   } while(0)
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+    
+#define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
 
 /**
   * @}
@@ -530,31 +376,22 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
   * @{
   */
 
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup I2C_Exported_Functions_Group1
   * @{
   */
-/* Initialization and de-initialization functions******************************/
+/* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @addtogroup I2C_Exported_Functions_Group2
   * @{
   */
-/* IO operation functions  ****************************************************/
+/* I/O operation functions  *****************************************************/
 /******* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -572,14 +409,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
 /******* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@@ -588,17 +417,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -606,22 +424,18 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
 /**
   * @}
   */
 
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+/** @addtogroup I2C_Exported_Functions_Group3
   * @{
   */
-/* Peripheral State, Mode and Error functions  *********************************/
+/* Peripheral Control and State functions  **************************************/
 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 /**
@@ -637,9 +451,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /** @defgroup I2C_Private_Constants I2C Private Constants
   * @{
   */
-#define I2C_FLAG_MASK                    0x0000FFFFU
-#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */
-#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */
+#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFF)
 /**
   * @}
   */
@@ -648,26 +460,24 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /** @defgroup I2C_Private_Macros I2C Private Macros
   * @{
   */
-
-#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
-#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
-#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
+    
+#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
 
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
 #define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
 
-#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
 
-#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
 
 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
   * @{
@@ -684,22 +494,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
                                     ((STRETCH) == I2C_NOSTRETCH_ENABLE))
 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                   ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
-                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \
-                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
-                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
-                                                       ((REQUEST) == I2C_LAST_FRAME)               || \
-                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \
-                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
-                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
 /**
   * @}
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h

@@ -2,31 +2,49 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2s.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_I2S_H
-#define STM32F2xx_HAL_I2S_H
+#ifndef __STM32F2xx_HAL_I2S_H
+#define __STM32F2xx_HAL_I2S_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
+#include "stm32f2xx_hal_def.h"  
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -34,217 +52,187 @@ extern "C" {
 
 /** @addtogroup I2S
   * @{
-  */
+  */ 
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup I2S_Exported_Types I2S Exported Types
   * @{
   */
-
-/**
-  * @brief I2S Init structure definition
+  
+/** 
+  * @brief I2S Init structure definition  
   */
 typedef struct
 {
-  uint32_t Mode;                /*!< Specifies the I2S operating mode.
-                                     This parameter can be a value of @ref I2S_Mode */
+  uint32_t Mode;         /*!< Specifies the I2S operating mode.
+                              This parameter can be a value of @ref I2S_Mode */
 
-  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Standard */
+  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
+                              This parameter can be a value of @ref I2S_Standard */
 
-  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Data_Format */
+  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
+                              This parameter can be a value of @ref I2S_Data_Format */
 
-  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                     This parameter can be a value of @ref I2S_MCLK_Output */
+  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                              This parameter can be a value of @ref I2S_MCLK_Output */
 
-  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Audio_Frequency */
+  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                              This parameter can be a value of @ref I2S_Audio_Frequency */
 
-  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
-                                     This parameter can be a value of @ref I2S_Clock_Polarity */
+  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
+                              This parameter can be a value of @ref I2S_Clock_Polarity */
 
-  uint32_t ClockSource;     /*!< Specifies the I2S Clock Source.
-                                 This parameter can be a value of @ref I2S_Clock_Source */
-} I2S_InitTypeDef;
+  uint32_t ClockSource;  /*!< Specifies the I2S Clock Source.
+                              This parameter can be a value of @ref I2S_Clock_Source */
 
-/**
+}I2S_InitTypeDef;
+
+/** 
   * @brief  HAL State structures definition
-  */
+  */ 
 typedef enum
 {
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
-} HAL_I2S_StateTypeDef;
+  HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
+  HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
+  HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */
+  HAL_I2S_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
+  HAL_I2S_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
+  HAL_I2S_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
+  HAL_I2S_STATE_TIMEOUT    = 0x03,  /*!< I2S timeout state                                  */
+  HAL_I2S_STATE_ERROR      = 0x04   /*!< I2S error state                                    */
 
-/**
-  * @brief I2S handle Structure definition
+}HAL_I2S_StateTypeDef;
+
+/** 
+  * @brief I2S handle Structure definition  
   */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
-typedef struct __I2S_HandleTypeDef
-#else
 typedef struct
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 {
-  SPI_TypeDef                *Instance;    /*!< I2S registers base address */
-
-  I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
-
-  uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
-
-  __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
-
-  __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
-
-  uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
-
-  __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
-
-  __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
-                                              (This field is initialized at the
-                                               same value as transfer size at the
-                                               beginning of the transfer and
-                                               decremented when a sample is received
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-  DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
-
-  __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
-
-  __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
-
-  __IO uint32_t              ErrorCode;    /*!< I2S Error code
-                                                This parameter can be a value of @ref I2S_Error */
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
-  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
-  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
-  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
-  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
-  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
-
-#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
-} I2S_HandleTypeDef;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  SPI_TypeDef                *Instance;    /* I2S registers base address        */
+
+  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
+  
+  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
+  
+  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
+  
+  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
+  
+  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
+  
+  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
+  
+  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter           */
+
+  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
+
+  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
+  
+  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
+  
+  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
+  
+  __IO uint32_t              ErrorCode;    /* I2S Error code                    */
+  
+}I2S_HandleTypeDef;
 /**
-  * @brief  HAL I2S Callback ID enumeration definition
+  * @}
   */
-typedef enum
-{
-  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
-  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
-  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
-  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
-  HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
-  HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
-  HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
 
-} HAL_I2S_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2S Callback pointer definition
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+  * @{
   */
-typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
 
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/** @defgroup I2S_Error_Code I2S Error Code
+  * @brief    I2S Error Code 
+  * @{
+  */ 
+#define HAL_I2S_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error                    */
+#define HAL_I2S_ERROR_UDR           ((uint32_t)0x00000001)    /*!< I2S Underrun error          */
+#define HAL_I2S_ERROR_OVR           ((uint32_t)0x00000002)    /*!< I2S Overrun error           */
+#define HAL_I2SEX_ERROR_UDR         ((uint32_t)0x00000004)    /*!< I2S extended Underrun error */
+#define HAL_I2SEX_ERROR_OVR         ((uint32_t)0x00000008)    /*!< I2S extended Overrun error  */
+#define HAL_I2S_ERROR_FRE           ((uint32_t)0x00000010)    /*!< I2S Frame format error      */
+#define HAL_I2S_ERROR_DMA           ((uint32_t)0x00000020)    /*!< DMA transfer error          */
 /**
   * @}
   */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-/** @defgroup I2S_Error I2S Error
+/** @defgroup I2S_Clock_Source I2S Clock Source 
   * @{
   */
-#define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
-#define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
-#define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
-#define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
-#define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
-#define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+#define I2S_CLOCK_PLL                     ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001)
 /**
   * @}
   */
 
-/** @defgroup I2S_Mode I2S Mode
+/** @defgroup I2S_Mode I2S Mode 
   * @{
   */
-#define I2S_MODE_SLAVE_TX                (0x00000000U)
-#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
+#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
 /**
   * @}
   */
-
+  
 /** @defgroup I2S_Standard I2S Standard
   * @{
   */
-#define I2S_STANDARD_PHILIPS             (0x00000000U)
-#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
+#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0)
 /**
   * @}
   */
-
+  
 /** @defgroup I2S_Data_Format I2S Data Format
   * @{
   */
-#define I2S_DATAFORMAT_16B               (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
+#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005)
 /**
   * @}
   */
 
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
+/** @defgroup I2S_MCLK_Output I2S Mclk Output
   * @{
   */
-#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
+#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
 /**
   * @}
   */
 
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency 
   * @{
   */
-#define I2S_AUDIOFREQ_192K               (192000U)
-#define I2S_AUDIOFREQ_96K                (96000U)
-#define I2S_AUDIOFREQ_48K                (48000U)
-#define I2S_AUDIOFREQ_44K                (44100U)
-#define I2S_AUDIOFREQ_32K                (32000U)
-#define I2S_AUDIOFREQ_22K                (22050U)
-#define I2S_AUDIOFREQ_16K                (16000U)
-#define I2S_AUDIOFREQ_11K                (11025U)
-#define I2S_AUDIOFREQ_8K                 (8000U)
-#define I2S_AUDIOFREQ_DEFAULT            (2U)
+#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
 /**
   * @}
   */
 
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+/** @defgroup I2S_Clock_Polarity  I2S Clock Polarity
   * @{
   */
-#define I2S_CPOL_LOW                     (0x00000000U)
-#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
+#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
 /**
   * @}
   */
@@ -252,9 +240,9 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
   * @{
   */
-#define I2S_IT_TXE                       SPI_CR2_TXEIE
-#define I2S_IT_RXNE                      SPI_CR2_RXNEIE
-#define I2S_IT_ERR                       SPI_CR2_ERRIE
+#define I2S_IT_TXE                      SPI_CR2_TXEIE
+#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
+#define I2S_IT_ERR                      SPI_CR2_ERRIE
 /**
   * @}
   */
@@ -262,103 +250,68 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 /** @defgroup I2S_Flags_Definition I2S Flags Definition
   * @{
   */
-#define I2S_FLAG_TXE                     SPI_SR_TXE
-#define I2S_FLAG_RXNE                    SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                     SPI_SR_UDR
-#define I2S_FLAG_OVR                     SPI_SR_OVR
-#define I2S_FLAG_FRE                     SPI_SR_FRE
+#define I2S_FLAG_TXE                    SPI_SR_TXE
+#define I2S_FLAG_RXNE                   SPI_SR_RXNE
 
-#define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                     SPI_SR_BSY
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define I2S_FLAG_OVR                    SPI_SR_OVR
+#define I2S_FLAG_FRE                    SPI_SR_FRE
 
-#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
-                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_BSY                    SPI_SR_BSY
 /**
   * @}
   */
 
-/** @defgroup I2S_Clock_Source I2S Clock Source
-  * @{
-  */
-#define I2S_CLOCK_PLL                     0x00000000U
-#define I2S_CLOCK_EXTERNAL                0x00000001U
 /**
   * @}
-  */
-/**
-  * @}
-  */
+  */ 
 
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
   * @{
   */
 
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__ specifies the I2S Handle.
+/** @brief Reset I2S handle state
+  * @param  __HANDLE__: specifies the I2S Handle.
   * @retval None
   */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 
-/** @brief  Enable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
+/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__: specifies the I2S Handle. 
   * @retval None
   */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
 
-/** @brief  Disable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+/** @brief  Enable or disable the specified I2S interrupts.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
   *         This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg I2S_IT_ERR: Error interrupt enable
   * @retval None
-  */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
+  */  
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
+ 
 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __HANDLE__: specifies the I2S Handle.
   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
+  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg I2S_IT_ERR: Error interrupt enable
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __FLAG__: specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -372,28 +325,31 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __HANDLE__: specifies the I2S Handle.
   * @retval None
   */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
-                                                __IO uint32_t tmpreg_ovr = 0x00U; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
-                                                UNUSED(tmpreg_ovr); \
-                                              }while(0U)
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
+  do{                                           \
+    __IO uint32_t tmpreg;                       \
+    tmpreg = (__HANDLE__)->Instance->DR;        \
+    tmpreg = (__HANDLE__)->Instance->SR;        \
+    UNUSED(tmpreg);                             \
+  } while(0)
+    
 /** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __HANDLE__: specifies the I2S Handle.
   * @retval None
   */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
-                                                __IO uint32_t tmpreg_udr = 0x00U;\
-                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
-                                                UNUSED(tmpreg_udr); \
-                                              }while(0U)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
+  do{                                             \
+  __IO uint32_t tmpreg;                         \
+  tmpreg = (__HANDLE__)->Instance->SR;          \
+  UNUSED(tmpreg);                               \
+  } while(0)
 /**
   * @}
   */
-
+  
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup I2S_Exported_Functions
   * @{
@@ -402,18 +358,11 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 /** @addtogroup I2S_Exported_Functions_Group1
   * @{
   */
-/* Initialization/de-initialization functions  ********************************/
+/* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -421,12 +370,12 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
 /** @addtogroup I2S_Exported_Functions_Group2
   * @{
   */
-/* I/O operation functions  ***************************************************/
+/* I/O operation functions  *****************************************************/
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
 
-/* Non-Blocking mode: Interrupt */
+ /* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
@@ -439,6 +388,10 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
 
+/* Peripheral Control and State functions  **************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+
 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
@@ -447,17 +400,7 @@ void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
 /**
   * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
+  */ 
 
 /**
   * @}
@@ -466,92 +409,72 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
+/** @defgroup I2S_Private_Constants I2S Private Constants
   * @{
   */
 
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of I2S SR regsiter.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun error flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_CHSIDE: Channel side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
-                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of I2S CR2 regsiter.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
-                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if I2S Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the I2S Mode.
-  *         This parameter can be a value of @ref I2S_Mode
-  * @retval None
+/**
+  * @}
   */
-#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
-                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
-                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
-                               ((__MODE__) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
-                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
-                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
 
-#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
-                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
-                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
-
-/** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the I2S serial clock steady state.
-  *         This parameter can be a value of @ref I2S_Clock_Polarity
-  * @retval None
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+  * @{
   */
-#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
-                               ((__CPOL__) == I2S_CPOL_HIGH))
-
 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
                                    ((CLOCK) == I2S_CLOCK_PLL))
+                                   
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
+                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
+                           ((MODE) == I2S_MODE_MASTER_TX) || \
+                           ((MODE) == I2S_MODE_MASTER_RX))
+                           
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
+                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+                                    
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+                           ((CPOL) == I2S_CPOL_HIGH))
+ 
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+  * @{
+  */
 /**
   * @}
   */
 
 /**
   * @}
-  */
+  */ 
+
+/**
+  * @}
+  */  
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_I2S_H */
+
+#endif /* __STM32F2xx_HAL_I2S_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_irda.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_IRDA_H
 #define __STM32F2xx_HAL_IRDA_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,15 +52,15 @@ extern "C" {
 
 /** @addtogroup IRDA
   * @{
-  */
+  */ 
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup IRDA_Exported_Types IRDA Exported Types
   * @{
   */
-/**
-  * @brief IRDA Init Structure definition
-  */
+/** 
+  * @brief IRDA Init Structure definition  
+  */ 
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
@@ -53,177 +71,70 @@ typedef struct
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
                                            This parameter can be a value of @ref IRDA_Word_Length */
 
-  uint32_t Parity;                    /*!< Specifies the parity mode.
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref IRDA_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ 
+  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref IRDA_Mode */
-
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value to be programmed
-                                           in the IrDA low-power Baud Register, for defining pulse width on which
-                                           burst acceptance/rejection will be decided. This value is used as divisor
-                                           of system clock to achieve required pulse width. */
-
+                                            
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler */
+  
   uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
                                            This parameter can be a value of @ref IRDA_Low_Power */
-} IRDA_InitTypeDef;
+}IRDA_InitTypeDef;
 
-/**
-  * @brief HAL IRDA State structures definition
-  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains IRDA state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
+/** 
+  * @brief HAL State structures definition  
+  */ 
 typedef enum
 {
-  HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error
-                                                   Value is allowed for gState only */
-} HAL_IRDA_StateTypeDef;
-
-/**
-  * @brief IRDA handle Structure definition
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-typedef struct __IRDA_HandleTypeDef
-#else
+  HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
+  HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_IRDA_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing */
+  HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/** 
+  * @brief IRDA handle Structure definition  
+  */  
 typedef struct
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 {
-  USART_TypeDef               *Instance;        /*!<  USART registers base address       */
-
-  IRDA_InitTypeDef            Init;             /*!<  IRDA communication parameters      */
-
-  uint8_t                     *pTxBuffPtr;      /*!<  Pointer to IRDA Tx transfer Buffer */
-
-  uint16_t                    TxXferSize;       /*!<  IRDA Tx Transfer size              */
-
-  __IO uint16_t               TxXferCount;      /*!<  IRDA Tx Transfer Counter           */
-
-  uint8_t                     *pRxBuffPtr;      /*!<  Pointer to IRDA Rx transfer Buffer */
-
-  uint16_t                    RxXferSize;       /*!<  IRDA Rx Transfer size              */
-
-  __IO uint16_t               RxXferCount;      /*!<  IRDA Rx Transfer Counter           */
-
-  DMA_HandleTypeDef           *hdmatx;          /*!<  IRDA Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef           *hdmarx;          /*!<  IRDA Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef             Lock;             /*!<  Locking object                     */
-
-  __IO HAL_IRDA_StateTypeDef  gState;           /*!<  IRDA state information related to global Handle management
-                                                   and also related to Tx operations.
-                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO HAL_IRDA_StateTypeDef  RxState;          /*!<  IRDA state information related to Rx operations.
-                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO uint32_t               ErrorCode;        /*!< IRDA Error code                    */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
-
-  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
-
-  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
-
-  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
-
-
-  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-} IRDA_HandleTypeDef;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL IRDA Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
-  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
-  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
-  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
-  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
-  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
-  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
-  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
-
-  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
-  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
-
-} HAL_IRDA_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL IRDA Callback pointer definition
-  */
-typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
-
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
+  USART_TypeDef               *Instance;        /* USART registers base address       */
+  
+  IRDA_InitTypeDef            Init;             /* IRDA communication parameters      */
+  
+  uint8_t                     *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
+  
+  uint16_t                    TxXferSize;       /* IRDA Tx Transfer size              */
+  
+  uint16_t                    TxXferCount;      /* IRDA Tx Transfer Counter           */
+  
+  uint8_t                     *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
+  
+  uint16_t                    RxXferSize;       /* IRDA Rx Transfer size              */
+  
+  uint16_t                    RxXferCount;      /* IRDA Rx Transfer Counter           */  
+  
+  DMA_HandleTypeDef           *hdmatx;          /* IRDA Tx DMA Handle parameters      */
+    
+  DMA_HandleTypeDef           *hdmarx;          /* IRDA Rx DMA Handle parameters      */
+  
+  HAL_LockTypeDef             Lock;             /* Locking object                     */
+  
+  __IO HAL_IRDA_StateTypeDef  State;            /* IRDA communication state           */
+  
+  __IO uint32_t               ErrorCode;        /* IRDA Error code                    */
+
+}IRDA_HandleTypeDef;
 /**
   * @}
   */
@@ -233,17 +144,15 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @{
   */
 /** @defgroup IRDA_Error_Code IRDA Error Code
+  * @brief    IRDA Error Code 
   * @{
-  */
-#define HAL_IRDA_ERROR_NONE        0x00000000U   /*!< No error            */
-#define HAL_IRDA_ERROR_PE          0x00000001U   /*!< Parity error        */
-#define HAL_IRDA_ERROR_NE          0x00000002U   /*!< Noise error         */
-#define HAL_IRDA_ERROR_FE          0x00000004U   /*!< Frame error         */
-#define HAL_IRDA_ERROR_ORE         0x00000008U   /*!< Overrun error       */
-#define HAL_IRDA_ERROR_DMA         0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)   /*!< Invalid Callback error  */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+  */ 
+#define HAL_IRDA_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
+#define HAL_IRDA_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
+#define HAL_IRDA_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
+#define HAL_IRDA_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
+#define HAL_IRDA_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
+#define HAL_IRDA_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
 /**
   * @}
   */
@@ -251,28 +160,28 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
 /** @defgroup IRDA_Word_Length IRDA Word Length
   * @{
   */
-#define IRDA_WORDLENGTH_8B         0x00000000U
-#define IRDA_WORDLENGTH_9B         ((uint32_t)USART_CR1_M)
+#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
 
 /** @defgroup IRDA_Parity  IRDA Parity
   * @{
-  */
-#define IRDA_PARITY_NONE           0x00000000U
-#define IRDA_PARITY_EVEN           ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD            ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+  */ 
+#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
+#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup IRDA_Mode IRDA Transfer Mode
+/** @defgroup IRDA_Mode IRDA Transfer Mode 
   * @{
-  */
-#define IRDA_MODE_RX               ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX               ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX            ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+  */ 
+#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
@@ -280,8 +189,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
 /** @defgroup IRDA_Low_Power IRDA Low Power
   * @{
   */
-#define IRDA_POWERMODE_LOWPOWER    ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL      0x00000000U
+#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x00000000)
 /**
   * @}
   */
@@ -291,18 +200,18 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define IRDA_FLAG_TXE              ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC               ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE             ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE             ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE              ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE               ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE               ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE               ((uint32_t)USART_SR_PE)
+#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)
+#define IRDA_FLAG_TC                        ((uint32_t)0x00000040)
+#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define IRDA_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)
+#define IRDA_FLAG_NE                        ((uint32_t)0x00000004)
+#define IRDA_FLAG_FE                        ((uint32_t)0x00000002)
+#define IRDA_FLAG_PE                        ((uint32_t)0x00000001)
 /**
   * @}
   */
-
+  
 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
   *        Elements values convention: 0xY000XXXX
   *           - XXXX  : Interrupt mask in the XX register
@@ -312,16 +221,16 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   *                 - 11: CR3 register
   * @{
   */
-#define IRDA_IT_PE                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define IRDA_IT_TXE                ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define IRDA_IT_TC                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define IRDA_IT_RXNE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define IRDA_IT_PE                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define IRDA_IT_TXE                         ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define IRDA_IT_TC                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define IRDA_IT_RXNE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
 
-#define IRDA_IT_LBD                ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+#define IRDA_IT_LBD                         ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
 
-#define IRDA_IT_CTS                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define IRDA_IT_ERR                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define IRDA_IT_CTS                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define IRDA_IT_ERR                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
 /**
   * @}
   */
@@ -329,45 +238,32 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
 /**
   * @}
   */
-
+  
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
   * @{
   */
 
-/** @brief Reset IRDA handle gstate & RxState
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief Reset IRDA handle state
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the IRDA DR register
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief  Flushes the IRDA DR register 
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   */
 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
 
-/** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+/** @brief  Checks whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
   *            @arg IRDA_FLAG_TC:   Transmission Complete flag
@@ -381,78 +277,78 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   */
 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+/** @brief  Clears the specified IRDA pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *   
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)     \
   do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
+    __IO uint32_t tmpreg;                       \
     tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0U)
+  } while(0)
 
 /** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
+/** @brief  Enables or disables the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg IRDA_IT_TC:   Transmission complete interrupt
@@ -462,71 +358,57 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-/** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__ specifies the IRDA interrupt source to check.
+    
+/** @brief  Checks whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
   *            @arg IRDA_IT_TC:  Transmission complete interrupt
   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_ERR: Error interrupt
+  *            @arg USART_IT_ERR: Error interrupt
   *            @arg IRDA_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
 
 /** @brief  Macro to enable the IRDA's one bit sample method
-  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
   * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
+  */     
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the IRDA's one bit sample method
-  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
   * @retval None
-  */
+  */      
 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral 
   *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+#define __HAL_IRDA_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral 
   *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+#define __HAL_IRDA_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 
 /**
   * @}
@@ -536,7 +418,7 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
 /** @addtogroup IRDA_Exported_Functions
   * @{
   */
-
+  
 /** @addtogroup IRDA_Exported_Functions_Group1
   * @{
   */
@@ -545,13 +427,6 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
@@ -569,23 +444,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
 /**
   * @}
   */
@@ -598,7 +462,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
@@ -612,14 +476,14 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
   */
 
 /** @brief IRDA interruptions flag mask
-  *
-  */
+  * 
+  */ 
 #define IRDA_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
 
-#define IRDA_CR1_REG_INDEX         1U
-#define IRDA_CR2_REG_INDEX         2U
-#define IRDA_CR3_REG_INDEX         3U
+#define IRDA_CR1_REG_INDEX                  1    
+#define IRDA_CR2_REG_INDEX                  2    
+#define IRDA_CR3_REG_INDEX                  3 
 /**
   * @}
   */
@@ -628,31 +492,20 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
   * @{
   */
-#define IS_IRDA_WORD_LENGTH(LENGTH)   (((LENGTH) == IRDA_WORDLENGTH_8B) || \
-                                       ((LENGTH) == IRDA_WORDLENGTH_9B))
-
-#define IS_IRDA_PARITY(PARITY)        (((PARITY) == IRDA_PARITY_NONE) || \
-                                       ((PARITY) == IRDA_PARITY_EVEN) || \
-                                       ((PARITY) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_MODE(MODE)            ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
-
-#define IS_IRDA_POWERMODE(MODE)       (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
-                                       ((MODE) == IRDA_POWERMODE_NORMAL))
-
-#define IS_IRDA_BAUDRATE(BAUDRATE)    ((BAUDRATE) < 115201U)
-
-#define IRDA_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(4U*(_BAUD_)))
-
-#define IRDA_DIVMANT(_PCLK_, _BAUD_)  (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_)  (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define IRDA_BRR(_PCLK_, _BAUD_)      (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
-                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
-                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+                                     ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+                                ((PARITY) == IRDA_PARITY_EVEN) || \
+                                ((PARITY) == IRDA_PARITY_ODD))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+                                 ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+
+#define IRDA_DIV(_PCLK_, _BAUD_)                  (((_PCLK_)*25)/(4*(_BAUD_)))
+#define IRDA_DIVMANT(_PCLK_, _BAUD_)              (IRDA_DIV((_PCLK_), (_BAUD_))/100)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_)              (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define IRDA_BRR(_PCLK_, _BAUD_)                  ((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
 
 /**
   * @}
@@ -669,12 +522,12 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-
+  */ 
+  
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h

@@ -2,24 +2,42 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_iwdg.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_IWDG_H
-#define STM32F2xx_HAL_IWDG_H
+#ifndef __STM32F2xx_HAL_IWDG_H
+#define __STM32F2xx_HAL_IWDG_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -34,35 +52,49 @@
 
 /** @addtogroup IWDG
   * @{
-  */
+  */ 
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup IWDG_Exported_Types IWDG Exported Types
   * @{
   */
+   
+/** 
+  * @brief  IWDG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
+  HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
+  HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
+  HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
+  HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
+}HAL_IWDG_StateTypeDef;
 
 /** 
-  * @brief  IWDG Init structure definition
-  */
+  * @brief  IWDG Init structure definition  
+  */ 
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
                             This parameter can be a value of @ref IWDG_Prescaler */
-
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+  
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+}IWDG_InitTypeDef;
 
-} IWDG_InitTypeDef;
-
-/**
-  * @brief  IWDG Handle Structure definition
-  */
+/** 
+  * @brief  IWDG Handle Structure definition  
+  */ 
 typedef struct
 {
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
-
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
+  
   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-
+  
+  HAL_LockTypeDef              Lock;       /*!< IWDG Locking object      */
+  
+  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
 }IWDG_HandleTypeDef;
 
 /**
@@ -74,20 +106,43 @@ typedef struct
   * @{
   */
 
-/** @defgroup IWDG_Prescaler IWDG Prescaler
+/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
+  * @brief IWDG registers bit mask
   * @{
   */
-#define IWDG_PRESCALER_4                0x00000000U                   /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define IWDG_KEY_RELOAD                            ((uint32_t)0xAAAA)  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                            ((uint32_t)0xCCCC)  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE               ((uint32_t)0x5555)  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE              ((uint32_t)0x0000)  /*!< IWDG KR Write Access Disable */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag_definition IWDG Flag definition
+  * @{
+  */ 
+#define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
+#define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
 /**
   * @}
   */
 
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */ 
+#define IWDG_PRESCALER_4     ((uint8_t)0x00)  /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
+/**
+  * @}
+  */ 
+
 /**
   * @}
   */
@@ -97,107 +152,120 @@ typedef struct
   * @{
   */
 
+/** @brief Reset IWDG handle state
+  * @param  __HANDLE__: IWDG handle.
+  * @retval None
+  */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
 /**
-  * @brief  Enable the IWDG peripheral.
-  * @param  __HANDLE__  IWDG handle
+  * @brief  Enables the IWDG peripheral.
+  * @param  __HANDLE__: IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
 
 /**
-  * @brief  Reload IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR & IWDG_RLR registers disabled).
-  * @param  __HANDLE__  IWDG handle
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  __HANDLE__: IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
 
 /**
-  * @}
+  * @brief  Gets the selected IWDG's flag status.
+  * @param  __HANDLE__: IWDG handle
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @}
+  */ 
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+/** @addtogroup IWDG_Exported_Functions
   * @{
   */
 
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+/** @addtogroup IWDG_Exported_Functions_Group1
   * @{
   */
-/* Initialization/Start functions  ********************************************/
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+/** @addtogroup IWDG_Exported_Functions_Group2
   * @{
   */
 /* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
+/** @addtogroup IWDG_Exported_Functions_Group3
   * @{
   */
+/* Peripheral State functions  ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
 
 /**
-  * @brief  IWDG Key Register BitMask
+  * @}
   */
-#define IWDG_KEY_RELOAD                 0x0000AAAAU  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                 0x0000CCCCU  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555U  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000U  /*!< IWDG KR Write Access Disable */
 
 /**
   * @}
-  */
+  */ 
 
-/* Private macros ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
 /** @defgroup IWDG_Private_Macros IWDG Private Macros
   * @{
   */
 
 /**
-  * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__  IWDG handle
+  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__: IWDG handle
   * @retval None
   */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
 
 /**
-  * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__  IWDG handle
+  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__: IWDG handle
   * @retval None
   */
 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
 
+
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                          ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
 /**
-  * @brief  Check IWDG prescaler value.
-  * @param  __PRESCALER__  IWDG prescaler value
-  * @retval None
+  * @}
   */
-#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
 
-/**
-  * @brief  Check IWDG reload value.
-  * @param  __RELOAD__  IWDG reload value
-  * @retval None
+/* Private define ------------------------------------------------------------*/
+ /** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
   */
-#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
 
 /**
   * @}
@@ -205,17 +273,16 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-
-
+  */ 
+  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_IWDG_H */
+#endif /* __STM32F2xx_HAL_IWDG_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h

@@ -2,32 +2,50 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nand.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_NAND_H
-#define STM32F2xx_HAL_NAND_H
+#ifndef __STM32F2xx_HAL_NAND_H
+#define __STM32F2xx_HAL_NAND_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
+  #include "stm32f2xx_ll_fsmc.h"
+
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -35,7 +53,7 @@ extern "C" {
 
 /** @addtogroup NAND
   * @{
-  */
+  */ 
 
 /* Exported typedef ----------------------------------------------------------*/
 /* Exported types ------------------------------------------------------------*/
@@ -43,139 +61,92 @@ extern "C" {
   * @{
   */
 
-/**
+/** 
   * @brief  HAL NAND State structures definition
   */
 typedef enum
 {
-  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
-  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
-  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
-  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
-} HAL_NAND_StateTypeDef;
-
-/**
+  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
+}HAL_NAND_StateTypeDef;
+   
+/** 
   * @brief  NAND Memory electronic signature Structure definition
   */
 typedef struct
 {
   /*<! NAND memory electronic signature maker and device IDs */
 
-  uint8_t Maker_Id;
+  uint8_t Maker_Id; 
 
   uint8_t Device_Id;
 
   uint8_t Third_Id;
 
   uint8_t Fourth_Id;
-} NAND_IDTypeDef;
+}NAND_IDTypeDef;
 
-/**
+/** 
   * @brief  NAND Memory address Structure definition
   */
-typedef struct
+typedef struct 
 {
   uint16_t Page;   /*!< NAND memory Page address  */
 
-  uint16_t Plane;   /*!< NAND memory Zone address  */
+  uint16_t Zone;   /*!< NAND memory Zone address  */
 
   uint16_t Block;  /*!< NAND memory Block address */
 
-} NAND_AddressTypeDef;
+}NAND_AddressTypeDef;
 
-/**
+/** 
   * @brief  NAND Memory info Structure definition
-  */
+  */ 
 typedef struct
 {
-  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
-                                              for 8 bits adressing or words for 16 bits addressing             */
-
-  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
-                                              for 8 bits adressing or words for 16 bits addressing             */
+  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
 
-  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
+  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
 
-  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
+  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
 
-  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
+  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
 
-  uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
+  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+}NAND_InfoTypeDef;
 
-  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
-                                              parameter is mandatory for some NAND parts after the read
-                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
-                                              Example: Toshiba THTH58BYG3S0HBAI6.
-                                              This parameter could be ENABLE or DISABLE
-                                              Please check the Read Mode sequnece in the NAND device datasheet */
-} NAND_DeviceConfigTypeDef;
-
-/**
+/** 
   * @brief  NAND handle Structure definition
-  */
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-typedef struct __NAND_HandleTypeDef
-#else
+  */   
 typedef struct
-#endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
 {
-  FSMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
+  FSMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
+  
+  FSMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
 
-  FSMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
+  HAL_LockTypeDef              Lock;       /*!< NAND locking object                           */
 
-  HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
-
-  __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
-
-  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
-
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-  void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */
-  void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */
-  void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */
-#endif
-} NAND_HandleTypeDef;
-
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL NAND Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
-  HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
-  HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
-}HAL_NAND_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL NAND Callback pointer definition
-  */
-typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                      */
 
+  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure     */
+}NAND_HandleTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
 /** @defgroup NAND_Exported_Macros NAND Exported Macros
  * @{
- */
+ */ 
 
 /** @brief Reset NAND handle state
-  * @param  __HANDLE__ specifies the NAND handle.
+  * @param  __HANDLE__: specifies the NAND handle.
   * @retval None
   */
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
-                                                               (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
 
 /**
   * @}
@@ -185,60 +156,43 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
   * @{
   */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+    
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
   * @{
   */
 
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-
-void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 
 /**
   * @}
   */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+  
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 
   * @{
   */
 
 /* IO operation functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
+HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
+uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-/* NAND callback registering/unregistering */
-HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
-HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
-
 /**
   * @}
   */
 
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 
   * @{
   */
 
@@ -250,8 +204,8 @@ HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
 /**
   * @}
   */
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+    
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 
   * @{
   */
 /* NAND State functions *******************************************************/
@@ -264,41 +218,41 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 /**
   * @}
   */
-
+    
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup NAND_Private_Constants NAND Private Constants
   * @{
   */
-#define NAND_DEVICE1               ((uint32_t)0x70000000U)
-#define NAND_DEVICE2               ((uint32_t)0x80000000U)
-#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
-
-#define CMD_AREA                   ((uint32_t)(1UL<<16U))  /* A16 = CLE high */
-#define ADDR_AREA                  ((uint32_t)(1UL<<17U))  /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A            ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B            ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C            ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
-
-#define NAND_CMD_WRITE0            ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0            ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
-#define NAND_CMD_READID            ((uint8_t)0x90U)
-#define NAND_CMD_STATUS            ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
-#define NAND_CMD_RESET             ((uint8_t)0xFFU)
+#define NAND_DEVICE1               ((uint32_t)0x70000000) 
+#define NAND_DEVICE2               ((uint32_t)0x80000000) 
+#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
+
+#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
 
 /* NAND memory status */
-#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
-#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
-#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
-#define NAND_BUSY                  ((uint32_t)0x00000000U)
-#define NAND_ERROR                 ((uint32_t)0x00000001U)
-#define NAND_READY                 ((uint32_t)0x00000040U)
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
 /**
   * @}
   */
@@ -310,59 +264,42 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 
 /**
   * @brief  NAND memory address computation.
-  * @param  __ADDRESS__ NAND memory address.
-  * @param  __HANDLE__  NAND handle.
+  * @param  __ADDRESS__: NAND memory address.
+  * @param  __HANDLE__ : NAND handle.
   * @retval NAND Raw address value
   */
 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
-                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
-
-/**
-  * @brief  NAND memory Column address computation.
-  * @param  __HANDLE__ NAND handle.
-  * @retval NAND Raw address value
-  */
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
 
 /**
   * @brief  NAND memory address cycling.
-  * @param  __ADDRESS__ NAND memory address.
+  * @param  __ADDRESS__: NAND memory address.
   * @retval NAND address cycling value.
   */
 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
-
-/**
-  * @brief  NAND memory Columns cycling.
-  * @param  __ADDRESS__ NAND memory address.
-  * @retval NAND Column address cycling value.
-  */
-#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
-
 /**
   * @}
   */
 
+    
 /**
   * @}
   */
-
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-
+  */ 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_NAND_H */
+#endif /* __STM32F2xx_HAL_NAND_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h

@@ -2,32 +2,50 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nor.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_NOR_H
-#define STM32F2xx_HAL_NOR_H
+#ifndef __STM32F2xx_HAL_NOR_H
+#define __STM32F2xx_HAL_NOR_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
+  #include "stm32f2xx_ll_fsmc.h"
+
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -35,35 +53,35 @@ extern "C" {
 
 /** @addtogroup NOR
   * @{
-  */
+  */ 
 
 /* Exported typedef ----------------------------------------------------------*/
 /** @defgroup NOR_Exported_Types NOR Exported Types
   * @{
   */
 
-/**
-  * @brief  HAL SRAM State structures definition
-  */
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
 typedef enum
-{
-  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
-  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
-  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
-  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
-} HAL_NOR_StateTypeDef;
+{  
+  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
+}HAL_NOR_StateTypeDef;
 
 /**
   * @brief  FSMC NOR Status typedef
   */
 typedef enum
 {
-  HAL_NOR_STATUS_SUCCESS  = 0U,
+  HAL_NOR_STATUS_SUCCESS  = 0,
   HAL_NOR_STATUS_ONGOING,
   HAL_NOR_STATUS_ERROR,
   HAL_NOR_STATUS_TIMEOUT
-} HAL_NOR_StatusTypeDef;
+}HAL_NOR_StatusTypeDef;
 
 /**
   * @brief  FSMC NOR ID typedef
@@ -76,11 +94,11 @@ typedef struct
 
   uint16_t Device_Code2;
 
-  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
-                                    These codes can be accessed by performing read operations with specific
-                                    control signals and addresses set.They can also be accessed by issuing
+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
+                                    These codes can be accessed by performing read operations with specific 
+                                    control signals and addresses set.They can also be accessed by issuing 
                                     an Auto Select command                                                   */
-} NOR_IDTypeDef;
+}NOR_IDTypeDef;
 
 /**
   * @brief  FSMC NOR CFI typedef
@@ -88,7 +106,7 @@ typedef struct
 typedef struct
 {
   /*!< Defines the information stored in the memory's Common flash interface
-       which contains a description of various electrical and timing parameters,
+       which contains a description of various electrical and timing parameters, 
        density information and functions supported by the memory                   */
 
   uint16_t CFI_1;
@@ -98,17 +116,12 @@ typedef struct
   uint16_t CFI_3;
 
   uint16_t CFI_4;
-} NOR_CFITypeDef;
+}NOR_CFITypeDef;
 
-/**
+/** 
   * @brief  NOR handle Structure definition
-  */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-typedef struct __NOR_HandleTypeDef
-#else
+  */ 
 typedef struct
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
-
 {
   FSMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
 
@@ -120,62 +133,33 @@ typedef struct
 
   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-  void  (* MspInitCallback)        ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp Init callback              */
-  void  (* MspDeInitCallback)      ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp DeInit callback            */
-#endif
-} NOR_HandleTypeDef;
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL NOR Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
-  HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
-}HAL_NOR_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL NOR Callback pointer definition
-  */
-typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif
+}NOR_HandleTypeDef;
 /**
   * @}
   */
-
+  
 /* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
 /** @defgroup NOR_Exported_Macros NOR Exported Macros
   * @{
   */
 /** @brief Reset NOR handle state
-  * @param  __HANDLE__ specifies the NOR handle.
+  * @param  __HANDLE__: specifies the NOR handle.
   * @retval None
   */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
-                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
-  * @{
-  */
-
-/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
+/** @addtogroup NOR_Exported_Functions 
+ *  @{
+ */
 
+/** @addtogroup NOR_Exported_Functions_Group1
+ *  @{
+ */
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
@@ -185,11 +169,10 @@ void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 /**
   * @}
   */
-
-/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
-  * @{
-  */
-
+  
+/** @addtogroup NOR_Exported_Functions_Group2
+ *  @{
+ */
 /* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
@@ -202,42 +185,34 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif
 /**
   * @}
   */
-
-/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
-  * @{
-  */
-
+  
+/** @addtogroup NOR_Exported_Functions_Group3
+ *  @{
+ */
 /* NOR Control functions  *****************************************************/
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 /**
   * @}
   */
-
-/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
-  * @{
-  */
-
+  
+/** @addtogroup NOR_Exported_Functions_Group4
+ *  @{
+ */
 /* NOR State functions ********************************************************/
 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 /**
   * @}
   */
-
+    
 /**
   * @}
   */
-
+  
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -245,29 +220,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   * @{
   */
 /* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
+#define MC_ADDRESS               ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
 
 /* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x61U)
-#define CFI2_ADDRESS             ((uint16_t)0x62U)
-#define CFI3_ADDRESS             ((uint16_t)0x63U)
-#define CFI4_ADDRESS             ((uint16_t)0x64U)
+#define CFI1_ADDRESS             ((uint16_t)0x61)
+#define CFI2_ADDRESS             ((uint16_t)0x62)
+#define CFI3_ADDRESS             ((uint16_t)0x63)
+#define CFI4_ADDRESS             ((uint16_t)0x64)
 
 /* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFFU)
-
+#define NOR_TMEOUT               ((uint16_t)0xFFFF)
+   
 /* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x0U)
-#define NOR_MEMORY_16B           ((uint8_t)0x1U)
+#define NOR_MEMORY_8B            ((uint8_t)0x0)
+#define NOR_MEMORY_16B           ((uint8_t)0x1)
 
 /* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
-#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
-#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
-#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
+#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
+#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
+#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
+#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
 /**
   * @}
   */
@@ -278,26 +253,21 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   */
 /**
   * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS NOR base address
-  * @param  __NOR_MEMORY_WIDTH_ NOR memory width
-  * @param  __ADDRESS__ NOR memory address
+  * @param  __NOR_ADDRESS__: NOR base address 
+  * @param  NOR_MEMORY_WIDTH: NOR memory width
+  * @param  ADDRESS: NOR memory address 
   * @retval NOR shifted address value
   */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
-              ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
-              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
-              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS)    (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
+                                                                                 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
+ 
 /**
   * @brief  NOR memory write data to specified address.
-  * @param  __ADDRESS__ NOR memory address
-  * @param  __DATA__ Data to write
+  * @param  ADDRESS: NOR memory address 
+  * @param  DATA: Data to write
   * @retval None
   */
-#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
-                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
-                                               __DSB();                                                    \
-                                             } while(0)
+#define NOR_WRITE(ADDRESS, DATA)  (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
 
 /**
   * @}
@@ -305,17 +275,16 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
 
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_NOR_H */
+#endif /* __STM32F2xx_HAL_NOR_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h

@@ -2,30 +2,47 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pccard.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of PCCARD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCCARD_H
-#define STM32F2xx_HAL_PCCARD_H
+#ifndef __STM32F2xx_HAL_PCCARD_H
+#define __STM32F2xx_HAL_PCCARD_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_fsmc.h"
 
@@ -33,74 +50,49 @@ extern "C" {
   * @{
   */
 
+
 /** @addtogroup PCCARD
   * @{
-  */
+  */ 
 
 /* Exported typedef ----------------------------------------------------------*/
 /** @defgroup PCCARD_Exported_Types PCCARD Exported Types
   * @{
   */
 
-/**
-  * @brief  HAL PCCARD State structures definition
-  */
+/** 
+  * @brief  HAL PCCARD State structures definition  
+  */ 
 typedef enum
 {
-  HAL_PCCARD_STATE_RESET     = 0x00U,    /*!< PCCARD peripheral not yet initialized or disabled */
-  HAL_PCCARD_STATE_READY     = 0x01U,    /*!< PCCARD peripheral ready                           */
-  HAL_PCCARD_STATE_BUSY      = 0x02U,    /*!< PCCARD peripheral busy                            */
-  HAL_PCCARD_STATE_ERROR     = 0x04U     /*!< PCCARD peripheral error                           */
-} HAL_PCCARD_StateTypeDef;
+  HAL_PCCARD_STATE_RESET     = 0x00,    /*!< PCCARD peripheral not yet initialized or disabled */
+  HAL_PCCARD_STATE_READY     = 0x01,    /*!< PCCARD peripheral ready                           */
+  HAL_PCCARD_STATE_BUSY      = 0x02,    /*!< PCCARD peripheral busy                            */   
+  HAL_PCCARD_STATE_ERROR     = 0x04     /*!< PCCARD peripheral error                           */
+}HAL_PCCARD_StateTypeDef;
 
 typedef enum
 {
-  HAL_PCCARD_STATUS_SUCCESS = 0U,
+  HAL_PCCARD_STATUS_SUCCESS = 0,
   HAL_PCCARD_STATUS_ONGOING,
   HAL_PCCARD_STATUS_ERROR,
   HAL_PCCARD_STATUS_TIMEOUT
-} HAL_PCCARD_StatusTypeDef;
+}HAL_PCCARD_StatusTypeDef;
 
-/**
-  * @brief  FSMC_PCCARD handle Structure definition
-  */
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)  
-typedef struct __PCCARD_HandleTypeDef
-#else
+/** 
+  * @brief  FSMC_PCCARD handle Structure definition  
+  */   
 typedef struct
-#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS  */
 {
   FSMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
-
+  
   FSMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
 
   __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
-
-  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */
-
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-  void  (* MspInitCallback)        ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD Msp Init callback              */
-  void  (* MspDeInitCallback)      ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD Msp DeInit callback            */
-  void  (* ItCallback)             ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD IT callback                    */
-#endif
-} PCCARD_HandleTypeDef;
-
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL PCCARD Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_PCCARD_MSP_INIT_CB_ID       = 0x00U,  /*!< PCCARD MspInit Callback ID          */
-  HAL_PCCARD_MSP_DEINIT_CB_ID     = 0x01U,  /*!< PCCARD MspDeInit Callback ID        */
-  HAL_PCCARD_IT_CB_ID             = 0x02U   /*!< PCCARD IT Callback ID               */
-}HAL_PCCARD_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL PCCARD Callback pointer definition
-  */
-typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
-#endif
+   
+  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */ 
+ 
+}PCCARD_HandleTypeDef;
 /**
   * @}
   */
@@ -111,28 +103,20 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
   * @{
   */
 /** @brief Reset PCCARD handle state
-  * @param  __HANDLE__ specifies the PCCARD handle.
+  * @param  __HANDLE__: specifies the PCCARD handle.
   * @retval None
   */
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__)       do {                                               \
-                                                               (__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;         \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \
-                                                             } while(0)
-#else
 #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-#endif
 /**
   * @}
-  */
+  */ 
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions
+/** @addtogroup PCCARD_Exported_Functions 
   * @{
   */
 
-/** @addtogroup PCCARD_Exported_Functions_Group1
+/** @addtogroup PCCARD_Exported_Functions_Group1 
   * @{
   */
 /* Initialization/de-initialization functions  **********************************/
@@ -156,11 +140,6 @@ HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
 void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
 void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
 
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-/* PCCARD callback registering/unregistering */
-HAL_StatusTypeDef  HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef  HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
-#endif
 /**
   * @}
   */
@@ -185,11 +164,11 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 /** @defgroup PCCARD_Private_Constants PCCARD Private Constants
   * @{
   */
-#define PCCARD_DEVICE_ADDRESS             0x90000000U
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS    0x98000000U              /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_DEVICE_ADDRESS             ((uint32_t)0x90000000)
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS    ((uint32_t)0x98000000)   /* Attribute space size to @0x9BFF FFFF */
 #define PCCARD_COMMON_SPACE_ADDRESS       PCCARD_DEVICE_ADDRESS    /* Common space size to @0x93FF FFFF    */
-#define PCCARD_IO_SPACE_ADDRESS           0x9C000000U              /* IO space size to @0x9FFF FFFF        */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR      0x9C0001F0U              /* IO space size to @0x9FFF FFFF        */
+#define PCCARD_IO_SPACE_ADDRESS           ((uint32_t)0x9C000000)   /* IO space size to @0x9FFF FFFF        */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR      ((uint32_t)0x9C0001F0)   /* IO space size to @0x9FFF FFFF        */
 
 /* Flash-ATA registers description */
 #define ATA_DATA                       ((uint8_t)0x00)    /* Data register */
@@ -215,7 +194,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define PCCARD_PROGR                   ((uint8_t)0x01)
 #define PCCARD_READY                   ((uint8_t)0x40)
 
-#define PCCARD_SECTOR_SIZE             255U               /* In half words */
+#define PCCARD_SECTOR_SIZE             ((uint32_t)255)    /* In half words */ 
 
 /**
   * @}
@@ -225,7 +204,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define HAL_CF_DeInit               HAL_PCCARD_DeInit
 #define HAL_CF_MspInit              HAL_PCCARD_MspInit
 #define HAL_CF_MspDeInit            HAL_PCCARD_MspDeInit
-
+                                        
 #define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
 #define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
 #define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
@@ -233,27 +212,28 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define HAL_CF_Reset                HAL_PCCARD_Reset
 #define HAL_CF_IRQHandler           HAL_PCCARD_IRQHandler
 #define HAL_CF_ITCallback           HAL_PCCARD_ITCallback
-
+                                        
 #define HAL_CF_GetState             HAL_PCCARD_GetState
 #define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
 #define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
-
+                                        
 #define HAL_CF_STATUS_SUCCESS       HAL_PCCARD_STATUS_SUCCESS
 #define HAL_CF_STATUS_ONGOING       HAL_PCCARD_STATUS_ONGOING
 #define HAL_CF_STATUS_ERROR         HAL_PCCARD_STATUS_ERROR
 #define HAL_CF_STATUS_TIMEOUT       HAL_PCCARD_STATUS_TIMEOUT
 #define HAL_CF_StatusTypeDef        HAL_PCCARD_StatusTypeDef
 
-#define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS
+
+#define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS               
 #define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS
-#define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS
-#define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR
+#define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS   
+#define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS       
+#define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR  
 
 #define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
-#define CF_BUSY                     PCCARD_BUSY
-#define CF_PROGR                    PCCARD_PROGR
-#define CF_READY                    PCCARD_READY
+#define CF_BUSY                     PCCARD_BUSY         
+#define CF_PROGR                    PCCARD_PROGR        
+#define CF_READY                    PCCARD_READY        
 
 #define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
 
@@ -263,15 +243,15 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
   */
 
 
+
 /**
   * @}
   */
-
-
+  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_PCCARD_H */
+#endif /* __STM32F2xx_HAL_PCCARD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h

@@ -2,51 +2,67 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCD_H
-#define STM32F2xx_HAL_PCD_H
+#ifndef __STM32F2xx_HAL_PCD_H
+#define __STM32F2xx_HAL_PCD_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_usb.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-
+   
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup PCD
   * @{
-  */
+  */ 
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup PCD_Exported_Types PCD Exported Types
   * @{
   */
-
+   
 /**
   * @brief  PCD State structure definition
   */
-typedef enum
+typedef enum 
 {
   HAL_PCD_STATE_RESET   = 0x00,
   HAL_PCD_STATE_READY   = 0x01,
@@ -55,85 +71,30 @@ typedef enum
   HAL_PCD_STATE_TIMEOUT = 0x04
 } PCD_StateTypeDef;
 
-/* Device LPM suspend state */
-typedef enum
-{
-  LPM_L0 = 0x00, /* on */
-  LPM_L1 = 0x01, /* LPM L1 sleep */
-  LPM_L2 = 0x02, /* suspend */
-  LPM_L3 = 0x03, /* off */
-} PCD_LPM_StateTypeDef;
-
-typedef enum
-{
-  PCD_LPM_L0_ACTIVE = 0x00, /* on */
-  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-} PCD_LPM_MsgTypeDef;
-
-typedef enum
-{
-  PCD_BCD_ERROR                     = 0xFF,
-  PCD_BCD_CONTACT_DETECTION         = 0xFE,
-  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
-  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
-  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
-  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
-
-} PCD_BCD_MsgTypeDef;
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
 
-/**
-  * @brief  PCD Handle Structure definition
-  */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-typedef struct __PCD_HandleTypeDef
-#else
+/** 
+  * @brief  PCD Handle Structure definition  
+  */ 
 typedef struct
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
-  PCD_TypeDef             *Instance;   /*!< Register base address              */
-  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
-  __IO uint8_t            USB_Address; /*!< USB Address                        */
-  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
-  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
-  uint32_t                Setup[12];   /*!< Setup packet buffer                */
-  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
-  uint32_t                BESL;
-
-  void                    *pData;      /*!< Pointer to upper stack Handler */
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
-  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
-  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
-  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
-  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
-  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
-  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
-
-  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
-  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
-  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
-  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
-
-  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
-  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  PCD_TypeDef             *Instance;    /*!< Register base address              */
+  PCD_InitTypeDef         Init;         /*!< PCD required parameters            */
+  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
+  HAL_LockTypeDef         Lock;         /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;        /*!< PCD communication state            */
+  uint32_t                Setup[12];    /*!< Setup packet buffer                */
+  void                    *pData;       /*!< Pointer to upper stack Handler     */
 } PCD_HandleTypeDef;
 
 /**
   * @}
   */
 
-/* Include PCD HAL Extended module */
+/* Include PCD HAL Extension module */
 #include "stm32f2xx_hal_pcd_ex.h"
 
 /* Exported constants --------------------------------------------------------*/
@@ -144,31 +105,31 @@ typedef struct
 /** @defgroup PCD_Speed PCD Speed
   * @{
   */
-#define PCD_SPEED_HIGH               USBD_HS_SPEED
-#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
-#define PCD_SPEED_FULL               USBD_FS_SPEED
+#define PCD_SPEED_HIGH               0
+#define PCD_SPEED_HIGH_IN_FULL       1
+#define PCD_SPEED_FULL               2
 /**
   * @}
   */
-
+  
 /** @defgroup PCD_PHY_Module PCD PHY Module
   * @{
   */
-#define PCD_PHY_ULPI                 1U
-#define PCD_PHY_EMBEDDED             2U
-#define PCD_PHY_UTMI                 3U
+#define PCD_PHY_ULPI                 1
+#define PCD_PHY_EMBEDDED             2
 /**
   * @}
   */
 
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition
-  * @brief  PCD Error Code definition
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
   * @{
   */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
+#ifndef USBD_HS_TRDT_VALUE
+ #define USBD_HS_TRDT_VALUE           9
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE           5
+#endif /* USBD_FS_TRDT_VALUE */
 /**
   * @}
   */
@@ -182,45 +143,68 @@ typedef struct
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
+#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
 
 
 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
+                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
 
 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+                                                      
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+                                                         
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
 
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
+
+#define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
 
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
 
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
-                        do { \
-                             EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
-                             EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
-                           } while(0U)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+                                                          EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+                                                      
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
+                                                            EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+                                                                    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
+                                                                    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+                                                                    EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 
+
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
 
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
-                        do { \
-                             EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
-                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
-                           } while(0U)
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                          EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
+
+                                                      
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
 
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                                   EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE 
 
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 
 /**
   * @}
   */
@@ -238,61 +222,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
-  * @brief  HAL USB OTG PCD Callback ID enumeration definition
-  * @{
-  */
-typedef enum
-{
-  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
-  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
-  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
-  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
-  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
-  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
-  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
-
-  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
-  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
-
-} HAL_PCD_CallbackIDTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
-  * @brief  HAL USB OTG PCD Callback pointer definition
-  * @{
-  */
-
-typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
-typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
-
-/**
-  * @}
-  */
-
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -302,22 +231,22 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
+/* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
 
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
 /**
   * @}
   */
@@ -333,7 +262,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
@@ -350,88 +279,41 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
-  * @{
-  */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
-  * @{
-  */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
-#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 20)  /*!< USB HS EXTI Line WakeUp Interrupt */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#ifndef USB_OTG_DOEPINT_OTEPSPR
-#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
-#endif
-
-#ifndef USB_OTG_DOEPMSK_OTEPSPRM
-#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
-#endif
-
-#ifndef USB_OTG_DOEPINT_NAK
-#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
-#endif
-
-#ifndef USB_OTG_DOEPMSK_NAKM
-#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
-#endif
-
-#ifndef USB_OTG_DOEPINT_STPKTRX
-#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
-#endif
-
-#ifndef USB_OTG_DOEPMSK_NYETM
-#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
-#endif
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
+ 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup PCD_Private_Macros PCD Private Macros
  * @{
  */
-
+/** @defgroup PCD_Instance_definition PCD Instance definition
+  * @{
+  */
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+/**
+  * @}
+  */ 
 /**
   * @}
   */
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  */ 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_PCD_H */
+
+#endif /* __STM32F2xx_HAL_PCD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h

@@ -2,33 +2,50 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @brief   Header file of PCD HAL Extension module.
+  * @version V1.1.0
+  * @date    09-October-2015
+  * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCD_EX_H
-#define STM32F2xx_HAL_PCD_EX_H
+#ifndef __STM32F2xx_HAL_PCD_EX_H
+#define __STM32F2xx_HAL_PCD_EX_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+   
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
@@ -36,47 +53,41 @@ extern "C" {
 /** @addtogroup PCDEx
   * @{
   */
+
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /* Exported macros -----------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+/** @addtogroup PCDEx_Exported_Functions
   * @{
   */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+/** @addtogroup PCDEx_Exported_Functions_Group1
   * @{
   */
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* STM32F2xx_HAL_PCD_EX_H */
+#endif /* __STM32F2xx_HAL_PCD_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_PWR_H
@@ -66,7 +84,7 @@ typedef struct
 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
   * @{
   */
-#define PWR_WAKEUP_PIN1                 0x00000100U
+#define PWR_WAKEUP_PIN1                 ((uint32_t)0x00000100)
 /**
   * @}
   */
@@ -90,13 +108,13 @@ typedef struct
 /** @defgroup PWR_PVD_Mode PWR PVD Mode
   * @{
   */
-#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
 /**
   * @}
   */
@@ -105,7 +123,7 @@ typedef struct
 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
   * @{
   */
-#define PWR_MAINREGULATOR_ON                        0x00000000U
+#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
 #define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
 /**
   * @}
@@ -150,7 +168,7 @@ typedef struct
   */
 
 /** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __FLAG__: specifies the flag to check.
   *           This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
   *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
@@ -171,12 +189,12 @@ typedef struct
 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__ specifies the flag to clear.
+  * @param  __FLAG__: specifies the flag to clear.
   *          This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag
   *            @arg PWR_FLAG_SB: StandBy flag
   */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2)
 
 /**
   * @brief Enable the PVD Exti Line 16.
@@ -232,18 +250,14 @@ typedef struct
   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
-                                                              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
-                                                            }while(0)
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
 
 /**
   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
-                                                              __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
-                                                            }while(0)
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
 
 /**
   * @brief checks whether the specified PVD Exti interrupt flag is set or not.
@@ -341,8 +355,8 @@ void HAL_PWR_DisableSEVOnPend(void);
   */
 /* ------------- PWR registers bit address in the alias region ---------------*/
 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00U
-#define PWR_CSR_OFFSET           0x04U
+#define PWR_CR_OFFSET            0x00
+#define PWR_CSR_OFFSET           0x04
 #define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
 #define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
 /**
@@ -355,11 +369,11 @@ void HAL_PWR_DisableSEVOnPend(void);
 /* --- CR Register ---*/
 /* Alias word address of DBP bit */
 #define DBP_BIT_NUMBER   POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
+#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
 
 /* Alias word address of PVDE bit */
 #define PVDE_BIT_NUMBER  POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
+#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
 /**
   * @}
   */
@@ -370,7 +384,7 @@ void HAL_PWR_DisableSEVOnPend(void);
 /* --- CSR Register ---*/
 /* Alias word address of EWUP bit */
 #define EWUP_BIT_NUMBER  POSITION_VAL(PWR_CSR_EWUP)
-#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
+#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
 /**
   * @}
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_PWR_EX_H
@@ -38,7 +56,7 @@
 
 /* Exported types ------------------------------------------------------------*/ 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWR Exported Constants
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
   * @{
   */
 
@@ -47,7 +65,7 @@
   */ 
 
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWR Exported Constants
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
   *  @{
   */
 /**
@@ -55,7 +73,7 @@
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWR Exported Functions
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
   *  @{
   */
  
@@ -76,30 +94,30 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWR Private Constants
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
   * @{
   */
 
-/** @defgroup PWREx_register_alias_address PWR Register alias address
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
   * @{
   */
 /* ------------- PWR registers bit address in the alias region ---------------*/
 /* --- CR Register ---*/
 /* Alias word address of FPDS bit */
 #define FPDS_BIT_NUMBER          POSITION_VAL(PWR_CR_FPDS)
-#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
+#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
 
  /**
   * @}
   */
 
-/** @defgroup PWREx_CSR_register_alias PWR CSR Register alias address
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
   * @{
   */  
 /* --- CSR Register ---*/
 /* Alias word address of BRE bit */
 #define BRE_BIT_NUMBER   POSITION_VAL(PWR_CSR_BRE)
-#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))    
+#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))    
 /**
   * @}
   */
@@ -109,11 +127,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWR Private Macros
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
   * @{
   */
 
-/** @defgroup PWREx_IS_PWR_Definitions PWR Private macros to check input parameters
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
   * @{
   */
 

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h

@@ -2,20 +2,38 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rcc_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RCC_EX_H
@@ -108,7 +126,7 @@ typedef struct
   */
      
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCC Exported Macros
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
   * @{
   */
 
@@ -117,32 +135,31 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.
-  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
@@ -154,31 +171,6 @@ typedef struct
 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
 
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()    ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET) 
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-	                                       __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-	                                        __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-/**
-  * @}
-  */ 
-
 /**
   * @brief  Enable ETHERNET clock.
   */
@@ -205,11 +197,10 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.
-  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
@@ -221,14 +212,14 @@ typedef struct
 
 #if defined(STM32F215xx) || defined(STM32F217xx)
 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00; \
+                                       __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -242,31 +233,8 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
-#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
-#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
-
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
-#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
-/**
-  * @}
-  */ 
-                                         
 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
   * @brief  Force or release AHB1 peripheral reset.
-  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
@@ -303,7 +271,6 @@ typedef struct
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
@@ -369,7 +336,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCC Private Constants
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
   * @{
   */
 
@@ -387,7 +354,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCC Private Macros
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
   * @{
   */
 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h

@@ -2,24 +2,42 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rng.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_RNG_H
-#define STM32F2xx_HAL_RNG_H
+#ifndef __STM32F2xx_HAL_RNG_H
+#define __STM32F2xx_HAL_RNG_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -32,103 +50,59 @@
   * @{
   */
 
-#if defined (RNG)
-
 /** @defgroup RNG RNG
   * @brief RNG HAL module driver
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 
 /** @defgroup RNG_Exported_Types RNG Exported Types
   * @{
   */
 
-/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition 
   * @{
   */
 typedef enum
 {
-  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
-  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
-
-} HAL_RNG_StateTypeDef;
-
-/**
+  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
+    
+}HAL_RNG_StateTypeDef;
+
+/** 
   * @}
   */
 
-/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   
   * @{
-  */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-typedef struct  __RNG_HandleTypeDef
-#else
+  */ 
 typedef struct
-#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
 {
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */
-
+  RNG_TypeDef                 *Instance;    /*!< Register base address   */ 
+  
   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-
+  
   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-
-  __IO  uint32_t              ErrorCode;     /*!< RNG Error code               */
-
+  
   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
+  
+}RNG_HandleTypeDef;
 
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
-  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
-
-  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
-  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
-#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-} RNG_HandleTypeDef;
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL RNG Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
-
-  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
-  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
-
-} HAL_RNG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RNG Callback pointer definition
-  */
-typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
-typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
-
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
+/** 
   * @}
   */
 
 /**
   * @}
-  */
-
+  */ 
+   
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup RNG_Exported_Constants RNG Exported Constants
   * @{
   */
@@ -149,78 +123,57 @@ typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-/**
-  * @}
-  */
 
-/** @defgroup RNG_Error_Definition   RNG Error Definition
-  * @{
-  */
-#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error             */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */
-#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
-#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
-#define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */
 /**
   * @}
   */
 
 /**
   * @}
-  */
-
+  */ 
+  
 /* Exported macros -----------------------------------------------------------*/
+
 /** @defgroup RNG_Exported_Macros RNG Exported Macros
   * @{
   */
 
 /** @brief Reset RNG handle state
-  * @param  __HANDLE__ RNG Handle
+  * @param  __HANDLE__: RNG Handle
   * @retval None
   */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
-                                                       (__HANDLE__)->MspInitCallback = NULL;            \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0U)
-#else
 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
+  * @param  __HANDLE__: RNG Handle
   * @retval None
   */
 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
 
 /**
   * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
+  * @param  __HANDLE__: RNG Handle
   * @retval None
   */
 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
 
 /**
   * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __FLAG__ RNG flag
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
   *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY:  Data ready
-  *            @arg RNG_FLAG_CECS:  Clock error current status
-  *            @arg RNG_FLAG_SECS:  Seed error current status
+  *            @arg RNG_FLAG_DRDY: Data ready                
+  *            @arg RNG_FLAG_CECS: Clock error current status
+  *            @arg RNG_FLAG_SECS: Seed error current status 
   * @retval The new state of __FLAG__ (SET or RESET).
   */
 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
 /**
   * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__ RNG handle
-  * @param  __FLAG__ RNG flag to clear
+  * @param  __HANDLE__: RNG handle
+  * @param  __FLAG__: RNG flag to clear  
   * @note   WARNING: This is a dummy macro for HAL code alignment,
   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
   * @retval None
@@ -229,102 +182,130 @@ typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
 
 /**
   * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
+  * @param  __HANDLE__: RNG Handle
   * @retval None
   */
 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-
+    
 /**
   * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
+  * @param  __HANDLE__: RNG Handle
   * @retval None
   */
 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
 
 /**
   * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
   *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt
+  *            @arg RNG_IT_DRDY: Data ready interrupt              
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
 
 /**
   * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:            
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
   * @retval None
   */
 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
 
 /**
   * @}
-  */
+  */ 
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup RNG_Exported_Functions RNG Exported Functions
   * @{
   */
 
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
-  */
+  */  
 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
 
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
 
 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
 
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNG_Private_Types RNG Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Defines RNG Private Defines
+  * @{
+  */
+
 /**
   * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Variables RNG Private Variables
+  * @{
   */
 
 /**
   * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+  * @{
   */
 
+/**
+  * @}
+  */ 
+
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup RNG_Private_Macros RNG Private Macros
   * @{
@@ -333,28 +314,43 @@ uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
                        ((IT) == RNG_IT_SEI))
 
 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                            ((FLAG) == RNG_FLAG_CECS) || \
-                            ((FLAG) == RNG_FLAG_SECS))
+                           ((FLAG) == RNG_FLAG_CECS) || \
+                           ((FLAG) == RNG_FLAG_SECS))
 
 /**
   * @}
+  */ 
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
+  * @{
   */
 
 /**
   * @}
   */
 
-#endif /* RNG */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private Functions
+  * @{
+  */
 
 /**
   * @}
   */
 
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /* STM32F2xx_HAL_RNG_H */
+#endif /* __STM32F2xx_HAL_RNG_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RTC_H
 #define __STM32F2xx_HAL_RTC_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,52 +52,52 @@ extern "C" {
 
 /** @addtogroup RTC
   * @{
-  */
+  */ 
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup RTC_Exported_Types RTC Exported Types
   * @{
   */
-
-/**
-  * @brief  HAL State structures definition
-  */
+    
+/** 
+  * @brief  HAL State structures definition  
+  */ 
 typedef enum
 {
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
+  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */     
+  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */  
+  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */      
+                                                                        
+}HAL_RTCStateTypeDef;
 
-} HAL_RTCStateTypeDef;
-
-/**
-  * @brief  RTC Configuration Structure definition
+/** 
+  * @brief  RTC Configuration Structure definition  
   */
 typedef struct
 {
   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
+                                 This parameter can be a value of @ref RTC_Hour_Formats */         
 
   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        
+                               
   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
-
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */
-
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-} RTC_InitTypeDef;
-
-/**
-  * @brief  RTC Time structure definition
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */   
+  
+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   
+                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */      
+  
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ 
+  
+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
   */
 typedef struct
 {
@@ -89,117 +107,75 @@ typedef struct
 
   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
+  
   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
+  
   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ 
+  
   uint32_t DayLightSaving;  /*!< Specifies DayLight Save Operation.
                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+  
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
                                  in CR register to store the operation.
                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-} RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
+}RTC_TimeTypeDef; 
+  
+/** 
+  * @brief  RTC Date structure definition  
   */
 typedef struct
 {
   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
+  
   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
 
   uint8_t Date;     /*!< Specifies the RTC Date.
                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
+  
   uint8_t Year;     /*!< Specifies the RTC Date Year.
                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+                        
+}RTC_DateTypeDef;
 
-} RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
+/** 
+  * @brief  RTC Alarm structure definition  
   */
 typedef struct
 {
   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
+    
   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
+  
   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
+  
   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
+                                                                     
   uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-} RTC_AlarmTypeDef;
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            
+}RTC_AlarmTypeDef;
 
-/**
-  * @brief  RTC Handle Structure definition
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-typedef struct __RTC_HandleTypeDef
-#else
+/** 
+  * @brief  RTC Handle Structure definition  
+  */ 
 typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
 {
   RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
-
+   
+  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ 
+  
   HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
+  
   __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm A Event callback         */
-
-  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm B Event callback         */
-
-  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);        /*!< RTC TimeStamp Event callback       */
-
-  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);      /*!< RTC WakeUpTimer Event callback     */
-
-  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 1 Event callback        */
-
-  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);               /*!< RTC Msp Init callback              */
-
-  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);             /*!< RTC Msp DeInit callback            */
-
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-} RTC_HandleTypeDef;
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL RTC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00u,    /*!< RTC Alarm A Event Callback ID       */
-  HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01u,    /*!< RTC Alarm B Event Callback ID       */
-  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02u,    /*!< RTC TimeStamp Event Callback ID     */
-  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03u,    /*!< RTC Wake-Up Timer Event Callback ID */
-  HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04u,    /*!< RTC Tamper 1 Callback ID            */
-  HAL_RTC_MSPINIT_CB_ID                 = 0x0Eu,    /*!< RTC Msp Init callback ID            */
-  HAL_RTC_MSPDEINIT_CB_ID               = 0x0Fu     /*!< RTC Msp DeInit callback ID          */
-} HAL_RTC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RTC Callback pointer definition
-  */
-typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+    
+}RTC_HandleTypeDef;
 
 /**
   * @}
@@ -212,82 +188,82 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 
 /** @defgroup RTC_Hour_Formats RTC Hour Formats
   * @{
-  */
-#define RTC_HOURFORMAT_24              0x00000000U
-#define RTC_HOURFORMAT_12              0x00000040U
+  */ 
+#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
 /**
   * @}
-  */
-
+  */ 
+  
 /** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
   * @{
-  */
-#define RTC_OUTPUT_DISABLE             0x00000000U
-#define RTC_OUTPUT_ALARMA              0x00200000U
-#define RTC_OUTPUT_ALARMB              0x00400000U
-#define RTC_OUTPUT_WAKEUP              0x00600000U
+  */ 
+#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
   * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH       0x00000000U
-#define RTC_OUTPUT_POLARITY_LOW        0x00100000U
+  */ 
+#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
   * @{
-  */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000U
-#define RTC_OUTPUT_TYPE_PUSHPULL       0x00040000U
+  */ 
+#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
   * @{
-  */
+  */ 
 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
   * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H       0x00020000U
-#define RTC_DAYLIGHTSAVING_ADD1H       0x00010000U
-#define RTC_DAYLIGHTSAVING_NONE        0x00000000U
+  */ 
+#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
 /**
   * @}
   */
 
 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
   * @{
-  */
-#define RTC_STOREOPERATION_RESET        0x00000000U
-#define RTC_STOREOPERATION_SET          0x00040000U
+  */ 
+#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
 /**
   * @}
   */
 
 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
   * @{
-  */
-#define RTC_FORMAT_BIN                      0x00000000U
-#define RTC_FORMAT_BCD                      0x00000001U
+  */ 
+#define RTC_FORMAT_BIN                      ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD                      ((uint32_t)0x000000001)
 /**
   * @}
   */
 
 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
   * @{
-  */
+  */ 
 /* Coded in BCD format */
 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
@@ -303,11 +279,11 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
   * @{
-  */
+  */   
 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
@@ -317,205 +293,197 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
   * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000U
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   0x40000000U
+  */ 
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
   * @{
-  */
-#define RTC_ALARMMASK_NONE                0x00000000U
+  */ 
+#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 0x80808080U
+#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
   * @{
-  */
+  */ 
 #define RTC_ALARM_A                       RTC_CR_ALRAE
 #define RTC_ALARM_B                       RTC_CR_ALRBE
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
   * @{
-  */
-#define RTC_IT_TS                         0x00008000U
-#define RTC_IT_WUT                        0x00004000U
-#define RTC_IT_ALRB                       0x00002000U
-#define RTC_IT_ALRA                       0x00001000U
-#define RTC_IT_TAMP                       0x00000004U /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      0x00020000U
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
 /**
   * @}
   */
 
 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
   * @{
-  */
-#define RTC_FLAG_TAMP1F                   0x00002000U
-#define RTC_FLAG_TSOVF                    0x00001000U
-#define RTC_FLAG_TSF                      0x00000800U
-#define RTC_FLAG_WUTF                     0x00000400U
-#define RTC_FLAG_ALRBF                    0x00000200U
-#define RTC_FLAG_ALRAF                    0x00000100U
-#define RTC_FLAG_INITF                    0x00000040U
-#define RTC_FLAG_RSF                      0x00000020U
-#define RTC_FLAG_INITS                    0x00000010U
-#define RTC_FLAG_WUTWF                    0x00000004U
-#define RTC_FLAG_ALRBWF                   0x00000002U
-#define RTC_FLAG_ALRAWF                   0x00000001U
+  */ 
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
 /**
   * @}
   */
 
 /**
   * @}
-  */
-
+  */ 
+  
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup RTC_Exported_Macros RTC Exported Macros
   * @{
   */
 
 /** @brief Reset RTC handle state
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0u)
-#else
 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
 
 /**
   * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
                         do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCAU;  \
-                            (__HANDLE__)->Instance->WPR = 0x53U;  \
-                          } while(0U)
+                            (__HANDLE__)->Instance->WPR = 0xCA;   \
+                            (__HANDLE__)->Instance->WPR = 0x53;   \
+                          } while(0)
 
 /**
   * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
                         do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFFU;  \
-                          } while(0U)
-
+                            (__HANDLE__)->Instance->WPR = 0xFF;   \
+                          } while(0)                            
+ 
 /**
   * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
 
 /**
   * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
 
 /**
   * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
 
 /**
   * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
 
 /**
   * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
+  *             @arg RTC_IT_ALRB: Alarm B interrupt  
   * @retval None
-  */
+  */   
 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
   *         This parameter can be any combination of the following values:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt  
   * @retval None
   */
 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt  
   * @retval None
   */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
 
 /**
   * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag to check.
   *         This parameter can be:
   *            @arg RTC_FLAG_ALRAF
   *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
+  *            @arg RTC_FLAG_ALRAWF     
+  *            @arg RTC_FLAG_ALRBWF    
   * @retval None
   */
 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
   *          This parameter can be:
   *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
+  *             @arg RTC_FLAG_ALRBF 
   * @retval None
   */
 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
+  
+  
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
   *            @arg RTC_IT_ALRB: Alarm B interrupt
@@ -548,44 +516,40 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();\
-                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
-                                                            }while(0U)
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
 
 /**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
   * @retval None.
   */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
-                                                               __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
-                                                             }while(0U)
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
 
 /**
   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
@@ -624,12 +588,6 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
 void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
 void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -665,7 +623,7 @@ void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
 /**
   * @}
   */
@@ -690,16 +648,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Masks Definition */
-#define RTC_TR_RESERVED_MASK    0x007F7F7FU
-#define RTC_DR_RESERVED_MASK    0x00FFFF3FU
-#define RTC_INIT_MASK           0xFFFFFFFFU
-#define RTC_RSF_MASK            0xFFFFFF5FU
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
 #define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
                                             RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
                                             RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
 
-#define RTC_TIMEOUT_VALUE       1000U
+#define RTC_TIMEOUT_VALUE       1000
 
 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
 /**
@@ -724,12 +682,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x1FFFU)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x1FFF)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
 
 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
@@ -738,9 +696,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                            ((OPERATION) == RTC_STOREOPERATION_SET))
 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -748,7 +706,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -758,7 +716,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
 /**
   * @}
@@ -772,7 +730,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 /** @defgroup RTC_Private_Functions RTC Private Functions
   * @{
   */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
 uint8_t            RTC_ByteToBcd2(uint8_t Value);
 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 /**
@@ -781,12 +739,12 @@ uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-
+  */ 
+  
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc_ex.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RTC_EX_H
 #define __STM32F2xx_HAL_RTC_EX_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -35,73 +53,73 @@ extern "C" {
 /** @addtogroup RTCEx
   * @{
   */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTC Exported Types
+ 
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
   * @{
   */
 
-/** @brief  RTC Tamper structure definition
+/** @brief  RTC Tamper structure definition  
   */
-typedef struct
+typedef struct 
 {
   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-
+  
   uint32_t PinSelection;                /*!< Specifies the Tamper Pin.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Selection */
-
+                                             
   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-} RTC_TamperTypeDef;
+}RTC_TamperTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTC Exported Constants
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
   * @{
-  */
+  */ 
 
 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
   * @{
   */
-#define RTC_BKP_DR0                       0x00000000U
-#define RTC_BKP_DR1                       0x00000001U
-#define RTC_BKP_DR2                       0x00000002U
-#define RTC_BKP_DR3                       0x00000003U
-#define RTC_BKP_DR4                       0x00000004U
-#define RTC_BKP_DR5                       0x00000005U
-#define RTC_BKP_DR6                       0x00000006U
-#define RTC_BKP_DR7                       0x00000007U
-#define RTC_BKP_DR8                       0x00000008U
-#define RTC_BKP_DR9                       0x00000009U
-#define RTC_BKP_DR10                      0x0000000AU
-#define RTC_BKP_DR11                      0x0000000BU
-#define RTC_BKP_DR12                      0x0000000CU
-#define RTC_BKP_DR13                      0x0000000DU
-#define RTC_BKP_DR14                      0x0000000EU
-#define RTC_BKP_DR15                      0x0000000FU
-#define RTC_BKP_DR16                      0x00000010U
-#define RTC_BKP_DR17                      0x00000011U
-#define RTC_BKP_DR18                      0x00000012U
-#define RTC_BKP_DR19                      0x00000013U
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
   * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING          0x00000000U
-#define RTC_TIMESTAMPEDGE_FALLING         0x00000008U
+  */ 
+#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
 /**
   * @}
   */
-
+  
 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
   * @{
-  */
+  */ 
 #define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
 /**
   * @}
@@ -109,62 +127,62 @@ typedef struct
 
 /** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
   * @{
-  */
-#define RTC_TAMPERPIN_DEFAULT               0x00000000U
-#define RTC_TAMPERPIN_POS1                  0x00010000U
+  */ 
+#define RTC_TAMPERPIN_DEFAULT               ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_POS1                  ((uint32_t)0x00010000)
 
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
   * @{
-  */
-#define RTC_TIMESTAMPPIN_DEFAULT            0x00000000U
-#define RTC_TIMESTAMPPIN_POS1               0x00020000U
+  */ 
+#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00020000)
 
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
   * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE       0x00000000U
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      0x00000002U
+  */ 
+#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
 
 /**
   * @}
-  */
+  */  
 
 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
   * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         0x00000001U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         0x00000002U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         0x00000003U
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      0x00000004U
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      0x00000006U
+  */ 
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
   * @{
-  */
-#define RTC_CALIBSIGN_POSITIVE            0x00000000U
-#define RTC_CALIBSIGN_NEGATIVE            0x00000080U
+  */ 
+#define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000) 
+#define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080)
 /**
   * @}
   */
 
 /**
   * @}
-  */
-
+  */ 
+  
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTC Exported Macros
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
   * @{
   */
 
@@ -175,22 +193,22 @@ typedef struct
 
 /**
   * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
 
 /**
   * @brief  Disable the RTC Wake-up Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
 
 /**
   * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
   * @retval None
@@ -199,8 +217,8 @@ typedef struct
 
 /**
   * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
   * @retval None
@@ -209,18 +227,18 @@ typedef struct
 
 /**
   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
   * @retval None
   */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
   * @retval None
@@ -229,24 +247,24 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to check.
   *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF
-  *             @arg RTC_FLAG_WUTWF
+  *             @arg RTC_FLAG_WUTF   
+  *             @arg RTC_FLAG_WUTWF     
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
   *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF
+  *            @arg RTC_FLAG_WUTF   
   * @retval None
   */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))  
 
 /**
   * @brief  Enable interrupt on the RTC Wake-up Timer associated Exti line.
@@ -273,7 +291,7 @@ typedef struct
 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+  * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line. 
   * @retval None.
   */
 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -300,18 +318,14 @@ typedef struct
   * @brief  Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
-                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
-                                                                  }while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
 
 /**
   * @brief  Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
-                                                                     __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
-                                                                   }while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
 
 /**
   * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
@@ -342,22 +356,22 @@ typedef struct
 
 /**
   * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
 
 /**
   * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
 
 /**
   * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -366,8 +380,8 @@ typedef struct
 
 /**
   * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -376,18 +390,18 @@ typedef struct
 
 /**
   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
   */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -396,21 +410,21 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC TimeStamp flag to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC TimeStamp flag to check.
   *         This parameter can be:
-  *            @arg RTC_FLAG_TSF
-  *            @arg RTC_FLAG_TSOVF
+  *            @arg RTC_FLAG_TSF   
+  *            @arg RTC_FLAG_TSOVF     
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
   *          This parameter can be:
-  *             @arg RTC_FLAG_TSF
+  *             @arg RTC_FLAG_TSF  
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -426,32 +440,32 @@ typedef struct
 
 /**
   * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
   *         This parameter can be:
   *            @arg  RTC_IT_TAMP1
   * @retval None
   */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TAMP: Tamper interrupt
   * @retval None
@@ -460,18 +474,18 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
   *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F
+  *             @arg RTC_FLAG_TAMP1F 
   * @retval None
   */
 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F
   * @retval None
@@ -511,7 +525,7 @@ typedef struct
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
   * @retval None.
   */
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -538,18 +552,14 @@ typedef struct
   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
-                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\
-                                                                       }while(0U)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
 
 /**
   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
-                                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
-                                                                        }while(0U)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
 
 /**
   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
@@ -579,42 +589,42 @@ typedef struct
 
 /**
   * @brief  Enable the Coarse calibration process.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
 
 /**
   * @brief  Disable the Coarse calibration process.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
 
 /**
   * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
 
 /**
   * @brief  Disable the calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
 
 /**
   * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
 
 /**
   * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __HANDLE__: specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
@@ -628,7 +638,7 @@ typedef struct
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTC Exported Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
   * @{
   */
 
@@ -641,8 +651,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
 
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
 
@@ -678,7 +688,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
 
 HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
@@ -690,7 +700,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
 /**
   * @}
@@ -700,26 +710,26 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/ 
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTC Private Constants
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
   * @{
   */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */  
 /**
   * @}
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTC Private Macros
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
   * @{
   */
 
 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
   * @{
-  */
+  */ 
 #define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0)  || \
                                            ((BKP) == RTC_BKP_DR1)  || \
                                            ((BKP) == RTC_BKP_DR2)  || \
@@ -759,12 +769,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
 
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFFU)
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
 #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
                                  ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
 
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~(RTC_TAFCR_TAMP1E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E))) == 0x00) && ((TAMPER) != (uint32_t)RESET)) 
 /**
   * @}
   */
@@ -775,11 +785,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 #ifdef __cplusplus
 }

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h

@@ -2,31 +2,47 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sd.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SD_H
-#define STM32F2xx_HAL_SD_H
+#ifndef __STM32F2xx_HAL_SD_H
+#define __STM32F2xx_HAL_SD_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-#if defined(SDIO)
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_sdmmc.h"
 
@@ -37,135 +53,55 @@
 /** @defgroup SD SD
   * @brief SD HAL module driver
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/ 
 /** @defgroup SD_Exported_Types SD Exported Types
   * @{
   */
 
-/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
-  * @{
-  */   
-typedef enum
-{
-  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
-  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
-  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
-  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
-  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
-  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
-  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */
-  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
-}HAL_SD_StateTypeDef;
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
-  * @{
-  */   
-typedef uint32_t HAL_SD_CardStateTypeDef;
-
-#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
-#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
-#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
-#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
-#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
-#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
-#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
-#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
-#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
-/** 
-  * @}
-  */
-
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   
   * @{
   */
 #define SD_InitTypeDef      SDIO_InitTypeDef 
 #define SD_TypeDef          SDIO_TypeDef
 
-/** 
-  * @brief  SD Card Information Structure definition
-  */ 
 typedef struct
 {
-  uint32_t CardType;                     /*!< Specifies the card Type                         */
+  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
   
-  uint32_t CardVersion;                  /*!< Specifies the card version                      */
-
-  uint32_t Class;                        /*!< Specifies the class of the card class           */
-
-  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
   
-  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
-
-  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
   
-  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
-
-  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
-
-}HAL_SD_CardInfoTypeDef;
-
-/** 
-  * @brief  SD handle Structure definition
-  */ 
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-typedef struct __SD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-{
-  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+  uint32_t                     CardType;         /*!< SD card type                                   */
   
-  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+  uint32_t                     RCA;              /*!< SD relative card address                       */
   
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
   
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
-
-  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
-
-  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
-
-  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+  uint32_t                     CID[4];           /*!< SD card identification number table            */
   
-  __IO uint32_t                Context;          /*!< SD transfer context                 */
- 
-  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
   
-  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
- 
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
-
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
+  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
+  
+  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
   
-  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
   
-  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
   
-  uint32_t                     CID[4];           /*!< SD card identification number table */
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
   
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
-  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
-  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
-  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
-
-  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
-  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 }SD_HandleTypeDef;
-
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register 
   * @{
-  */
+  */ 
 typedef struct
 {
   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
@@ -197,7 +133,7 @@ typedef struct
   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
   __IO uint8_t  Reserved3;            /*!< Reserved                              */
   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
@@ -205,14 +141,15 @@ typedef struct
   __IO uint8_t  ECC;                  /*!< ECC code                              */
   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
   __IO uint8_t  Reserved4;            /*!< Always 1                              */
-}HAL_SD_CardCSDTypeDef;
+
+}HAL_SD_CSDTypedef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
   * @{
-  */
+  */ 
 typedef struct
 {
   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
@@ -226,202 +163,304 @@ typedef struct
   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
   __IO uint8_t  Reserved2;       /*!< Always 1              */
 
-}HAL_SD_CardCIDTypeDef;
+}HAL_SD_CIDTypedef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 
   * @{
-  */
+  */ 
 typedef struct
 {
-  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t CardType;               /*!< Carries information about card type                        */
-  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypeDef;
+  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypedef;
 /** 
   * @}
   */
 
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition 
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure 
   * @{
-  */
-typedef enum
+  */ 
+typedef struct
 {
-  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
-  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
-  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
-  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
-
-  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
-  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
-}HAL_SD_CallbackIDTypeDef;
+  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
+  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
+  uint64_t            CardCapacity;   /*!< Card capacity                          */
+  uint32_t            CardBlockSize;  /*!< Card block size                        */
+  uint16_t            RCA;            /*!< SD relative card address               */
+  uint8_t             CardType;       /*!< SD card type                           */
+
+}HAL_SD_CardInfoTypedef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition 
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition 
   * @{
-  */
-typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
+  */ 
+typedef enum
+{
 /** 
-  * @}
-  */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  * @brief  SD specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
+  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
+  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
+  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
+  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
+  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
+  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
+  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
+  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
+  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
+  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
+  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
+  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
+  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
+  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
+  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
+  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
+  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
+  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
+  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
+  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR                  = (34),
+  SD_NOT_CONFIGURED                  = (35),
+  SD_REQUEST_PENDING                 = (36),
+  SD_REQUEST_NOT_APPLICABLE          = (37),
+  SD_INVALID_PARAMETER               = (38),
+  SD_UNSUPPORTED_FEATURE             = (39),
+  SD_UNSUPPORTED_HW                  = (40),
+  SD_ERROR                           = (41),
+  SD_OK                              = (0) 
+
+}HAL_SD_ErrorTypedef;
 /** 
   * @}
   */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
   * @{
-  */
+  */ 
+typedef enum
+{
+  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
+  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
+  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
 
-#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+}HAL_SD_TransferStateTypedef;
+/** 
+  * @}
+  */
 
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
   * @{
   */  
-#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
-#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
-#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
-#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
-#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
-#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
-#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
-#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
-                                                                                       number of transferred bytes does not match the block length   */
-#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
-#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
-#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
-                                                                                       command or if there was an attempt to access a locked card    */
-#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
-#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
-#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
-#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
-#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
-#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
-#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
-#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
-#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
-#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
-#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
-                                                                                       of erase sequence command was received                        */
-#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
-#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
-#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
-#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
-#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
-#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
-                                                
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
+
+}HAL_SD_CardStateTypedef;
 /** 
   * @}
   */
- 
-/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
   * @{
-  */ 
-#define SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
-#define SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
-#define SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
-#define SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
+  */  
+typedef enum
+{
+  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
+  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
+  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
+  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
 
+}HAL_SD_OperationTypedef;
 /**
   * @}
   */
 
-/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
-  * @{
-  */
-#define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
-#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
-#define CARD_SECURED               ((uint32_t)0x00000003U)
-    
 /**
   * @}
   */
 
-/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants SD Exported Constants
   * @{
   */
-#define CARD_V1_X                  ((uint32_t)0x00000000U)
-#define CARD_V2_X                  ((uint32_t)0x00000001U)
-/**
-  * @}
+
+/** 
+  * @brief SD Commands Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
+                                                                       operating condition register (OCR) content in the response on the CMD line.              */
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
+                                                                       and asks the card whether card supports voltage.                                         */
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
+                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                       for SDHS and SDXC.                                                                       */
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
+                                                                       STOP_TRANSMISSION command.                                                               */
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
+                                                                       system set by switch function command (CMD6).                                            */
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
+                                                                       Reserved for each command system set by switch function command (CMD6).                  */
+#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
+#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
+                                                                       the SET_BLOCK_LEN command.                                                               */
+#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
+                                                                       than a standard command.                                                                 */
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
+                                                                       for general purpose/application specific commands.                                       */
+#define SD_CMD_NO_CMD                              ((uint8_t)64) 
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
+                                                                       widths are given in SCR register.                                                          */
+#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
+                                                                       32bit+CRC data block.                                                                      */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
+                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SD_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
+
+/** 
+  * @brief Supported SD Memory Cards 
   */
-      
+#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
 /**
   * @}
   */
   
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup SD_Exported_macros SD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset SD handle state.
-  * @param  __HANDLE__ : SD handle.
-  * @retval None
+  * @brief macros to handle interrupts and specific clock configurations
+  * @{
   */
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
-                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
  
 /**
   * @brief  Enable the SD device.
   * @retval None
   */ 
-#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
 
 /**
   * @brief  Disable the SD device.
   * @retval None
   */
-#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
 
 /**
-  * @brief  Enable the SDMMC DMA transfer.
+  * @brief  Enable the SDIO DMA transfer.
   * @retval None
   */ 
-#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
 
 /**
-  * @brief  Disable the SDMMC DMA transfer.
+  * @brief  Disable the SDIO DMA transfer.
   * @retval None
   */
-#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+#define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
  
 /**
   * @brief  Enable the SD device interrupt.
   * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
   *         This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -431,7 +470,9 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -444,15 +485,16 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
   * @retval None
   */
-#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 
 /**
   * @brief  Disable the SD device interrupt.
   * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -462,7 +504,9 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -475,10 +519,11 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
   * @retval None
   */
-#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 
 /**
   * @brief  Check whether the specified SD flag is set or not. 
@@ -493,7 +538,8 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
@@ -506,10 +552,11 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
   * @retval The new state of SD FLAG (SET or RESET).
   */
-#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
 
 /**
   * @brief  Clear the SD's pending flags.
@@ -524,17 +571,19 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
   * @retval None
   */
-#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
 
 /**
   * @brief  Check whether the specified SD interrupt has occurred or not.
   * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
   *          This parameter can be one of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -544,7 +593,9 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -557,14 +608,15 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
   * @retval The new state of SD IT (SET or RESET).
   */
-#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
 
 /**
   * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
+  * @param  __HANDLE__ : SD Handle
   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
   *          This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -575,12 +627,14 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
-  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
   * @retval None
   */
-#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 /**
   * @}
   */
@@ -589,87 +643,68 @@ typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
 /** @defgroup SD_Exported_Functions SD Exported Functions
   * @{
   */
-  
+
 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
-  
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+
+/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
   * @{
   */
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
 
+/* Non-Blocking mode: Interrupt */
 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
 
 /* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/* SD callback registering/unregistering */
-HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
 
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
 /**
   * @}
   */
 
-/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
-HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
 /**
   * @}
   */
-
-/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  
+/* Peripheral State functions  ************************************************/
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
-
-/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
-  * @{
-  */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+  
 /**
   * @}
   */
@@ -737,26 +772,18 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
   * @}
   */
 
-
 /**
   * @}
   */ 
 
 /**
   * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* SDIO */
+  */ 
 
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /* STM32F2xx_HAL_SD_H */ 
+#endif /* __STM32F2xx_HAL_SD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h

@@ -2,17 +2,35 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_smartcard.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -36,20 +54,20 @@
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
   * @{
   */
 
-/**
+/** 
   * @brief SMARTCARD Init Structure definition
   */
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
                                            The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+                                           - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
 
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
                                            This parameter can be a value of @ref SMARTCARD_Word_Length */
@@ -57,7 +75,7 @@ typedef struct
   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits */
 
-  uint32_t Parity;                    /*!< Specifies the parity mode.
+  uint32_t Parity;                   /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref SMARTCARD_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
@@ -77,157 +95,65 @@ typedef struct
                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
 
-  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
-                                           to provide the smartcard clock. The value given in the register (5 significant bits)
-                                           is multiplied by 2 to give the division factor of the source clock frequency.
+  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock 
+                                           to provide the smartcard clock
                                            This parameter can be a value of @ref SMARTCARD_Prescaler */
-
-  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
+  
+  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
+                                           The value given in the register (5 significant bits) is multiplied by 2 
+                                           to give the division factor of the source clock frequency */
 
   uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state.
                                            This parameter can be a value of @ref SMARTCARD_NACK_State */
 }SMARTCARD_InitTypeDef;
 
-/**
-  * @brief HAL SMARTCARD State structures definition
-  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains SMARTCARD state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     IP initilisation status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP not initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
+/** 
+  * @brief HAL State structures definition
   */
 typedef enum
 {
-  HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                        Value is allowed for gState and RxState */
-  HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                        Value is allowed for gState and RxState */
-  HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                        Value is allowed for RxState only */
-  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                        Not to be used for neither gState nor RxState.
-                                                        Value is result of combination (Or) between gState and RxState values */
-  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                        Value is allowed for gState only */
-  HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error
-                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
+  HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */ 
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error                                              */
 }HAL_SMARTCARD_StateTypeDef;
 
-/**
+/** 
   * @brief  SMARTCARD handle Structure definition
   */
-typedef struct __SMARTCARD_HandleTypeDef
+typedef struct
 {
-  USART_TypeDef                    *Instance;        /*!< USART registers base address */
-
-  SMARTCARD_InitTypeDef            Init;             /*!< SmartCard communication parameters */
-
-  uint8_t                          *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer */
-
-  uint16_t                         TxXferSize;       /*!< SmartCard Tx Transfer size */
-
-  __IO uint16_t                    TxXferCount;      /*!< SmartCard Tx Transfer Counter */
+  USART_TypeDef                    *Instance;        /* USART registers base address */
 
-  uint8_t                          *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer */
+  SMARTCARD_InitTypeDef            Init;             /* SmartCard communication parameters */
 
-  uint16_t                         RxXferSize;       /*!< SmartCard Rx Transfer size */
+  uint8_t                          *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer */
 
-  __IO uint16_t                    RxXferCount;      /*!< SmartCard Rx Transfer Counter */
+  uint16_t                         TxXferSize;       /* SmartCard Tx Transfer size */
 
-  DMA_HandleTypeDef                *hdmatx;          /*!< SmartCard Tx DMA Handle parameters */
+  uint16_t                         TxXferCount;      /* SmartCard Tx Transfer Counter */
 
-  DMA_HandleTypeDef                *hdmarx;          /*!< SmartCard Rx DMA Handle parameters */
+  uint8_t                          *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer */
 
-  HAL_LockTypeDef                  Lock;             /*!< Locking object */
+  uint16_t                         RxXferSize;       /* SmartCard Rx Transfer size */
 
-  __IO HAL_SMARTCARD_StateTypeDef  gState;           /*!< SmartCard state information related to global Handle management
-                                                        and also related to Tx operations.
-                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+  uint16_t                         RxXferCount;      /* SmartCard Rx Transfer Counter */
 
-  __IO HAL_SMARTCARD_StateTypeDef  RxState;          /*!< SmartCard state information related to Rx operations.
-                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+  DMA_HandleTypeDef                *hdmatx;          /* SmartCard Tx DMA Handle parameters */
 
-  __IO uint32_t                    ErrorCode;        /*!< SmartCard Error code */
+  DMA_HandleTypeDef                *hdmarx;          /* SmartCard Rx DMA Handle parameters */
 
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Tx Complete Callback             */
+  HAL_LockTypeDef                  Lock;             /* Locking object */
 
-  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Rx Complete Callback             */
+  __IO HAL_SMARTCARD_StateTypeDef  State;            /* SmartCard communication state */
 
-  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc);             /*!< SMARTCARD Error Callback                   */
+  __IO uint32_t  ErrorCode;                          /* SmartCard Error code */
 
-  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);  /*!< SMARTCARD Abort Receive Complete Callback  */
-
-  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);           /*!< SMARTCARD Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Msp DeInit callback              */
-#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-} SMARTCARD_HandleTypeDef;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMARTCARD Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
-  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
-  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
-  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
-  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
-  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
-
-  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
-  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
-
-} HAL_SMARTCARD_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMARTCARD Callback pointer definition
-  */
-typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!< pointer to an SMARTCARD callback function */
-
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+}SMARTCARD_HandleTypeDef;
 
 /**
   * @}
@@ -237,19 +163,16 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
   * @{
   */
-
 /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
+  * @brief    SMARTCARD Error Code 
   * @{
-  */
-#define HAL_SMARTCARD_ERROR_NONE             0x00000000U   /*!< No error            */
-#define HAL_SMARTCARD_ERROR_PE               0x00000001U   /*!< Parity error        */
-#define HAL_SMARTCARD_ERROR_NE               0x00000002U   /*!< Noise error         */
-#define HAL_SMARTCARD_ERROR_FE               0x00000004U   /*!< Frame error         */
-#define HAL_SMARTCARD_ERROR_ORE              0x00000008U   /*!< Overrun error       */
-#define HAL_SMARTCARD_ERROR_DMA              0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+  */ 
+#define HAL_SMARTCARD_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
+#define HAL_SMARTCARD_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
+#define HAL_SMARTCARD_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
+#define HAL_SMARTCARD_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
+#define HAL_SMARTCARD_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
+#define HAL_SMARTCARD_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
 /**
   * @}
   */
@@ -257,7 +180,7 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
   * @{
   */
-#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M)
+#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
@@ -265,8 +188,8 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
   * @{
   */
-#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
 /**
   * @}
   */
@@ -274,8 +197,8 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
   * @{
   */
-#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
   * @}
   */
@@ -283,9 +206,9 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Mode SMARTCARD Mode
   * @{
   */
-#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
@@ -293,17 +216,17 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
   * @{
   */
-#define SMARTCARD_POLARITY_LOW              0x00000000U
-#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)
+#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
   * @{
   */
-#define SMARTCARD_PHASE_1EDGE               0x00000000U
-#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)
+#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
   */
@@ -311,8 +234,8 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
   * @{
   */
-#define SMARTCARD_LASTBIT_DISABLE           0x00000000U
-#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)
+#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
   */
@@ -320,8 +243,8 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
   * @{
   */
-#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE              0x00000000U
+#define SMARTCARD_NACK_ENABLE                  ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE                 ((uint32_t)0x00000000)
 /**
   * @}
   */
@@ -329,8 +252,8 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests
   * @{
   */
-#define SMARTCARD_DMAREQ_TX                 ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX                 ((uint32_t)USART_CR3_DMAR)
+#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
 /**
   * @}
   */
@@ -338,72 +261,72 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
   * @{
   */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2     0x00000001U          /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4     0x00000002U          /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6     0x00000003U          /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8     0x00000004U          /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10    0x00000005U          /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12    0x00000006U          /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14    0x00000007U          /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16    0x00000008U          /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18    0x00000009U          /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20    0x0000000AU          /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22    0x0000000BU          /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24    0x0000000CU          /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26    0x0000000DU          /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28    0x0000000EU          /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30    0x0000000FU          /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32    0x00000010U          /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34    0x00000011U          /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36    0x00000012U          /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38    0x00000013U          /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40    0x00000014U          /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42    0x00000015U          /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44    0x00000016U          /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46    0x00000017U          /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48    0x00000018U          /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50    0x00000019U          /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52    0x0000001AU          /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54    0x0000001BU          /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56    0x0000001CU          /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58    0x0000001DU          /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60    0x0000001EU          /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62    0x0000001FU          /*!< SYSCLK divided by 62 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2         ((uint32_t)0x00000001)          /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4         ((uint32_t)0x00000002)          /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6         ((uint32_t)0x00000003)          /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8         ((uint32_t)0x00000004)          /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10        ((uint32_t)0x00000005)          /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12        ((uint32_t)0x00000006)          /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14        ((uint32_t)0x00000007)          /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16        ((uint32_t)0x00000008)          /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18        ((uint32_t)0x00000009)          /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20        ((uint32_t)0x0000000A)          /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22        ((uint32_t)0x0000000B)          /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24        ((uint32_t)0x0000000C)          /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26        ((uint32_t)0x0000000D)          /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28        ((uint32_t)0x0000000E)          /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30        ((uint32_t)0x0000000F)          /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32        ((uint32_t)0x00000010)          /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34        ((uint32_t)0x00000011)          /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36        ((uint32_t)0x00000012)          /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38        ((uint32_t)0x00000013)          /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40        ((uint32_t)0x00000014)          /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42        ((uint32_t)0x00000015)          /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44        ((uint32_t)0x00000016)          /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46        ((uint32_t)0x00000017)          /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48        ((uint32_t)0x00000018)          /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50        ((uint32_t)0x00000019)          /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52        ((uint32_t)0x0000001A)          /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54        ((uint32_t)0x0000001B)          /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56        ((uint32_t)0x0000001C)          /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58        ((uint32_t)0x0000001D)          /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60        ((uint32_t)0x0000001E)          /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62        ((uint32_t)0x0000001F)          /*!< SYSCLK divided by 62 */
 /**
   * @}
   */
 
-/** @defgroup SmartCard_Flags SMARTCARD Flags
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
   *        Elements values convention: 0xXXXX
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define SMARTCARD_FLAG_TXE                  ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC                   ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE                 ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE                 ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE                  ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE                   ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE                   ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE                   ((uint32_t)USART_SR_PE)
+#define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001)
 /**
   * @}
   */
 
-/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
   *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the Y register
+  *           - XXXX  : Interrupt mask in the XX register
   *           - Y  : Interrupt source register (2bits)
   *                 - 01: CR1 register
-  *                 - 11: CR3 register
+  *                 - 10: CR3 register
   * @{
   */
-#define SMARTCARD_IT_PE                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE                    ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR                    ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define SMARTCARD_IT_PE                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE                        ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR                        ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
 /**
   * @}
   */
@@ -411,42 +334,26 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /**
   * @}
   */
-
+  
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
   * @{
   */
 
-/** @brief Reset SMARTCARD handle gstate & RxState
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+/** @brief Reset SMARTCARD handle state
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
   * @retval None
   */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                           (__HANDLE__)->MspInitCallback = NULL;                  \
-                                                           (__HANDLE__)->MspDeInitCallback = NULL;                \
-                                                          } while(0U)
-#else
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                          } while(0U)
-#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the Smartcard DR register
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @retval None
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief  Flushes the Smartcard DR register 
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
   */
 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+    
+/** @brief  Checks whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
@@ -460,86 +367,73 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
   */
 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clear the specified Smartcard pending flags.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+/** @brief  Clears the specified Smartcard pending flags.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
-  *          error) flags are cleared by software sequence: a read operation to
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun 
+  *          error) flags are cleared by software sequence: a read operation to 
   *          USART_SR register followed by a read operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)  \
-    do{                                           \
-      __IO uint32_t tmpreg = 0x00U;               \
-      tmpreg = (__HANDLE__)->Instance->SR;        \
-      tmpreg = (__HANDLE__)->Instance->DR;        \
-      UNUSED(tmpreg);                             \
-    } while(0U)
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)     \
+  do{                                                \
+    __IO uint32_t tmpreg;                            \
+    tmpreg = (__HANDLE__)->Instance->SR;             \
+    tmpreg = (__HANDLE__)->Instance->DR;             \
+    UNUSED(tmpreg);                                  \
+  } while(0)
 
 /** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                                 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
 
-/** @brief  Disable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+/** @brief  Enables or disables the specified SmartCard interrupts.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
@@ -547,14 +441,15 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
   */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+                                                                 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                  ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
 
 /** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __IT__ specifies the SMARTCARD interrupt source to check.
+  * @param  __HANDLE__: specifies the SmartCard Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
   *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
@@ -564,52 +459,42 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
   *            @arg SMARTCARD_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
 
 /** @brief  Macro to enable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
   * @retval None
-  */
+  */     
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
   * @retval None
-  */
+  */      
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 
-/** @brief  Macros to enable the SmartCard DMA request.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __REQUEST__ specifies the SmartCard DMA request.
+/** @brief  Macros to enable or disable the SmartCard DMA request.
+  * @param  __HANDLE__: specifies the SmartCard Handle.
+  * @param  __REQUEST__: specifies the SmartCard DMA request.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
   */
 #define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
-
-/** @brief  Macros to disable the SmartCard DMA request.
-  * @param  __HANDLE__ specifies the SmartCard Handle.
-  * @param  __REQUEST__ specifies the SmartCard DMA request.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  * @retval None
-  */
 #define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
 
 /**
@@ -620,7 +505,7 @@ typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!<
 /** @addtogroup SMARTCARD_Exported_Functions
   * @{
   */
-
+  
 /** @addtogroup SMARTCARD_Exported_Functions_Group1
   * @{
   */
@@ -630,11 +515,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -649,21 +529,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
-
 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 /**
   * @}
   */
@@ -674,9 +543,10 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 /* Peripheral State functions  **************************************************/
 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
@@ -689,13 +559,17 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
   */
 
 /** @brief SMARTCARD interruptions flag mask
-  *
-  */
-#define SMARTCARD_IT_MASK                   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                                        USART_CR1_IDLEIE | USART_CR3_EIE )
-
-#define SMARTCARD_CR1_REG_INDEX             1U
-#define SMARTCARD_CR3_REG_INDEX             3U
+  * 
+  */ 
+#define SMARTCARD_IT_MASK   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+                                        USART_CR1_IDLEIE | USART_CR3_EIE )
+#define SMARTCARD_DIV(_PCLK_, _BAUD_)              (((_PCLK_)*25)/(4*(_BAUD_)))
+#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_)          (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100)
+#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_)          (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define SMARTCARD_BRR(_PCLK_, _BAUD_)              ((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define SMARTCARD_CR1_REG_INDEX                 1
+#define SMARTCARD_CR3_REG_INDEX                 3
 /**
   * @}
   */
@@ -704,29 +578,19 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
 /** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
   * @{
   */
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH)    ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS)     (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
-                                             ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY)         (((PARITY) == SMARTCARD_PARITY_EVEN) || \
-                                             ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
-#define IS_SMARTCARD_POLARITY(CPOL)         (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA)            (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT)       (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
-                                             ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK)       (((NACK) == SMARTCARD_NACK_ENABLE) || \
-                                             ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE)     ((BAUDRATE) < 10500001U)
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25U)/(4U*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__)            (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__)            (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
-/* SMARTCARD BRR = mantissa + overflow + fraction
-            = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
-#define SMARTCARD_BRR(__PCLK__, __BAUD__)       (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
-                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
-                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
-
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+                                     ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+                                       ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
 /**
   * @}
   */
@@ -742,12 +606,11 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h

@@ -2,31 +2,49 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_spi.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SPI_H
-#define STM32F2xx_HAL_SPI_H
+#ifndef __STM32F2xx_HAL_SPI_H
+#define __STM32F2xx_HAL_SPI_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
+#include "stm32f2xx_hal_def.h"  
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -40,140 +58,102 @@ extern "C" {
 /** @defgroup SPI_Exported_Types SPI Exported Types
   * @{
   */
-
-/**
-  * @brief  SPI Configuration Structure definition
+  
+/** 
+  * @brief  SPI Configuration Structure definition  
   */
 typedef struct
 {
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
+  uint32_t Mode;               /*!< Specifies the SPI operating mode.
+                                    This parameter can be a value of @ref SPI_mode */
+
+  uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
+                                    This parameter can be a value of @ref SPI_Direction_mode */
 
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
+  uint32_t DataSize;           /*!< Specifies the SPI data size.
+                                    This parameter can be a value of @ref SPI_data_size */
 
-  uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
+  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
+                                    This parameter can be a value of @ref SPI_Clock_Polarity */
 
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
+  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
+                                    This parameter can be a value of @ref SPI_Clock_Phase */
 
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
+  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
+                                    hardware (NSS pin) or by software using the SSI bit.
+                                    This parameter can be a value of @ref SPI_Slave_Select_management */
 
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
+  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
+                                    used to configure the transmit and receive SCK clock.
+                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                    @note The communication clock is derived from the master
+                                    clock. The slave clock does not need to be set */
 
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
+  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
 
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
+                                    This parameter can be a value of @ref SPI_TI_mode */
 
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
-                                     This parameter can be a value of @ref SPI_TI_mode */
+  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
+                                    This parameter can be a value of @ref SPI_CRC_Calculation */
 
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
+  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
+                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
 
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-} SPI_InitTypeDef;
+}SPI_InitTypeDef;
 
 /**
   * @brief  HAL SPI State structure definition
   */
 typedef enum
 {
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
-  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
-} HAL_SPI_StateTypeDef;
-
-/**
+  HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
+  HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
+  HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
+  HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
+    
+}HAL_SPI_StateTypeDef;
+
+/** 
   * @brief  SPI handle Structure definition
   */
 typedef struct __SPI_HandleTypeDef
 {
-  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
-
-  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
-
-  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
-
-  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
+  SPI_TypeDef                *Instance;    /* SPI registers base address */
 
-  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
+  SPI_InitTypeDef            Init;         /* SPI communication parameters */
 
-  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
+  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
 
-  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
+  uint16_t                   TxXferSize;   /* SPI Tx transfer size */
+  
+  uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
 
-  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
+  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
 
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
+  uint16_t                   RxXferSize;   /* SPI Rx transfer size */
 
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
+  uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
 
-  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
+  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
 
-  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
+  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
 
-  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
+  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
 
-  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
+  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
 
-  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
+  HAL_LockTypeDef            Lock;         /* SPI locking object */
 
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
-  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
-  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
-  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
-  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
-  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
-  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
-  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
+  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
 
-#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
+  __IO uint32_t              ErrorCode;    /* SPI Error code */
 
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL SPI Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
-  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
-  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
-  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
-  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
-  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
-  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
-  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SPI Callback pointer definition
-  */
-typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}SPI_HandleTypeDef;
 /**
   * @}
   */
@@ -184,55 +164,52 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   */
 
 /** @defgroup SPI_Error_Code SPI Error Code
+  * @brief    SPI Error Code 
   * @{
-  */
-#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
-#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
-#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
-#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
-#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
-#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY Flag             */
-#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  */ 
+#define HAL_SPI_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error             */
+#define HAL_SPI_ERROR_MODF         ((uint32_t)0x00000001)   /*!< MODF error           */
+#define HAL_SPI_ERROR_CRC          ((uint32_t)0x00000002)   /*!< CRC error            */
+#define HAL_SPI_ERROR_OVR          ((uint32_t)0x00000004)   /*!< OVR error            */
+#define HAL_SPI_ERROR_FRE          ((uint32_t)0x00000008)   /*!< FRE error            */
+#define HAL_SPI_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error   */
+#define HAL_SPI_ERROR_FLAG         ((uint32_t)0x00000020)   /*!< Flag: RXNE,TXE, BSY  */
 /**
   * @}
   */
 
-/** @defgroup SPI_Mode SPI Mode
+/** @defgroup SPI_mode SPI Mode
   * @{
   */
-#define SPI_MODE_SLAVE                  (0x00000000U)
+#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 /**
   * @}
   */
 
-/** @defgroup SPI_Direction SPI Direction Mode
+/** @defgroup SPI_Direction_mode SPI Direction Mode
   * @{
   */
-#define SPI_DIRECTION_2LINES            (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
+#define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
 /**
   * @}
   */
 
-/** @defgroup SPI_Data_Size SPI Data Size
+/** @defgroup SPI_data_size SPI Data Size
   * @{
   */
-#define SPI_DATASIZE_8BIT               (0x00000000U)
+#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity 
   * @{
   */
-#define SPI_POLARITY_LOW                (0x00000000U)
+#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 /**
   * @}
@@ -241,7 +218,7 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 /** @defgroup SPI_Clock_Phase SPI Clock Phase
   * @{
   */
-#define SPI_PHASE_1EDGE                 (0x00000000U)
+#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 /**
   * @}
@@ -251,31 +228,31 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   * @{
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
+#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
   * @{
   */
-#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission 
   * @{
   */
-#define SPI_FIRSTBIT_MSB                (0x00000000U)
+#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 /**
   * @}
@@ -284,8 +261,8 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 /** @defgroup SPI_TI_mode SPI TI Mode
   * @{
   */
-#define SPI_TIMODE_DISABLE              (0x00000000U)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
+#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE              SPI_CR2_FRF
 /**
   * @}
   */
@@ -293,8 +270,8 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
   * @{
   */
-#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
+#define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
 /**
   * @}
   */
@@ -309,18 +286,16 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   * @}
   */
 
-/** @defgroup SPI_Flags_definition SPI Flags Definition
+/** @defgroup SPI_Flags_definition SPI Flags Definition 
   * @{
   */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
-                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE
+#define SPI_FLAG_TXE                    SPI_SR_TXE
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
+#define SPI_FLAG_MODF                   SPI_SR_MODF
+#define SPI_FLAG_OVR                    SPI_SR_OVR
+#define SPI_FLAG_BSY                    SPI_SR_BSY
+#define SPI_FLAG_FRE                    SPI_SR_FRE
 /**
   * @}
   */
@@ -329,67 +304,46 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   * @}
   */
 
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup SPI_Exported_Macros SPI Exported Macros
   * @{
   */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__ specifies the SPI Handle.
+/** @brief Reset SPI handle state
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 
-/** @brief  Enable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI Handle.
+/** @brief  Enable or disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Disable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI handle.
-  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
   *         This parameter can be one of the following values:
   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg SPI_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
 
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
+/** @brief  Check if the specified SPI interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
   *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
+  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *             @arg SPI_IT_ERR: Error interrupt enable
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __FLAG__: specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
@@ -397,245 +351,71 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   *            @arg SPI_FLAG_MODF: Mode fault flag
   *            @arg SPI_FLAG_OVR: Overrun flag
   *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag  
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
 
 /** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
   * @retval None
   */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
-  do{                                                    \
-    __IO uint32_t tmpreg_modf = 0x00U;                   \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
-    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                                 \
-  } while(0U)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)            \
+  do{                                                   \
+    __IO uint32_t tmpreg;                               \
+    tmpreg = (__HANDLE__)->Instance->SR;                \
+    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);      \
+    UNUSED(tmpreg);                                     \
+  } while(0) 
 
 /** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
   * @retval None
   */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0U)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)     \
+  do{                                           \
+    __IO uint32_t tmpreg;                       \
+    tmpreg = (__HANDLE__)->Instance->DR;        \
+    tmpreg = (__HANDLE__)->Instance->SR;        \
+    UNUSED(tmpreg);                             \
+  } while(0) 
 
 /** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
+  * @param  __HANDLE__: specifies the SPI handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_fre = 0x00U;              \
-    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_fre);                            \
-  }while(0U)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  */                                           
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)     \
+  do{                                             \
+  __IO uint32_t tmpreg;                         \
+  tmpreg = (__HANDLE__)->Instance->SR;          \
+  UNUSED(tmpreg);                               \
+  }while(0) 
+
+/** @brief Enable SPI
+  * @param __HANDLE__: specifies the SPI Handle.
   * @retval None
   */
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
 
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+/** @brief Disable SPI
+  * @param __HANDLE__: specifies the SPI Handle.
   * @retval None
   */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SPI_CR1_SPE)
 /**
   * @}
   */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of SPI SR regsiter.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of SPI CR2 regsiter.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if SPI Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Mode.
-  *         This parameter can be a value of @ref SPI_Mode
-  * @retval None
-  */
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
-                               ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  *         This parameter can be a value of @ref SPI_Direction
-  * @retval None
-  */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
-                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Data Size parameter is in allowed range.
-  * @param  __DATASIZE__ specifies the SPI Data Size.
-  *         This parameter can be a value of @ref SPI_Data_Size
-  * @retval None
-  */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the SPI serial clock steady state.
-  *         This parameter can be a value of @ref SPI_Clock_Polarity
-  * @retval None
-  */
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
-                               ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
-  * @param  __CPHA__ specifies the SPI Clock Phase.
-  *         This parameter can be a value of @ref SPI_Clock_Phase
-  * @retval None
-  */
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
-                               ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief  Checks if SPI Slave Select parameter is in allowed range.
-  * @param  __NSS__ specifies the SPI Slave Select management parameter.
-  *         This parameter can be a value of @ref SPI_Slave_Select_management
-  * @retval None
-  */
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \
-                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \
-                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-  * @retval None
-  */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
-  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
-  * @retval None
-  */
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
-                                   ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief  Checks if SPI TI mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI TI mode.
-  *         This parameter can be a value of @ref SPI_TI_mode
-  * @retval None
-  */
-#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
-                                 ((__MODE__) == SPI_TIMODE_ENABLE))
-
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
-  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
-  *         This parameter can be a value of @ref SPI_CRC_Calculation
-  * @retval None
-  */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
-  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
-  * @retval None
-  */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief  Checks if DMA handle is valid.
-  * @param  __HANDLE__ specifies a DMA Handle.
-  * @retval None
-  */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
-  * @}
-  */
-
+  
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SPI_Exported_Functions
   * @{
@@ -644,17 +424,11 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 /** @addtogroup SPI_Exported_Functions_Group1
   * @{
   */
-/* Initialization/de-initialization functions  ********************************/
+/* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -662,65 +436,140 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
 /** @addtogroup SPI_Exported_Functions_Group2
   * @{
   */
-/* I/O operation functions  ***************************************************/
+/* I/O operation functions  *****************************************************/
 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                             uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 
 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
-
+  
 /** @addtogroup SPI_Exported_Functions_Group3
   * @{
   */
-/* Peripheral State and Error functions ***************************************/
+/* Peripheral State and Control functions  **************************************/
 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+  * @}
+  */ 
+
 /**
   * @}
   */
+  
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+  * @{
+  */
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+                           ((MODE) == SPI_MODE_MASTER))
+                           
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
+                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                     ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
+                                                ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+  
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+                           ((CPOL) == SPI_POLARITY_HIGH))                         
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+                           ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
+                         ((NSS) == SPI_NSS_HARD_INPUT) || \
+                         ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+                               ((BIT) == SPI_FIRSTBIT_LSB))
 
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+                             ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+                                                                                                      
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+ 
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE) 
+
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+                                           (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)                           
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+  * @{
+  */
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */ 
+
 /**
   * @}
   */
 
+  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_SPI_H */
+#endif /* __STM32F2xx_HAL_SPI_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h

@@ -2,105 +2,95 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sram.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SRAM_H
-#define STM32F2xx_HAL_SRAM_H
+#ifndef __STM32F2xx_HAL_SRAM_H
+#define __STM32F2xx_HAL_SRAM_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_fsmc.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
+
 /** @addtogroup SRAM
   * @{
-  */
+  */ 
 
 /* Exported typedef ----------------------------------------------------------*/
 
 /** @defgroup SRAM_Exported_Types SRAM Exported Types
   * @{
-  */
-/**
-  * @brief  HAL SRAM State structures definition
-  */
+  */ 
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
 typedef enum
 {
-  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
-  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
-  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
-  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
-  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
-
-} HAL_SRAM_StateTypeDef;
-
-/**
-  * @brief  SRAM handle Structure definition
-  */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-typedef struct __SRAM_HandleTypeDef
-#else
+  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
+  
+}HAL_SRAM_StateTypeDef;
+
+/** 
+  * @brief  SRAM handle Structure definition  
+  */ 
 typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */	
 {
-  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
-
+  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ 
+  
   FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
-
+  
   FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
 
-  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
-
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
+  
   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
-
+  
   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+  
+}SRAM_HandleTypeDef; 
 
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-  void  (* MspInitCallback)        ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp Init callback              */
-  void  (* MspDeInitCallback)      ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp DeInit callback            */
-  void  (* DmaXferCpltCallback)    ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Complete callback     */
-  void  (* DmaXferErrorCallback)   ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Error callback        */
-#endif
-} SRAM_HandleTypeDef;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SRAM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
-  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
-  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
-  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
-}HAL_SRAM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SRAM Callback pointer definition
-  */
-typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
-typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif
 /**
   * @}
   */
@@ -109,51 +99,42 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
 /* Exported macro ------------------------------------------------------------*/
 
 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
-
+  * @{
+  */
 /** @brief Reset SRAM handle state
-  * @param  __HANDLE__ SRAM handle
+  * @param  __HANDLE__: SRAM handle
   * @retval None
   */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
-                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
-                                                               (__HANDLE__)->MspInitCallback = NULL;       \
-                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                             } while(0)
-#else
 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif
 
 /**
   * @}
   */
-
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
-  * @{
-  */
 
-/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
+/** @addtogroup SRAM_Exported_Functions
+ *  @{
  */
 
-/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup SRAM_Exported_Functions_Group1
+ *  @{
+ */
+/* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 
+void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
+/** @addtogroup SRAM_Exported_Functions_Group2
+ *  @{
  */
-
-/* I/O operation functions  ***************************************************/
+/* I/O operation functions  *****************************************************/
 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
@@ -162,40 +143,25 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
-#endif
-
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
+/** @addtogroup SRAM_Exported_Functions_Group3
+ *  @{
  */
-
-/* SRAM Control functions  ****************************************************/
+/* SRAM Control functions  ******************************************************/
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
 /**
   * @}
-  */
+  */ 
 
-/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
+/** @addtogroup SRAM_Exported_Functions_Group4
+ *  @{
  */
-
-/* SRAM  State functions ******************************************************/
+/* SRAM State functions *********************************************************/
 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
 /**
   * @}
   */
@@ -204,19 +170,22 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
   * @}
   */
 
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* STM32F2xx_HAL_SRAM_H */
+#endif /* __STM32F2xx_HAL_SRAM_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @brief   Header file of TIM HAL Extended module.
+  * @version V1.1.0
+  * @date    09-October-2015
+  * @brief   Header file of TIM HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_TIM_EX_H
-#define STM32F2xx_HAL_TIM_EX_H
+#ifndef __STM32F2xx_HAL_TIM_EX_H
+#define __STM32F2xx_HAL_TIM_EX_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,250 +52,256 @@ extern "C" {
 
 /** @addtogroup TIMEx
   * @{
-  */
+  */ 
 
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup TIMEx_Exported_Types TIM Exported Types
   * @{
   */
-
-/**
-  * @brief  TIM Hall sensor Configuration Structure definition
+  
+/** 
+  * @brief  TIM Hall sensor Configuration Structure definition  
   */
 
 typedef struct
 {
-  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
-                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
+                                  
+  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
+                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                                                                   
   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
+                                  
   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
 } TIM_HallSensor_InitTypeDef;
+
+/** 
+  * @brief  TIM Master configuration Structure definition  
+  */ 
+typedef struct {
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. 
+                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ 
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. 
+                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/** 
+  * @brief  TIM Break and Dead time configuration Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t OffStateRunMode;            /*!< TIM off state in run mode.
+                                         This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode.
+                                         This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;                     /*!< TIM Lock level.
+                                         This parameter can be a value of @ref TIM_Lock_level */                             
+  uint32_t DeadTime;                     /*!< TIM dead Time. 
+                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;                   /*!< TIM Break State. 
+                                         This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;                 /*!< TIM Break input polarity. 
+                                         This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t AutomaticOutput;               /*!< TIM Automatic Output Enable state. 
+                                         This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           
+}TIM_BreakDeadTimeConfigTypeDef;
 /**
   * @}
   */
-/* End of exported types -----------------------------------------------------*/
-
+  
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+/** @defgroup TIMEx_Exported_Constants  TIM Exported Constants
   * @{
   */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
+  
+/** @defgroup TIMEx_Remap  TIM Remap
   * @{
   */
-#define TIM_TIM2_TIM8_TRGO                     0x00000000U                              /*!< TIM2 ITR1 is connected to TIM8 TRGO */
-#define TIM_TIM2_ETH_PTP                       TIM_OR_ITR1_RMP_0                        /*!< TIM2 ITR1 is connected to PTP trigger output */
-#define TIM_TIM2_USBFS_SOF                     TIM_OR_ITR1_RMP_1                        /*!< TIM2 ITR1 is connected to OTG FS SOF */
-#define TIM_TIM2_USBHS_SOF                     (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0)  /*!< TIM2 ITR1 is connected to OTG HS SOF */
-
-#define TIM_TIM5_GPIO                          0x00000000U                              /*!< TIM5 TI4 is connected to GPIO */
-#define TIM_TIM5_LSI                           TIM_OR_TI4_RMP_0                         /*!< TIM5 TI4 is connected to LSI */
-#define TIM_TIM5_LSE                           TIM_OR_TI4_RMP_1                         /*!< TIM5 TI4 is connected to LSE */
-#define TIM_TIM5_RTC                           (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)    /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
+#define TIM_TIM2_TIM8_TRGO                     (0x00000000)
+#define TIM_TIM2_ETH_PTP                       (0x00000400)
+#define TIM_TIM2_USBFS_SOF                     (0x00000800)
+#define TIM_TIM2_USBHS_SOF                     (0x00000C00)
+#define TIM_TIM5_GPIO                          (0x00000000)
+#define TIM_TIM5_LSI                           (0x00000040)
+#define TIM_TIM5_LSE                           (0x00000080)
+#define TIM_TIM5_RTC                           (0x000000C0)
+#define TIM_TIM11_GPIO                         (0x00000000)
+#define TIM_TIM11_HSE                          (0x00000002)
 
-#define TIM_TIM11_GPIO                         0x00000000U                              /*!< TIM11 TI1 is connected to GPIO */
-#define TIM_TIM11_HSE                          TIM_OR_TI1_RMP_1                         /*!< TIM11 TI1 is connected to HSE_RTC clock */
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-/* End of exported constants -------------------------------------------------*/
-
+  */ 
+  
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
-  * @{
-  */
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                       \
-        ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \
-                                    ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
-                                    ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
-         (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
-                                    ((TIM_REMAP) == TIM_TIM5_LSI)            || \
-                                    ((TIM_REMAP) == TIM_TIM5_LSE)            || \
-                                    ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
-         (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
-                                    ((TIM_REMAP) == TIM_TIM11_HSE))))
-
-/**
-  * @}
-  */
-/* End of private macro ------------------------------------------------------*/
-
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+/** @addtogroup TIMEx_Exported_Functions
   * @{
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
-  *  @brief    Timer Hall Sensor functions
+/** @addtogroup TIMEx_Exported_Functions_Group1
   * @{
   */
 /*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
 
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
 
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
-  *  @brief   Timer Complementary Output Compare functions
+/** @addtogroup TIMEx_Exported_Functions_Group2
   * @{
   */
 /*  Timer Complementary Output Compare functions  *****************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
 
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
-  *  @brief    Timer Complementary PWM functions
+/** @addtogroup TIMEx_Exported_Functions_Group3
   * @{
   */
 /*  Timer Complementary PWM functions  ****************************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
-  *  @brief    Timer Complementary One Pulse functions
+/** @addtogroup TIMEx_Exported_Functions_Group4
   * @{
   */
 /*  Timer Complementary One Pulse functions  **********************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
-  *  @brief    Peripheral Control functions
+/** @addtogroup TIMEx_Exported_Functions_Group5
   * @{
   */
-/* Extended Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
-                                              uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
-                                                 uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
-                                                  uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/* Extension Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
-  * @brief    Extended Callbacks functions
+/** @addtogroup TIMEx_Exported_Functions_Group6
   * @{
-  */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+  */ 
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
-  * @brief    Extended Peripheral State functions
+/** @addtogroup TIMEx_Exported_Functions_Group7
   * @{
   */
-/* Extended Peripheral State functions  ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/* Extension Peripheral State functions  **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
-/* End of exported functions -------------------------------------------------*/
+  */ 
 
-/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Private Macros
   * @{
   */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+#define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
+                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
+                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
+                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+                                  ((TIM_REMAP) == TIM_TIM11_HSE))
+
+#define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFF) 
 /**
   * @}
+  */  
+  
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Private Functions
+  * @{
   */
-/* End of private functions --------------------------------------------------*/
-
+  
 /**
   * @}
   */
 
 /**
   * @}
-  */
+  */ 
 
+/**
+  * @}
+  */
+    
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /* STM32F2xx_HAL_TIM_EX_H */
+#endif /* __STM32F2xx_HAL_TIM_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_uart.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_UART_H
 #define __STM32F2xx_HAL_UART_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,22 +52,22 @@ extern "C" {
 
 /** @addtogroup UART
   * @{
-  */
+  */ 
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup UART_Exported_Types UART Exported Types
   * @{
   */
 
-/**
-  * @brief UART Init Structure definition
-  */
+/** 
+  * @brief UART Init Structure definition  
+  */ 
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
                                            The baud rate is computed using the following formula:
                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
                                            Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
 
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
@@ -64,179 +82,84 @@ typedef struct
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
-
+ 
   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref UART_Mode */
 
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
+                                           or disabled.
                                            This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
+  
   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */
-} UART_InitTypeDef;
+                                           This parameter can be a value of @ref UART_Over_Sampling */ 
+}UART_InitTypeDef;
 
-/**
-  * @brief HAL UART State structures definition
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains UART state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral not initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
+/** 
+  * @brief HAL UART State structures definition  
+  */ 
 typedef enum
 {
-  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
-                                                   Value is allowed for gState only */
-} HAL_UART_StateTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct __UART_HandleTypeDef
+  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
+  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */   
+  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */ 
+  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */  
+  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */      
+}HAL_UART_StateTypeDef;
+
+/** 
+  * @brief  UART handle Structure definition  
+  */  
+typedef struct
 {
   USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-
+  
   UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-
+  
   uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
+  
   uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
-
+  
+  uint16_t                      TxXferCount;      /*!< UART Tx Transfer Counter           */
+  
   uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
+  
   uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
-
+  
+  uint16_t                      RxXferCount;      /*!< UART Rx Transfer Counter           */  
+  
   DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
+    
   DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
+  
   HAL_LockTypeDef               Lock;             /*!< Locking object                     */
 
-  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
-                                                       and also related to Tx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
+  __IO HAL_UART_StateTypeDef    State;            /*!< UART communication state           */
+  
   __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
 
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
-  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
-  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
-  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
-  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
-  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
-
-  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
-#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL UART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
-  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
-  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
-  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
-  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
-  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
-  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
-  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
-  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
-
-  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
-  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL UART Callback pointer definition
-  */
-typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
+}UART_HandleTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
+/** @defgroup UART_Exported_Constants UART Exported constants
   * @{
   */
 
 /** @defgroup UART_Error_Code UART Error Code
+  * @brief    UART Error Code 
   * @{
-  */
-#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
-#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
-#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
-#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
-#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  */ 
+#define HAL_UART_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
+#define HAL_UART_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
+#define HAL_UART_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
+#define HAL_UART_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
+#define HAL_UART_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
 /**
   * @}
   */
@@ -244,7 +167,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 /** @defgroup UART_Word_Length UART Word Length
   * @{
   */
-#define UART_WORDLENGTH_8B                  0x00000000U
+#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
@@ -253,26 +176,26 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 /** @defgroup UART_Stop_Bits UART Number of Stop Bits
   * @{
   */
-#define UART_STOPBITS_1                     0x00000000U
+#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup UART_Parity UART Parity
   * @{
-  */
-#define UART_PARITY_NONE                    0x00000000U
+  */ 
+#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
   * @{
-  */
-#define UART_HWCONTROL_NONE                  0x00000000U
+  */ 
+#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
@@ -282,18 +205,18 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 
 /** @defgroup UART_Mode UART Transfer Mode
   * @{
-  */
+  */ 
 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
-
-/** @defgroup UART_State UART State
+    
+ /** @defgroup UART_State UART State
   * @{
-  */
-#define UART_STATE_DISABLE                  0x00000000U
+  */ 
+#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
 /**
   * @}
@@ -302,7 +225,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 /** @defgroup UART_Over_Sampling UART Over Sampling
   * @{
   */
-#define UART_OVERSAMPLING_16                    0x00000000U
+#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
 #define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
 /**
   * @}
@@ -310,18 +233,18 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 
 /** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
   * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
+  */  
+#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)0x00000020)
 /**
   * @}
   */
-
+                                         
 /** @defgroup UART_WakeUp_functions  UART Wakeup Functions
   * @{
   */
-#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
+#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)0x00000800)
 /**
   * @}
   */
@@ -349,22 +272,23 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *        Elements values convention: 0xY000XXXX
   *           - XXXX  : Interrupt mask (16 bits) in the Y register
   *           - Y  : Interrupt source register (2bits)
-  *                   - 0001: CR1 register
-  *                   - 0010: CR2 register
-  *                   - 0011: CR3 register
+  *                 - 0001: CR1 register
+  *                 - 0010: CR2 register
+  *                 - 0011: CR3 register
+  *
   * @{
-  */
+  */ 
 
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
 
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
 
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
 /**
   * @}
   */
@@ -372,44 +296,30 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 /**
   * @}
   */
-
+  
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup UART_Exported_Macros UART Exported Macros
   * @{
   */
 
-/** @brief Reset UART handle gstate & RxState
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief Reset UART handle state
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief  Flushes the UART DR register
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief  Flushes the UART DR register 
+  * @param  __HANDLE__: specifies the UART Handle.
   */
 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
 
 /** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
   *            @arg UART_FLAG_LBD:  LIN Break detection flag
@@ -423,83 +333,84 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg UART_FLAG_PE:   Parity Error flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
+     
 /** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
   *            @arg UART_FLAG_LBD:  LIN Break detection flag.
   *            @arg UART_FLAG_TC:   Transmission Complete flag.
   *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *
+  *   
   * @retval None
   */
 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
-/** @brief  Clears the UART PE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
   do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
+    __IO uint32_t tmpreg;                       \
     tmpreg = (__HANDLE__)->Instance->SR;        \
     tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0U)
+  } while(0)
 
-/** @brief  Clears the UART FE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clears the UART NE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clears the UART ORE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clears the UART IDLE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
   * @retval None
   */
 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
+                                                 
 /** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS:  CTS change interrupt
   *            @arg UART_IT_LBD:  LIN Break detection interrupt
@@ -511,15 +422,15 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
+#define UART_IT_MASK  ((uint32_t)0x0000FFFF)
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
 /** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS:  CTS change interrupt
   *            @arg UART_IT_LBD:  LIN Break detection interrupt
@@ -531,15 +442,15 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+    
 /** @brief  Checks whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__ specifies the UART interrupt source to check.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __IT__: specifies the UART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
   *            @arg UART_IT_LBD: LIN Break detection interrupt
@@ -547,114 +458,110 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg UART_IT_TC:  Transmission complete interrupt
   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
   *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ERR: Error interrupt
+  *            @arg USART_IT_ERR: Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
 
-/** @brief  Enable CTS flow control
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+/** @brief  Enable CTS flow control 
+  *         This macro allows to enable CTS hardware flow control for a given UART instance, 
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         The Handle Instance can be USART1, USART2 or LPUART.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
   do{                                                      \
     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0U)
+  } while(0)
 
-/** @brief  Disable CTS flow control
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+/** @brief  Disable CTS flow control 
+  *         This macro allows to disable CTS hardware flow control for a given UART instance, 
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         The Handle Instance can be USART1, USART2 or LPUART.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
   do{                                                       \
     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0U)
+  } while(0)
 
-/** @brief  Enable RTS flow control
-  *         This macro allows to enable RTS hardware flow control for a given UART instance,
+/** @brief  Enable RTS flow control 
+  *         This macro allows to enable RTS hardware flow control for a given UART instance, 
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         The Handle Instance can be USART1, USART2 or LPUART.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
   do{                                                     \
     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0U)
+  } while(0)
 
-/** @brief  Disable RTS flow control
-  *         This macro allows to disable RTS hardware flow control for a given UART instance,
+/** @brief  Disable RTS flow control 
+  *         This macro allows to disable RTS hardware flow control for a given UART instance, 
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         The Handle Instance can be USART1, USART2 or LPUART.
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
   do{                                                      \
     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0U)
+  } while(0)
 
-/** @brief  Macro to enable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
+/** @brief  macros to enables the UART's one bit sample method
+  * @param  __HANDLE__: specifies the UART Handle.  
   * @retval None
-  */
+  */     
 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
-/** @brief  Macro to disable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
+/** @brief  macros to disables the UART's one bit sample method
+  * @param  __HANDLE__: specifies the UART Handle.  
   * @retval None
-  */
+  */      
 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART
-  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
-  */
+  */    
 #define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART
-  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __HANDLE__: specifies the UART Handle.
   * @retval None
-  */
+  */    
 #define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 /**
   * @}
@@ -664,34 +571,25 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 /** @addtogroup UART_Exported_Functions
   * @{
   */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  
+/** @addtogroup UART_Exported_Functions_Group1
   * @{
-  */
-
+  */    
 /* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
 
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+/** @addtogroup UART_Exported_Functions_Group2
   * @{
   */
-
 /* IO operation functions *******************************************************/
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -702,24 +600,12 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
 /**
   * @}
   */
@@ -745,11 +631,11 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -757,13 +643,11 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
   * @{
   */
 /** @brief UART interruptions flag mask
-  *
-  */
-#define UART_IT_MASK                     0x0000FFFFU
-
-#define UART_CR1_REG_INDEX               1U
-#define UART_CR2_REG_INDEX               2U
-#define UART_CR3_REG_INDEX               3U
+  * 
+  */ 
+#define UART_CR1_REG_INDEX               1    
+#define UART_CR2_REG_INDEX               2    
+#define UART_CR3_REG_INDEX               3
 /**
   * @}
   */
@@ -785,7 +669,7 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
                                ((CONTROL) == UART_HWCONTROL_RTS) || \
                                ((CONTROL) == UART_HWCONTROL_CTS) || \
                                ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
                               ((STATE) == UART_STATE_ENABLE))
 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
@@ -795,26 +679,18 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
                                                  ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
                                       ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
-                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25)/(4*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25)/(2*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
 
 /**
   * @}
@@ -835,8 +711,7 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
 
 /**
   * @}
-  */
-
+  */   
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_usart.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_USART_H
 #define __STM32F2xx_HAL_USART_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,16 +52,16 @@ extern "C" {
 
 /** @addtogroup USART
   * @{
-  */
+  */ 
 
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/ 
 /** @defgroup USART_Exported_Types USART Exported Types
   * @{
   */
-
-/**
-  * @brief USART Init Structure definition
-  */
+   
+/** 
+  * @brief USART Init Structure definition  
+  */ 
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
@@ -57,13 +75,13 @@ typedef struct
   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
                                            This parameter can be a value of @ref USART_Stop_Bits */
 
-  uint32_t Parity;                    /*!< Specifies the parity mode.
+  uint32_t Parity;                   /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref USART_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
-
+ 
   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref USART_Mode */
 
@@ -76,95 +94,55 @@ typedef struct
   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
                                            This parameter can be a value of @ref USART_Last_Bit */
-} USART_InitTypeDef;
+}USART_InitTypeDef;
 
-/**
-  * @brief HAL State structures definition
-  */
+/** 
+  * @brief HAL State structures definition  
+  */ 
 typedef enum
 {
-  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized   */
-  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
-  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
-  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */
-  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
-  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */
-} HAL_USART_StateTypeDef;
-
-/**
-  * @brief  USART handle Structure definition
-  */
-typedef struct __USART_HandleTypeDef
-{
-  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
-
-  USART_InitTypeDef             Init;             /*!< Usart communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;      /*!< Pointer to Usart Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /*!< Usart Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;      /*!< Usart Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to Usart Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /*!< Usart Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;      /*!< Usart Rx Transfer Counter           */
-
-  DMA_HandleTypeDef             *hdmatx;          /*!< Usart Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /*!< Usart Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef                Lock;            /*!< Locking object                      */
-
-  __IO HAL_USART_StateTypeDef    State;           /*!< Usart communication state           */
-
-  __IO uint32_t                  ErrorCode;       /*!< USART Error code                    */
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
-  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
-  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
-  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
-
-  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
-#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-} USART_HandleTypeDef;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL USART Callback ID enumeration definition
-  */
-typedef enum
+  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized   */
+  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */   
+  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */ 
+  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_USART_STATE_ERROR             = 0x04     /*!< Error */      
+}HAL_USART_StateTypeDef;
+
+/** 
+  * @brief  USART handle Structure definition  
+  */  
+typedef struct
 {
-  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
-  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
-  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
-  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
-  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
-  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
-  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
-
-  HAL_USART_MSPINIT_CB_ID                 = 0x07U,    /*!< USART MspInit callback ID                 */
-  HAL_USART_MSPDEINIT_CB_ID               = 0x08U     /*!< USART MspDeInit callback ID               */
-
-} HAL_USART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL USART Callback pointer definition
-  */
-typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
-
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
+  USART_TypeDef                 *Instance;        /* USART registers base address        */
+  
+  USART_InitTypeDef             Init;             /* Usart communication parameters      */
+  
+  uint8_t                       *pTxBuffPtr;      /* Pointer to Usart Tx transfer Buffer */
+  
+  uint16_t                      TxXferSize;       /* Usart Tx Transfer size              */
+  
+  __IO uint16_t                 TxXferCount;      /* Usart Tx Transfer Counter           */
+  
+  uint8_t                       *pRxBuffPtr;      /* Pointer to Usart Rx transfer Buffer */
+  
+  uint16_t                      RxXferSize;       /* Usart Rx Transfer size              */
+  
+  __IO uint16_t                 RxXferCount;      /* Usart Rx Transfer Counter           */  
+  
+  DMA_HandleTypeDef             *hdmatx;          /* Usart Tx DMA Handle parameters      */
+    
+  DMA_HandleTypeDef             *hdmarx;          /* Usart Rx DMA Handle parameters      */
+  
+  HAL_LockTypeDef                Lock;            /* Locking object                      */
+  
+  __IO HAL_USART_StateTypeDef    State;           /* Usart communication state           */
+  
+  __IO uint32_t                  ErrorCode;       /* USART Error code                    */
+
+}USART_HandleTypeDef;
 /**
   * @}
   */
@@ -175,18 +153,15 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   */
 
 /** @defgroup USART_Error_Code USART Error Code
-  * @brief    USART Error Code
+  * @brief    USART Error Code 
   * @{
-  */
-#define HAL_USART_ERROR_NONE             0x00000000U   /*!< No error                */
-#define HAL_USART_ERROR_PE               0x00000001U   /*!< Parity error            */
-#define HAL_USART_ERROR_NE               0x00000002U   /*!< Noise error             */
-#define HAL_USART_ERROR_FE               0x00000004U   /*!< Frame error             */
-#define HAL_USART_ERROR_ORE              0x00000008U   /*!< Overrun error           */
-#define HAL_USART_ERROR_DMA              0x00000010U   /*!< DMA transfer error      */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U    /*!< Invalid Callback error */
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+  */ 
+#define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
+#define HAL_USART_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
+#define HAL_USART_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
+#define HAL_USART_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
+#define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
+#define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
 /**
   * @}
   */
@@ -194,8 +169,8 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
 /** @defgroup USART_Word_Length USART Word Length
   * @{
   */
-#define USART_WORDLENGTH_8B          0x00000000U
-#define USART_WORDLENGTH_9B          ((uint32_t)USART_CR1_M)
+#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
@@ -203,66 +178,66 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
   * @{
   */
-#define USART_STOPBITS_1             0x00000000U
-#define USART_STOPBITS_0_5           ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2             ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5           ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define USART_STOPBITS_1                     ((uint32_t)0x00000000)
+#define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup USART_Parity USART Parity
   * @{
-  */
-#define USART_PARITY_NONE            0x00000000U
-#define USART_PARITY_EVEN            ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD             ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+  */ 
+#define USART_PARITY_NONE                    ((uint32_t)0x00000000)
+#define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup USART_Mode USART Mode
   * @{
-  */
-#define USART_MODE_RX                ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX                ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX             ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
+  */ 
+#define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
-
+    
 /** @defgroup USART_Clock USART Clock
   * @{
-  */
-#define USART_CLOCK_DISABLE          0x00000000U
-#define USART_CLOCK_ENABLE           ((uint32_t)USART_CR2_CLKEN)
+  */ 
+#define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup USART_Clock_Polarity USART Clock Polarity
   * @{
   */
-#define USART_POLARITY_LOW           0x00000000U
-#define USART_POLARITY_HIGH          ((uint32_t)USART_CR2_CPOL)
+#define USART_POLARITY_LOW                   ((uint32_t)0x00000000)
+#define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup USART_Clock_Phase USART Clock Phase
+/** @defgroup USART_Clock_Phase  USART Clock Phase
   * @{
   */
-#define USART_PHASE_1EDGE            0x00000000U
-#define USART_PHASE_2EDGE            ((uint32_t)USART_CR2_CPHA)
+#define USART_PHASE_1EDGE                    ((uint32_t)0x00000000)
+#define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
   */
 
-/** @defgroup USART_Last_Bit USART Last Bit
+/** @defgroup USART_Last_Bit  USART Last Bit
   * @{
   */
-#define USART_LASTBIT_DISABLE        0x00000000U
-#define USART_LASTBIT_ENABLE         ((uint32_t)USART_CR2_LBCL)
+#define USART_LASTBIT_DISABLE                ((uint32_t)0x00000000)
+#define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
   */
@@ -270,8 +245,8 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
 /** @defgroup USART_NACK_State USART NACK State
   * @{
   */
-#define USART_NACK_ENABLE            ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE           0x00000000U
+#define USART_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE          ((uint32_t)0x00000000)
 /**
   * @}
   */
@@ -281,14 +256,14 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define USART_FLAG_TXE               ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC                ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE              ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE              ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE               ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE                ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE                ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE                ((uint32_t)USART_SR_PE)
+#define USART_FLAG_TXE                       ((uint32_t)0x00000080)
+#define USART_FLAG_TC                        ((uint32_t)0x00000040)
+#define USART_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define USART_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define USART_FLAG_ORE                       ((uint32_t)0x00000008)
+#define USART_FLAG_NE                        ((uint32_t)0x00000004)
+#define USART_FLAG_FE                        ((uint32_t)0x00000002)
+#define USART_FLAG_PE                        ((uint32_t)0x00000001)
 /**
   * @}
   */
@@ -300,14 +275,19 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   *                 - 01: CR1 register
   *                 - 10: CR2 register
   *                 - 11: CR3 register
+  *
   * @{
-  */
-#define USART_IT_PE                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define USART_IT_TXE                 ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define USART_IT_TC                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define USART_IT_RXNE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define USART_IT_IDLE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define USART_IT_ERR                 ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+  */  
+#define USART_IT_PE                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
+#define USART_IT_TXE                    ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
+#define USART_IT_TC                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
+#define USART_IT_RXNE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
+#define USART_IT_IDLE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+
+#define USART_IT_LBD                    ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+
+#define USART_IT_CTS                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
+#define USART_IT_ERR                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
 /**
   * @}
   */
@@ -322,24 +302,16 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   */
 
 /** @brief Reset USART handle state
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
-                                                      (__HANDLE__)->State = HAL_USART_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback = NULL;        \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
-                                                    } while(0U)
-#else
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/** @brief  Check whether the specified USART flag is set or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief  Checks whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg USART_FLAG_TXE:  Transmit data register empty flag
   *            @arg USART_FLAG_TC:   Transmission Complete flag
@@ -353,72 +325,72 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   */
 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clear the specified USART pending flags.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __FLAG__ specifies the flag to check.
+/** @brief  Clears the specified Smartcard pending flags.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg USART_FLAG_TC:   Transmission Complete flag.
   *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *
+  *   
   * @retval None
   */
 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)    \
   do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
+    __IO uint32_t tmpreg;                       \
     tmpreg = (__HANDLE__)->Instance->SR;        \
     tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0U)
-
+  } while(0)
+                                               
 /** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
   * @retval None
   */
 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Enables or disables the specified USART interrupts.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg USART_IT_TC:   Transmission complete interrupt
@@ -426,19 +398,20 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   *            @arg USART_IT_IDLE: Idle line detection interrupt
   *            @arg USART_IT_PE:   Parity Error interrupt
   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  *          This parameter can be: ENABLE or DISABLE.
   * @retval None
   */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+                                                            (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
                                                              ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+                                                            (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                              ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
+    
 /** @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the USART Handle.
-  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-  * @param  __IT__ specifies the USART interrupt source to check.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __IT__: specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
   *            @arg USART_IT_TC:  Transmission complete interrupt
@@ -448,34 +421,34 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   *            @arg USART_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
 
 /** @brief  Macro to enable the USART's one bit sample method
-  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __HANDLE__: specifies the USART Handle.  
   * @retval None
-  */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
+  */     
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the USART's one bit sample method
-  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __HANDLE__: specifies the USART Handle.  
   * @retval None
-  */
+  */      
 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable USART
-  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __HANDLE__: specifies the USART Handle.
   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
-#define __HAL_USART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_USART_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable USART
-  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __HANDLE__: specifies the USART Handle.
   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
-  */
-#define __HAL_USART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+  */ 
+#define __HAL_USART_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 
 /**
   * @}
@@ -493,13 +466,6 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
@@ -520,10 +486,6 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
@@ -531,10 +493,9 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
 /**
   * @}
-  */
+  */ 
 
 /** @addtogroup USART_Exported_Functions_Group3
   * @{
@@ -544,7 +505,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
@@ -556,14 +517,14 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
   * @{
   */
 /** @brief USART interruptions flag mask
-  *
-  */
+  * 
+  */ 
 #define USART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                    USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
 
-#define USART_CR1_REG_INDEX          1U
-#define USART_CR2_REG_INDEX          2U
-#define USART_CR3_REG_INDEX          3U
+#define USART_CR1_REG_INDEX             1    
+#define USART_CR2_REG_INDEX             2    
+#define USART_CR3_REG_INDEX             3 
 /**
   * @}
   */
@@ -572,49 +533,30 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 /** @defgroup USART_Private_Macros USART Private Macros
   * @{
   */
-#define IS_USART_NACK_STATE(NACK)    (((NACK) == USART_NACK_ENABLE) || \
-                                      ((NACK) == USART_NACK_DISABLE))
-
-#define IS_USART_LASTBIT(LASTBIT)    (((LASTBIT) == USART_LASTBIT_DISABLE) || \
-                                      ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_PHASE(CPHA)         (((CPHA) == USART_PHASE_1EDGE) || \
-                                      ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_POLARITY(CPOL)      (((CPOL) == USART_POLARITY_LOW) || \
-                                      ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_CLOCK(CLOCK)        (((CLOCK) == USART_CLOCK_DISABLE) || \
-                                      ((CLOCK) == USART_CLOCK_ENABLE))
-
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+                                   ((NACK) == USART_NACK_DISABLE))
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+                                       ((LASTBIT) == USART_LASTBIT_ENABLE))
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+                               ((CLOCK) == USART_CLOCK_ENABLE))
 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
-                                      ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS)  (((STOPBITS) == USART_STOPBITS_1) || \
-                                      ((STOPBITS) == USART_STOPBITS_0_5) || \
-                                      ((STOPBITS) == USART_STOPBITS_1_5) || \
-                                      ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY)      (((PARITY) == USART_PARITY_NONE) || \
-                                      ((PARITY) == USART_PARITY_EVEN) || \
-                                      ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE)          ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
-
-#define IS_USART_BAUDRATE(BAUDRATE)  ((BAUDRATE) <= 7500000U)
-
-#define USART_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(2U*(_BAUD_)))
-
-#define USART_DIVMANT(_PCLK_, _BAUD_)  (USART_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define USART_DIVFRAQ(_PCLK_, _BAUD_)  (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
-
-  /* UART BRR = mantissa + overflow + fraction
-              = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-              
-#define USART_BRR(_PCLK_, _BAUD_)      (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
-                                        ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
-                                         (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U))
+                                          ((LENGTH) == USART_WORDLENGTH_9B))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
+                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
+                                         ((STOPBITS) == USART_STOPBITS_2))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+                                     ((PARITY) == USART_PARITY_EVEN) || \
+                                     ((PARITY) == USART_PARITY_ODD))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+#define USART_DIV(_PCLK_, _BAUD_)                  (((_PCLK_)*25)/(2*(_BAUD_)))
+#define USART_DIVMANT(_PCLK_, _BAUD_)              (USART_DIV((_PCLK_), (_BAUD_))/100)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_)              (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define USART_BRR(_PCLK_, _BAUD_)                  ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
 /**
   * @}
   */
@@ -630,12 +572,12 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
+  
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h

@@ -2,27 +2,45 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_wwdg.h
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_WWDG_H
-#define STM32F2xx_HAL_WWDG_H
+#ifndef __STM32F2xx_HAL_WWDG_H
+#define __STM32F2xx_HAL_WWDG_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -34,83 +52,68 @@ extern "C" {
 
 /** @addtogroup WWDG
   * @{
-  */
+  */ 
 
 /* Exported types ------------------------------------------------------------*/
-
 /** @defgroup WWDG_Exported_Types WWDG Exported Types
   * @{
   */
-
+   
 /**
-  * @brief  WWDG Init structure definition
+  * @brief  WWDG HAL State Structure definition
   */
-typedef struct
+typedef enum
 {
-  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
-                               This parameter can be a value of @ref WWDG_Prescaler */
-
-  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
-                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
-                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
-                               This parameter can be a value of @ref WWDG_EWI_Mode */
-
-} WWDG_InitTypeDef;
-
-/**
-  * @brief  WWDG handle Structure definition
-  */
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-typedef struct __WWDG_HandleTypeDef
-#else
+  HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
+  HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
+  HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */
+  HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
+  HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
+}HAL_WWDG_StateTypeDef;
+
+/** 
+  * @brief  WWDG Init structure definition  
+  */ 
 typedef struct
-#endif
 {
-  WWDG_TypeDef      *Instance;  /*!< Register base address */
-
-  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-  void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);     /*!< WWDG Early WakeUp Interrupt callback */
-
-  void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif
-} WWDG_HandleTypeDef;
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL WWDG common Callback ID enumeration definition
-  */
-typedef enum
+  uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
+                            This parameter can be a value of @ref WWDG_Prescaler */
+  
+  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
+                            This parameter must be a number lower than Max_Data = 0x80 */ 
+  
+  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
+                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+}WWDG_InitTypeDef;
+
+/** 
+  * @brief  WWDG handle Structure definition  
+  */ 
+typedef struct
 {
-  HAL_WWDG_EWI_CB_ID          = 0x00u,    /*!< WWDG EWI callback ID */
-  HAL_WWDG_MSPINIT_CB_ID      = 0x01u,    /*!< WWDG MspInit callback ID */
-} HAL_WWDG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL WWDG Callback pointer definition
-  */
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
-
-#endif
+  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
+  
+  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
+  
+  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
+  
+  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
+  
+}WWDG_HandleTypeDef;
 /**
   * @}
-  */
+  */ 
 
 /* Exported constants --------------------------------------------------------*/
-
 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
   * @{
   */
 
 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
   * @{
-  */
-#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+  */ 
+#define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
 /**
   * @}
   */
@@ -118,136 +121,130 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer t
 /** @defgroup WWDG_Flag_definition WWDG Flag definition
   * @brief WWDG Flag definition
   * @{
-  */
-#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+  */ 
+#define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
 /**
   * @}
   */
 
 /** @defgroup WWDG_Prescaler WWDG Prescaler
   * @{
-  */
-#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
+  */ 
+#define WWDG_PRESCALER_1                 ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
-  * @{
-  */
-#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
-#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
 /**
   * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
+  */ 
 
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
   * @{
   */
-#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
-                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
-                                             ((__MODE__) == WWDG_EWI_DISABLE))
-/**
-  * @}
-  */
-
 
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
-  * @{
+/** @brief Reset WWDG handle state
+  * @param  __HANDLE__: WWDG handle
+  * @retval None
   */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
 
 /**
-  * @brief  Enable the WWDG peripheral.
-  * @param  __HANDLE__  WWDG handle
+  * @brief  Enables the WWDG peripheral.
+  * @param  __HANDLE__: WWDG handle
   * @retval None
   */
-#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
 
 /**
-  * @brief  Enable the WWDG early wakeup interrupt.
+  * @brief  Disables the WWDG peripheral.
   * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @note   WARNING: This is a dummy macro for HAL code alignment.
+  *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
   * @retval None
   */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+#define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
 
 /**
-  * @brief  Check whether the selected WWDG interrupt has occurred or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the it to check.
+  * @brief  Gets the selected WWDG's it status.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__: specifies the it to check.
   *        This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
   * @retval The new state of WWDG_FLAG (SET or RESET).
   */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
 
-/** @brief  Clear the WWDG interrupt pending bits.
+/** @brief  Clear the WWDG's interrupt pending bits
   *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
 
 /**
-  * @brief  Check whether the specified WWDG flag is set or not.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to check.
+  * @brief  Enables the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__: specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+    
+/**
+  * @brief  Disables the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__: specifies the interrupt to disable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   WARNING: This is a dummy macro for HAL code alignment. 
+  *         Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
+    
+/**
+  * @brief  Gets the selected WWDG's flag status.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __FLAG__: specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   * @retval The new state of WWDG_FLAG (SET or RESET).
   */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
 /**
-  * @brief  Clear the WWDG's pending flags.
-  * @param  __HANDLE__  WWDG handle
-  * @param  __FLAG__  specifies the flag to clear.
+  * @brief  Clears the WWDG's pending flags.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __FLAG__: specifies the flag to clear.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   * @retval None
   */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
 
-/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
-  * @param  __HANDLE__  WWDG Handle.
-  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
-  *         This parameter can be one of the following values:
+/** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
+  * @param  __HANDLE__: WWDG Handle.
+  * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
+  *          This parameter can be one of the following values:
   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
   * @retval state of __INTERRUPT__ (TRUE or FALSE).
   */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
-
 /** @addtogroup WWDG_Exported_Functions
   * @{
   */
@@ -256,14 +253,11 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer t
   * @{
   */
 /* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif
-
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
 /**
   * @}
   */
@@ -272,9 +266,42 @@ HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL
   * @{
   */
 /* I/O operation functions ******************************************************/
-HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Constants WWDG Private Constants
+  * @{
+  */
+/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
+  * @brief WWDG registers bit address in the alias region
+  * @{
+  */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define WWDG_CFR_BASE   (uint32_t)(WWDG_BASE + 0x04)
+
 /**
   * @}
   */
@@ -283,14 +310,36 @@ void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
   * @}
   */
 
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+                                          ((__PRESCALER__) == WWDG_PRESCALER_8))
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup WWDG_Private_Functions WWDG Private Functions
+  * @{
+  */
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
 #ifdef __cplusplus
 }
 #endif

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h

@@ -2,510 +2,460 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_usb.h
   * @author  MCD Application Team
-  * @brief   Header file of USB Low Layer HAL module.
+  * @version V1.1.0
+  * @date    09-October-2015
+  * @brief   Header file of USB Core HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_USB_H
-#define STM32F2xx_LL_USB_H
+#ifndef __STM32F2xx_LL_USB_H
+#define __STM32F2xx_LL_USB_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @addtogroup STM32F2xx_HAL_Driver
+/** @addtogroup STM32F2xx_HAL
   * @{
   */
 
-/** @addtogroup USB_LL
+/** @addtogroup USB_Core
   * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  USB Mode definition
-  */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  */ 
 
-typedef enum
-{
-  USB_DEVICE_MODE  = 0,
-  USB_HOST_MODE    = 1,
-  USB_DRD_MODE     = 2
-} USB_OTG_ModeTypeDef;
+/* Exported types ------------------------------------------------------------*/ 
 
-/**
-  * @brief  URB States definition
-  */
-typedef enum
+/** 
+  * @brief  USB Mode definition  
+  */  
+typedef enum 
 {
+   USB_OTG_DEVICE_MODE  = 0,
+   USB_OTG_HOST_MODE    = 1,
+   USB_OTG_DRD_MODE     = 2
+   
+}USB_OTG_ModeTypeDef;
+
+/** 
+  * @brief  URB States definition  
+  */ 
+typedef enum {
   URB_IDLE = 0,
   URB_DONE,
   URB_NOTREADY,
   URB_NYET,
   URB_ERROR,
   URB_STALL
-} USB_OTG_URBStateTypeDef;
+    
+}USB_OTG_URBStateTypeDef;
 
-/**
-  * @brief  Host channel States  definition
-  */
-typedef enum
-{
+/** 
+  * @brief  Host channel States  definition  
+  */ 
+typedef enum {
   HC_IDLE = 0,
   HC_XFRC,
   HC_HALTED,
   HC_NAK,
   HC_NYET,
   HC_STALL,
-  HC_XACTERR,
-  HC_BBLERR,
+  HC_XACTERR,  
+  HC_BBLERR,   
   HC_DATATGLERR
-} USB_OTG_HCStateTypeDef;
+    
+}USB_OTG_HCStateTypeDef;
 
-/**
-  * @brief  USB OTG Initialization Structure definition
+/** 
+  * @brief  PCD Initialization Structure definition  
   */
 typedef struct
 {
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.
-                                         This parameter depends on the used USB core.
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t Host_channels;           /*!< Host Channels number.
-                                         This parameter Depends on the used USB core.
-                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
-  uint32_t speed;                   /*!< USB Core speed.
-                                         This parameter can be any value of @ref USB_Core_Speed_                */
-
-  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
-
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
-
-  uint32_t phy_itface;              /*!< Select the used PHY interface.
-                                         This parameter can be any value of @ref USB_Core_PHY_                  */
-
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
-
-  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
-
-  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
-
-  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
-
-  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
-
-  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
-} USB_OTG_CfgTypeDef;
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
+  
+  uint32_t Host_channels;        /*!< Host Channels number.
+                                      This parameter Depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
+
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref USB_Core_Speed_                */        
+                               
+  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
+
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
+                       
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
+                                
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
+                               
+  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
+                          
+  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
+
+  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
+  
+  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
+  
+}USB_OTG_CfgTypeDef;
 
 typedef struct
 {
-  uint8_t   num;                  /*!< Endpoint number
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-
-  uint8_t   is_in;                /*!< Endpoint direction
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint8_t   is_stall;             /*!< Endpoint stall condition
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint8_t   type;                 /*!< Endpoint type
-                                       This parameter can be any value of @ref USB_EP_Type_                     */
-
-  uint8_t   data_pid_start;       /*!< Initial data PID
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint8_t   even_odd_frame;       /*!< IFrame parity
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-
-  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-
-  uint32_t  maxpacket;            /*!< Endpoint Max packet size
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
-
-  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
-
-  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
-
-  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
-} USB_OTG_EPTypeDef;
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
+                                
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
+                                
+  uint8_t   data_pid_start; /*!< Initial data PID
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+                                
+  uint8_t   even_odd_frame; /*!< IFrame parity
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+                                
+  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+                                
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+                                
+  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+}USB_OTG_EPTypeDef;
 
 typedef struct
 {
-  uint8_t   dev_addr ;          /*!< USB device address.
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
-
-  uint8_t   ch_num;             /*!< Host channel number.
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_num;             /*!< Endpoint number.
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
-
-  uint8_t   ep_is_in;           /*!< Endpoint direction
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   speed;              /*!< USB Host speed.
-                                     This parameter can be any value of @ref USB_Core_Speed_                    */
-
-  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
-
-  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
-
-  uint8_t   ep_type;            /*!< Endpoint Type.
-                                     This parameter can be any value of @ref USB_EP_Type_                       */
-
-  uint16_t  max_packet;         /*!< Endpoint Max packet size.
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-
-  uint8_t   data_pid;           /*!< Initial data PID.
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
-
-  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
-
-  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
-
-  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-
-  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
-
-  uint32_t  ErrCnt;             /*!< Host channel error count.*/
-
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
-                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */
-} USB_OTG_HCTypeDef;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-
+  uint8_t   dev_addr ;     /*!< USB device address.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
+
+  uint8_t   ch_num;        /*!< Host channel number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_num;        /*!< Endpoint number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_is_in;      /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
+                                
+  uint8_t   speed;         /*!< USB Host speed.
+                                This parameter can be any value of @ref USB_Core_Speed_                    */
+                                
+  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  
+  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;       /*!< Endpoint Type.
+                                This parameter can be any value of @ref USB_EP_Type_                       */
+                                
+  uint16_t  max_packet;    /*!< Endpoint Max packet size.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+                                
+  uint8_t   data_pid;      /*!< Initial data PID.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
+  
+  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
+  
+  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
+  
+  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+  
+  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
+  
+  uint32_t  ErrCnt;        /*!< Host channel error count.*/
+  
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
+                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
+  
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
+                                             
+}USB_OTG_HCTypeDef;
+  
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup PCD_Exported_Constants PCD Exported Constants
   * @{
   */
 
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @defgroup USB_OTG_CORE VERSION ID
-  * @{
-  */
-#define USB_OTG_CORE_ID_300A          0x4F54300AU
-#define USB_OTG_CORE_ID_310A          0x4F54310AU
-/**
-  * @}
-  */
-
 /** @defgroup USB_Core_Mode_ USB Core Mode
   * @{
   */
-#define USB_OTG_MODE_DEVICE                    0U
-#define USB_OTG_MODE_HOST                      1U
-#define USB_OTG_MODE_DRD                       2U
+#define USB_OTG_MODE_DEVICE                    0
+#define USB_OTG_MODE_HOST                      1
+#define USB_OTG_MODE_DRD                       2
 /**
   * @}
   */
 
-/** @defgroup USB_LL Device Speed
+/** @defgroup USB_Core_Speed_   USB Core Speed
   * @{
-  */
-#define USBD_HS_SPEED               0U
-#define USBD_HSINFS_SPEED           1U
-#define USBH_HS_SPEED               0U
-#define USBD_FS_SPEED               2U
-#define USBH_FS_SPEED               1U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
-  * @{
-  */
-#define USB_OTG_SPEED_HIGH                     0U
-#define USB_OTG_SPEED_HIGH_IN_FULL             1U
-#define USB_OTG_SPEED_FULL                     3U
+  */  
+#define USB_OTG_SPEED_HIGH                     0
+#define USB_OTG_SPEED_HIGH_IN_FULL             1
+#define USB_OTG_SPEED_LOW                      2  
+#define USB_OTG_SPEED_FULL                     3
 /**
   * @}
   */
-
-/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+  
+/** @defgroup USB_Core_PHY_   USB Core PHY
   * @{
-  */
-#define USB_OTG_ULPI_PHY                       1U
-#define USB_OTG_EMBEDDED_PHY                   2U
+  */   
+#define USB_OTG_ULPI_PHY                       1
+#define USB_OTG_EMBEDDED_PHY                   2
 /**
   * @}
   */
-
-/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+  
+/** @defgroup USB_Core_MPS_   USB Core MPS
   * @{
   */
-#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE           9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE           5U
-#define USBD_DEFAULT_TRDT_VALUE      9U
-#endif /* USBD_HS_TRDT_VALUE */
+#define USB_OTG_HS_MAX_PACKET_SIZE           512
+#define USB_OTG_FS_MAX_PACKET_SIZE           64
+#define USB_OTG_MAX_EP0_SIZE                 64
 /**
   * @}
   */
 
-/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
   * @{
   */
-#define USB_OTG_HS_MAX_PACKET_SIZE             512U
-#define USB_OTG_FS_MAX_PACKET_SIZE             64U
-#define USB_OTG_MAX_EP0_SIZE                   64U
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
 /**
   * @}
   */
-
-/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+  
+/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
   * @{
-  */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+  */  
+#define DCFG_FRAME_INTERVAL_80                 0
+#define DCFG_FRAME_INTERVAL_85                 1
+#define DCFG_FRAME_INTERVAL_90                 2
+#define DCFG_FRAME_INTERVAL_95                 3
 /**
   * @}
   */
 
-/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+/** @defgroup USB_EP0_MPS_  USB EP0 MPS
   * @{
   */
-#define DCFG_FRAME_INTERVAL_80                 0U
-#define DCFG_FRAME_INTERVAL_85                 1U
-#define DCFG_FRAME_INTERVAL_90                 2U
-#define DCFG_FRAME_INTERVAL_95                 3U
+#define DEP0CTL_MPS_64                         0
+#define DEP0CTL_MPS_32                         1
+#define DEP0CTL_MPS_16                         2
+#define DEP0CTL_MPS_8                          3
 /**
   * @}
   */
 
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+/** @defgroup USB_EP_Speed_  USB EP Speed
   * @{
   */
-#define DEP0CTL_MPS_64                         0U
-#define DEP0CTL_MPS_32                         1U
-#define DEP0CTL_MPS_16                         2U
-#define DEP0CTL_MPS_8                          3U
+#define EP_SPEED_LOW                           0
+#define EP_SPEED_FULL                          1
+#define EP_SPEED_HIGH                          2
 /**
   * @}
   */
 
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+/** @defgroup USB_EP_Type_  USB EP Type
   * @{
   */
-#define EP_SPEED_LOW                           0U
-#define EP_SPEED_FULL                          1U
-#define EP_SPEED_HIGH                          2U
+#define EP_TYPE_CTRL                           0
+#define EP_TYPE_ISOC                           1
+#define EP_TYPE_BULK                           2
+#define EP_TYPE_INTR                           3
+#define EP_TYPE_MSK                            3
 /**
   * @}
   */
 
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+/** @defgroup USB_STS_Defines_   USB STS Defines
   * @{
   */
-#define EP_TYPE_CTRL                           0U
-#define EP_TYPE_ISOC                           1U
-#define EP_TYPE_BULK                           2U
-#define EP_TYPE_INTR                           3U
-#define EP_TYPE_MSK                            3U
+#define STS_GOUT_NAK                           1
+#define STS_DATA_UPDT                          2
+#define STS_XFER_COMP                          3
+#define STS_SETUP_COMP                         4
+#define STS_SETUP_UPDT                         6
 /**
   * @}
   */
 
-/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
   * @{
-  */
-#define STS_GOUT_NAK                           1U
-#define STS_DATA_UPDT                          2U
-#define STS_XFER_COMP                          3U
-#define STS_SETUP_COMP                         4U
-#define STS_SETUP_UPDT                         6U
+  */  
+#define HCFG_30_60_MHZ                         0
+#define HCFG_48_MHZ                            1
+#define HCFG_6_MHZ                             2
 /**
   * @}
   */
-
-/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+    
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
   * @{
-  */
-#define HCFG_30_60_MHZ                         0U
-#define HCFG_48_MHZ                            1U
-#define HCFG_6_MHZ                             2U
+  */    
+#define HPRT0_PRTSPD_HIGH_SPEED                0
+#define HPRT0_PRTSPD_FULL_SPEED                1
+#define HPRT0_PRTSPD_LOW_SPEED                 2
 /**
   * @}
-  */
-
-/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
-  * @{
-  */
-#define HPRT0_PRTSPD_HIGH_SPEED                0U
-#define HPRT0_PRTSPD_FULL_SPEED                1U
-#define HPRT0_PRTSPD_LOW_SPEED                 2U
+  */  
+   
+#define HCCHAR_CTRL                            0
+#define HCCHAR_ISOC                            1
+#define HCCHAR_BULK                            2
+#define HCCHAR_INTR                            3
+       
+#define HC_PID_DATA0                           0
+#define HC_PID_DATA2                           1
+#define HC_PID_DATA1                           2
+#define HC_PID_SETUP                           3
+
+#define GRXSTS_PKTSTS_IN                       2
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
+#define GRXSTS_PKTSTS_CH_HALTED                7
+    
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
 /**
   * @}
   */
-
-#define HCCHAR_CTRL                            0U
-#define HCCHAR_ISOC                            1U
-#define HCCHAR_BULK                            2U
-#define HCCHAR_INTR                            3U
-
-#define HC_PID_DATA0                           0U
-#define HC_PID_DATA2                           1U
-#define HC_PID_DATA1                           2U
-#define HC_PID_SETUP                           3U
-
-#define GRXSTS_PKTSTS_IN                       2U
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
-#define GRXSTS_PKTSTS_CH_HALTED                7U
-
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
-
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#define EP_ADDR_MSK                            0xFU
-/**
-  * @}
-  */
-
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
-  * @{
-  */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
 #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
+    
 #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-/**
-  * @}
-  */
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
-  * @{
-  */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
 uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
 uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
-                              uint8_t ch_num,
-                              uint8_t epnum,
-                              uint8_t dev_address,
-                              uint8_t speed,
-                              uint8_t ep_type,
-                              uint16_t mps);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
   */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
+  
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* STM32F2xx_LL_USB_H */
+#endif /* __STM32F2xx_LL_USB_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -13,7 +15,7 @@
     The common HAL driver contains a set of generic and common APIs that can be
     used by the PPP peripheral drivers and the user to start using the HAL. 
     [..]
-    The HAL contains two APIs' categories: 
+    The HAL contains two APIs categories: 
          (+) Common HAL APIs
          (+) Services HAL APIs
 
@@ -21,16 +23,32 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -50,18 +68,18 @@
   * @{
   */
 /**
-  * @brief STM32F2xx HAL Driver version number V1.2.3
-  */
-#define __STM32F2xx_HAL_VERSION_MAIN   0x01U /*!< [31:24] main version */
-#define __STM32F2xx_HAL_VERSION_SUB1   0x02U /*!< [23:16] sub1 version */
-#define __STM32F2xx_HAL_VERSION_SUB2   0x03U /*!< [15:8]  sub2 version */
-#define __STM32F2xx_HAL_VERSION_RC     0x00U /*!< [7:0]  release candidate */ 
-#define __STM32F2xx_HAL_VERSION         ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
-                                        |(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
-                                        |(__STM32F2xx_HAL_VERSION_SUB2 << 8U) \
+  * @brief STM32F2xx HAL Driver version number V1.1.0
+  */
+#define __STM32F2xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F2xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F2xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F2xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F2xx_HAL_VERSION         ((__STM32F2xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32F2xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32F2xx_HAL_VERSION_SUB2 << 8 )\
                                         |(__STM32F2xx_HAL_VERSION_RC))
                                         
-#define IDCODE_DEVID_MASK    0x00000FFFU
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
 
 /* ------------ RCC registers bit address in the alias region ----------- */
 #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
@@ -69,25 +87,23 @@
 /* Alias word address of UFB_MODE bit */ 
 #define MEMRMP_OFFSET             SYSCFG_OFFSET 
 #define UFB_MODE_BIT_NUMBER       POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
-#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
+#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4)) 
 
 /* ---  CMPCR Register ---*/ 
 /* Alias word address of CMP_PD bit */ 
-#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
 #define CMP_PD_BIT_NUMBER         POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
-#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
+#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
 /**
   * @}
   */
 
 /* Private macro -------------------------------------------------------------*/
-/* Exported variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
   * @{
   */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+static __IO uint32_t uwTick;
 /**
   * @}
   */
@@ -151,15 +167,15 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
 HAL_StatusTypeDef HAL_Init(void)
 {
   /* Configure Flash prefetch, Instruction cache, Data cache */ 
-#if (INSTRUCTION_CACHE_ENABLE != 0U)
+#if (INSTRUCTION_CACHE_ENABLE != 0)
    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 #endif /* INSTRUCTION_CACHE_ENABLE */
 
-#if (DATA_CACHE_ENABLE != 0U)
+#if (DATA_CACHE_ENABLE != 0)
    __HAL_FLASH_DATA_CACHE_ENABLE();
 #endif /* DATA_CACHE_ENABLE */
 
-#if (PREFETCH_ENABLE != 0U)
+#if (PREFETCH_ENABLE != 0)
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 #endif /* PREFETCH_ENABLE */
 
@@ -241,27 +257,16 @@ __weak void HAL_MspDeInit(void)
   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *       The function is declared as __weak  to be overwritten  in case of other
   *       implementation  in user file.
-  * @param  TickPriority Tick interrupt priority.
+  * @param TickPriority: Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
-  /* Configure the SysTick to have interrupt in 1ms time basis*/
-  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
-  {
-    return HAL_ERROR;
-  }
+  /*Configure the SysTick to have interrupt in 1ms time basis*/
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-  /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-  {
-    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
-    uwTickPrio = TickPriority;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
+  /*Configure the SysTick IRQ priority */
+  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
 
   /* Return function status */
   return HAL_OK;
@@ -305,7 +310,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
   */
 __weak void HAL_IncTick(void)
 {
-  uwTick += uwTickFreq;
+  uwTick++;
 }
 
 /**
@@ -320,68 +325,21 @@ __weak uint32_t HAL_GetTick(void)
 }
 
 /**
-  * @brief This function returns a tick priority.
-  * @retval tick priority
-  */
-uint32_t HAL_GetTickPrio(void)
-{
-  return uwTickPrio;
-}
-
-/**
-  * @brief Set new tick Freq.
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
-  HAL_StatusTypeDef status  = HAL_OK;
-  assert_param(IS_TICKFREQ(Freq));
-
-  if (uwTickFreq != Freq)
-  {
-    /* Apply the new tick Freq  */
-    status = HAL_InitTick(uwTickPrio);
-    if (status == HAL_OK)
-    {
-      uwTickFreq = Freq;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief return tick frequency.
-  * @retval tick period in Hz
-  */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
-  return uwTickFreq;
-}
-
-/**
-  * @brief This function provides minimum delay (in milliseconds) based 
+  * @brief This function provides accurate delay (in milliseconds) based 
   *        on variable incremented.
   * @note In the default implementation , SysTick timer is the source of time base.
   *       It is used to generate interrupts at regular time intervals where uwTick
   *       is incremented.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
-  * @param  Delay specifies the delay time length, in milliseconds.
+  * @param Delay: specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(__IO uint32_t Delay)
 {
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t wait = Delay;
-
-  /* Add a freq to guarantee minimum wait */
-  if (wait < HAL_MAX_DELAY)
-  {
-    wait += (uint32_t)(uwTickFreq);
-  }
-
-  while ((HAL_GetTick() - tickstart) < wait)
+  uint32_t tickstart = 0;
+  tickstart = HAL_GetTick();
+  while((HAL_GetTick() - tickstart) < Delay)
   {
   }
 }
@@ -433,7 +391,7 @@ uint32_t HAL_GetHalVersion(void)
   */
 uint32_t HAL_GetREVID(void)
 {
-   return((DBGMCU->IDCODE) >> 16U);
+   return((DBGMCU->IDCODE) >> 16);
 }
 
 /**
@@ -521,33 +479,6 @@ void HAL_DisableCompensationCell(void)
   *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
 }
 
-/**
-  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw0(void)
-{
-  return (READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
-  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw1(void)
-{
-  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
-}
-
-/**
-  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw2(void)
-{
-  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
 /**
   * @}
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
@@ -157,93 +159,37 @@
   (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA using function HAL_DMA_DeInit().
         (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   
-                      *** Callback registration ***
-  ==============================================================================
-    [..]
-
-     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
-     allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_ADC_RegisterCallback()
-     to register an interrupt callback.
-    [..]
-
-     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
-       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
-       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
-       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
-       (+) EndOfSamplingCallback          : ADC end of sampling callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     This function takes as parameters the HAL peripheral handle, the Callback ID
-     and a pointer to the user callback function.
-    [..]
-
-     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
-     weak function.
-    [..]
-
-     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
-     and the Callback ID.
-     This function allows to reset following callbacks:
-       (+) ConvCpltCallback               : ADC conversion complete callback
-       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
-       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
-       (+) ErrorCallback                  : ADC error callback
-       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
-       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
-       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
-       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
-       (+) EndOfSamplingCallback          : ADC end of sampling callback
-       (+) MspInitCallback                : ADC Msp Init callback
-       (+) MspDeInitCallback              : ADC Msp DeInit callback
-     [..]
-
-     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
-     all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
-     Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
-     these callbacks are null (not registered beforehand).
-    [..]
-
-     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
-     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-     [..]
-
-     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
-     Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
-     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-    [..]
-
-     Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
-     or @ref HAL_ADC_Init() function.
-     [..]
-
-     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
-     not defined, the callback registration feature is not available and all callbacks
-     are set to the corresponding weak functions.
 
     @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -305,7 +251,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
   *         External trigger source and edge, DMA continuous request after the  
   *         last transfer and End of conversion selection).
   *             
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval HAL status
   */
@@ -339,30 +285,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   
   if(hadc->State == HAL_ADC_STATE_RESET)
   {
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    /* Init the ADC Callback settings */
-    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
-    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
-    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
-    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
-    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
-    if (hadc->MspInitCallback == NULL)
-    {
-      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
-    }
-
-    /* Init the low level hardware */
-    hadc->MspInitCallback(hadc);
-#else
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
     /* Initialize ADC error code */
     ADC_CLEAR_ERRORCODE(hadc);
     
     /* Allocate lock resource and initialize it */
     hadc->Lock = HAL_UNLOCKED;
+    
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
   }
   
   /* Configuration of ADC parameters if previous preliminary actions are      */ 
@@ -399,7 +329,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval HAL status
   */
@@ -427,18 +357,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   /* correctly completed.                                                     */
   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  if (hadc->MspDeInitCallback == NULL)
-  {
-    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
-  }
-
-  /* DeInit the low level hardware: RCC clock, NVIC */
-  hadc->MspDeInitCallback(hadc);
-#else
-  /* DeInit the low level hardware: RCC clock, NVIC */
-  HAL_ADC_MspDeInit(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
     
     /* Set ADC error code to none */
     ADC_CLEAR_ERRORCODE(hadc);
@@ -454,218 +374,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   return tmp_hal_status;
 }
 
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User ADC Callback
-  *         To be used instead of the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = pCallback;
-        break;
-
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = pCallback;
-        break;
-
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = pCallback;
-        break;
-
-      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
-        hadc->InjectedConvCpltCallback = pCallback;
-        break;
-
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = pCallback;
-        break;
-
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status = HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Unregister a ADC Callback
-  *         ADC callback is redirected to the weak predefined callback
-  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
-  *                the configuration information for the specified ADC.
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
-  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
-  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
-  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
-  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
-  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
-  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
-  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
-        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
-        break;
-
-      case HAL_ADC_CONVERSION_HALF_CB_ID :
-        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
-        break;
-
-      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
-        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
-        break;
-
-      case HAL_ADC_ERROR_CB_ID :
-        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
-        break;
-
-      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
-        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
-        break;
-
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
-        break;
-
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_ADC_STATE_RESET == hadc->State)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ADC_MSPINIT_CB_ID :
-        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
-        break;
-
-      case HAL_ADC_MSPDEINIT_CB_ID :
-        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
-        break;
-
-      default :
-        /* Update the error code */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
 /**
   * @brief  Initializes the ADC MSP.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspInit could be implemented in the user file
    */ 
@@ -673,14 +389,12 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  DeInitializes the ADC MSP.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspDeInit could be implemented in the user file
    */ 
@@ -712,13 +426,13 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables ADC and starts conversion of the regular channels.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0U;
+  __IO uint32_t counter = 0;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -737,8 +451,8 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -780,7 +494,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
     
     /* Check if Multimode enabled */
     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@@ -812,7 +526,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   * 
   * @note   Caution: This function will stop also injected channels.  
   *
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   *
   * @retval HAL status.
@@ -855,14 +569,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
   *         In this case, DMA resets the flag EOC and polling cannot be
   *         performed on each conversion. Nevertheless, polling can still 
   *         be performed on the complete sequence.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  Timeout Timeout value in millisecond.  
+  * @param  Timeout: Timeout value in millisecond.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
+  uint32_t tickstart = 0;
  
   /* Verification that ADC configuration is compliant with polling for      */
   /* each conversion:                                                       */
@@ -891,7 +605,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
     /* Check if timeout is disabled (set to infinite wait) */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update ADC state machine to timeout */
         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -936,18 +650,18 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
 
 /**
   * @brief  Poll for conversion event
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  EventType the ADC event type.
+  * @param  EventType: the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
   *            @arg ADC_OVR_EVENT: ADC Overrun event.
-  * @param  Timeout Timeout value in millisecond.   
+  * @param  Timeout: Timeout value in millisecond.   
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
+  uint32_t tickstart = 0;
   
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -962,7 +676,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update ADC state machine to timeout */
         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1003,13 +717,13 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
 
 /**
   * @brief  Enables the interrupt and starts ADC conversion of regular channels.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0U;
+  __IO uint32_t counter = 0;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -1028,8 +742,8 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -1071,7 +785,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
     
     /* Enable end of conversion interrupt for regular group */
     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
@@ -1106,7 +820,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   * 
   * @note   Caution: This function will stop also injected channels.  
   *
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status.
   */
@@ -1143,13 +857,13 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Handles ADC interrupt request  
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 {
-  uint32_t tmp1 = 0U, tmp2 = 0U;
+  uint32_t tmp1 = 0, tmp2 = 0;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -1194,12 +908,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
       }
     }
     
-    /* Conversion complete callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvCpltCallback(hadc);
-#else
+    /* Conversion complete callback */ 
     HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
     
     /* Clear regular group conversion flag */
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
@@ -1241,11 +951,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
     }
 
     /* Conversion complete callback */ 
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->InjectedConvCpltCallback(hadc);
-#else
-      HAL_ADCEx_InjectedConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
     
     /* Clear injected group conversion flag */
     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
@@ -1261,12 +967,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
       /* Set ADC state */
       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
       
-      /* Level out of window callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->LevelOutOfWindowCallback(hadc);
-#else
+      /* Level out of window callback */ 
       HAL_ADC_LevelOutOfWindowCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
       
       /* Clear the ADC analog watchdog flag */
       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
@@ -1289,11 +991,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
     
     /* Error callback */ 
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ErrorCallback(hadc);
-#else
-      HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    HAL_ADC_ErrorCallback(hadc);
     
     /* Clear the Overrun flag */
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
@@ -1302,15 +1000,15 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  pData The destination Buffer address.
-  * @param  Length The length of data to be transferred from ADC peripheral to memory.
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
 {
-  __IO uint32_t counter = 0U;
+  __IO uint32_t counter = 0;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -1329,8 +1027,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -1385,7 +1083,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
 
     /* Enable ADC overrun interrupt */
     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
@@ -1423,7 +1121,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
 
 /**
   * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
@@ -1469,7 +1167,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Gets the converted value from data register of regular channel.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval Converted value
   */
@@ -1481,14 +1179,12 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Regular conversion complete callback in non blocking mode 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvCpltCallback could be implemented in the user file
    */
@@ -1496,14 +1192,12 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Regular conversion half DMA transfer callback in non blocking mode 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
    */
@@ -1511,14 +1205,12 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Analog watchdog callback in non blocking mode 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
    */
@@ -1526,20 +1218,12 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Error ADC callback.
-  * @note   In case of error due to overrun when using ADC with DMA transfer 
-  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
-  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
-  *         - If needed, restart a new ADC conversion using function
-  *           "HAL_ADC_Start_DMA()"
-  *           (this function is also clearing overrun flag)
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ErrorCallback could be implemented in the user file
    */
@@ -1569,14 +1253,14 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
   /**
   * @brief  Configures for the selected ADC regular channel its corresponding
   *         rank in the sequencer and its sample time.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  sConfig ADC configuration structure. 
+  * @param  sConfig: ADC configuration structure. 
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
 {
-  __IO uint32_t counter = 0U;
+  __IO uint32_t counter = 0;
   
   /* Check the parameters */
   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
@@ -1605,7 +1289,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
   }
   
   /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7U)
+  if (sConfig->Rank < 7)
   {
     /* Clear the old SQx bits for the selected rank */
     hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
@@ -1614,7 +1298,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
     hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
   }
   /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13U)
+  else if (sConfig->Rank < 13)
   {
     /* Clear the old SQx bits for the selected rank */
     hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
@@ -1649,8 +1333,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
     {
       /* Delay for temperature sensor stabilization time */
       /* Compute number of CPU cycles to wait for */
-      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
-      while(counter != 0U)
+      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+      while(counter != 0)
       {
         counter--;
       }
@@ -1666,24 +1350,16 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
 
 /**
   * @brief  Configures the analog watchdog.
-  * @note Analog watchdog thresholds can be modified while ADC conversion
-  * is on going.
-  * In this case, some constraints must be taken into account:
-  * The programmed threshold values are effective from the next
-  * ADC EOC (end of unitary conversion).
-  * Considering that registers write delay may happen due to
-  * bus activity, this might cause an uncertainty on the
-  * effective timing of the new programmed threshold values.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure 
+  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure 
   *         that contains the configuration information of ADC analog watchdog.
   * @retval HAL status	  
   */
 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
 {
 #ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0U;
+  uint32_t tmp = 0;
 #endif /* USE_FULL_ASSERT  */  
   
   /* Check the parameters */
@@ -1758,7 +1434,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   
 /**
   * @brief  return the ADC state
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL state
   */
@@ -1770,7 +1446,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Return the ADC error code
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval ADC Error Code
   */
@@ -1790,7 +1466,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
 /**
   * @brief  Initializes the ADCx peripheral according to the specified parameters 
   *         in the ADC_InitStruct without initializing the ADC MSP.       
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
@@ -1871,7 +1547,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1913,52 +1589,31 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
     }
     
     /* Conversion complete callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-    hadc->ConvCpltCallback(hadc);
-#else
     HAL_ADC_ConvCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
   }
-  else /* DMA and-or internal error occurred */
+  else
   {
-    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
-    {
-      /* Call HAL ADC Error Callback function */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-      hadc->ErrorCallback(hadc);
-#else
-      HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-    }
-	else
-	{
-      /* Call DMA error callback */
-      hadc->DMA_Handle->XferErrorCallback(hdma);
-    }
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
   }
 }
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
 {
   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Half conversion callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  hadc->ConvHalfCpltCallback(hadc);
-#else
-  HAL_ADC_ConvHalfCpltCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  /* Conversion complete callback */
+  HAL_ADC_ConvHalfCpltCallback(hadc); 
 }
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1968,12 +1623,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
   hadc->State= HAL_ADC_STATE_ERROR_DMA;
   /* Set ADC error code to DMA error */
   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-   /* Error callback */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  hadc->ErrorCallback(hadc);
-#else
-  HAL_ADC_ErrorCallback(hadc);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  HAL_ADC_ErrorCallback(hadc); 
 }
 
 /**

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc_ex.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions
@@ -84,16 +86,32 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -152,14 +170,14 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
 
 /**
   * @brief  Enables the selected ADC software start conversion of the injected channels.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0U;
-  uint32_t tmp1 = 0U, tmp2 = 0U;
+  __IO uint32_t counter = 0;
+  uint32_t tmp1 = 0, tmp2 = 0;
   
   /* Process locked */
   __HAL_LOCK(hadc);
@@ -175,8 +193,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -240,15 +258,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables the interrupt and starts ADC conversion of injected channels.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   *
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0U;
-  uint32_t tmp1 = 0U, tmp2 = 0U;
+  __IO uint32_t counter = 0;
+  uint32_t tmp1 = 0, tmp2 = 0;
   
   /* Process locked */
   __HAL_LOCK(hadc);
@@ -264,8 +282,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -301,7 +319,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
     
     /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
     
     /* Check if Multimode enabled */
     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@@ -339,7 +357,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
   * @note   If injected group mode auto-injection is enabled,
   *         function HAL_ADC_Stop must be used.
   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc ADC handle
+  * @param  hadc: ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -391,14 +409,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Poll for injected conversion complete
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  Timeout Timeout value in millisecond.  
+  * @param  Timeout: Timeout value in millisecond.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
 {
-  uint32_t tickstart = 0U;
+  uint32_t tickstart = 0;
 
   /* Get tick */ 
   tickstart = HAL_GetTick();
@@ -409,7 +427,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         hadc->State= HAL_ADC_STATE_TIMEOUT;
         /* Process unlocked */
@@ -460,7 +478,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
   *         injected and regular groups, and disable the ADC.
   * @note   If injected group mode auto-injection is enabled,
   *         function HAL_ADC_Stop must be used.
-  * @param  hadc ADC handle
+  * @param  hadc: ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -490,7 +508,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
     {
       /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
       
       /* Set ADC state */
       ADC_STATE_CLR_SET(hadc->State,
@@ -515,9 +533,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Gets the converted value from data register of injected channel.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  InjectedRank the ADC injected rank.
+  * @param  InjectedRank: the ADC injected rank.
   *          This parameter can be one of the following values:
   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -527,7 +545,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
   */
 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
 {
-  __IO uint32_t tmp = 0U;
+  __IO uint32_t tmp = 0;
   
   /* Check the parameters */
   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
@@ -570,15 +588,15 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   * 
   * @note   Caution: This function must be used only with the ADC master.  
   *
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
-  * @param  Length  The length of data to be transferred from ADC peripheral to memory.  
+  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
+  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
 {
-  __IO uint32_t counter = 0U;
+  __IO uint32_t counter = 0;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -597,8 +615,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     
     /* Delay for temperature sensor stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
-    while(counter != 0U)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+    while(counter != 0)
     {
       counter--;
     }
@@ -685,7 +703,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
 
 /**
   * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
@@ -732,28 +750,24 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
   *         data in the selected multi mode.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval The converted data value.
   */
 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* Return the multi mode conversion value */
   return ADC->CDR;
 }
 
 /**
   * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
    */
@@ -762,16 +776,16 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Configures for the selected ADC injected channel its corresponding
   *         rank in the sequencer and its sample time.
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  sConfigInjected ADC configuration structure for injected channel. 
+  * @param  sConfigInjected: ADC configuration structure for injected channel. 
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
 {
   
 #ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0U;
+  uint32_t tmp = 0;
 #endif /* USE_FULL_ASSERT  */
   
   /* Check the parameters */
@@ -788,7 +802,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
 #endif /* USE_FULL_ASSERT  */
 
-  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
   {
     assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
   }
@@ -917,9 +931,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
 
 /**
   * @brief  Configures the ADC multi-mode 
-  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
-  *              the configuration information for the specified ADC.  
-  * @param  multimode pointer to an ADC_MultiModeTypeDef structure that contains 
+  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
+  *                     the configuration information for the specified ADC.  
+  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains 
   *                     the configuration information for  multimode.
   * @retval HAL status
   */
@@ -956,9 +970,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   * @}
   */
 
-/**
+  /**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1011,7 +1025,7 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1024,7 +1038,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cortex.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
@@ -24,7 +26,7 @@
         function according to the following table.
     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programming manual for details in how to configure priority. 
+    (#) please refer to programing manual for details in how to configure priority. 
       
      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
          The pending IRQ priority will be managed only by the sub priority.
@@ -43,7 +45,7 @@
    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
        is a CMSIS function that:
         (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
         (++) Resets the SysTick Counter register.
         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
         (++) Enables the SysTick Interrupt.
@@ -68,13 +70,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -124,7 +142,7 @@
 /**
   * @brief  Sets the priority grouping field (preemption priority and subpriority)
   *         using the required unlock sequence.
-  * @param  PriorityGroup The priority grouping bits length. 
+  * @param  PriorityGroup: The priority grouping bits length. 
   *         This parameter can be one of the following values:
   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
   *                                    4 bits for subpriority
@@ -151,20 +169,20 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 
 /**
   * @brief  Sets the priority of an interrupt.
-  * @param  IRQn External interrupt number.
+  * @param  IRQn: External interrupt number.
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
-  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  * @param  PreemptPriority: The preemption priority for the IRQn channel.
   *         This parameter can be a value between 0 and 15
   *         A lower priority value indicates a higher priority 
-  * @param  SubPriority the subpriority level for the IRQ channel.
+  * @param  SubPriority: the subpriority level for the IRQ channel.
   *         This parameter can be a value between 0 and 15
   *         A lower priority value indicates a higher priority.          
   * @retval None
   */
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 { 
-  uint32_t prioritygroup = 0x00U;
+  uint32_t prioritygroup = 0x00;
   
   /* Check the parameters */
   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
@@ -222,7 +240,7 @@ void HAL_NVIC_SystemReset(void)
 /**
   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
   *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
@@ -250,50 +268,10 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
   * @{
   */
 
-#if (__MPU_PRESENT == 1U)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU and clear the control register*/
-  MPU->CTRL = 0U;
-}
-
-/**
-  * @brief  Enable the MPU.
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged access to the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Ensure MPU setting take effects */
-  __DSB();
-  __ISB();
-}
-
+#if (__MPU_PRESENT == 1)
 /**
   * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
   *                the initialization and configuration information.
   * @retval None
   */
@@ -331,8 +309,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
   }
   else
   {
-    MPU->RBAR = 0x00U;
-    MPU->RASR = 0x00U;
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
   }
 }
 #endif /* __MPU_PRESENT */
@@ -349,10 +327,10 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
 
 /**
   * @brief  Gets the priority of an interrupt.
-  * @param  IRQn External interrupt number.
+  * @param  IRQn: External interrupt number.
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
-  * @param   PriorityGroup the priority grouping bits length.
+  * @param   PriorityGroup: the priority grouping bits length.
   *         This parameter can be one of the following values:
   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
   *                                      4 bits for subpriority
@@ -364,8 +342,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
   *                                      1 bits for subpriority
   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
   *                                      0 bits for subpriority
-  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
   * @retval None
   */
 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
@@ -445,7 +423,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
 
 /**
   * @brief  Configures the SysTick clock source.
-  * @param  CLKSource specifies the SysTick clock source.
+  * @param  CLKSource: specifies the SysTick clock source.
   *          This parameter can be one of the following values:
   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c

@@ -2,42 +2,59 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_crc.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   CRC HAL module driver.
-  *          This file provides firmware functions to manage the following
+  *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
   *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
+  *           + Peripheral Control functions 
   *           + Peripheral State functions
   *
   @verbatim
- ===============================================================================
+  ==============================================================================
                      ##### How to use this driver #####
- ===============================================================================
+  ==============================================================================
     [..]
-         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-         (+) Initialize CRC calculator
-             (++) specify generating polynomial (peripheral default or non-default one)
-             (++) specify initialization value (peripheral default or non-default one)
-             (++) specify input data format
-             (++) specify input or output data inversion mode if any
-         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
-             input data buffer starting with the previously computed CRC as
-             initialization value
-         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
-             input data buffer starting with the defined initialization value
-             (default or non-default) to initiate CRC calculation
+      The CRC HAL driver can be used as follows:
+
+      (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+
+      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of 
+          a 32-bit data buffer using combination of the previous CRC value
+          and the new one.
+
+      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of 
+          a new 32-bit data buffer. This function resets the CRC computation  
+          unit before starting the computation to avoid getting wrong CRC values.
 
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -49,8 +66,7 @@
   * @{
   */
 
-/** @defgroup CRC CRC
-  * @brief CRC HAL module driver.
+/** @addtogroup CRC 
   * @{
   */
 
@@ -61,41 +77,42 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-
+/* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
+/** @addtogroup CRC_Exported_Functions
   * @{
   */
 
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions.
+/** @addtogroup CRC_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions 
  *
-@verbatim
- ===============================================================================
+@verbatim     
+  ==============================================================================
             ##### Initialization and de-initialization functions #####
- ===============================================================================
+  ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the CRC according to the specified parameters
+      (+) Initialize the CRC according to the specified parameters 
           in the CRC_InitTypeDef and create the associated handle
       (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP (MCU Specific Package)
-      (+) DeInitialize the CRC MSP
-
+      (+) Initialize the CRC MSP
+      (+) DeInitialize CRC MSP 
+ 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initialize the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and create the associated handle.
-  * @param  hcrc CRC handle
+  * @brief  Initializes the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and creates the associated handle.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
 {
   /* Check the CRC handle allocation */
-  if (hcrc == NULL)
+  if(hcrc == NULL)
   {
     return HAL_ERROR;
   }
@@ -103,30 +120,34 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
   /* Check the parameters */
   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
 
-  if (hcrc->State == HAL_CRC_STATE_RESET)
+  if(hcrc->State == HAL_CRC_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hcrc->Lock = HAL_UNLOCKED;
     /* Init the low level hardware */
     HAL_CRC_MspInit(hcrc);
   }
-
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+   
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
-
+  
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitialize the CRC peripheral.
-  * @param  hcrc CRC handle
+  * @brief  DeInitializes the CRC peripheral.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 {
   /* Check the CRC handle allocation */
-  if (hcrc == NULL)
+  if(hcrc == NULL)
   {
     return HAL_ERROR;
   }
@@ -134,28 +155,16 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
   /* Check the parameters */
   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
 
-  /* Check the CRC peripheral state */
-  if (hcrc->State == HAL_CRC_STATE_BUSY)
-  {
-    return HAL_BUSY;
-  }
-
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
-  /* Reset CRC calculation unit */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  /* Reset IDR register content */
-  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
-
   /* DeInit the low level hardware */
   HAL_CRC_MspDeInit(hcrc);
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_RESET;
 
-  /* Process unlocked */
+  /* Release Lock */
   __HAL_UNLOCK(hcrc);
 
   /* Return function status */
@@ -164,52 +173,45 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 
 /**
   * @brief  Initializes the CRC MSP.
-  * @param  hcrc CRC handle
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
   * @retval None
   */
 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspInit can be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DeInitialize the CRC MSP.
-  * @param  hcrc CRC handle
+  * @brief  DeInitializes the CRC MSP.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
   * @retval None
   */
 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcrc);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_CRC_MspDeInit can be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- *  @brief    management functions.
+/** @addtogroup CRC_Exported_Functions_Group2
+ *  @brief   Peripheral Control functions 
  *
-@verbatim
- ===============================================================================
+@verbatim  
+  ==============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================
+  ==============================================================================  
     [..]  This section provides functions allowing to:
-      (+) compute the 32-bit CRC value of a 32-bit data buffer
+      (+) Compute the 32-bit CRC value of 32-bit data buffer,
           using combination of the previous CRC value and the new one.
-
-       [..]  or
-
-      (+) compute the 32-bit CRC value of a 32-bit data buffer
+      (+) Compute the 32-bit CRC value of 32-bit data buffer,
           independently of the previous CRC value.
 
 @endverbatim
@@ -217,95 +219,106 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
   */
 
 /**
-  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
-  *         starting with the previously computed CRC as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer.
-  * @param  BufferLength input data buffer length (number of uint32_t words).
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
+  *         of the previous CRC value and the new one.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
   */
 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
 {
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+  uint32_t index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hcrc);
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
   /* Enter Data to the CRC calculator */
-  for (index = 0U; index < BufferLength; index++)
+  for(index = 0; index < BufferLength; index++)
   {
     hcrc->Instance->DR = pBuffer[index];
   }
-  temp = hcrc->Instance->DR;
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
 
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcrc);
+
   /* Return the CRC computed value */
-  return temp;
+  return hcrc->Instance->DR;
 }
 
 /**
-  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
-  *         starting with hcrc->Instance->INIT as initialization value.
-  * @param  hcrc CRC handle
-  * @param  pBuffer pointer to the input data buffer.
-  * @param  BufferLength input data buffer length (number of uint32_t words).
-  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
+  *         of the previous CRC value.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @param  pBuffer: Pointer to the buffer containing the data to be computed
+  * @param  BufferLength: Length of the buffer to be computed
+  * @retval 32-bit CRC
   */
 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
 {
-  uint32_t index;      /* CRC input data buffer index */
-  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+  uint32_t index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hcrc); 
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
-  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
-  *  written in hcrc->Instance->DR) */
+  /* Reset CRC Calculation Unit */
   __HAL_CRC_DR_RESET(hcrc);
 
-  /* Enter 32-bit input data to the CRC calculator */
-  for (index = 0U; index < BufferLength; index++)
+  /* Enter Data to the CRC calculator */
+  for(index = 0; index < BufferLength; index++)
   {
     hcrc->Instance->DR = pBuffer[index];
   }
-  temp = hcrc->Instance->DR;
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
 
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcrc);
+
   /* Return the CRC computed value */
-  return temp;
+  return hcrc->Instance->DR;
 }
 
 /**
   * @}
-  */
+  */ 
 
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- *  @brief    Peripheral State functions.
+  
+/** @addtogroup CRC_Exported_Functions_Group3
+ *  @brief   Peripheral State functions 
  *
-@verbatim
- ===============================================================================
+@verbatim   
+  ==============================================================================
                       ##### Peripheral State functions #####
- ===============================================================================
+  ==============================================================================  
     [..]
-    This subsection permits to get in run-time the status of the peripheral.
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Return the CRC handle state.
-  * @param  hcrc CRC handle
+  * @brief  Returns the CRC state.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
   * @retval HAL state
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
 {
-  /* Return CRC handle state */
   return hcrc->State;
 }
 
@@ -317,7 +330,6 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
   * @}
   */
 
-
 #endif /* HAL_CRC_MODULE_ENABLED */
 /**
   * @}

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac_ex.c

@@ -2,42 +2,55 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dac_ex.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   DAC HAL module driver.
-  *          This file provides firmware functions to manage the extended
-  *          functionalities of the DAC peripheral.
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of DAC extension peripheral:
+  *           + Extended features functions
+  *     
   *
-  *
-  @verbatim
+  @verbatim      
   ==============================================================================
                       ##### How to use this driver #####
   ==============================================================================
-    [..]
-     *** Dual mode IO operation ***
-     ==============================
-      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+    [..]          
+      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
-          Channel 1 and Channel 2.
-
-     *** Signal generation operation ***
-     ===================================
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
+   
+ @endverbatim    
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 
 /* Includes ------------------------------------------------------------------*/
@@ -47,33 +60,31 @@
   * @{
   */
 
-#ifdef HAL_DAC_MODULE_ENABLED
-
-#if defined(DAC)
-
 /** @defgroup DACEx DACEx
-  * @brief DAC Extended HAL module driver
+  * @brief DAC driver modules
   * @{
-  */
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+/** @defgroup DACEx_Exported_Functions DAC Exported Functions
   * @{
   */
 
-/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
-  *  @brief    Extended IO operation functions
-  *
-@verbatim
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+ *  @brief    Extended features functions 
+ *
+@verbatim   
   ==============================================================================
                  ##### Extended features functions #####
-  ==============================================================================
+  ==============================================================================  
     [..]  This section provides functions allowing to:
       (+) Start conversion.
       (+) Stop conversion.
@@ -81,20 +92,37 @@
       (+) Stop conversion and disable DMA transfer.
       (+) Get result of conversion.
       (+) Get result of dual mode conversion.
-
+                     
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+  uint32_t tmp = 0;
+  
+  tmp |= hdac->Instance->DOR1;
+  
+  tmp |= hdac->Instance->DOR2 << 16;
+  
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
+  * @param  Channel: The selected DAC channel. 
   *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude Select max triangle amplitude.
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Select max triangle amplitude. 
   *          This parameter can be one of the following values:
   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -107,312 +135,238 @@
   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
+  
   /* Process locked */
   __HAL_LOCK(hdac);
-
+  
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the triangle wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
-
+  
+  /* Enable the selected wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+  
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-
+  
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-
+  
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Enable or disable the selected DAC channel wave generation.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC. 
+  * @param  Channel: The selected DAC channel. 
   *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
+  *          This parameter can be one of the following values: 
   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
-{
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
+  
   /* Process locked */
   __HAL_LOCK(hdac);
-
+  
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* Enable the noise wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
-
+  
+  /* Enable the selected wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+  
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-
+  
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-
+  
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *               the configuration information for the specified DAC.
-  * @param  Alignment Specifies the data alignment for dual channel DAC.
+  * @param  Alignment: Specifies the data alignment for dual channel DAC.
   *          This parameter can be one of the following values:
   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
-  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
+  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
   * @note   In dual mode, a unique register access is required to write in both
   *          DAC channels at the same time.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
-  uint32_t data;
-  uint32_t tmp;
-
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{  
+  uint32_t data = 0, tmp = 0;
+  
   /* Check the parameters */
   assert_param(IS_DAC_ALIGN(Alignment));
   assert_param(IS_DAC_DATA(Data1));
   assert_param(IS_DAC_DATA(Data2));
-
+  
   /* Calculate and set dual DAC data holding register value */
   if (Alignment == DAC_ALIGN_8B_R)
   {
-    data = ((uint32_t)Data2 << 8U) | Data1;
+    data = ((uint32_t)Data2 << 8) | Data1; 
   }
   else
   {
-    data = ((uint32_t)Data2 << 16U) | Data1;
+    data = ((uint32_t)Data2 << 16) | Data1;
   }
-
+  
   tmp = (uint32_t)hdac->Instance;
   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
 
   /* Set the dual DAC selected data holding register */
   *(__IO uint32_t *)tmp = data;
-
+  
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Conversion complete callback in non-blocking mode for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @}
+  */
+
+/**
+  * @brief  Conversion complete callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
   * @brief  Error DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DMA underrun DAC callback for Channel2.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  DMA underrun DAC callback for channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hdac);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
-  * @}
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Extended Peripheral Control functions
-  *
-@verbatim
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the last data output value of the selected DAC channel.
-  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
-{
-  uint32_t tmp = 0U;
-
-  tmp |= hdac->Instance->DOR1;
-
-  tmp |= hdac->Instance->DOR2 << 16U;
-
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx private functions
-  *  @brief    Extended private functions
-   * @{
-  */
-
-/**
-  * @brief  DMA conversion complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
 {
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvCpltCallbackCh2(hdac);
-#else
-  HAL_DACEx_ConvCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
 }
 
 /**
-  * @brief  DMA half transfer complete callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
 {
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ConvHalfCpltCallbackCh2(hdac);
-#else
-  HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
 }
 
 /**
-  * @brief  DMA error callback.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
 {
-  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
   /* Set DAC error code to DMA error */
   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  hdac->ErrorCallbackCh2(hdac);
-#else
-  HAL_DACEx_ErrorCallbackCh2(hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-  hdac->State = HAL_DAC_STATE_READY;
+    
+  HAL_DACEx_ErrorCallbackCh2(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
 }
 
 /**
   * @}
   */
 
+#endif /* HAL_DAC_MODULE_ENABLED */
+
 /**
   * @}
   */
 
-#endif /* DAC */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
 /**
   * @}
   */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma_ex.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:
@@ -25,13 +27,29 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -69,7 +87,6 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   * @{
   */
 
-
 /** @addtogroup DMAEx_Exported_Functions_Group1
   *
 @verbatim   
@@ -87,151 +104,124 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   * @{
   */
 
-
 /**
   * @brief  Starts the multi_buffer DMA Transfer.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength The length of data to be transferred from source to destination
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength: The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Memory-to-memory transfer not supported in double buffering mode */
-  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  /* Process Locked */
+  __HAL_LOCK(hdma);
+
+  /* Current memory buffer used is Memory 0 */
+  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
   {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    status = HAL_ERROR;
+    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
   }
-  else
+  /* Current memory buffer used is Memory 1 */
+  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
   {
-    /* Process Locked */
-    __HAL_LOCK(hdma);
-    
-    if(HAL_DMA_STATE_READY == hdma->State)
-    {
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_BUSY; 
-      
-      /* Enable the double buffer mode */
-      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-      
-      /* Configure DMA Stream destination address */
-      hdma->Instance->M1AR = SecondMemAddress;
-      
-      /* Configure the source, destination address and the data length */
-      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-      
-      /* Enable the peripheral */
-      __HAL_DMA_ENABLE(hdma);
-    }
-    else
-    {
-      /* Return error status */
-      status = HAL_BUSY;
-    }
+    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
   }
-  return status;
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);  
+
+  /* Enable the double buffer mode */
+  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+  /* Configure DMA Stream destination address */
+  hdma->Instance->M1AR = SecondMemAddress;
+
+  /* Configure the source, destination address and the data length */
+  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength The length of data to be transferred from source to destination
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength: The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Memory-to-memory transfer not supported in double buffering mode */
-  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-  
-  /* Check callback functions */
-  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
+  /* Process Locked */
+  __HAL_LOCK(hdma);
+
+  /* Current memory buffer used is Memory 0 */
+  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
   {
-    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-    return HAL_ERROR;
+    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
   }
-  
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
+  /* Current memory buffer used is Memory 1 */
+  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
   {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Enable the Double buffer mode */
-    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-    
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M1AR = SecondMemAddress;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
-    
-    /* Clear all flags */
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
-
-    /* Enable Common interrupts*/
-    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
-    
-    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-    {
-      hdma->Instance->CR  |= DMA_IT_HT;
-    }
-    
-    /* Enable the peripheral */
-    __HAL_DMA_ENABLE(hdma); 
+    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
   }
-  else
-  {     
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);	  
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  }  
-  return status; 
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);  
+
+  /* Enable the Double buffer mode */
+  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+  /* Configure DMA Stream destination address */
+  hdma->Instance->M1AR = SecondMemAddress;
+
+  /* Configure the source, destination address and the data length */
+  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+
+  /* Enable the transfer complete interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+  /* Enable the Half transfer interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+  /* Enable the fifo Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);  
+
+  /* Enable the direct mode Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); 
+
+  /* Enable the peripheral */
+  __HAL_DMA_ENABLE(hdma); 
+
+  return HAL_OK; 
 }
 
 /**
   * @brief  Change the memory0 or memory1 address on the fly.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  Address    The new address
-  * @param  memory     the memory to be changed, This parameter can be one of 
-  *                     the following values:
-  *                      MEMORY0 /
-  *                      MEMORY1
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA Stream.  
+  * @param  Address: The new address
+  * @param  memory: the memory to be changed, This parameter can be one of 
+  *         the following values:
+  *              MEMORY0 /
+  *              MEMORY1
   * @note   The MEMORY0 address can be changed only when the current transfer use
   *         MEMORY1 and the MEMORY1 address can be changed only when the current 
   *         transfer use MEMORY0.
@@ -267,11 +257,11 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
 
 /**
   * @brief  Set the DMA Transfer parameter.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -63,16 +65,32 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -93,7 +111,7 @@
 /** @addtogroup FLASH_Private_Constants
   * @{
   */
-#define FLASH_TIMEOUT_VALUE       50000U   /* 50 s */
+#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
 /**
   * @}
   */         
@@ -147,10 +165,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
 
 /**
   * @brief  Program byte, halfword, word or double word at a specified address
-  * @param  TypeProgram  Indicate the way to program at a specified address.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
   *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address  specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
   * 
   * @retval HAL_StatusTypeDef HAL Status
   */
@@ -205,10 +223,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
 
 /**
   * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
-  * @param  TypeProgram  Indicate the way to program at a specified address.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
   *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address  specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
   * 
   * @retval HAL Status
   */
@@ -261,7 +279,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
   */
 void HAL_FLASH_IRQHandler(void)
 {
-  uint32_t addresstmp = 0U;
+  uint32_t addresstmp = 0;
   
   /* Check FLASH operation error flags */
   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
@@ -271,7 +289,7 @@ void HAL_FLASH_IRQHandler(void)
     {
       /*return the faulty sector*/
       addresstmp = pFlash.Sector;
-      pFlash.Sector = 0xFFFFFFFFU;
+      pFlash.Sector = 0xFFFFFFFF;
     }
     else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
     {
@@ -306,7 +324,7 @@ void HAL_FLASH_IRQHandler(void)
       pFlash.NbSectorsToErase--;
       
       /* Check if there are still sectors to erase*/
-      if(pFlash.NbSectorsToErase != 0U)
+      if(pFlash.NbSectorsToErase != 0)
       {
         addresstmp = pFlash.Sector;
         /*Indicate user which sector has been erased*/
@@ -321,7 +339,7 @@ void HAL_FLASH_IRQHandler(void)
       {
         /*No more sectors to Erase, user callback can be called.*/
         /*Reset Sector and stop Erase sectors procedure*/
-        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
+        pFlash.Sector = addresstmp = 0xFFFFFFFF;
         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
         
         /* Flush the caches to be sure of the data consistency */
@@ -370,7 +388,7 @@ void HAL_FLASH_IRQHandler(void)
 
 /**
   * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
   *                  Mass Erase: Bank number which has been requested to erase
   *                  Sectors Erase: Sector which has been erased 
   *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
@@ -379,8 +397,6 @@ void HAL_FLASH_IRQHandler(void)
   */
 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
    */ 
@@ -388,7 +404,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 
 /**
   * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
   *                 Mass Erase: Bank number which has been requested to erase
   *                 Sectors Erase: Sector number which returned an error
   *                 Program: Address which was selected for data program
@@ -396,8 +412,6 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
   */
 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
    */ 
@@ -428,22 +442,18 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
   */
 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
 {
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
   {
     /* Authorize the FLASH Registers access */
-    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
-    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-
-    /* Verify Flash is unlocked */
-    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
-    {
-      status = HAL_ERROR;
-    }
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
   }
-
-  return status;
+  else
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK; 
 }
 
 /**
@@ -542,12 +552,12 @@ uint32_t HAL_FLASH_GetError(void)
 
 /**
   * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout maximum flash operationtimeout
+  * @param  Timeout: maximum flash operationtimeout
   * @retval HAL Status
   */
 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
 { 
-  uint32_t tickstart = 0U;
+  uint32_t tickstart = 0;
   
   /* Clear Error Code */
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
@@ -562,7 +572,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
   { 
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         return HAL_TIMEOUT;
       }
@@ -570,7 +580,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
   }
 
   /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
   {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
@@ -592,13 +602,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
 /**
   * @brief  Program a double word (64-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V and an External Vpp in the range 7V to 9V.
+  *         2.7V to 3.6V and an External Vpp is present.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
@@ -611,17 +621,10 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
   FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
   FLASH->CR |= FLASH_CR_PG;
 
-  /* Program first word */
-  *(__IO uint32_t*)Address = (uint32_t)Data;
-
-  /* Barrier to ensure programming is performed in 2 steps, in right order
-    (independently of compiler optimization behavior) */
-  __ISB();
-
-  /* Program second word */
-  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+  *(__IO uint64_t*)Address = Data;
 }
 
+
 /**
   * @brief  Program word (32-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
@@ -630,8 +633,8 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
@@ -650,13 +653,13 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
 /**
   * @brief  Program a half-word (16-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         2.1V to 2.7V.
+  *         2.7V to 3.6V.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@@ -675,13 +678,13 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
 /**
   * @brief  Program byte (8-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         1.8V to 2.1V.
+  *         2.7V to 3.6V.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash_ex.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
@@ -34,16 +36,32 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -64,7 +82,7 @@
 /** @addtogroup FLASHEx_Private_Constants
   * @{
   */
-#define FLASH_TIMEOUT_VALUE       50000U   /* 50 s */
+#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
 /**
   * @}
   */
@@ -101,7 +119,7 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASH Exported Functions
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
   * @{
   */
 
@@ -121,10 +139,10 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
   */
 /**
   * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
-  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
   * 
-  * @param[out]  SectorError pointer to variable  that
+  * @param[out]  SectorError: pointer to variable  that
   *         contains the configuration information on faulty sector in case of error 
   *         (0xFFFFFFFF means that all the sectors have been correctly erased)
   * 
@@ -133,7 +151,7 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0U;
+  uint32_t index = 0;
   
   /* Process Locked */
   __HAL_LOCK(&pFlash);
@@ -147,7 +165,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
   if(status == HAL_OK)
   {
     /*Initialization of SectorError variable*/
-    *SectorError = 0xFFFFFFFFU;
+    *SectorError = 0xFFFFFFFF;
     
     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
     {
@@ -196,7 +214,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
 
 /**
   * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
-  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
   * 
   * @retval HAL Status
@@ -249,7 +267,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 
 /**
   * @brief   Program option bytes
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
   *         contains the configuration information for the programming.
   * 
   * @retval HAL Status
@@ -308,7 +326,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
 
 /**
   * @brief   Get the Option byte configuration
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
   *         contains the configuration information for the programming.
   * 
   * @retval None
@@ -336,9 +354,9 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 
 /**
   * @brief  Erase the specified FLASH memory sector
-  * @param  Sector FLASH sector to erase
+  * @param  Sector: FLASH sector to erase
   *         The value of this parameter depend on device used within the same series      
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
   *          This parameter can be one of the following values:
   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
   *                                  the operation will be done by byte (8-bit) 
@@ -353,7 +371,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
   */
 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
 {
-  uint32_t tmp_psize = 0U;
+  uint32_t tmp_psize = 0;
 
   /* Check the parameters */
   assert_param(IS_FLASH_SECTOR(Sector));
@@ -415,7 +433,7 @@ void FLASH_FlushCaches(void)
 
 /**
   * @brief  Mass erase of FLASH memory
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
   *          This parameter can be one of the following values:
   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
   *                                  the operation will be done by byte (8-bit) 
@@ -426,25 +444,25 @@ void FLASH_FlushCaches(void)
   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
   *                                  the operation will be done by double word (64-bit)
   * 
-  * @param  Banks Banks to be erased
+  * @param  Banks: Banks to be erased
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: Bank1 to be erased
   *
   * @retval None
   */
 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{ 
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(Banks);
-
+{
+  uint32_t tmp_psize = 0;
+  
   /* Check the parameters */
   assert_param(IS_VOLTAGERANGE(VoltageRange));
   assert_param(IS_FLASH_BANK(Banks));
   
   /* If the previous operation is completed, proceed to erase all sectors */
   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
   FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
+  FLASH->CR |= FLASH_CR_STRT;
 }
 
 /**
@@ -454,10 +472,10 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
   *         it is not possible to program or erase the flash sector i if CortexM3  
   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
   * 
-  * @param  WRPSector specifies the sector(s) to be write protected.
+  * @param  WRPSector: specifies the sector(s) to be write protected.
   *         The value of this parameter depend on device used within the same series 
   * 
-  * @param  Banks Enable write protection on all the sectors for the specific bank
+  * @param  Banks: Enable write protection on all the sectors for the specific bank
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
   *
@@ -466,10 +484,7 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
 {
   HAL_StatusTypeDef status = HAL_OK;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(Banks);
-
+  
   /* Check the parameters */
   assert_param(IS_OB_WRP_SECTOR(WRPSector));
   assert_param(IS_FLASH_BANK(Banks));
@@ -492,10 +507,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
   *         it is not possible to program or erase the flash sector if CortexM3  
   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
   * 
-  * @param  WRPSector specifies the sector(s) to be write protected.
+  * @param  WRPSector: specifies the sector(s) to be write protected.
   *         The value of this parameter depend on device used within the same series 
   * 
-  * @param  Banks Enable write protection on all the sectors for the specific bank
+  * @param  Banks: Enable write protection on all the sectors for the specific bank
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
   *
@@ -504,10 +519,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
 {
   HAL_StatusTypeDef status = HAL_OK;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(Banks);
-
+  
   /* Check the parameters */
   assert_param(IS_OB_WRP_SECTOR(WRPSector));
   assert_param(IS_FLASH_BANK(Banks));
@@ -525,7 +537,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
 
 /**
   * @brief  Set the read protection level.
-  * @param  Level specifies the read protection level.
+  * @param  Level: specifies the read protection level.
   *          This parameter can be one of the following values:
   *            @arg OB_RDP_LEVEL_0: No protection
   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
@@ -555,15 +567,15 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
 
 /**
   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
-  * @param  Iwdg Selects the IWDG mode
+  * @param  Iwdg: Selects the IWDG mode
   *          This parameter can be one of the following values:
   *            @arg OB_IWDG_SW: Software IWDG selected
   *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop Reset event when entering STOP mode.
+  * @param  Stop: Reset event when entering STOP mode.
   *          This parameter  can be one of the following values:
   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
   *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby Reset event when entering Standby mode.
+  * @param  Stdby: Reset event when entering Standby mode.
   *          This parameter  can be one of the following values:
   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
@@ -596,7 +608,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
 
 /**
   * @brief  Set the BOR Level. 
-  * @param  Level specifies the Option Bytes BOR Reset Level.
+  * @param  Level: specifies the Option Bytes BOR Reset Level.
   *          This parameter can be one of the following values:
   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
@@ -654,13 +666,13 @@ static uint8_t FLASH_OB_GetRDP(void)
   {
     readstatus = OB_RDP_LEVEL_2;
   }
-  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))
+  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
   {
-    readstatus = OB_RDP_LEVEL_0;
+    readstatus = OB_RDP_LEVEL_1;
   }
   else 
   {
-    readstatus = OB_RDP_LEVEL_1;
+    readstatus = OB_RDP_LEVEL_0;
   }
 
   return readstatus;

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c

@@ -2,6 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -93,16 +95,32 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -116,13 +134,6 @@
   * @{
   */
 
-/** MISRA C:2012 deviation rule has been granted for following rules:
-  * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
-  * which may be out of array bounds [..,UNKNOWN] in following APIs:
-  * HAL_GPIO_Init
-  * HAL_GPIO_DeInit
-  */
-
 #ifdef HAL_GPIO_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
@@ -130,15 +141,15 @@
 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
   * @{
   */
-#define GPIO_MODE             0x00000003U
-#define EXTI_MODE             0x10000000U
-#define GPIO_MODE_IT          0x00010000U
-#define GPIO_MODE_EVT         0x00020000U
-#define RISING_EDGE           0x00100000U
-#define FALLING_EDGE          0x00200000U
-#define GPIO_OUTPUT_TYPE      0x00000010U
-
-#define GPIO_NUMBER           16U
+#define GPIO_MODE             ((uint32_t)0x00000003)
+#define EXTI_MODE             ((uint32_t)0x10000000)
+#define GPIO_MODE_IT          ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
+#define RISING_EDGE           ((uint32_t)0x00100000)
+#define FALLING_EDGE          ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER           ((uint32_t)16)
 /**
   * @}
   */
@@ -169,16 +180,17 @@
 
 /**
   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
   *         the configuration information for the specified GPIO peripheral.
   * @retval None
   */
 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 {
-  uint32_t position = 0x00u;
-  uint32_t iocurrent;
-  uint32_t temp;
+  uint32_t position;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t temp = 0x00;
 
   /* Check the parameters */
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -187,32 +199,32 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 
   /* Configure the port pins */
-  while (((GPIO_Init->Pin) >> position) != 0x00u)
+  for(position = 0; position < GPIO_NUMBER; position++)
   {
-    /* Get current io position */
-    iocurrent = (GPIO_Init->Pin) & (1uL << position);
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 
-    if (iocurrent != 0x00u)
+    if(iocurrent == ioposition)
     {
       /*--------------------- GPIO Mode Configuration ------------------------*/
       /* In case of Alternate function mode selection */
       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
       {
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        /* Check the Alternate function parameter */
         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
         /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3u];
-        temp &= ~(0xFu << ((position & 0x07u) * 4u));
-        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
-        GPIOx->AFR[position >> 3u] = temp;
+        temp = GPIOx->AFR[position >> 3];
+        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+        GPIOx->AFR[position >> 3] = temp;
       }
 
       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
       temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
       GPIOx->MODER = temp;
 
       /* In case of Output or Alternate function mode selection */
@@ -222,22 +234,22 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         /* Check the Speed parameter */
         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
         /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR;
-        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
-        temp |= (GPIO_Init->Speed << (position * 2u));
+        temp = GPIOx->OSPEEDR; 
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+        temp |= (GPIO_Init->Speed << (position * 2));
         GPIOx->OSPEEDR = temp;
 
         /* Configure the IO Output Type */
         temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
         GPIOx->OTYPER = temp;
       }
 
       /* Activate the Pull-up or Pull down resistor for the current IO */
       temp = GPIOx->PUPDR;
-      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
-      temp |= ((GPIO_Init->Pull) << (position * 2u));
+      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+      temp |= ((GPIO_Init->Pull) << (position * 2));
       GPIOx->PUPDR = temp;
 
       /*--------------------- EXTI Mode Configuration ------------------------*/
@@ -247,14 +259,14 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         /* Enable SYSCFG Clock */
         __HAL_RCC_SYSCFG_CLK_ENABLE();
 
-        temp = SYSCFG->EXTICR[position >> 2u];
-        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
-        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
-        SYSCFG->EXTICR[position >> 2u] = temp;
+        temp = SYSCFG->EXTICR[position >> 2];
+        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+        SYSCFG->EXTICR[position >> 2] = temp;
 
         /* Clear EXTI line configuration */
         temp = EXTI->IMR;
-        temp &= ~(iocurrent);
+        temp &= ~((uint32_t)iocurrent);
         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
         {
           temp |= iocurrent;
@@ -262,7 +274,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->IMR = temp;
 
         temp = EXTI->EMR;
-        temp &= ~(iocurrent);
+        temp &= ~((uint32_t)iocurrent);
         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
         {
           temp |= iocurrent;
@@ -271,7 +283,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
         /* Clear Rising Falling edge configuration */
         temp = EXTI->RTSR;
-        temp &= ~(iocurrent);
+        temp &= ~((uint32_t)iocurrent);
         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
         {
           temp |= iocurrent;
@@ -279,7 +291,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->RTSR = temp;
 
         temp = EXTI->FTSR;
-        temp &= ~(iocurrent);
+        temp &= ~((uint32_t)iocurrent);
         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
         {
           temp |= iocurrent;
@@ -287,74 +299,70 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->FTSR = temp;
       }
     }
-
-    position++;
   }
 }
 
 /**
   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin specifies the port bit to be written.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin: specifies the port bit to be written.
   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 {
-  uint32_t position = 0x00u;
-  uint32_t iocurrent;
-  uint32_t tmp;
+  uint32_t position;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t tmp = 0x00;
 
   /* Check the parameters */
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
+  
   /* Configure the port pins */
-  while ((GPIO_Pin >> position) != 0x00u)
+  for(position = 0; position < GPIO_NUMBER; position++)
   {
-    /* Get current io position */
-    iocurrent = (GPIO_Pin) & (1uL << position);
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (GPIO_Pin) & ioposition;
 
-    if (iocurrent != 0x00u)
+    if(iocurrent == ioposition)
     {
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      /* Clear the External Interrupt or Event for the current IO */
-
-      tmp = SYSCFG->EXTICR[position >> 2u];
-      tmp &= (0x0FuL << (4u * (position & 0x03u)));
-      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
-      {
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-        
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-
-        /* Configure the External Interrupt or event for the current IO */
-        tmp = 0x0FuL << (4u * (position & 0x03u));
-        SYSCFG->EXTICR[position >> 2u] &= ~tmp;
-      }
-
       /*------------------------- GPIO Mode Configuration --------------------*/
       /* Configure IO Direction in Input Floating Mode */
-      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
 
       /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
+      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
 
       /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
 
       /* Configure the default value IO Output Type */
       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
 
       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-    }
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
 
-    position++;
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      tmp = SYSCFG->EXTICR[position >> 2];
+      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
+      {
+        /* Configure the External Interrupt or event for the current IO */
+        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+        SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~((uint32_t)iocurrent);
+        EXTI->EMR &= ~((uint32_t)iocurrent);
+        
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR &= ~((uint32_t)iocurrent);
+        EXTI->FTSR &= ~((uint32_t)iocurrent);
+      }
+    }
   }
 }
 
@@ -376,8 +384,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 
 /**
   * @brief  Reads the specified input port pin.
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin specifies the port bit to read.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin: specifies the port bit to read.
   *         This parameter can be GPIO_PIN_x where x can be (0..15).
   * @retval The input port pin value.
   */
@@ -406,10 +414,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         accesses. In this way, there is no risk of an IRQ occurring between
   *         the read and the modify access.
   *
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral for all STM32F2XX devices
-  * @param  GPIO_Pin specifies the port bit to be written.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral for all STM32F2XX devices
+  * @param  GPIO_Pin: specifies the port bit to be written.
   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState specifies the value to be written to the selected bit.
+  * @param  PinState: specifies the value to be written to the selected bit.
   *          This parameter can be one of the GPIO_PinState enum values:
   *            @arg GPIO_PIN_RESET: to clear the port pin
   *            @arg GPIO_PIN_SET: to set the port pin
@@ -427,14 +435,14 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
   }
   else
   {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
   }
 }
 
 /**
   * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin Specifies the pins to be toggled.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
   * @retval None
   */
 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -442,14 +450,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
-  if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin;
-  }
+  GPIOx->ODR ^= GPIO_Pin;
 }
 
 /**
@@ -458,8 +459,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
   * @note   The configuration of the locked GPIO pins can no longer be modified
   *         until the next reset.
-  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
-  * @param  GPIO_Pin specifies the port bit to be locked.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
@@ -478,11 +479,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   GPIOx->LCKR = GPIO_Pin;
   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
   GPIOx->LCKR = tmp;
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  /* Read LCKK bit*/
   tmp = GPIOx->LCKR;
 
-  /* read again in order to confirm lock is active */
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
   {
     return HAL_OK;
   }
@@ -494,13 +494,13 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
 /**
   * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 {
   /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
   {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
     HAL_GPIO_EXTI_Callback(GPIO_Pin);
@@ -509,13 +509,11 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 
 /**
   * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
   * @retval None
   */
 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_GPIO_EXTI_Callback could be implemented in the user file
    */

lib/SCSI2SD/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hash.c

@@ -2,277 +2,334 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hash.c
   * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    09-October-2015
   * @brief   HASH HAL module driver.
-  *          This file provides firmware functions to manage the following
+  *          This file provides firmware functions to manage the following 
   *          functionalities of the HASH peripheral:
-  *           + Initialization and de-initialization methods
-  *           + HASH or HMAC processing in polling mode
-  *           + HASH or HMAC processing in interrupt mode
-  *           + HASH or HMAC processing in DMA mode
-  *           + Peripheral State methods
-  *           + HASH or HMAC processing suspension/resumption
-  *
+  *           + Initialization and de-initialization functions
+  *           + HASH/HMAC Processing functions by algorithm using polling mode
+  *           + HASH/HMAC functions by algorithm using interrupt mode
+  *           + HASH/HMAC functions by algorithm using DMA mode
+  *           + Peripheral State functions
+  *         
   @verbatim
- ===============================================================================
+  ==============================================================================
                      ##### How to use this driver #####
- ===============================================================================
+  ==============================================================================
     [..]
     The HASH HAL driver can be used as follows:
-
     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
-        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
-        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
+        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
+        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
-            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
-        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
-            (+++) Enable the DMAx interface clock using
-                   __DMAx_CLK_ENABLE()
-            (+++) Configure and enable one DMA stream to manage data transfer from
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
+        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
+            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+            (+++) Configure and enable one DMA stream one for managing data transfer from
                 memory to peripheral (input stream). Managing data transfer from
-                peripheral to memory can be performed only using CPU.
+                peripheral to memory can be performed only using CPU
             (+++) Associate the initialized DMA handle to the HASH DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
-                interrupt on the DMA Stream: use
-                 HAL_NVIC_SetPriority() and
-                 HAL_NVIC_EnableIRQ()
-
-    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
-        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
-        (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
-
-    (#)Three processing schemes are available:
+                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
+        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
+        (##) For HMAC, the encryption key.
+        (##) For HMAC, the key size used for encryption.
+    (#)Three processing functions are available:
         (##) Polling mode: processing APIs are blocking functions
-             i.e. they process the data and wait till the digest computation is finished,
-             e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
-        (##) Interrupt mode: processing APIs are not blocking functions
-                i.e. they process the data under interrupt,
-                e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
+             i.e. they process the data and wait till the digest computation is finished
+             e.g. HAL_HASH_SHA1_Start()
+        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+                i.e. they process the data under interrupt
+                e.g. HAL_HASH_SHA1_Start_IT()
         (##) DMA mode: processing APIs are not blocking functions and the CPU is
-             not used for data transfer i.e. the data transfer is ensured by DMA,
-                e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
-                for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
-                is then required to retrieve the digest.
-
-    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
-       initialized and processes the buffer fed in input. When the input data have all been
-       fed to the IP, the digest computation can start.
-
-    (#)Multi-buffer processing is possible in polling and DMA mode.
-        (##) In polling mode, only multi-buffer HASH processing is possible.
-             API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
-             User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
-             well the computed digest.
-
-        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
-              (+++) HASH processing DMA mode: processing APIs are not blocking functions and the CPU is
              not used for data transfer i.e. the data transfer is ensured by DMA
                 e.g. HAL_HASH_SHA1_Start_DMA()
-             (+++) HMAC processing (requires to resort to extended functions):
-             after initialization, the key and the first input buffer are entered
-             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
-             starts step 2.
-             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
-             point, the HMAC processing is still carrying out step 2.
-             Then, step 2 for the last input buffer and step 3 are carried out by a single call
-             to HAL_HMACEx_xxx_Step2_3_DMA().
-
-             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
-
-
-    (#)Context swapping.
-        (##) Two APIs are available to suspend HASH or HMAC processing:
-             (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
-             (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
-
-        (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
-            to save in memory the IP context. This context can be restored afterwards
-            to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
-
-        (##) Once the HASH IP has been restored to the same configuration as that at suspension
-             time, processing can be restarted with the same API call (same API, same handle,
-             same parameters) as done before the suspension. Relevant parameters to restart at
-             the proper location are internally saved in the HASH handle.
-
+    (#)When the processing function is called at first time after HAL_HASH_Init()
+       the HASH peripheral is initialized and processes the buffer in input.
+       After that, the digest computation is started.
+       When processing multi-buffer use the accumulate function to write the
+       data in the peripheral without starting the digest computation. In last 
+       buffer use the start function to input the last buffer ans start the digest
+       computation.
+       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
+       (##) write (n-1)th data buffer in the peripheral without starting the digest computation
+       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
+    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
+    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
+       After that, call the finish function in order to get the digest value
+       e.g. HAL_HASH_SHA1_Finish()
     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
 
-     *** Callback registration ***
-     ===================================
-     [..]
-      (#) The compilation define  USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
-          allows the user to configure dynamically the driver callbacks.
-          Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
-
-      (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
-            (+) InCpltCallback    : callback for input completion.
-            (+) DgstCpltCallback  : callback for digest computation completion.
-            (+) ErrorCallback     : callback for error.
-            (+) MspInitCallback   : HASH MspInit.
-            (+) MspDeInitCallback : HASH MspDeInit.
-          This function takes as parameters the HAL peripheral handle, the Callback ID
-          and a pointer to the user callback function.
-
-      (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
-          weak (surcharged) function.
-          @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-          and the Callback ID.
-          This function allows to reset following callbacks:
-            (+) InCpltCallback    : callback for input completion.
-            (+) DgstCpltCallback  : callback for digest computation completion.
-            (+) ErrorCallback     : callback for error.
-            (+) MspInitCallback   : HASH MspInit.
-            (+) MspDeInitCallback : HASH MspDeInit.
-
-      (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
-          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
-          examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
-          Exception done for MspInit and MspDeInit callbacks that are respectively
-          reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
-          and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
-          If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
-          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-          Callbacks can be registered/unregistered in READY state only.
-          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
-          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
-          during the Init/DeInit.
-          In that case first register the MspInit/MspDeInit user callbacks
-          using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
-          or @ref HAL_HASH_Init function.
-
-          When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
-          not defined, the callback registering feature is not available
-          and weak (surcharged) callbacks are used.
-
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
-
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
-#if defined (HASH)
 
-/** @defgroup HASH  HASH
+/** @defgroup HASH HASH
   * @brief HASH HAL module driver.
   * @{
   */
 
 #ifdef HAL_HASH_MODULE_ENABLED
 
+#if defined(STM32F215xx) || defined(STM32F217xx)
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @defgroup HASH_Private_Constants HASH Private Constants
-  * @{
-  */
-
-/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
   * @{
   */
-#define HASH_DIGEST_CALCULATION_NOT_STARTED       ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
-#define HASH_DIGEST_CALCULATION_STARTED           ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register     */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
 /**
   * @}
   */
-
-/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
+  
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HASH_Private_Functions
   * @{
   */
-#define HASH_NUMBER_OF_CSR_REGISTERS              54U     /*!< Number of Context Swap Registers */
+
 /**
-  * @}
+  * @brief  DMA HASH Input Data complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
   */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t inputaddr = 0;
+  uint32_t buffersize = 0;
+  
+  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+  {
+    /* Disable the DMA transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    /* Change HASH peripheral state */
+    hhash->State = HAL_HASH_STATE_READY;
+    
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  else
+  {
+    /* Increment Interrupt counter */
+    hhash->HashInCount++;
+    /* Disable the DMA transfer before starting the next transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    if(hhash->HashInCount <= 2)
+    {
+      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+      if(hhash->HashInCount == 1)
+      {
+        inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+        buffersize = hhash->HashBuffSize;
+      }
+      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+      else if(hhash->HashInCount == 2)
+      {
+        inputaddr = (uint32_t)hhash->Init.pKey;
+        buffersize = hhash->Init.KeySize;
+      }
+      /* Configure the number of valid bits in last word of the message */
+      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
+      
+      /* Set the HASH DMA transfer complete */
+      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+      
+      /* Enable the DMA In DMA Stream */
+      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
+      
+      /* Enable DMA requests */
+      HASH->CR |= (HASH_CR_DMAE);
+    }
+    else
+    {
+      /* Disable the DMA transfer */
+      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+      
+      /* Reset the InCount */
+      hhash->HashInCount = 0;
+      
+      /* Change HASH peripheral state */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+      /* Call Input data transfer complete callback */
+      HAL_HASH_InCpltCallback(hhash);
+    }
+  }
+}
 
-/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
-  * @{
-  */
-#define HASH_TIMEOUTVALUE                         1000U   /*!< Time-out value  */
 /**
-  * @}
+  * @brief  DMA HASH communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
   */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hhash->State= HAL_HASH_STATE_READY;
+  HAL_HASH_ErrorCallback(hhash);
+}
 
-/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
-  * @{
-  */
-#define HASH_DMA_SUSPENSION_WORDS_LIMIT             20U   /*!< Number of words below which DMA suspension is aborted */
 /**
-  * @}
+  * @brief  Writes the input buffer in data register.
+  * @param  pInBuffer: Pointer to input buffer
+  * @param  Size: The size of input buffer
+  * @retval None
   */
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  uint32_t inputaddr = (uint32_t) pInBuffer;
+  
+  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
+  {
+    HASH->DIN = *(uint32_t*)inputaddr;
+    inputaddr+=4;
+  }
+}
 
 /**
-  * @}
+  * @brief  Provides the message digest result.
+  * @param  pMsgDigest: Pointer to the message digest
+  * @param  Size: The size of the message digest in bytes
+  * @retval None
   */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+  
+  switch(Size)
+  {
+  case 16:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    break;
+  case 20:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  case 28:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  case 32:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  default:
+    break;
+  }
+}
 
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
-  * @{
-  */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
-static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
-static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions HASH Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HASH_Exported_Functions
   * @{
   */
+  
 
-/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization, configuration and call-back functions.
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
  *
-@verbatim
+@verbatim    
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the HASH according to the specified parameters
-          in the HASH_InitTypeDef and create the associated handle
-      (+) DeInitialize the HASH peripheral
-      (+) Initialize the HASH MCU Specific Package (MSP)
-      (+) DeInitialize the HASH MSP
-
-    [..]  This section provides as well call back functions definitions for user
-          code to manage:
-      (+) Input data transfer to IP completion
-      (+) Calculated digest retrieval completion
-      (+) Error management
-
-
-
+      (+) Initialize the HASH according to the specified parameters 
+          in the HASH_InitTypeDef and creates the associated handle.
+      (+) DeInitialize the HASH peripheral.
+      (+) Initialize the HASH MSP.
+      (+) DeInitialize HASH MSP. 
+ 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initialize the HASH according to the specified parameters in the
-            HASH_HandleTypeDef and create the associated handle.
-  * @note   Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
-  *         other configuration bits are set by HASH or HMAC processing APIs.
-  * @param  hhash: HASH handle
+  * @brief  Initializes the HASH according to the specified parameters in the
+            HASH_HandleTypeDef and creates the associated handle.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
@@ -282,2694 +339,1513 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-  if (hhash->State == HAL_HASH_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hhash->Lock = HAL_UNLOCKED;
-
-    /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
-    hhash->InCpltCallback =  HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
-    hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
-    hhash->ErrorCallback =  HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
-    if(hhash->MspInitCallback == NULL)
-    {
-      hhash->MspInitCallback = HAL_HASH_MspInit;
-    }
-
-    /* Init the low level hardware */
-    hhash->MspInitCallback(hhash);
-  }
-#else
+   
   if(hhash->State == HAL_HASH_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hhash->Lock = HAL_UNLOCKED;
-
     /* Init the low level hardware */
     HAL_HASH_MspInit(hhash);
   }
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
-
-    /* Change the HASH state */
+  
+  /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_BUSY;
-
-  /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
+  
+  /* Reset HashInCount, HashBuffSize and HashITCounter */
   hhash->HashInCount = 0;
   hhash->HashBuffSize = 0;
   hhash->HashITCounter = 0;
-  hhash->NbWordsAlreadyPushed = 0;
-  /* Reset digest calculation bridle (MDMAT bit control) */
-  hhash->DigestCalculationDisable = RESET;
-  /* Set phase to READY */
-  hhash->Phase = HAL_HASH_PHASE_READY;
-
-  /* Set the data type bit */
-  MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
-  /* Reset HASH handle status */
-  hhash->Status = HAL_OK;
-
-  /* Set the HASH state to Ready */
+  
+  /* Set the data type */
+  HASH->CR |= (uint32_t) (hhash->Init.DataType);
+  
+  /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_READY;
-
-  /* Initialise the error code */
-  hhash->ErrorCode = HAL_HASH_ERROR_NONE;
-
+  
+  /* Set the default HASH phase */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+  
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitialize the HASH peripheral.
-  * @param  hhash: HASH handle.
+  * @brief  DeInitializes the HASH peripheral.
+  * @note   This API must be called before starting a new processing. 
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
-{
+{ 
   /* Check the HASH handle allocation */
   if(hhash == NULL)
   {
     return HAL_ERROR;
   }
-
+  
   /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_BUSY;
-
+  
   /* Set the default HASH phase */
   hhash->Phase = HAL_HASH_PHASE_READY;
-
-  /* Reset HashInCount, HashITCounter and HashBuffSize */
+  
+  /* Reset HashInCount, HashBuffSize and HashITCounter */
   hhash->HashInCount = 0;
   hhash->HashBuffSize = 0;
   hhash->HashITCounter = 0;
-  /* Reset digest calculation bridle (MDMAT bit control) */
-  hhash->DigestCalculationDisable = RESET;
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-    if(hhash->MspDeInitCallback == NULL)
-    {
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
-    }
-
-    /* DeInit the low level hardware */
-    hhash->MspDeInitCallback(hhash);
-#else
-  /* DeInit the low level hardware: CLOCK, NVIC */
+  
+  /* DeInit the low level hardware */
   HAL_HASH_MspDeInit(hhash);
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
-
-
-  /* Reset HASH handle status */
-  hhash->Status = HAL_OK;
-
-  /* Set the HASH state to Ready */
-  hhash->State = HAL_HASH_STATE_RESET;
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_RESET;  
 
-  /* Initialise the error code */
-  hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+  /* Release Lock */
+  __HAL_UNLOCK(hhash);
 
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Initialize the HASH MSP.
-  * @param  hhash: HASH handle.
+  * @brief  Initializes the HASH MSP.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval None
   */
 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_HASH_MspInit() can be implemented in the user file.
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_MspInit could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DeInitialize the HASH MSP.
-  * @param  hhash: HASH handle.
+  * @brief  DeInitializes HASH MSP.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval None
   */
 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_HASH_MspDeInit() can be implemented in the user file.
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_MspDeInit could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Input data transfer complete call back.
-  * @note   HAL_HASH_InCpltCallback() is called when the complete input message
-  *         has been fed to the IP. This API is invoked only when input data are
-  *         entered under interruption or thru DMA.
-  * @param  hhash: HASH handle.
+  * @brief  Input data transfer complete callback.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval None
   */
-__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_HASH_InCpltCallback() can be implemented in the user file.
-   */
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_InCpltCallback could be implemented in the user file
+   */ 
 }
 
 /**
-  * @brief  Digest computation complete call back.
-  * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not
-  *         relevant with DMA.
-  * @param  hhash: HASH handle.
+  * @brief  Data transfer Error callback.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval None
   */
-__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
 {
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_HASH_DgstCpltCallback() can be implemented in the user file.
-   */
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_ErrorCallback could be implemented in the user file
+   */ 
 }
 
 /**
-  * @brief  Error callback.
-  * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
-  *         to retrieve the error type.
-  * @param  hhash: HASH handle.
+  * @brief  Digest computation complete callback. It is used only with interrupt.
+  * @note   This callback is not relevant with DMA.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
   * @retval None
   */
-__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* NOTE : This function should not be modified; when the callback is needed,
-            HAL_HASH_ErrorCallback() can be implemented in the user file.
-   */
-}
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User HASH Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hhash HASH handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
-  *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
-  *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
-  *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
-  *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
-  * @param pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(pCallback == NULL)
-  {
-    /* Update the error code */
-    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(hhash);
-
-  if(HAL_HASH_STATE_READY == hhash->State)
-  {
-    switch (CallbackID)
-    {
-    case HAL_HASH_INPUTCPLT_CB_ID :
-      hhash->InCpltCallback = pCallback;
-      break;
-
-    case HAL_HASH_DGSTCPLT_CB_ID :
-      hhash->DgstCpltCallback = pCallback;
-      break;
-
-    case HAL_HASH_ERROR_CB_ID :
-      hhash->ErrorCallback = pCallback;
-      break;
-
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = pCallback;
-      break;
-
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = pCallback;
-      break;
-
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if(HAL_HASH_STATE_RESET == hhash->State)
-  {
-    switch (CallbackID)
-    {
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = pCallback;
-      break;
-
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = pCallback;
-      break;
-
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hhash);
-  return status;
-}
-
-/**
-  * @brief  Unregister a HASH Callback
-  *         HASH Callback is redirected to the weak (surcharged) predefined callback
-  * @param hhash HASH handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
-  *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
-  *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
-  *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
-  *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
 {
-HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hhash);
-
-  if(HAL_HASH_STATE_READY == hhash->State)
-  {
-    switch (CallbackID)
-    {
-    case HAL_HASH_INPUTCPLT_CB_ID :
-      hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
-      break;
-
-    case HAL_HASH_DGSTCPLT_CB_ID :
-      hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
-      break;
-
-    case HAL_HASH_ERROR_CB_ID :
-      hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
-      break;
-
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
-      break;
-
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
-      break;
-
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else if(HAL_HASH_STATE_RESET == hhash->State)
-  {
-    switch (CallbackID)
-    {
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
-      break;
-
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
-      break;
-
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hhash);
-  return status;
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_DgstCpltCallback could be implemented in the user file
+   */ 
 }
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- *  @brief   HASH processing functions using polling mode.
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode 
+ *  @brief   processing functions using polling mode 
  *
-@verbatim
- ===============================================================================
-                 ##### Polling mode HASH processing functions #####
+@verbatim   
  ===============================================================================
+              ##### HASH processing using polling mode functions#####
+ ===============================================================================  
     [..]  This section provides functions allowing to calculate in polling mode
           the hash value using one of the following algorithms:
       (+) MD5
-         (++) HAL_HASH_MD5_Start()
-         (++) HAL_HASH_MD5_Accumulate()
       (+) SHA1
-         (++) HAL_HASH_SHA1_Start()
-         (++) HAL_HASH_SHA1_Accumulate()
-
-    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
-
-    [..]  In case of multi-buffer HASH processing (a single digest is computed while
-          several buffers are fed to the IP), the user can resort to successive calls
-          to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
-          to HAL_HASH_xxx_Start().
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
+  *          and appending the input buffer is no more possible.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
   * @param  Timeout: Timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
-}
-
-/**
-  * @brief  If not already done, initialize the HASH peripheral in MD5 mode then
-  *         processes pInBuffer.
-  * @note   Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
-  *         several input buffers back-to-back to the IP that will yield a single
-  *         HASH signature once all buffers have been entered. Wrap-up of input
-  *         buffers feeding and retrieval of digest is done by a call to
-  *         HAL_HASH_MD5_Start().
-  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
-  *         the IP has already been initialized.
-  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
-  *         to read it, feeding at the same time the last input buffer to the IP.
-  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
-  *         HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
-  *         to manage the ending buffer with a length in bytes not a multiple of 4.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
-}
-
-/**
-  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
-  * @param  Timeout: Timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
-  * @brief  If not already done, initialize the HASH peripheral in SHA1 mode then
-  *         processes pInBuffer.
-  * @note   Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
-  *         several input buffers back-to-back to the IP that will yield a single
-  *         HASH signature once all buffers have been entered. Wrap-up of input
-  *         buffers feeding and retrieval of digest is done by a call to
-  *         HAL_HASH_SHA1_Start().
-  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
-  *         the IP has already been initialized.
-  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
-  *         to read it, feeding at the same time the last input buffer to the IP.
-  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
-  *         HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
-  *         to manage the ending buffer with a length in bytes not a multiple of 4.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- *  @brief   HASH processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
-                 ##### Interruption mode HASH processing functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to calculate in interrupt mode
-          the hash value using one of the following algorithms:
-      (+) MD5
-         (++) HAL_HASH_MD5_Start_IT()
-      (+) SHA1
-         (++) HAL_HASH_SHA1_Start_IT()
-
-    [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.
-
-    [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
-         HMAC processing mode.
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
-  *         read the computed digest in interruption mode.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
-}
-
-
-/**
-  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
-  *         read the computed digest in interruption mode.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
-}
-
-/**
-  * @brief Handle HASH interrupt request.
-  * @param hhash: HASH handle.
-  * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
-  * @note  In case of error reported during the HASH interruption processing,
-  *        HAL_HASH_ErrorCallback() API is called so that user code can
-  *        manage the error. The error type is available in hhash->Status field.
-  * @retval None
-  */
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
-{
-  hhash->Status = HASH_IT(hhash);
-  if (hhash->Status != HAL_OK)
-  {
-    hhash->ErrorCode |= HAL_HASH_ERROR_IT;
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-    hhash->ErrorCallback(hhash);
-#else
-    HAL_HASH_ErrorCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-    /* After error handling by code user, reset HASH handle HAL status */
-    hhash->Status = HAL_OK;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- *  @brief   HASH processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
-                    ##### DMA mode HASH processing functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to calculate in DMA mode
-          the hash value using one of the following algorithms:
-      (+) MD5
-         (++) HAL_HASH_MD5_Start_DMA()
-         (++) HAL_HASH_MD5_Finish()
-      (+) SHA1
-         (++) HAL_HASH_SHA1_Start_DMA()
-         (++) HAL_HASH_SHA1_Finish()
-
-    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
-          to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
-          HAL_HASH_xxx_Finish().
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
-  *         to feed the input buffer to the IP.
-  * @note   Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
-  *         be called to retrieve the computed digest.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-/**
-  * @brief  Return the computed digest in MD5 mode.
-  * @note   The API waits for DCIS to be set then reads the computed digest.
-  * @note   HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
-  *         HMAC MD5 mode.
-  * @param  hhash: HASH handle.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
-  * @param  Timeout: Timeout value.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
-  * @brief  Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
-  *         to feed the input buffer to the IP.
-  * @note   Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
-  *         be called to retrieve the computed digest.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-
-/**
-  * @brief  Return the computed digest in SHA1 mode.
-  * @note   The API waits for DCIS to be set then reads the computed digest.
-  * @note   HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
-  *         HMAC SHA1 mode.
-  * @param  hhash: HASH handle.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
-  * @param  Timeout: Timeout value.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- *  @brief   HMAC processing functions using polling mode.
- *
-@verbatim
- ===============================================================================
-                 ##### Polling mode HMAC processing functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to calculate in polling mode
-          the HMAC value using one of the following algorithms:
-      (+) MD5
-         (++) HAL_HMAC_MD5_Start()
-      (+) SHA1
-         (++) HAL_HMAC_SHA1_Start()
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
-  * @param  Timeout: Timeout value.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
-}
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
-  * @param  Timeout: Timeout value.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
-{
-  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- *  @brief   HMAC processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
-                 ##### Interrupt mode HMAC processing functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to calculate in interrupt mode
-          the HMAC value using one of the following algorithms:
-      (+) MD5
-         (++) HAL_HMAC_MD5_Start_IT()
-      (+) SHA1
-         (++) HAL_HMAC_SHA1_Start_IT()
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
-  *         read the computed digest in interrupt mode.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
-  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
-}
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
-  *         read the computed digest in interrupt mode.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
-  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- *  @brief   HMAC processing functions using DMA modes.
- *
-@verbatim
- ===============================================================================
-                 ##### DMA mode HMAC processing functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to calculate in DMA mode
-          the HMAC value using one of the following algorithms:
-      (+) MD5
-         (++) HAL_HMAC_MD5_Start_DMA()
-      (+) SHA1
-         (++) HAL_HMAC_SHA1_Start_DMA()
-
-    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
-          user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
-          with HAL_HASH_xxx_Finish().
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
-  *         DMA transfers to feed the key and the input buffer to the IP.
-  * @note   Once the DMA transfers are finished (indicated by hhash->State set back
-  *         to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
-  *         the computed digest.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
-}
-
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
-  *         DMA transfers to feed the key and the input buffer to the IP.
-  * @note   Once the DMA transfers are finished (indicated by hhash->State set back
-  *         to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
-  *         the computed digest.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
- *  @brief   Peripheral State functions.
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State methods #####
- ===============================================================================
-    [..]
-    This section permits to get in run-time the state and the peripheral handle
-    status of the peripheral:
-      (+) HAL_HASH_GetState()
-      (+) HAL_HASH_GetStatus()
-
-    [..]
-    Additionally, this subsection provides functions allowing to save and restore
-    the HASH or HMAC processing context in case of calculation suspension:
-      (+) HAL_HASH_ContextSaving()
-      (+) HAL_HASH_ContextRestoring()
-
-    [..]
-    This subsection provides functions allowing to suspend the HASH processing
-      (+) when input are fed to the IP by software
-          (++) HAL_HASH_SwFeed_ProcessSuspend()
-      (+) when input are fed to the IP by DMA
-          (++) HAL_HASH_DMAFeed_ProcessSuspend()
-
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the HASH handle state.
-  * @note   The API yields the current state of the handle (BUSY, READY,...).
-  * @param  hhash: HASH handle.
-  * @retval HAL HASH state
-  */
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
-{
-  return hhash->State;
-}
-
-
-/**
-  * @brief Return the HASH HAL status.
-  * @note  The API yields the HAL status of the handle: it is the result of the
-  *        latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
-  * @param  hhash: HASH handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
-{
-  return hhash->Status;
-}
-
-/**
-  * @brief  Save the HASH context in case of processing suspension.
-  * @param  hhash: HASH handle.
-  * @param  pMemBuffer: pointer to the memory buffer where the HASH context
-  *         is saved.
-  * @note   The IMR, STR, CR then all the CSR registers are saved
-  *         in that order. Only the r/w bits are read to be restored later on.
-  * @note   By default, all the context swap registers (there are
-  *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
-  * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
-  *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
-  * @retval None
-  */
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
-{
-  uint32_t mem_ptr = (uint32_t)pMemBuffer;
-  uint32_t csr_ptr = (uint32_t)HASH->CSR;
-  uint32_t i;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* Save IMR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
-  mem_ptr+=4U;
-  /* Save STR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
-  mem_ptr+=4U;
-  /* Save CR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY);
-  mem_ptr+=4U;
-  /* By default, save all CSRs registers */
-  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
-  {
-    *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
-    mem_ptr+=4U;
-    csr_ptr+=4U;
-  }
-}
-
-
-/**
-  * @brief  Restore the HASH context in case of processing resumption.
-  * @param  hhash: HASH handle.
-  * @param  pMemBuffer: pointer to the memory buffer where the HASH context
-  *         is stored.
-  * @note   The IMR, STR, CR then all the CSR registers are restored
-  *         in that order. Only the r/w bits are restored.
-  * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
-  *         of those) are restored (all of them have been saved by default
-  *         beforehand).
-  * @retval None
-  */
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
-{
-  uint32_t mem_ptr = (uint32_t)pMemBuffer;
-  uint32_t csr_ptr = (uint32_t)HASH->CSR;
-  uint32_t i;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hhash);
-
-  /* Restore IMR register content */
-  WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
-  /* Restore STR register content */
-  WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
-  /* Restore CR register content */
-  WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
-
-  /* Reset the HASH processor before restoring the Context
-  Swap Registers (CSR) */
-  __HAL_HASH_INIT();
-
-  /* By default, restore all CSR registers */
-  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
-  {
-    WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
-    mem_ptr+=4U;
-    csr_ptr+=4U;
-  }
-}
-
-
-/**
-  * @brief  Initiate HASH processing suspension when in polling or interruption mode.
-  * @param  hhash: HASH handle.
-  * @note   Set the handle field SuspendRequest to the appropriate value so that
-  *         the on-going HASH processing is suspended as soon as the required
-  *         conditions are met. Note that the actual suspension is carried out
-  *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
-  *         interruption mode.
-  * @retval None
-  */
-void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
-{
-  /* Set Handle Suspend Request field */
-  hhash->SuspendRequest = HAL_HASH_SUSPEND;
-}
-
-/**
-  * @brief  Suspend the HASH processing when in DMA mode.
-  * @param  hhash: HASH handle.
-  * @note   When suspension attempt occurs at the very end of a DMA transfer and
-  *         all the data have already been entered in the IP, hhash->State is
-  *         set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
-  *         recommended to wrap-up the processing in reading the digest as usual.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
-{
-  uint32_t tmp_remaining_DMATransferSize_inWords;
-  uint32_t tmp_initial_DMATransferSize_inWords;
-  uint32_t tmp_words_already_pushed;
-
-  if (hhash->State == HAL_HASH_STATE_READY)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-
-   /* Make sure there is enough time to suspend the processing */
-    tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
-
-    if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
-    {
-      /* No suspension attempted since almost to the end of the transferred data. */
-      /* Best option for user code is to wrap up low priority message hashing     */
-      return HAL_ERROR;
-    }
-
-    /* Wait for DMAS to be reset */
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
-    {
-       return HAL_TIMEOUT;
-    }
-
-    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Wait for DMAS to be set */
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
-    {
-       return HAL_TIMEOUT;
-    }
-    /* Disable DMA channel */
-    /* Note that the Abort function will
-      - Clear the transfer error flags
-      - Unlock
-      - Set the State
-    */
-    if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Clear DMAE bit */
-    CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
-
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
-    {
-      return HAL_ERROR;
-    }
-
-    /* At this point, DMA interface is disabled and no transfer is on-going */
-    /* Retrieve from the DMA handle how many words remain to be written */
-    tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
-
-    if (tmp_remaining_DMATransferSize_inWords == 0U)
-    {
-      /* All the DMA transfer is actually done. Suspension occurred at the very end
-         of the transfer. Either the digest computation is about to start (HASH case)
-         or processing is about to move from one step to another (HMAC case).
-         In both cases, the processing can't be suspended at this point. It is
-         safer to
-         - retrieve the low priority block digest before starting the high
-           priority block processing (HASH case)
-         - re-attempt a new suspension (HMAC case)
-         */
-      return HAL_ERROR;
-    }
-    else
-    {
-
-      /* Compute how many words were supposed to be transferred by DMA */
-      tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ?  ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
-
-      /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
-        by HASH IP, correct it */
-      /* tmp_words_already_pushed reflects the number of words that were already pushed before
-         the start of DMA transfer (multi-buffer processing case) */
-      tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
-      if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U)  != HASH_NBW_PUSHED())
-      {
-        tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
-      }
-
-      /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
-      hhash->pHashInBuffPtr +=  4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
-
-      /* And store in HashInCount the remaining size to transfer (in bytes) */
-      hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
-
-    }
-
-    /* Set State as suspended */
-    hhash->State = HAL_HASH_STATE_SUSPENDED;
-
-    return HAL_OK;
-
+  uint32_t tickstart = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
   }
-}
-
-/**
-  * @brief  Return the HASH handle error code.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure.
-  * @retval HASH Error Code
-*/
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
-{
-  /* Return HASH Error Code */
-  return hhash->ErrorCode;
-}
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Private_Functions HASH Private Functions
-  * @{
-  */
-
-/**
-  * @brief DMA HASH Input Data transfer completion callback.
-  * @param hdma: DMA handle.
-  * @note  In case of HMAC processing, HASH_DMAXferCplt() initiates
-  *        the next DMA transfer for the following HMAC step.
-  * @retval None
-  */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint32_t inputaddr;
-  uint32_t buffersize;
-  HAL_StatusTypeDef status ;
   
-  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
   {
-    
-    /* Disable the DMA transfer */
-    CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
-    
-    if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
-    {
-      /* If no HMAC processing, input data transfer is now over */
-      
-      /* Change the HASH state to ready */
-      hhash->State = HAL_HASH_STATE_READY;
-      
-      /* Call Input data transfer complete call back */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-      hhash->InCpltCallback(hhash);
-#else
-      HAL_HASH_InCpltCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-      
-    }
-    else
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* HMAC processing: depending on the current HMAC step and whether or
-      not multi-buffer processing is on-going, the next step is initiated
-      and MDMAT bit is set.  */
-      
-      
-      if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
-      {
-        /* This is the end of HMAC processing */
-        
-        /* Change the HASH state to ready */
-        hhash->State = HAL_HASH_STATE_READY;
-        
-        /* Call Input data transfer complete call back
-        (note that the last DMA transfer was that of the key
-        for the outer HASH operation). */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-        hhash->InCpltCallback(hhash);
-#else
-        HAL_HASH_InCpltCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-        
-        return;
-      }
-      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
-        inputaddr = (uint32_t)hhash->pHashMsgBuffPtr;     /* DMA transfer start address */
-        buffersize = hhash->HashBuffSize;                 /* DMA transfer size (in bytes) */
-        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
         
-        /* In case of suspension request, save the new starting parameters */
-        hhash->HashInCount = hhash->HashBuffSize;         /* Initial DMA transfer size (in bytes) */
-        hhash->pHashInBuffPtr  = hhash->pHashMsgBuffPtr ; /* DMA transfer start address           */
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
         
-        hhash->NbWordsAlreadyPushed = 0U;                  /* Reset number of words already pushed */
-      }
-      else  /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
-      {
-        if (hhash->DigestCalculationDisable != RESET)
-        {
-          /* No automatic move to Step 3 as a new message buffer will be fed to the IP
-          (case of multi-buffer HMAC processing):
-          DCAL must not be set.
-          Phase remains in Step 2, MDMAT remains set at this point.
-          Change the HASH state to ready and call Input data transfer complete call back. */
-          hhash->State = HAL_HASH_STATE_READY;
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-          hhash->InCpltCallback(hhash);
-#else
-          HAL_HASH_InCpltCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-          return ;
-        }
-        else
-        {
-          /* Digest calculation is not disabled (case of single buffer input or last buffer
-          of multi-buffer HMAC processing) */
-          inputaddr = (uint32_t)hhash->Init.pKey;       /* DMA transfer start address */
-          buffersize = hhash->Init.KeySize;             /* DMA transfer size (in bytes) */
-          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;    /* Move phase from Step 2 to Step 3 */
-          /* In case of suspension request, save the new starting parameters */
-          hhash->HashInCount = hhash->Init.KeySize;     /* Initial size for second DMA transfer (input data) */
-          hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* address passed to DMA, now entering data message */
-          
-          hhash->NbWordsAlreadyPushed = 0U;              /* Reset number of words already pushed */
-        }
-      }
-   
-    /* Configure the Number of valid bits in last word of the message */
-    __HAL_HASH_SET_NBVALIDBITS(buffersize);
-
-      /* Set the HASH DMA transfert completion call back */
-      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-     
-      /* Enable the DMA In DMA Stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
-
-    /* Enable DMA requests */
-    SET_BIT(HASH->CR, HASH_CR_DMAE);
-    
-          /* Return function status */
-      if (status != HAL_OK)
-      {
-        /* Update DAC state machine to error */
-        hhash->State = HAL_HASH_STATE_ERROR;      
+        return HAL_TIMEOUT;
       }
-      else
-      {
-        /* Change DAC state */
-        hhash->State = HAL_HASH_STATE_READY;
-      }     
-  }
-  }
-
-  return;
-}
-
-/**
-  * @brief DMA HASH communication error callback.
-  * @param hdma: DMA handle.
-  * @note  HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
-  *        can contain user code to manage the error.
-  * @retval None
-  */
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
-  {
-    hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
-    /* Set HASH state to ready to prevent any blocking issue in user code
-       present in HAL_HASH_ErrorCallback() */
-    hhash->State= HAL_HASH_STATE_READY;
-    /* Set HASH handle status to error */
-    hhash->Status = HAL_ERROR;
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-    hhash->ErrorCallback(hhash);
-#else
-    HAL_HASH_ErrorCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-    /* After error handling by code user, reset HASH handle HAL status */
-    hhash->Status = HAL_OK;
-
+    }
   }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+   
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
 /**
-  * @brief  Feed the input buffer to the HASH IP.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to input buffer.
-  * @param  Size: the size of input buffer in bytes.
-  * @note   HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
-  *         or not the HASH processing must be suspended. If this is the case, the
-  *         processing is suspended when possible and the IP feeding point reached at
-  *         suspension time is stored in the handle for resumption later on.
+  * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
+  *          and appending the input buffer is no more possible.
   * @retval HAL status
   */
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{
-  uint32_t buffercounter;
-  __IO uint32_t inputaddr = (uint32_t) pInBuffer;
-
-  for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
-  {
-    /* Write input data 4 bytes at a time */
-    HASH->DIN = *(uint32_t*)inputaddr;
-    inputaddr+=4U;
-
-    /* If the suspension flag has been raised and if the processing is not about
-    to end, suspend processing */
-    if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
-    {
-      /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
-      in the input buffer */
-      if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
-      {
-        /* Reset SuspendRequest */
-        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
-
-        /* Depending whether the key or the input data were fed to the IP, the feeding point
-        reached at suspension time is not saved in the same handle fields */
-        if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
-        {
-          /* Save current reading and writing locations of Input and Output buffers */
-          hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
-          /* Save the number of bytes that remain to be processed at this point */
-          hhash->HashInCount    =  Size - (buffercounter + 4U);
-        }
-        else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-        {
-          /* Save current reading and writing locations of Input and Output buffers */
-          hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
-          /* Save the number of bytes that remain to be processed at this point */
-          hhash->HashKeyCount  =  Size - (buffercounter + 4U);
-        }
-        else
-        {
-          /* Unexpected phase: unlock process and report error */
-          hhash->State = HAL_HASH_STATE_READY;
-          __HAL_UNLOCK(hhash);
-          return HAL_ERROR;
-        }
-
-        /* Set the HASH state to Suspended and exit to stop entering data */
-        hhash->State = HAL_HASH_STATE_SUSPENDED;
-
-        return HAL_OK;
-      } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))  */
-    } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
-  }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
-
-  /* At this point, all the data have been entered to the IP: exit */
-  return  HAL_OK;
-}
-
-/**
-  * @brief  Retrieve the message digest.
-  * @param  pMsgDigest: pointer to the computed digest.
-  * @param  Size: message digest size in bytes.
-  * @retval None
-  */
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
-  uint32_t msgdigest = (uint32_t)pMsgDigest;
-
-  switch(Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
   {
-    /* Read the message digest */
-    case 16:  /* MD5 */
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    break;
-    case 20:  /* SHA1 */
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    break;
-    default:
-    break;
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
   }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
-
 /**
-  * @brief  Handle HASH processing Timeout.
-  * @param  hhash: HASH handle.
-  * @param  Flag: specifies the HASH flag to check.
-  * @param  Status: the Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration.
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).  
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
   * @retval HAL status
   */
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = HAL_GetTick();
+  uint32_t tickstart = 0;   
 
-  /* Wait until flag is set */
-  if(Status == RESET)
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
   {
-    while(__HAL_HASH_GET_FLAG(Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
-        {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          /* Store time out issue in handle status */
-          hhash->Status = HAL_TIMEOUT;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
   }
-  else
-  {
-    while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
     {
       /* Check for the Timeout */
       if(Timeout != HAL_MAX_DELAY)
       {
-        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
         {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          /* Store time out issue in handle status */
-          hhash->Status = HAL_TIMEOUT;
-
+          /* Change state */
+          hhash->State = HAL_HASH_STATE_TIMEOUT;
+          
           /* Process Unlocked */
           __HAL_UNLOCK(hhash);
-
+          
           return HAL_TIMEOUT;
         }
       }
     }
-  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
   return HAL_OK;
 }
 
-
 /**
-  * @brief  HASH processing in interruption mode.
-  * @param  hhash: HASH handle.
-  * @note   HASH_IT() regularly reads hhash->SuspendRequest to check whether
-  *         or not the HASH processing must be suspended. If this is the case, the
-  *         processing is suspended when possible and the IP feeding point reached at
-  *         suspension time is stored in the handle for resumption later on.
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
   * @retval HAL status
   */
-static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  if (hhash->State == HAL_HASH_STATE_BUSY)
-  {
-    /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
-    if(hhash->HashITCounter == 0U)
-    {
-      /* Disable Interrupts */
-      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-      /* HASH state set back to Ready to prevent any issue in user code
-         present in HAL_HASH_ErrorCallback() */
-      hhash->State = HAL_HASH_STATE_READY;
-      return HAL_ERROR;
-    }
-    else if (hhash->HashITCounter == 1U)
-    {
-     /* This is the first call to HASH_IT, the first input data are about to be
-        entered in the IP. A specific processing is carried out at this point to
-        start-up the processing. */
-      hhash->HashITCounter = 2U;
-    }
-    else
-    {
-      /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
-        the HASH processing or the end of the current step for HMAC processing. */
-      hhash->HashITCounter = 3U;
-    }
-
-    /* If digest is ready */
-    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
-    {
-      /* Read the digest */
-      HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
-
-      /* Disable Interrupts */
-      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
-      /* Call digest computation complete call back */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-      hhash->DgstCpltCallback(hhash);
-#else
-      HAL_HASH_DgstCpltCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-      return HAL_OK;
-    }
-
-    /* If IP ready to accept new data */
-    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
-    {
-
-      /* If the suspension flag has been raised and if the processing is not about
-         to end, suspend processing */
-      if ( (hhash->HashInCount != 0U) &&  (hhash->SuspendRequest == HAL_HASH_SUSPEND))
-      {
-        /* Disable Interrupts */
-        __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
-        /* Reset SuspendRequest */
-        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
-
-        /* Change the HASH state */
-        hhash->State = HAL_HASH_STATE_SUSPENDED;
-
-        return HAL_OK;
-      }
-
-      /* Enter input data in the IP thru HASH_Write_Block_Data() call and
-        check whether the digest calculation has been triggered */
-      if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
-      {
-        /* Call Input data transfer complete call back
-           (called at the end of each step for HMAC) */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-        hhash->InCpltCallback(hhash);
-#else
-        HAL_HASH_InCpltCallback(hhash);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-        if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
-        {
-          /* Wait until IP is not busy anymore */
-          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
-          {
-            /* Disable Interrupts */
-            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-            return HAL_TIMEOUT;
-          }
-          /* Initialization start for HMAC STEP 2 */
-          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
-          __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
-          hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
-          hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
-          hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
-          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
-        }
-        else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
-        {
-          /* Wait until IP is not busy anymore */
-          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
-          {
-            /* Disable Interrupts */
-            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-            return HAL_TIMEOUT;
-          }
-          /* Initialization start for HMAC STEP 3 */
-          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;         /* Move phase from Step 2 to Step 3 */
-          __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */
-          hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */
-          hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */
-          hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
-          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */
-        }
-        else
-        {
-          /* Nothing to do */
-        }
-      } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
-    }  /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
+  
+  /* Check the parameters */
+  assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
   {
-    return HAL_BUSY;
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
   }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
 /**
-  * @brief  Write a block of data in HASH IP in interruption mode.
-  * @param  hhash: HASH handle.
-  * @note   HASH_Write_Block_Data() is called under interruption by HASH_IT().
-  * @retval HAL status
+  * @}
   */
-static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
-{
-  uint32_t inputaddr;
-  uint32_t buffercounter;
-  uint32_t inputcounter;
-  uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
 
-  /* If there are more than 64 bytes remaining to be entered */
-  if(hhash->HashInCount > 64U)
-  {
-    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-    /* Write the Input block in the Data IN register
-      (16 32-bit words, or 64 bytes are entered) */
-    for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
-    {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      inputaddr+=4U;
-    }
-    /* If this is the start of input data entering, an additional word
-      must be entered to start up the HASH processing */
-    if(hhash->HashITCounter == 2U)
-    {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      if(hhash->HashInCount >= 68U)
-      {
-        /* There are still data waiting to be entered in the IP.
-           Decrement buffer counter and set pointer to the proper
-           memory location for the next data entering round. */
-        hhash->HashInCount -= 68U;
-        hhash->pHashInBuffPtr+= 68U;
-      }
-      else
-      {
-        /* All the input buffer has been fed to the HW. */
-        hhash->HashInCount = 0U;
-      }
-    }
-    else
-    {
-      /* 64 bytes have been entered and there are still some remaining:
-         Decrement buffer counter and set pointer to the proper
-        memory location for the next data entering round.*/
-      hhash->HashInCount -= 64U;
-      hhash->pHashInBuffPtr+= 64U;
-    }
-  }
-  else
-  {
-    /* 64 or less bytes remain to be entered. This is the last
-      data entering round. */
-
-    /* Get the buffer address */
-    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-    /* Get the buffer counter */
-    inputcounter = hhash->HashInCount;
-    /* Disable Interrupts */
-    __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
-
-    /* Write the Input block in the Data IN register */
-    for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
-    {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      inputaddr+=4U;
-    }
-    /* Start the Digest calculation */
-    __HAL_HASH_START_DIGEST();
-    /* Return indication that digest calculation has started:
-       this return value triggers the call to Input data transfer
-       complete call back as well as the proper transition from
-       one step to another in HMAC mode. */
-    ret = HASH_DIGEST_CALCULATION_STARTED;
-    /* Reset buffer counter */
-    hhash->HashInCount = 0;
-  }
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
+ *  @brief   processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using interrupt mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
 
-  /* Return whether or digest calculation has started */
-  return ret;
-}
+@endverbatim
+  * @{
+  */
 
 /**
-  * @brief  HMAC processing in polling mode.
-  * @param  hhash: HASH handle.
-  * @param  Timeout: Timeout value.
+  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).   
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
   * @retval HAL status
   */
-static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  /* Ensure first that Phase is correct */
-  if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  if(hhash->State == HAL_HASH_STATE_READY)
   {
     /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_READY;
-
-    /* Process Unlock */
-    __HAL_UNLOCK(hhash);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-  /* HMAC Step 1 processing */
-  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
-  {
-    /************************** STEP 1 ******************************************/
-    /* Configure the Number of valid bits in last word of the message */
-    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
-    /* Write input buffer in Data register */
-    hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
-    if (hhash->Status != HAL_OK)
-    {
-      return hhash->Status;
-    }
-
-    /* Check whether or not key entering process has been suspended */
-    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhash);
-
-      /* Stop right there and return function status */
-      return HAL_OK;
-    }
-
-    /* No processing suspension at this point: set DCAL bit. */
-    __HAL_HASH_START_DIGEST();
-
-    /* Wait for BUSY flag to be cleared */
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
     {
-      return HAL_TIMEOUT;
+      /* Select the SHA1 mode */
+      HASH->CR |= HASH_ALGOSELECTION_MD5;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
     }
-
-    /* Move from Step 1 to Step 2 */
-    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
-
+    /* Reset interrupt counter */
+    hhash->HashITCounter = 0;
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
   }
-
-  /* HMAC Step 2 processing.
-     After phase check, HMAC_Processing() may
-     - directly start up from this point in resumption case
-       if the same Step 2 processing was suspended previously
-    - or fall through from the Step 1 processing carried out hereabove */
-  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
   {
-    /************************** STEP 2 ******************************************/
-    /* Configure the Number of valid bits in last word of the message */
-    __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
-
-    /* Write input buffer in Data register */
-    hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
-    if (hhash->Status != HAL_OK)
-    {
-      return hhash->Status;
-    }
-
-    /* Check whether or not data entering process has been suspended */
-    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+    
+    if(hhash->HashInCount == 0)
     {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
+      
       /* Process Unlocked */
       __HAL_UNLOCK(hhash);
-
-      /* Stop right there and return function status */
+      
+      /* Return function status */
       return HAL_OK;
     }
-
-    /* No processing suspension at this point: set DCAL bit. */
-    __HAL_HASH_START_DIGEST();
-
-    /* Wait for BUSY flag to be cleared */
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Move from Step 2 to Step 3 */
-    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
-    /* In case Step 1 phase was suspended then resumed,
-       set again Key input buffers and size before moving to
-       next step */
-    hhash->pHashKeyBuffPtr = hhash->Init.pKey;
-    hhash->HashKeyCount    = hhash->Init.KeySize;
   }
-
-
- /* HMAC Step 3 processing.
-     After phase check, HMAC_Processing() may
-     - directly start up from this point in resumption case
-       if the same Step 3 processing was suspended previously
-    - or fall through from the Step 2 processing carried out hereabove */
-  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
   {
-    /************************** STEP 3 ******************************************/
-    /* Configure the Number of valid bits in last word of the message */
-    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
-    /* Write input buffer in Data register */
-    hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
-    if (hhash->Status != HAL_OK)
+    if(hhash->HashInCount >= 68)
     {
-      return hhash->Status;
-    }
-
-    /* Check whether or not key entering process has been suspended */
-    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhash);
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      if(hhash->HashITCounter == 0)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
 
-      /* Stop right there and return function status */
-      return HAL_OK;
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount = 0;
+          hhash->pHashInBuffPtr+= hhash->HashInCount;
+        }
+        /* Set Interrupt counter */
+        hhash->HashITCounter = 1;
+      }
+      else
+      {
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
+      }
     }
-
-    /* No processing suspension at this point: start the Digest calculation. */
-    __HAL_HASH_START_DIGEST();
-
-    /* Wait for DCIS flag to be set */
-     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    else
     {
-      return HAL_TIMEOUT;
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+      
+      if((inputcounter > 4) && (inputcounter%4))
+      {
+        inputcounter = (inputcounter+4-inputcounter%4);
+      }
+      else if ((inputcounter < 4) && (inputcounter != 0))
+      {
+        inputcounter = 4;
+      }
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+      
+      /* Call Input data transfer complete callback */
+      HAL_HASH_InCpltCallback(hhash);
     }
-
-    /* Read the message digest */
-    HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
   }
 
-   /* Change the HASH state */
-   hhash->State = HAL_HASH_STATE_READY;
-
-   /* Process Unlock */
-   __HAL_UNLOCK(hhash);
-
-   /* Return function status */
-   return HAL_OK;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
 /**
-  * @brief  Initialize the HASH peripheral, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest.
-  * @param  Timeout: Timeout value.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
-  uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
-  HAL_HASH_StateTypeDef State_tmp = hhash->State; 
-
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
   
-  /* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  {  
-    /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
     {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
+      /* Select the SHA1 mode */
+      HASH->CR |= HASH_ALGOSELECTION_SHA1;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
     }
     
-    /* Process Locked */
-    __HAL_LOCK(hhash);
+    /* Reset interrupt counter */
+    hhash->HashITCounter = 0;
     
-    /* Check if initialization phase has not been already performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+  {
+    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
+    if(hhash->HashInCount == 0)
     {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
       /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-      
-      /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-      
-      /* Configure the number of valid bits in last word of the message */
-      __HAL_HASH_SET_NBVALIDBITS(Size);
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
       
-      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
-      input parameters of HASH_WriteData() */
-      pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
-      Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
       
-      /* Set the phase */
-      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+      /* Return function status */
+      return HAL_OK;
     }
-    else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+  {
+    if(hhash->HashInCount >= 68)
     {
-      /* if the IP has already been initialized, two cases are possible */
-      
-      /* Process resumption time ... */
-      if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      if(hhash->HashITCounter == 0)
       {
-        /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
-        to the API input parameters but to those saved beforehand by HASH_WriteData()
-        when the processing was suspended */
-        pInBuffer_tmp = hhash->pHashInBuffPtr;
-        Size_tmp = hhash->HashInCount;
+        HASH->DIN = *(uint32_t*)inputaddr;
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount = 0;
+          hhash->pHashInBuffPtr+= hhash->HashInCount;
+        }
+        /* Set Interrupt counter */
+        hhash->HashITCounter = 1;
       }
-      /* ... or multi-buffer HASH processing end */
       else
       {
-        /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
-        input parameters of HASH_WriteData() */
-        pInBuffer_tmp = pInBuffer;
-        Size_tmp = Size;
-        /* Configure the number of valid bits in last word of the message */
-        __HAL_HASH_SET_NBVALIDBITS(Size);
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
       }
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
     }
     else
     {
-      /* Phase error */
-      hhash->State = HAL_HASH_STATE_READY;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhash);
-      
-      /* Return function status */
-      return HAL_ERROR;
-    }
-    
-    
-    /* Write input buffer in Data register */
-    hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
-    if (hhash->Status != HAL_OK)
-    {
-      return hhash->Status;
-    }
-    
-    /* If the process has not been suspended, carry on to digest calculation */
-    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
-    {
-      /* Start the Digest calculation */
-      __HAL_HASH_START_DIGEST();
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
       
-      /* Wait for DCIS flag to be set */
-      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+      if((inputcounter > 4) && (inputcounter%4))
       {
-        return HAL_TIMEOUT;
+        inputcounter = (inputcounter+4-inputcounter%4);
       }
-      
-      /* Read the message digest */
-      HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-      
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
-      
+      else if ((inputcounter < 4) && (inputcounter != 0))
+      {
+        inputcounter = 4;
+      }
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+
+      /* Call Input data transfer complete callback */
+      HAL_HASH_InCpltCallback(hhash);
     }
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hhash);
-    
-    /* Return function status */
-    return HAL_OK;
-    
   }
-  else
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles HASH interrupt request.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+  switch(HASH->CR & HASH_CR_ALGO)
   {
-    return HAL_BUSY;
+    case HASH_ALGOSELECTION_MD5:
+       HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    case HASH_ALGOSELECTION_SHA1:
+      HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    default:
+    break;
   }
 }
 
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
+ *  @brief   processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using DMA mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
 
 /**
-  * @brief  If not already done, initialize the HASH peripheral then
-  *         processes pInBuffer.
-  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
-  *         the IP has already been initialized.
-  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
-  *         HASH digest computation is corrupted.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to
+            control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
-  uint32_t Size_tmp;  /* input data size (in bytes), input parameter of HASH_WriteData() */
-  HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+  }
    
-  /* Make sure the input buffer size (in bytes) is a multiple of 4 */
-   assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
-
-  /* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  { 
-    /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U))
-    {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
-    }
-
-     /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* If resuming the HASH processing */
-    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
-    {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
 
-      /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
-         to the API input parameters but to those saved beforehand by HASH_WriteData()
-         when the processing was suspended */
-      pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
-      Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
+/**
+  * @brief  Returns the computed digest in MD5 mode
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-    }
-    else
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-
-      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
-         input parameters of HASH_WriteData() */
-      pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */
-      Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */
-
-      /* Check if initialization phase has already be performed */
-      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
-        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
       }
-
-      /* Set the phase */
-      hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
-    }
-
-    /* Write input buffer in Data register */
-    hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
-    if (hhash->Status != HAL_OK)
-    {
-      return hhash->Status;
-    }
-
-    /* If the process has not been suspended, move the state to Ready */
-    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
-    {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
     }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hhash);
-
-    /* Return function status */
-    return HAL_OK;
-
-  }
-  else
-  {
-    return HAL_BUSY;
   }
-
-
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+      
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
 /**
-  * @brief  Initialize the HASH peripheral, next process pInBuffer then
-  *         read the computed digest in interruption mode.
-  * @note   Digest is available in pOutBuffer.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to
+            control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-   HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
-  /* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  {     
-    /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
-    {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_BUSY;
-
-    /* Initialize IT counter */
-    hhash->HashITCounter = 1;
-
-    /* Check if initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
-      /* Configure the number of valid bits in last word of the message */
-     __HAL_HASH_SET_NBVALIDBITS(Size);
-
-
-      hhash->HashInCount = Size;               /* Counter used to keep track of number of data
-                                                  to be fed to the IP */
-      hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the IP at
-                                                  the next interruption */
-     /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
-        the information describing where the HASH process is stopped.
-        These variables are used later on to resume the HASH processing at the
-        correct location. */
-
-      hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
-    }
-
-    /* Set the phase */
-    hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
-    /* Process Unlock */
-    __HAL_UNLOCK(hhash);
-
-    /* Enable Interrupts */
-    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
   {
-    return HAL_BUSY;
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_ALGOSELECTION_SHA1;
+    HASH->CR |= HASH_CR_INIT;
   }
-
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
 /**
-  * @brief  Initialize the HASH peripheral then initiate a DMA transfer
-  *         to feed the input buffer to the IP.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Returns the computed digest in SHA1 mode.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.  
+  * @param  Timeout: Timeout value    
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t inputaddr;
-  uint32_t inputSize;
-  HAL_StatusTypeDef status ;
-  HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
-   /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  { 
-    /* Check input parameters */
-    if ( (pInBuffer == NULL ) || (Size == 0U) ||
-    /* Check phase coherency. Phase must be
-       either READY (fresh start)
-       or PROCESS (multi-buffer HASH management) */
-       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
-    {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
-    }
-
-
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* If not a resumption case */
-    if (hhash->State == HAL_HASH_STATE_READY)
+  uint32_t tickstart = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-
-      /* Check if initialization phase has already been performed.
-         If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
-         API is processing a new input data message in case of multi-buffer HASH
-         computation. */
-      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
       {
-        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
-        /* Set the phase */
-        hhash->Phase = HAL_HASH_PHASE_PROCESS;
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
       }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process UnLock */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
 
-      /* Configure the Number of valid bits in last word of the message */
-      __HAL_HASH_SET_NBVALIDBITS(Size);
 
-      inputaddr = (uint32_t)pInBuffer;     /* DMA transfer start address   */
-      inputSize = Size;                    /* DMA transfer size (in bytes) */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode 
+ *  @brief   HMAC processing functions using polling mode . 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HMAC processing using polling mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
 
-      /* In case of suspension request, save the starting parameters */
-      hhash->pHashInBuffPtr =  pInBuffer;  /* DMA transfer start address   */
-      hhash->HashInCount = Size;           /* DMA transfer size (in bytes) */
+@endverbatim
+  * @{
+  */
 
+/**
+  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
     }
-    /* If resumption case */
     else
     {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-
-      /* Resumption case, inputaddr and inputSize are not set to the API input parameters
-         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
-         processing was suspended */
-      inputaddr = (uint32_t)hhash->pHashInBuffPtr;  /* DMA transfer start address   */
-      inputSize = hhash->HashInCount;               /* DMA transfer size (in bytes) */
-
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
     }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-    /* Set the HASH DMA transfert complete callback */
-    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-    /* Set the DMA error callback */
-    hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
-    /* Store number of words already pushed to manage proper DMA processing suspension */
-    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
-
-    /* Enable the DMA In DMA Stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
-    
-    /* Enable DMA requests */
-    SET_BIT(HASH->CR, HASH_CR_DMAE);
-    
-    /* Process Unlock */
-    __HAL_UNLOCK(hhash);
-    
-    /* Return function status */
-    if (status != HAL_OK)
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Update HASH state machine to error */
-      hhash->State = HAL_HASH_STATE_ERROR;      
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
     }
-    else
+  }
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Change HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
     }
-    
-    return status;
   }
-  else
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
   {
-    return HAL_BUSY;
-  } 
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
 /**
-  * @brief  Return the computed digest.
-  * @note   The API waits for DCIS to be set then reads the computed digest.
-  * @param  hhash: HASH handle.
-  * @param  pOutBuffer: pointer to the computed digest.
-  * @param  Timeout: Timeout value.
+  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param   Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-
-  if(hhash->State == HAL_HASH_STATE_READY)
+  uint32_t tickstart = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
   {
-    /* Check parameter */
-    if (pOutBuffer == NULL)
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
     {
-      return  HAL_ERROR;
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
     }
-
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* Change the HASH state to busy */
-    hhash->State = HAL_HASH_STATE_BUSY;
-
-    /* Wait for DCIS flag to be set */
-    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    else
     {
-      return HAL_TIMEOUT;
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
     }
-
-    /* Read the message digest */
-    HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
-    /* Change the HASH state to ready */
-    hhash->State = HAL_HASH_STATE_READY;
-
-    /* Process UnLock */
-    __HAL_UNLOCK(hhash);
-
-    /* Return function status */
-    return HAL_OK;
-
   }
-  else
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
   {
-    return HAL_BUSY;
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
   }
-
-}
-
-
-/**
-  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
-  *         read the computed digest.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest.
-  * @param  Timeout: Timeout value.
-  * @param  Algorithm: HASH algorithm.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
-{
-    HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */  
+  __HAL_HASH_SET_NBVALIDBITS(Size);
   
-   /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  { 
-    /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
+      if((HAL_GetTick() - tickstart ) > Timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
     }
+  }
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_BUSY;
-
-    /* Check if initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
-      if(hhash->Init.KeySize > 64U)
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-      }
-      else
+      if((HAL_GetTick() - tickstart ) > Timeout)
       {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
       }
-      /* Set the phase to Step 1 */
-      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-      /* Resort to hhash internal fields to feed the IP.
-         Parameters will be updated in case of suspension to contain the proper
-         information at resumption time. */
-      hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
-      hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
-      hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
-      hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */
-      hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
-      hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */
     }
-
-    /* Carry out HMAC processing */
-    return HMAC_Processing(hhash, Timeout);
-
-  }
-  else
-  {
-    return HAL_BUSY;
   }
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode 
+ *  @brief   HMAC processing functions using DMA mode . 
+ *
+@verbatim   
+ ===============================================================================
+                ##### HMAC processing using DMA mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
 
+@endverbatim
+  * @{
+  */
 
 /**
-  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
-  *         read the computed digest in interruption mode.
-  * @note   Digest is available in pOutBuffer.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  pOutBuffer: pointer to the computed digest.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
   * @retval HAL status
   */
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-    HAL_HASH_StateTypeDef State_tmp = hhash->State; 
-    
-  /* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  { 
-    /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
-    {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_BUSY;
-
-    /* Initialize IT counter */
-    hhash->HashITCounter = 1;
-
-    /* Check if initialization phase has already be performed */
-    if (hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
-      if(hhash->Init.KeySize > 64U)
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-      }
-      else
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-      }
-
-      /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
-         to feed the IP whatever the HMAC step.
-         Lines below are set to start HMAC Step 1 processing where key is entered first. */
-      hhash->HashInCount     = hhash->Init.KeySize; /* Key size                      */
-      hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* Key address                   */
-
-      /* Store input and output parameters in handle fields to manage steps transition
-         or possible HMAC suspension/resumption */
-      hhash->pHashKeyBuffPtr = hhash->Init.pKey;    /* Key address                   */
-      hhash->pHashMsgBuffPtr = pInBuffer;           /* Input message address         */
-      hhash->HashBuffSize    = Size;                /* Input message size (in bytes) */
-      hhash->pHashOutBuffPtr = pOutBuffer;          /* Output digest address         */
-
-      /* Configure the number of valid bits in last word of the key */
-      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
-      /* Set the phase to Step 1 */
-      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-    }
-    else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-    {
-      /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
-
-    }
-    else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+  uint32_t inputaddr  = 0;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
     {
-      /* Restart IT-based HASH processing after Step 2 suspension */
-
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
     }
     else
     {
-      /* Error report as phase incorrect */
-      /* Process Unlock */
-      __HAL_UNLOCK(hhash);
-      hhash->State = HAL_HASH_STATE_READY;
-      return HAL_ERROR;
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
     }
-
-    /* Process Unlock */
-    __HAL_UNLOCK(hhash);
-
-    /* Enable Interrupts */
-    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
   }
-
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
 }
 
-
-
 /**
-  * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required
-  *         DMA transfers to feed the key and the input buffer to the IP.
-  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
-  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
-  * @note   In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
-  *         be a multiple of 4 otherwise, the HASH digest computation is corrupted.
-  *         Only the length of the last buffer of the thread doesn't have to be a
-  *         multiple of 4.
-  * @param  hhash: HASH handle.
-  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
-  * @param  Size: length of the input buffer in bytes.
-  * @param  Algorithm: HASH algorithm.
+  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
   * @retval HAL status
   */
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  uint32_t inputaddr;
-  uint32_t inputSize;
-  HAL_StatusTypeDef status ;
-  HAL_HASH_StateTypeDef State_tmp = hhash->State;  
-  /* If State is ready or suspended, start or resume DMA-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
-  {   
-    /* Check input parameters */
-    if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
-   /* Check phase coherency. Phase must be
-       either READY (fresh start)
-       or one of HMAC PROCESS steps (multi-buffer HASH management) */
-       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
-    {
-      hhash->State = HAL_HASH_STATE_READY;
-      return  HAL_ERROR;
-    }
-
-
-    /* Process Locked */
-    __HAL_LOCK(hhash);
-
-    /* If not a case of resumption after suspension */
-    if (hhash->State == HAL_HASH_STATE_READY)
-    {
-    /* Check whether or not initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
-      if(hhash->Init.KeySize > 64U)
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-      }
-      else
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-      }
-      /* Store input aparameters in handle fields to manage steps transition
-         or possible HMAC suspension/resumption */
-      hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
-      hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
-      hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
-      hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
-      hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
-
-      /* Set DMA input parameters */
-      inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
-      inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
-
-      /* Configure the number of valid bits in last word of the key */
-      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
-      /* Set the phase to Step 1 */
-      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-
-    }
-      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+  uint32_t inputaddr  = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
     {
-      /* Process a new input data message in case of multi-buffer HMAC processing
-        (this is not a resumption case) */
-
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-
-      /* Save input parameters to be able to manage possible suspension/resumption */
-        hhash->HashInCount = Size;                /* Input message address       */
-        hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
-
-      /* Set DMA input parameters */
-        inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
-        inputSize = Size;                          /* Input message size in bytes */
-
-      if (hhash->DigestCalculationDisable == RESET)
-      {
-        /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
-        __HAL_HASH_SET_NBVALIDBITS(inputSize);
-      }
-    }
-      else
-      {
-        /* Phase not aligned with handle READY state */
-        __HAL_UNLOCK(hhash);
-        /* Return function status */
-        return HAL_ERROR;
-      }
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
     }
     else
     {
-       /* Resumption case (phase may be Step 1, 2 or 3) */
-
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-
-      /* Set DMA input parameters at resumption location;
-         inputaddr and inputSize are not set to the API input parameters
-         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
-         processing was suspended. */
-      inputaddr = (uint32_t)(hhash->pHashInBuffPtr);  /* Input message address       */
-      inputSize = hhash->HashInCount;                 /* Input message size in bytes */
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
     }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
 
+/**
+  * @}
+  */
 
-    /* Set the HASH DMA transfert complete callback */
-    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-    /* Set the DMA error callback */
-    hhash->hdmain->XferErrorCallback = HASH_DMAError;
-
-    /* Store number of words already pushed to manage proper DMA processing suspension */
-    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
 
-    /* Enable the DMA In DMA Stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
-    /* Enable DMA requests */
-    SET_BIT(HASH->CR, HASH_CR_DMAE);
+@endverbatim
+  * @{
+  */
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hhash);
-    
-    /* Return function status */
-    if (status != HAL_OK)
-    {
-      /* Update HASH state machine to error */
-      hhash->State = HAL_HASH_STATE_ERROR;
-    }
-    else
-    {
-      /* Change HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
-    }
-    /* Return function status */
-    return status; 
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
+/**
+  * @brief return the HASH state
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL state
+  */
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+  return hhash->State;
 }
+
 /**
   * @}
   */
 
-#endif /* HAL_HASH_MODULE_ENABLED */
-
 /**
   * @}
   */
-#endif /*  HASH*/
+#endif /* STM32F215xx || STM32F217xx */
+#endif /* HAL_HASH_MODULE_ENABLED */
 /**
   * @}
   */
 
-
+/**
+  * @}
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/