Performance fixes, scsi2sd-util crash fixes, scsi2 config option.

lib/SCSI2SD/CHANGELOG

@@ -1,3 +1,18 @@
+201507XX		4.4
+	- Added configuration option to allow SCSI2 mode. This option is OFF by
+	default, and should only be enabled when using the SCSI2SD with a SCSI2 host
+	controller. Extra timing delays are added in the default SCSI1/SASI mode to
+	work with slow hardware.
+	- Modified hot-swap card detection to work with longer (60cm) microSD to SD
+	cables.
+	- Fixed off-by-one error in scsi2sd-util "Auto" sector start feature.
+	- Fixed crashes and stalls of scsi2sd-util after saving/loading options
+	to/from the device
+	- Fixed synchronous transfer request negotiation.
+	SCSI2SD now negotiates back to async transfers instead of simply
+	rejecting the message.
+	- Fixed INQUIRY response to commands lacking an allocation length.
+
 20150614        4.3
 	- Added configurable disk geometry.
 	- Added configuration import/export function to scsi2sd-util

lib/SCSI2SD/readme.txt

@@ -78,7 +78,7 @@ Compatibility
     Atari TT030 System V
     Atari MEGA STE
         needs J3 TERMPWR jumper
-        1GB limit (--blocks=2048000) 
+        1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
     Sharp X68000
         SASI models supported. See gamesx.com for information on building a custom cable.
         needs J3 TERMPWR jumper
@@ -118,7 +118,7 @@ Samplers
     EMU E6400 w/ EOS2.80f
     EMU Emax2
     Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
-        ASR-20 Requires TERMPWR jumper.
+        ASR-10 Requires TERMPWR jumper (applies to pre. 5.0 SCSI2SD boards only)
         ASR-X resets when writing to devices > 2Gb. 
     Kurzweil K2000R
         See kurzweil.com for size limits which a dependant on the OS version. Older OS versions have a 1GB limit.

lib/SCSI2SD/software/SCSI2SD/src/disk.c

@@ -527,14 +527,24 @@ void scsiDiskPoll()
 			// systick timer interrupt saves us on the event of a race.
 			int scsiBusy = scsiDMABusy();
 			int sdBusy = sdDMABusy();
-			if (scsiBusy && sdBusy) __WFI();
+			while (scsiBusy && sdBusy)
+			{
+				__WFI();
+				scsiBusy = scsiDMABusy();
+				sdBusy = sdDMABusy();
+			}
 
 			if (sdActive && !sdBusy && sdReadSectorDMAPoll())
 			{
 				sdActive = 0;
 				prep++;
 			}
-			else if (!sdActive &&
+
+			// Usually SD is slower than the SCSI interface.
+			// Prioritise starting the read of the next sector over starting a
+			// SCSI transfer for the last sector
+			// ie. NO "else" HERE.
+			if (!sdActive &&
 				(prep - i < buffers) &&
 				(prep < totalSDSectors))
 			{
@@ -555,7 +565,7 @@ void scsiDiskPoll()
 				scsiActive = 0;
 				++i;
 			}
-			else if (!scsiActive && ((prep - i) > 0))
+			if (!scsiActive && ((prep - i) > 0))
 			{
 				int dmaBytes = SD_SECTOR_SIZE;
 				if ((i % sdPerScsi) == (sdPerScsi - 1))
@@ -603,14 +613,19 @@ void scsiDiskPoll()
 			// systick timer interrupt saves us on the event of a race.
 			int scsiBusy = scsiDMABusy();
 			int sdBusy = sdDMABusy();
-			if (scsiBusy && sdBusy) __WFI();
+			while (scsiBusy && sdBusy)
+			{
+				__WFI();
+				scsiBusy = scsiDMABusy();
+				sdBusy = sdDMABusy();
+			}
 
 			if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))
 			{
 				sdActive = 0;
 				i++;
 			}
-			else if (!sdActive && ((prep - i) > 0))
+			if (!sdActive && ((prep - i) > 0))
 			{
 				// Start an SD transfer if we have space.
 				sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);
@@ -625,7 +640,7 @@ void scsiDiskPoll()
 				++prep;
 				lastActivityTime = now;
 			}
-			else if (!scsiActive &&
+			if (!scsiActive &&
 				((prep - i) < buffers) &&
 				(prep < totalSDSectors) &&
 				likely(!scsiDisconnected))

lib/SCSI2SD/software/SCSI2SD/src/inquiry.c

@@ -98,8 +98,10 @@ void scsiInquiry()
 	uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data.
 	uint8 pageCode = scsiDev.cdb[2];
 	uint32 allocationLength = scsiDev.cdb[4];
+
+	// SASI standard, X3T9.3_185_RevE  states that 0 == 256 bytes
 	if (allocationLength == 0) allocationLength = 256;
-	
+
 	if (!evpd)
 	{
 		if (pageCode)
@@ -171,6 +173,7 @@ void scsiInquiry()
 		// with zeroes. This only seems to happen for Inquiry responses, and not
 		// other commands that also supply an allocation length such as Mode Sense or
 		// Request Sense.
+		// (See below for exception to this rule when 0 allocation length)
 		if (scsiDev.dataLen < allocationLength)
 		{
 			memset(
@@ -178,9 +181,20 @@ void scsiInquiry()
 				0,
 				allocationLength - scsiDev.dataLen);
 		}
-		// Spec 8.2.5 requires us to simply truncate the response if it's too big.
-		scsiDev.dataLen = allocationLength;
-		
+		if (scsiDev.cdb[4] == 0 && scsiDev.dataLen < allocationLength)
+		{
+			// Only send back the minimum number of bytes.
+			// Don't forcably send back 256 bytes, as that may cause problems
+			// with some machines (SGI Iris Indigo running IRIX)
+			// scsiDev.dataLen is already the correct value.
+		}
+		else
+		{
+			// Spec 8.2.5 requires us to simply truncate the response if it's
+			// too big.
+			scsiDev.dataLen = allocationLength;
+		}
+
 		// Set the device type as needed.
 		switch (scsiDev.target->cfg->deviceType)
 		{

lib/SCSI2SD/software/SCSI2SD/src/mode.c

@@ -551,7 +551,10 @@ int scsiModeCommand()
 		int pc = scsiDev.cdb[2] >> 6; // Page Control
 		int pageCode = scsiDev.cdb[2] & 0x3F;
 		int allocLength = scsiDev.cdb[4];
-		if (allocLength == 0) allocLength = 256;
+
+		// SCSI1 standard: (CCS X3T9.2/86-52)
+		// "An Allocation Length of zero indicates that no MODE SENSE data shall
+		// be transferred. This condition shall not be considered as an error."
 		doModeSense(1, dbd, pc, pageCode, allocLength);
 	}
 	else if (command == 0x5A)

lib/SCSI2SD/software/SCSI2SD/src/scsi.c

@@ -560,6 +560,10 @@ static void process_SelectionPhase()
 			target->unitAttention = 0;
 			scsiDev.compatMode = COMPAT_SCSI1;
 		}
+		else if (!(target->cfg->flags & CONFIG_ENABLE_SCSI2))
+		{
+			scsiDev.compatMode = COMPAT_SCSI1;
+		}
 		else if (scsiDev.compatMode == COMPAT_UNKNOWN)
 		{
 			scsiDev.compatMode = COMPAT_SCSI2;
@@ -723,7 +727,7 @@ static void process_MessageOut()
 			// Discard bytes.
 			extmsg[i] = scsiReadByte();
 		}
-		
+
 		if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request
 		{
 			// Negotiate down to 8bit
@@ -731,7 +735,7 @@ static void process_MessageOut()
 			static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00};
 			scsiWrite(WDTR, sizeof(WDTR));
 		}
-		else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request
+		else if (extmsg[0] == 1 && msgLen == 3) // Synchronous data request
 		{
 			// Negotiate back to async
 			scsiEnterPhase(MESSAGE_IN);

lib/SCSI2SD/software/SCSI2SD/src/scsiPhy.c

@@ -25,8 +25,9 @@
 
 #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)
 
-// DMA controller can't handle any more bytes.
-#define MAX_DMA_BYTES 4095
+// DMA controller can't handle any more than 4095 bytes,
+// but we round down to nearest multiple of 4 bytes..
+#define MAX_DMA_BYTES 4088
 
 // Private DMA variables.
 static int dmaInProgress = 0;
@@ -235,7 +236,8 @@ scsiRead(uint8_t* data, uint32_t count)
 	}
 	else
 	{
-		scsiReadDMA(data, count);
+		uint32_t alignedCount = count & 0xFFFFFFF8;
+		scsiReadDMA(data, alignedCount);
 
 		// Wait for the next DMA interrupt (or the 1ms systick)
 		// It's beneficial to halt the processor to
@@ -243,7 +245,15 @@ scsiRead(uint8_t* data, uint32_t count)
 		__WFI();
 
 		trace(trace_spinReadDMAPoll);
-		while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};
+		while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))
+		{
+			__WFI();
+		};
+
+		if (count > alignedCount)
+		{
+			scsiReadPIO(data + alignedCount, count - alignedCount);
+		}
 	}
 }
 
@@ -363,7 +373,8 @@ scsiWrite(const uint8_t* data, uint32_t count)
 	}
 	else
 	{
-		scsiWriteDMA(data, count);
+		uint32_t alignedCount = count & 0xFFFFFFF8;
+		scsiWriteDMA(data, alignedCount);
 
 		// Wait for the next DMA interrupt (or the 1ms systick)
 		// It's beneficial to halt the processor to
@@ -371,7 +382,15 @@ scsiWrite(const uint8_t* data, uint32_t count)
 		__WFI();
 
 		trace(trace_spinWriteDMAPoll);
-		while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};
+		while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))
+		{
+			__WFI();
+		};
+		
+		if (count > alignedCount)
+		{
+			scsiWritePIO(data + alignedCount, count - alignedCount);
+		}
 	}
 }
 
@@ -452,7 +471,7 @@ static void scsiPhyInitDMA()
 	{
 		scsiDmaRxChan =
 			SCSI_RX_DMA_DmaInitialize(
-				1, // Bytes per burst
+				4, // Bytes per burst
 				1, // request per burst
 				HI16(CYDEV_PERIPH_BASE),
 				HI16(CYDEV_SRAM_BASE)
@@ -460,7 +479,7 @@ static void scsiPhyInitDMA()
 
 		scsiDmaTxChan =
 			SCSI_TX_DMA_DmaInitialize(
-				1, // Bytes per burst
+				4, // Bytes per burst
 				1, // request per burst
 				HI16(CYDEV_SRAM_BASE),
 				HI16(CYDEV_PERIPH_BASE)
@@ -486,6 +505,13 @@ void scsiPhyInit()
 
 	SCSI_SEL_ISR_StartEx(scsiSelectionISR);
 
+/*
+	// Disable the glitch filter for ACK to improve performance.
+	// TODO NEED SOME CONFIG
+	SCSI_Glitch_Ctl_Write(1);
+	CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);
+*/
+
 }
 
 // 1 = DBx error

lib/SCSI2SD/software/SCSI2SD/src/sd.c

@@ -41,16 +41,18 @@ static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
 
 // Dummy location for DMA to send unchecked CRC bytes to
-static uint8 discardBuffer;
+static uint8 discardBuffer __attribute__((aligned(4)));
 
 // 2 bytes CRC, response, 8bits to close the clock..
 // "NCR" time is up to 8 bytes.
-static uint8_t writeResponseBuffer[8];
+static uint8_t writeResponseBuffer[8]  __attribute__((aligned(4)));
 
-static uint8_t writeStartToken = 0xFC;
+// Padded with a dummy byte just to allow the tx DMA channel to
+// use 2-byte bursts for performance.
+static uint8_t writeStartToken[2]  __attribute__((aligned(4))) = {0xFF, 0xFC};
 
 // Source of dummy SPI bytes for DMA
-static uint8 dummyBuffer = 0xFF;
+static uint8_t dummyBuffer[2]  __attribute__((aligned(4))) = {0xFF, 0xFF};
 
 volatile uint8_t sdRxDMAComplete;
 volatile uint8_t sdTxDMAComplete;
@@ -109,7 +111,8 @@ static uint16_t sdDoCommand(
 
 	// send is static as the address must remain consistent for the static
 	// DMA descriptors to work.
-	static uint8_t send[7];
+	// Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.
+	static uint8_t send[6] __attribute__((aligned(4)));
 	send[0] = cmd | 0x40;
 	send[1] = param >> 24;
 	send[2] = param >> 16;
@@ -123,7 +126,6 @@ static uint16_t sdDoCommand(
 	{
 		send[5] = 1; // stop bit
 	}
-	send[6] = 0xFF; // Result code or stuff byte.
 
 	static uint8_t dmaRxTd = CY_DMA_INVALID_TD;
 	static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
@@ -161,7 +163,7 @@ static uint16_t sdDoCommand(
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
-	CyDmaClearPendingDrq(sdDMATxChan);
+	CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
 	CyDmaClearPendingDrq(sdDMARxChan);
 
 	// There is no flow control, so we must ensure we can read the bytes
@@ -172,7 +174,7 @@ static uint16_t sdDoCommand(
 	trace(trace_spinSDDMA);
 	while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }
 
-	uint16_t response = discardBuffer;
+	uint16_t response = sdSpiByte(0xFF); // Result code or stuff byte
 	if (unlikely(cmd == SD_STOP_TRANSMISSION))
 	{
 		// Stuff byte is required for this command only.
@@ -313,7 +315,7 @@ dmaReadSector(uint8_t* outputBuffer)
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
-	CyDmaClearPendingDrq(sdDMATxChan);
+	CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
 	CyDmaClearPendingDrq(sdDMARxChan);
 
 	// There is no flow control, so we must ensure we can read the bytes
@@ -423,7 +425,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 		
 		// Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
 		// We need to do this without stopping the clock
-		CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);
+		CyDmaTdSetConfiguration(dmaTxTd[0], 2, dmaTxTd[1], TD_INC_SRC_ADR);
 		CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
 
 		CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);
@@ -431,7 +433,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 		CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
 		CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-		CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);
+		CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 4, dmaRxTd[1], 0);
 		CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
 		CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
 		CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
@@ -443,7 +445,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
-	CyDmaClearPendingDrq(sdDMATxChan);
+	CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);
 	CyDmaClearPendingDrq(sdDMARxChan);
 
 	sdTxDMAComplete = 0;
@@ -733,7 +735,7 @@ static void sdInitDMA()
 	{
 		sdDMATxChan =
 			SD_TX_DMA_DmaInitialize(
-				1, // Bytes per burst
+				2, // Bytes per burst
 				1, // request per burst
 				HI16(CYDEV_SRAM_BASE),
 				HI16(CYDEV_PERIPH_BASE)
@@ -898,7 +900,8 @@ void sdPoll()
 		SD_CS_Write(0);
 		SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);
 
-		CyDelayCycles(64);
+		// Delay extended to work with 60cm cables running cards at 2.85V
+		CyDelayCycles(128);
 		uint8_t cs = SD_CS_Read();
 		SD_CS_SetDriveMode(SD_CS_DM_STRONG)	;
 

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c

@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control) 
+{
+    SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void) 
+{
+    return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h

@@ -0,0 +1,42 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h  
+* Version 1.70
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8   SCSI_Glitch_Ctl_Read(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control        (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR    (  (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h

@@ -146,8 +146,8 @@ extern uint8 SDCard_initVar;
 ***************************************/
 
 #define SDCard_INT_ON_SPI_DONE    ((uint8) (0u   << SDCard_STS_SPI_DONE_SHIFT))
-#define SDCard_INT_ON_TX_EMPTY    ((uint8) (0u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \
+#define SDCard_INT_ON_TX_EMPTY    ((uint8) (1u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
                                                                            SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
 #define SDCard_INT_ON_BYTE_COMP   ((uint8) (0u  << SDCard_STS_BYTE_COMPLETE_SHIFT))
 #define SDCard_INT_ON_SPI_IDLE    ((uint8) (0u   << SDCard_STS_SPI_IDLE_SHIFT))

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -381,34 +381,34 @@
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -416,9 +416,9 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@@ -436,8 +436,6 @@
 #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
@@ -1877,15 +1875,6 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1898,37 +1887,37 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@@ -2728,8 +2717,6 @@
 #define scsiTarget_StatusReg__0__POS 0
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
 #define scsiTarget_StatusReg__2__MASK 0x04u
 #define scsiTarget_StatusReg__2__POS 2
 #define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2737,9 +2724,9 @@
 #define scsiTarget_StatusReg__4__MASK 0x10u
 #define scsiTarget_StatusReg__4__POS 4
 #define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
 
 /* Debug_Timer_Interrupt */
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2860,8 +2847,8 @@
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2869,49 +2856,67 @@
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+
+/* SCSI_Glitch_Ctl */
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -381,34 +381,34 @@
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -416,9 +416,9 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@@ -436,8 +436,6 @@
 .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
@@ -1877,15 +1875,6 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1898,37 +1887,37 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@@ -2728,8 +2717,6 @@
 .set scsiTarget_StatusReg__0__POS, 0
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
 .set scsiTarget_StatusReg__2__MASK, 0x04
 .set scsiTarget_StatusReg__2__POS, 2
 .set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2737,9 +2724,9 @@
 .set scsiTarget_StatusReg__4__MASK, 0x10
 .set scsiTarget_StatusReg__4__POS, 4
 .set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
 
 /* Debug_Timer_Interrupt */
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2860,8 +2847,8 @@
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2869,49 +2856,67 @@
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+
+/* SCSI_Glitch_Ctl */
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
@@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
 /* SCSI_Out_DBx */
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
 
 /* Debug_Timer_Interrupt */
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2869,49 +2856,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
 
 /* SCSI_CTL_PHASE */
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+
+/* SCSI_Glitch_Ctl */
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
 SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
@@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
 
 ; SCSI_Out_Ctl
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
 
 ; Debug_Timer_Interrupt
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2869,49 +2856,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+
+; SCSI_Glitch_Ctl
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -70,6 +70,7 @@
 #include <SCSI_Parity_Error.h>
 #include <SCSI_Filtered.h>
 #include <SCSI_SEL_ISR.h>
+#include <SCSI_Glitch_Ctl.h>
 #include <USBFS_Dm_aliases.h>
 #include <USBFS_Dm.h>
 #include <USBFS_Dp_aliases.h>

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -1,11 +1,42 @@
 <?xml version="1.0" encoding="utf-8"?>
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
-  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="">
+      <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
+        <value name="ENABLED" value="1" desc="Enable counter" />
+        <value name="DISABLED" value="0" desc="Disable counter" />
+      </field>
+      <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
+        <value name="ENABLED" value="1" desc="Interrupt enabled" />
+        <value name="DISABLED" value="0" desc="Interrupt disabled" />
+      </field>
+      <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
+        <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+        <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+      </field>
+      <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
+        <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+        <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+      </field>
+      <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
+        <value name="ENABLED" value="1" desc="Clear FIFO state" />
+        <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+      </field>
+      <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
+        <value name="ENABLED" value="1" desc="Clear FIFO state" />
+        <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+      </field>
+    </register>
+  </block>
+  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -64,54 +95,24 @@
     <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
     <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
   </block>
-  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
-  </block>
+  <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+  </block>
+  <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
-      <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
-        <value name="ENABLED" value="1" desc="Enable counter" />
-        <value name="DISABLED" value="0" desc="Disable counter" />
-      </field>
-      <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
-        <value name="ENABLED" value="1" desc="Interrupt enabled" />
-        <value name="DISABLED" value="0" desc="Interrupt disabled" />
-      </field>
-      <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
-        <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
-        <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
-      </field>
-      <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
-        <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
-        <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
-      </field>
-      <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
-        <value name="ENABLED" value="1" desc="Clear FIFO state" />
-        <value name="DISABLED" value="0" desc="Normal FIFO operation" />
-      </field>
-      <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
-        <value name="ENABLED" value="1" desc="Clear FIFO state" />
-        <value name="DISABLED" value="0" desc="Normal FIFO operation" />
-      </field>
-    </register>
-  </block>
-  <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x40006467" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x40006487" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -138,38 +139,27 @@
       </field>
     </register>
   </block>
+  <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+  <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
   </block>
+  <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
-  </block>
+  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+  </block>
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  </block>
-  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
     <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -266,6 +256,20 @@
     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
   </block>
+  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  </block>
+  <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
+  </block>
+  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -3154,6 +3154,36 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd

@@ -6,6 +6,161 @@
   <addressUnitBits>8</addressUnitBits>
   <width>32</width>
   <peripherals>
+    <peripheral>
+      <name>SCSI_Parity_Error</name>
+      <description>No description available</description>
+      <baseAddress>0x4000646B</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_Parity_Error_STATUS_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+        <register>
+          <name>SCSI_Parity_Error_MASK_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x20</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+        <register>
+          <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x30</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+          <fields>
+            <field>
+              <name>FIFO0</name>
+              <description>FIFO0 clear</description>
+              <lsb>5</lsb>
+              <msb>5</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>Enable counter</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Disable counter</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>INTRENBL</name>
+              <description>Enables or disables the Interrupt</description>
+              <lsb>4</lsb>
+              <msb>4</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>Interrupt enabled</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Interrupt disabled</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FIFO1LEVEL</name>
+              <description>FIFO level</description>
+              <lsb>3</lsb>
+              <msb>3</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FIFO0LEVEL</name>
+              <description>FIFO level</description>
+              <lsb>2</lsb>
+              <msb>2</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FIFO1CLEAR</name>
+              <description>FIFO clear</description>
+              <lsb>1</lsb>
+              <msb>1</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>Clear FIFO state</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Normal FIFO operation</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FIFO0CLEAR</name>
+              <description>FIFO clear</description>
+              <lsb>0</lsb>
+              <msb>0</msb>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>ENABLED</name>
+                  <description>Clear FIFO state</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DISABLED</name>
+                  <description>Normal FIFO operation</description>
+                  <value>0</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
     <peripheral>
       <name>Debug_Timer</name>
       <description>No description available</description>
@@ -299,9 +454,9 @@
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_Out_Ctl</name>
+      <name>SCSI_Glitch_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x40006474</baseAddress>
+      <baseAddress>0x4000647A</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -309,7 +464,7 @@
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Out_Ctl_CONTROL_REG</name>
+          <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
           <description>No description available</description>
           <addressOffset>0x0</addressOffset>
           <size>8</size>
@@ -322,7 +477,7 @@
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x40006468</baseAddress>
+      <baseAddress>0x40006467</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -475,164 +630,9 @@
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_Parity_Error</name>
-      <description>No description available</description>
-      <baseAddress>0x40006466</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x0</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>SCSI_Parity_Error_STATUS_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x0</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-        <register>
-          <name>SCSI_Parity_Error_MASK_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x20</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-        <register>
-          <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x30</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-          <fields>
-            <field>
-              <name>FIFO0</name>
-              <description>FIFO0 clear</description>
-              <lsb>5</lsb>
-              <msb>5</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>Enable counter</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>Disable counter</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>INTRENBL</name>
-              <description>Enables or disables the Interrupt</description>
-              <lsb>4</lsb>
-              <msb>4</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>Interrupt enabled</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>Interrupt disabled</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>FIFO1LEVEL</name>
-              <description>FIFO level</description>
-              <lsb>3</lsb>
-              <msb>3</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>FIFO0LEVEL</name>
-              <description>FIFO level</description>
-              <lsb>2</lsb>
-              <msb>2</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>FIFO1CLEAR</name>
-              <description>FIFO clear</description>
-              <lsb>1</lsb>
-              <msb>1</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>Clear FIFO state</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>Normal FIFO operation</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>FIFO0CLEAR</name>
-              <description>FIFO clear</description>
-              <lsb>0</lsb>
-              <msb>0</msb>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ENABLED</name>
-                  <description>Clear FIFO state</description>
-                  <value>1</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DISABLED</name>
-                  <description>Normal FIFO operation</description>
-                  <value>0</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-          </fields>
-        </register>
-      </registers>
-    </peripheral>
-    <peripheral>
-      <name>SCSI_Out_Bits</name>
+      <name>SCSI_Out_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x40006478</baseAddress>
+      <baseAddress>0x4000647C</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -640,7 +640,7 @@
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_Out_Bits_CONTROL_REG</name>
+          <name>SCSI_Out_Ctl_CONTROL_REG</name>
           <description>No description available</description>
           <addressOffset>0x0</addressOffset>
           <size>8</size>
@@ -653,7 +653,7 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x40006472</baseAddress>
+      <baseAddress>0x40006471</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -1155,5 +1155,26 @@
         </register>
       </registers>
     </peripheral>
+    <peripheral>
+      <name>SCSI_Out_Bits</name>
+      <description>No description available</description>
+      <baseAddress>0x4000657B</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_Out_Bits_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
   </peripherals>
 </device>

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v

@@ -107,7 +107,7 @@ localparam STATE_FIFOLOAD = 3'b001;
 localparam STATE_TX = 3'b010;
 localparam STATE_DESKEW_INIT = 3'b011;
 localparam STATE_DESKEW = 3'b100;
-// This state intentionally not used.
+localparam STATE_WAIT_TIL_READY = 3'b101;
 localparam STATE_READY = 3'b110;
 localparam STATE_RX = 3'b111;
 
@@ -166,13 +166,15 @@ wire f1_blk_stat;	// Rx FIFO full
 wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK;
 cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
 (
-    /* input          */  .clock(op_clk),
-    /* input  [04:00] */  .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})
+	.clock(op_clk),
+	.status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})
 );
 
 // DMA outputs
-assign tx_intr = f0_bus_stat;
-assign rx_intr = f1_bus_stat;
+//assign tx_intr = f0_bus_stat;
+assign tx_intr = f0_blk_stat;
+//assign rx_intr = f1_bus_stat;
+assign rx_intr = f1_blk_stat;
 
 /////////////////////////////////////////////////////////////////////////////
 // State machine
@@ -181,18 +183,15 @@ always @(posedge op_clk) begin
 	case (state)
 		STATE_IDLE:
 		begin
-			// Check that SCSI initiator is ready, and input FIFO is not empty,
-			// and output FIFO is not full.
-			// Note that output FIFO is unused in TX mode.
 			if (!nRST) state <= STATE_IDLE;
-			else if (nACK & !f0_blk_stat  && ((IO == IO_WRITE) || !f1_blk_stat))
+			else if (!f0_blk_stat) // Input FIFO has some data
 				state <= STATE_FIFOLOAD;
 			else
 				state <= STATE_IDLE;
 
 			// Clear our output pins
 			data <= 8'b0;
-			
+
 			REQReg <= 1'b0;
 			fifoStore <= 1'b0;
 			parityErrReg <= 1'b0;
@@ -202,9 +201,13 @@ always @(posedge op_clk) begin
 			if (!nRST) state <= STATE_IDLE;
 			else if (IO == IO_WRITE)
 				state <= STATE_TX;
-			else begin
+
+			// Check that SCSI initiator is ready, and output FIFO is not full.
+			else if (nACK && !f1_blk_stat) begin
 				state <= STATE_READY;
 				REQReg <= 1'b1;
+			end else begin
+				state <= STATE_WAIT_TIL_READY;
 			end
 
 		STATE_TX:
@@ -220,11 +223,25 @@ always @(posedge op_clk) begin
 
 		STATE_DESKEW:
 			if (!nRST) state <= STATE_IDLE;
-			else if(deskewComplete) begin
+			else if(deskewComplete && nACK) begin
 				state <= STATE_READY;
 				REQReg <= 1'b1;
+			end else if (deskewComplete) begin
+				state <= STATE_WAIT_TIL_READY;
 			end else state <= STATE_DESKEW;
 
+		STATE_WAIT_TIL_READY:
+			if (!nRST) state <= STATE_IDLE;
+
+			// Check that SCSI initiator is ready, and output FIFO is not full.
+			// Note that output FIFO is unused in TX mode.
+			else if (nACK && ((IO == IO_WRITE) || !f1_blk_stat)) begin
+				state <= STATE_READY;
+				REQReg <= 1'b1;
+			end else begin
+				state <= STATE_WAIT_TIL_READY;
+			end
+
 		STATE_READY:
 			if (!nRST) state <= STATE_IDLE;
 			else if (~nACK) begin
@@ -255,56 +272,59 @@ end
 // D0 is used for the deskew count.
 // The data output is valid during the DESKEW_INIT phase as well,
 // so we subtract 1.
-// D0 = [0.000000055 / (1 / clk)] - 1
+// SCSI-1 deskew + cable skew = 55ns
+// D0 = [0.000000055 / (1 / clk)] - 1 = 2
+// SCSI-2 FAST deskew + cable skew = 25ns
+// D0 = [0.000000025 / (1 / clk)] - 1 = 0
 cy_psoc3_dp #(.d0_init(2), 
 .cy_dpconfig(
 {
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM0:          IDLE*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM0:           IDLE*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM1:          FIFO Load*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM1:           FIFO Load*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM2:          TX*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:           TX*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM3:          DESKEW INIT*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:           DESKEW INIT*/
     `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM4:          DESKEW*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:           DESKEW*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM5:    Not used*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM6:          READY*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:           READY*/
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM7:          RX*/
-    8'hFF, 8'h00,  /*CFG9:             */
-    8'hFF, 8'hFF,  /*CFG11-10:             */
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:           RX*/
+    8'hFF, 8'h00,  /*CFG9:              */
+    8'hFF, 8'hFF,  /*CFG11-10:              */
     `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
     `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
     `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
-    `SC_SI_A_DEFSI, /*CFG13-12:             */
+    `SC_SI_A_DEFSI, /*CFG13-12:              */
     `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
     1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
     `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
     `SC_FB_NOCHN, `SC_CMP1_NOCHN,
-    `SC_CMP0_NOCHN, /*CFG15-14:             */
+    `SC_CMP0_NOCHN, /*CFG15-14:              */
     10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
     `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
-    `SC_WRK16CAT_DSBL /*CFG17-16:             */
+    `SC_WRK16CAT_DSBL /*CFG17-16:              */
 }
 )) datapath(
         /*  input                   */  .reset(1'b0),
@@ -361,3 +381,4 @@ endmodule
 //`#start footer` -- edit after this line, do not edit this line
 //`#end` -- edit above this line, do not edit this line
 
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c

@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control) 
+{
+    SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void) 
+{
+    return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h

@@ -0,0 +1,42 @@
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h  
+* Version 1.70
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8   SCSI_Glitch_Ctl_Read(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control        (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR    (  (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h

@@ -146,8 +146,8 @@ extern uint8 SDCard_initVar;
 ***************************************/
 
 #define SDCard_INT_ON_SPI_DONE    ((uint8) (0u   << SDCard_STS_SPI_DONE_SHIFT))
-#define SDCard_INT_ON_TX_EMPTY    ((uint8) (0u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \
+#define SDCard_INT_ON_TX_EMPTY    ((uint8) (1u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
                                                                            SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
 #define SDCard_INT_ON_BYTE_COMP   ((uint8) (0u  << SDCard_STS_BYTE_COMPLETE_SHIFT))
 #define SDCard_INT_ON_SPI_IDLE    ((uint8) (0u   << SDCard_STS_SPI_IDLE_SHIFT))

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -414,34 +414,34 @@
 #define EXTLED__SLW CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -449,34 +449,32 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB09_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB09_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB09_10_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB09_10_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB09_10_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB09_10_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB09_10_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB09_10_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB09_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB09_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB09_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB09_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
 #define SDCard_BSPIM_TxStsReg__2__POS 2
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@@ -484,9 +482,9 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
 
 /* SD_SCK */
 #define SD_SCK__0__MASK 0x04u
@@ -1844,15 +1842,15 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1865,37 +1863,37 @@
 #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
 #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
 #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@@ -2648,55 +2646,57 @@
 #define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
 
 /* scsiTarget */
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK
 #define scsiTarget_StatusReg__0__MASK 0x01u
 #define scsiTarget_StatusReg__0__POS 0
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
 #define scsiTarget_StatusReg__2__MASK 0x04u
 #define scsiTarget_StatusReg__2__POS 2
 #define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2704,9 +2704,9 @@
 #define scsiTarget_StatusReg__4__MASK 0x10u
 #define scsiTarget_StatusReg__4__POS 4
 #define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST
 
 /* Debug_Timer_Interrupt */
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2827,8 +2827,8 @@
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2836,49 +2836,71 @@
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -414,34 +414,34 @@
 .set EXTLED__SLW, CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -449,34 +449,32 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB09_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB09_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB09_10_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB09_10_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB09_10_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB09_10_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB09_10_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB09_10_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB09_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB09_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB09_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB09_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
 .set SDCard_BSPIM_TxStsReg__2__POS, 2
 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@@ -484,9 +482,9 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
 
 /* SD_SCK */
 .set SD_SCK__0__MASK, 0x04
@@ -1844,15 +1842,15 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1865,37 +1863,37 @@
 .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
 .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@@ -2648,55 +2646,57 @@
 .set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
 
 /* scsiTarget */
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK
 .set scsiTarget_StatusReg__0__MASK, 0x01
 .set scsiTarget_StatusReg__0__POS, 0
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
 .set scsiTarget_StatusReg__2__MASK, 0x04
 .set scsiTarget_StatusReg__2__POS, 2
 .set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2704,9 +2704,9 @@
 .set scsiTarget_StatusReg__4__MASK, 0x10
 .set scsiTarget_StatusReg__4__POS, 4
 .set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST
 
 /* Debug_Timer_Interrupt */
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2827,8 +2827,8 @@
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2836,49 +2836,71 @@
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0
 EXTLED__SLW EQU CYREG_PRT0_SLW
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -449,34 +449,32 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -484,9 +482,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
 
 /* SD_SCK */
 SD_SCK__0__MASK EQU 0x04
@@ -1844,15 +1842,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1865,37 +1863,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 
 /* SCSI_Out_Ctl */
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2648,55 +2646,57 @@ SCSI_Noise__SEL__SHIFT EQU 3
 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
 
 /* scsiTarget */
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2704,9 +2704,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
 
 /* Debug_Timer_Interrupt */
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2827,8 +2827,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2836,49 +2836,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
 
 /* SCSI_CTL_PHASE */
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
 
 /* SCSI_Parity_Error */
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
 
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0
 EXTLED__SLW EQU CYREG_PRT0_SLW
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -449,34 +449,32 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -484,9 +482,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
 
 ; SD_SCK
 SD_SCK__0__MASK EQU 0x04
@@ -1844,15 +1842,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1865,37 +1863,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
 SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 
 ; SCSI_Out_Ctl
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2648,55 +2646,57 @@ SCSI_Noise__SEL__SHIFT EQU 3
 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
 
 ; scsiTarget
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2704,9 +2704,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
 
 ; Debug_Timer_Interrupt
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2827,8 +2827,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2836,49 +2836,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+
+; SCSI_Glitch_Ctl
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -68,6 +68,7 @@
 #include <EXTLED_aliases.h>
 #include <EXTLED.h>
 #include <SCSI_SEL_ISR.h>
+#include <SCSI_Glitch_Ctl.h>
 #include <USBFS_Dm_aliases.h>
 #include <USBFS_Dm.h>
 #include <USBFS_Dp_aliases.h>

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -1,77 +1,12 @@
 <?xml version="1.0" encoding="utf-8"?>
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
-  <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
-      <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
-    </register>
-    <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
-      <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
-      <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
-        <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
-        <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
-      </field>
-      <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
-      <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
-      <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
-      <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
-        <value name="Timer" value="0" desc="CMP and TC are output." />
-        <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
-      </field>
-      <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
-    </register>
-    <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
-      <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
-      <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
-        <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
-        <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
-      </field>
-      <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
-      <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
-      <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
-      <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
-    </register>
-    <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
-      <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
-        <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
-        <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
-        <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
-        <value name="Irq" value="11" desc="Timer runs until IRQ." />
-      </field>
-      <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
-      <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
-      <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
-        <value name="Equal" value="0" desc="Compare Equal " />
-        <value name="Less than" value="1" desc="Compare Less Than " />
-        <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
-        <value name="Greater" value="11" desc="Compare Greater Than ." />
-        <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
-      </field>
-      <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
-    </register>
-    <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
-    <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
-  </block>
-  <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
+  <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -98,18 +33,10 @@
       </field>
     </register>
   </block>
-  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="">
+  <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -136,24 +63,45 @@
       </field>
     </register>
   </block>
+  <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+  </block>
+  <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
   </block>
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
     <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -251,14 +199,70 @@
     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
   </block>
-  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
+      <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
+    </register>
+    <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
+      <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
+      <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
+        <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
+        <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
+      </field>
+      <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
+      <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
+      <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
+      <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
+        <value name="Timer" value="0" desc="CMP and TC are output." />
+        <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
+      </field>
+      <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
+    </register>
+    <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
+      <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
+      <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
+        <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
+        <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
+      </field>
+      <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
+      <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
+      <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
+      <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
+    </register>
+    <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
+      <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
+        <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
+        <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
+        <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
+        <value name="Irq" value="11" desc="Timer runs until IRQ." />
+      </field>
+      <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
+      <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
+      <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
+        <value name="Equal" value="0" desc="Compare Equal " />
+        <value name="Less than" value="1" desc="Compare Less Than " />
+        <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
+        <value name="Greater" value="11" desc="Compare Greater Than ." />
+        <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
+      </field>
+      <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
+    </register>
+    <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
+    <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
+  </block>
   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
   </block>
-  <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -2296,6 +2296,66 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl" persistent="">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctrl.c">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctrl.h">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>

lib/SCSI2SD/software/include/scsi2sd.h

@@ -85,6 +85,7 @@ typedef enum
 {
 	CONFIG_ENABLE_UNIT_ATTENTION = 1,
 	CONFIG_ENABLE_PARITY = 2,
+	CONFIG_ENABLE_SCSI2 = 4
 } CONFIG_FLAGS;
 
 typedef enum

lib/SCSI2SD/software/scsi2sd-util/ConfigUtil.cc

@@ -96,7 +96,7 @@ ConfigUtil::Default(size_t targetIdx)
 	config.deviceType = CONFIG_FIXED;
 
 	// Default to maximum fail-safe options.
-	config.flags = 0;// CONFIG_ENABLE_PARITY | CONFIG_ENABLE_UNIT_ATTENTION;
+	config.flags = 0;
 	config.deviceTypeModifier = 0;
 	config.sdSectorStart = 0;
 
@@ -170,6 +170,13 @@ ConfigUtil::toXML(const TargetConfig& config)
 			(config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
 			"</parity>\n" <<
 
+		"	<!-- Only set to true when using with a fast SCSI2 host\n " <<
+		"	controller. This can cause problems with older/slower\n" <<
+		"	 hardware.-->\n" <<
+		"	<enableScsi2>" <<
+			(config.flags & CONFIG_ENABLE_SCSI2 ? "true" : "false") <<
+			"</enableScsi2>\n" <<
+
 		"\n" <<
 		"	<!-- ********************************************************\n" <<
 		"	Space separated list. Available options:\n" <<
@@ -303,7 +310,7 @@ parseTarget(wxXmlNode* node)
 				result.scsiId = result.scsiId & ~CONFIG_TARGET_ENABLED;
 			}
 		}
-		if (child->GetName() == "unitAttention")
+		else if (child->GetName() == "unitAttention")
 		{
 			std::string s(child->GetNodeContent().mb_str());
 			if (s == "true")
@@ -315,7 +322,7 @@ parseTarget(wxXmlNode* node)
 				result.flags = result.flags & ~CONFIG_ENABLE_UNIT_ATTENTION;
 			}
 		}
-		if (child->GetName() == "parity")
+		else if (child->GetName() == "parity")
 		{
 			std::string s(child->GetNodeContent().mb_str());
 			if (s == "true")
@@ -327,6 +334,18 @@ parseTarget(wxXmlNode* node)
 				result.flags = result.flags & ~CONFIG_ENABLE_PARITY;
 			}
 		}
+		else if (child->GetName() == "enableScsi2")
+		{
+			std::string s(child->GetNodeContent().mb_str());
+			if (s == "true")
+			{
+				result.flags |= CONFIG_ENABLE_SCSI2;
+			}
+			else
+			{
+				result.flags = result.flags & ~CONFIG_ENABLE_SCSI2;
+			}
+		}
 		else if (child->GetName() == "quirks")
 		{
 			std::stringstream s(std::string(child->GetNodeContent().mb_str()));

lib/SCSI2SD/software/scsi2sd-util/TargetPanel.cc

@@ -72,7 +72,7 @@ TargetPanel::TargetPanel(wxWindow* parent, const TargetConfig& initialConfig) :
 	myNumSectorValidator(new wxIntegerValidator<uint32_t>),
 	mySizeValidator(new wxFloatingPointValidator<float>(2))
 {
-	wxFlexGridSizer *fgs = new wxFlexGridSizer(13, 3, 9, 25);
+	wxFlexGridSizer *fgs = new wxFlexGridSizer(14, 3, 9, 25);
 
 	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
 	myEnableCtrl =
@@ -131,6 +131,7 @@ TargetPanel::TargetPanel(wxWindow* parent, const TargetConfig& initialConfig) :
 			this,
 			ID_parityCtrl,
 			wxT("Enable Parity"));
+	myParityCtrl->SetToolTip(wxT("Enable to require valid SCSI parity bits when receiving data. Some hosts don't provide parity. SCSI2SD always outputs valid parity bits."));
 	fgs->Add(myParityCtrl);
 	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
 	Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_parityCtrl);
@@ -141,11 +142,22 @@ TargetPanel::TargetPanel(wxWindow* parent, const TargetConfig& initialConfig) :
 			this,
 			ID_unitAttCtrl,
 			wxT("Enable Unit Attention"));
-
+	myUnitAttCtrl->SetToolTip(wxT("Enable this to inform the host of changes after hot-swapping SD cards. Causes problems with Mac Plus."));
 	fgs->Add(myUnitAttCtrl);
 	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
 	Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_unitAttCtrl);
 
+	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+	myScsi2Ctrl =
+		new wxCheckBox(
+			this,
+			ID_scsi2Ctrl,
+			wxT("Enable SCSI2 Mode"));
+	myScsi2Ctrl->SetToolTip(wxT("Enable high-performance mode. May cause problems with SASI/SCSI1 hosts."));
+	fgs->Add(myScsi2Ctrl);
+	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+	Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_scsi2Ctrl);
+
 	fgs->Add(new wxStaticText(this, wxID_ANY, wxT("SD card start sector")));
 	wxWrapSizer* startContainer = new wxWrapSizer();
 	myStartSDSectorCtrl =
@@ -318,6 +330,7 @@ TargetPanel::evaluate()
 		myDeviceTypeCtrl->Enable(enabled);
 		myParityCtrl->Enable(enabled);
 		myUnitAttCtrl->Enable(enabled);
+		myScsi2Ctrl->Enable(enabled);
 		myStartSDSectorCtrl->Enable(enabled && !myAutoStartSectorCtrl->IsChecked());
 		myAutoStartSectorCtrl->Enable(enabled);
 		mySectorSizeCtrl->Enable(enabled);
@@ -550,7 +563,8 @@ TargetPanel::getConfig() const
 
 	config.flags =
 		(myParityCtrl->IsChecked() ? CONFIG_ENABLE_PARITY : 0) |
-		(myUnitAttCtrl->IsChecked() ? CONFIG_ENABLE_UNIT_ATTENTION : 0);
+		(myUnitAttCtrl->IsChecked() ? CONFIG_ENABLE_UNIT_ATTENTION : 0) |
+		(myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0);
 
 	auto startSDSector = CtrlGetValue<uint32_t>(myStartSDSectorCtrl);
 	config.sdSectorStart = startSDSector.first;
@@ -584,6 +598,7 @@ TargetPanel::setConfig(const TargetConfig& config)
 
 	myParityCtrl->SetValue(config.flags & CONFIG_ENABLE_PARITY);
 	myUnitAttCtrl->SetValue(config.flags & CONFIG_ENABLE_UNIT_ATTENTION);
+	myScsi2Ctrl->SetValue(config.flags & CONFIG_ENABLE_SCSI2);
 
 	{
 		std::stringstream ss; ss << config.sdSectorStart;

lib/SCSI2SD/software/scsi2sd-util/TargetPanel.hh

@@ -79,6 +79,7 @@ private:
 		ID_deviceTypeCtrl,
 		ID_parityCtrl,
 		ID_unitAttCtrl,
+		ID_scsi2Ctrl,
 		ID_startSDSectorCtrl,
 		ID_autoStartSectorCtrl,
 		ID_sectorSizeCtrl,
@@ -112,6 +113,7 @@ private:
 
 	wxCheckBox* myParityCtrl;
 	wxCheckBox* myUnitAttCtrl;
+	wxCheckBox* myScsi2Ctrl;
 
 	wxIntegerValidator<uint32_t>* myStartSDSectorValidator;
 	wxTextCtrl* myStartSDSectorCtrl;

lib/SCSI2SD/software/scsi2sd-util/scsi2sd-util.cc

@@ -157,7 +157,7 @@ class AppFrame : public wxFrame
 {
 public:
 	AppFrame() :
-		wxFrame(NULL, wxID_ANY, "scsi2sd-util", wxPoint(50, 50), wxSize(600, 650)),
+		wxFrame(NULL, wxID_ANY, "scsi2sd-util", wxPoint(50, 50), wxSize(600, 700)),
 		myInitialConfig(false),
 		myTickCounter(0),
 		myLastPollTime(0)
@@ -336,7 +336,7 @@ private:
 					}
 				}
 				sdSectors.push_back(sdSectorRange);
-				autoStartSector = sdSectorRange.second + 1;
+				autoStartSector = sdSectorRange.second;
 			}
 			else
 			{
@@ -841,6 +841,12 @@ private:
 					" row " << (flashRow + j);
 				mmLogStatus(ss.str());
 				currentProgress += 1;
+				if (currentProgress == totalProgress)
+				{
+					ss.str("Load Complete.");
+					mmLogStatus("Load Complete.");
+				}
+
 				if (!progress->Update(
 						(100 * currentProgress) / totalProgress,
 						ss.str()
@@ -873,21 +879,11 @@ private:
 		}
 
 		myInitialConfig = true;
-		mmLogStatus("Load Complete");
-		while (progress->Update(100, "Load Complete"))
-		{
-			// Wait for the user to click "Close"
-			wxMilliSleep(50);
-		}
 		goto out;
 
 	err:
 		mmLogStatus("Load failed");
-		while (progress->Update(100, "Load failed"))
-		{
-			// Wait for the user to click "Close"
-			wxMilliSleep(50);
-		}
+		progress->Update(100, "Load failed");
 		goto out;
 
 	abort:
@@ -930,6 +926,12 @@ private:
 					" row " << (flashRow + j);
 				mmLogStatus(ss.str());
 				currentProgress += 1;
+
+				if (currentProgress == totalProgress)
+				{
+					ss.str("Save Complete.");
+					mmLogStatus("Save Complete.");
+				}
 				if (!progress->Update(
 						(100 * currentProgress) / totalProgress,
 						ss.str()
@@ -961,21 +963,12 @@ private:
 		myHID->enterBootloader();
 		myHID.reset();
 
-		mmLogStatus("Save Complete");
-		while (progress->Update(100, "Save Complete"))
-		{
-			// Wait for the user to click "Close"
-			wxMilliSleep(50);
-		}
+
 		goto out;
 
 	err:
 		mmLogStatus("Save failed");
-		while (progress->Update(100, "Save failed"))
-		{
-			// Wait for the user to click "Close"
-			wxMilliSleep(50);
-		}
+		progress->Update(100, "Save failed");
 		goto out;
 
 	abort: