|  | @@ -156,6 +156,39 @@ void cycleSdClock() {
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														|  |      pio_sm_exec(SDIO_PIO, SDIO_CMD_SM, pio_encode_nop() | pio_encode_sideset_opt(1, 0) | pio_encode_delay(1));
 |  |      pio_sm_exec(SDIO_PIO, SDIO_CMD_SM, pio_encode_nop() | pio_encode_sideset_opt(1, 0) | pio_encode_delay(1));
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														|  |  }
 |  |  }
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														|  |  
 |  |  
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														|  | 
 |  | +/*******************************************************
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														|  | 
 |  | + * Status Register Receiver
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														|  | 
 |  | + *******************************************************/
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														|  | 
 |  | +sdio_status_t receive_status_register(uint8_t* sds) {
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														|  | 
 |  | +    rp2040_sdio_rx_start(sds, 1, 64);
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														|  | 
 |  | +
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														|  | 
 |  | +    // Wait for the DMA operation to complete, or fail if it took too long
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														|  | 
 |  | +waitagain:
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														|  | 
 |  | +    while (dma_channel_is_busy(SDIO_DMA_CHB) || dma_channel_is_busy(SDIO_DMA_CH))
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														|  | 
 |  | +    {
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														|  | 
 |  | +        if ((uint32_t)(millis() - g_sdio.transfer_start_time) > 2)
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														|  | 
 |  | +        {
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														|  | 
 |  | +            // Reset the state machine program
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														|  | 
 |  | +            dma_channel_abort(SDIO_DMA_CHB);
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														|  | 
 |  | +            pio_sm_set_enabled(SDIO_PIO, SDIO_CMD_SM, false);
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														|  | 
 |  | +            pio_sm_clear_fifos(SDIO_PIO, SDIO_CMD_SM);
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														|  | 
 |  | +            return SDIO_ERR_RESPONSE_TIMEOUT;
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														|  | 
 |  | +        }
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														|  | 
 |  | +    }
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														|  | 
 |  | +
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														|  | 
 |  | +    // Assert that both DMA channels are complete
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														|  | 
 |  | +    if(dma_channel_is_busy(SDIO_DMA_CHB) || dma_channel_is_busy(SDIO_DMA_CH)) {
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														|  | 
 |  | +        // Wait failure, go back.
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														|  | 
 |  | +        goto waitagain;
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														|  | 
 |  | +    }
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														|  | 
 |  | +
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														|  | 
 |  | +    pio_sm_set_enabled(SDIO_PIO, SDIO_DATA_SM, false);
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														|  | 
 |  | +    g_sdio.transfer_state = SDIO_IDLE;
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														|  | 
 |  | +
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														|  | 
 |  | +    return SDIO_OK;
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														|  | 
 |  | +}
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														|  | 
 |  | +
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														|  | 
 |  | +
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														|  |  /*******************************************************
 |  |  /*******************************************************
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														|  |   * Basic SDIO command execution
 |  |   * Basic SDIO command execution
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														|  |   *******************************************************/
 |  |   *******************************************************/
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														|  | @@ -437,7 +470,7 @@ sdio_status_t rp2040_sdio_command_R3(uint8_t command, uint32_t arg, uint32_t *re
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														|  |   * Data reception from SD card
 |  |   * Data reception from SD card
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														|  |   *******************************************************/
 |  |   *******************************************************/
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														|  |  
 |  |  
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														|  | -sdio_status_t rp2040_sdio_rx_start(uint8_t *buffer, uint32_t num_blocks)
 |  | 
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														|  | 
 |  | +sdio_status_t rp2040_sdio_rx_start(uint8_t *buffer, uint32_t num_blocks, uint32_t block_size)
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														|  |  {
 |  |  {
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														|  |      // Buffer must be aligned
 |  |      // Buffer must be aligned
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														|  |      assert(((uint32_t)buffer & 3) == 0 && num_blocks <= SDIO_MAX_BLOCKS);
 |  |      assert(((uint32_t)buffer & 3) == 0 && num_blocks <= SDIO_MAX_BLOCKS);
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														|  | @@ -450,12 +483,12 @@ sdio_status_t rp2040_sdio_rx_start(uint8_t *buffer, uint32_t num_blocks)
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														|  |      g_sdio.blocks_checksumed = 0;
 |  |      g_sdio.blocks_checksumed = 0;
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														|  |      g_sdio.checksum_errors = 0;
 |  |      g_sdio.checksum_errors = 0;
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														|  |  
 |  |  
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														|  | -    // Create DMA block descriptors to store each block of 512 bytes of data to buffer
 |  | 
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														|  | 
 |  | +    // Create DMA block descriptors to store each block of block_size bytes of data to buffer
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														|  |      // and then 8 bytes to g_sdio.received_checksums.
 |  |      // and then 8 bytes to g_sdio.received_checksums.
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														|  |      for (int i = 0; i < num_blocks; i++)
 |  |      for (int i = 0; i < num_blocks; i++)
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														|  |      {
 |  |      {
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														|  | -        g_sdio.dma_blocks[i * 2].write_addr = buffer + i * SDIO_BLOCK_SIZE;
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														|  | -        g_sdio.dma_blocks[i * 2].transfer_count = SDIO_BLOCK_SIZE / sizeof(uint32_t);
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														|  | 
 |  | +        g_sdio.dma_blocks[i * 2].write_addr = buffer + (i * block_size);
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														|  | 
 |  | +        g_sdio.dma_blocks[i * 2].transfer_count = block_size / sizeof(uint32_t);
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														|  |  
 |  |  
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														|  |          g_sdio.dma_blocks[i * 2 + 1].write_addr = &g_sdio.received_checksums[i];
 |  |          g_sdio.dma_blocks[i * 2 + 1].write_addr = &g_sdio.received_checksums[i];
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														|  |          g_sdio.dma_blocks[i * 2 + 1].transfer_count = 2;
 |  |          g_sdio.dma_blocks[i * 2 + 1].transfer_count = 2;
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														|  | @@ -488,7 +521,7 @@ sdio_status_t rp2040_sdio_rx_start(uint8_t *buffer, uint32_t num_blocks)
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														|  |      pio_sm_set_consecutive_pindirs(SDIO_PIO, SDIO_DATA_SM, SDIO_D0, 4, false);
 |  |      pio_sm_set_consecutive_pindirs(SDIO_PIO, SDIO_DATA_SM, SDIO_D0, 4, false);
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														|  |  
 |  |  
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														|  |      // Write number of nibbles to receive to Y register
 |  |      // Write number of nibbles to receive to Y register
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														|  | -    pio_sm_put(SDIO_PIO, SDIO_DATA_SM, SDIO_BLOCK_SIZE * 2 + 16 - 1);
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														|  | 
 |  | +    pio_sm_put(SDIO_PIO, SDIO_DATA_SM, (block_size * 2) + 16 - 1);
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														|  |      pio_sm_exec(SDIO_PIO, SDIO_DATA_SM, pio_encode_out(pio_y, 32));
 |  |      pio_sm_exec(SDIO_PIO, SDIO_DATA_SM, pio_encode_out(pio_y, 32));
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														|  |  
 |  |  
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														|  |      // Enable RX FIFO join because we don't need the TX FIFO during transfer.
 |  |      // Enable RX FIFO join because we don't need the TX FIFO during transfer.
 |