compile fixups

lib/SCSI2SD/software/SCSI2SD/src/config.c

@@ -32,7 +32,7 @@
 
 #include <string.h>
 
-static const uint16_t FIRMWARE_VERSION = 0x0440;
+static const uint16_t FIRMWARE_VERSION = 0x0441;
 
 // 1 flash row
 static const uint8_t DEFAULT_CONFIG[256] =

lib/SCSI2SD/software/SCSI2SD/src/mode.c

@@ -172,7 +172,7 @@ static const uint8_t SequentialDeviceConfigPage[] =
 0x00,0x01, // Write delay time, in 100ms units
 0x00, // Default gap size
 0x10, // auto-generation of default eod (end of data)
-0x00,0x00,0x00 // buffer-size at early warning
+0x00,0x00,0x00, // buffer-size at early warning
 0x00, // No data compression
 0x00 // reserved
 };
@@ -242,7 +242,10 @@ static void doModeSense(
 		break;
 
 	case CONFIG_MO:
-		TODO
+        mediumType = 0x03; // Optical reversible or erasable medium
+		deviceSpecificParam =
+			(blockDev.state & DISK_WP) ? 0x80 : 0;
+		density = 0x00; // Default
 		break;
 
 	};

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c

@@ -1,88 +1,88 @@
-/*******************************************************************************
-* File Name: Bootloadable_1.c
-* Version 1.30
-*
-*  Description:
-*   Provides an API for the Bootloadable application. The API includes a
-*   single function for starting the bootloader.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "Bootloadable_1.h"
-
-
-/*******************************************************************************
-* Function Name: Bootloadable_1_Load
-********************************************************************************
-* Summary:
-*  Begins the bootloading algorithm downloading a new ACD image from the host.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  This method will never return. It will load a new application and reset
-*  the device.
-*
-*******************************************************************************/
-void Bootloadable_1_Load(void) 
-{
-    /* Schedule Bootloader to start after reset */
-    Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR);
-
-    CySoftwareReset();
-}
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used.
-*******************************************************************************/
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) 
-{
-    uint32 flsAddr = address - CYDEV_FLASH_BASE;
-    uint8  rowData[CYDEV_FLS_ROW_SIZE];
-
-    #if !(CY_PSOC4)
-        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
-    #endif  /* !(CY_PSOC4) */
-
-    #if (CY_PSOC4)
-        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
-    #else
-        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
-    #endif  /* (CY_PSOC4) */
-
-    uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
-    uint16 idx;
-
-
-    for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
-    {
-        rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
-    }
-    rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
-
-    #if(CY_PSOC4)
-        (void) CySysFlashWriteRow((uint32) rowNum, rowData);
-    #else
-        (void) CyWriteRowData(arrayId, rowNum, rowData);
-    #endif  /* (CY_PSOC4) */
-
-    #if(CY_PSOC5)
-        /***************************************************************************
-        * When writing Flash, data in the instruction cache can become stale.
-        * Therefore, the cache data does not correlate to the data just written to
-        * Flash. A call to CyFlushCache() is required to invalidate the data in the
-        * cache and force fresh information to be loaded from Flash.
-        ***************************************************************************/
-        CyFlushCache();
-    #endif /* (CY_PSOC5) */
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Bootloadable_1.c
+* Version 1.30
+*
+*  Description:
+*   Provides an API for the Bootloadable application. The API includes a
+*   single function for starting the bootloader.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "Bootloadable_1.h"
+
+
+/*******************************************************************************
+* Function Name: Bootloadable_1_Load
+********************************************************************************
+* Summary:
+*  Begins the bootloading algorithm downloading a new ACD image from the host.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  This method will never return. It will load a new application and reset
+*  the device.
+*
+*******************************************************************************/
+void Bootloadable_1_Load(void) 
+{
+    /* Schedule Bootloader to start after reset */
+    Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR);
+
+    CySoftwareReset();
+}
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) 
+{
+    uint32 flsAddr = address - CYDEV_FLASH_BASE;
+    uint8  rowData[CYDEV_FLS_ROW_SIZE];
+
+    #if !(CY_PSOC4)
+        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+    #endif  /* !(CY_PSOC4) */
+
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
+    uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
+    uint16 idx;
+
+
+    for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)
+    {
+        rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx);
+    }
+    rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
+
+    #if(CY_PSOC4)
+        (void) CySysFlashWriteRow((uint32) rowNum, rowData);
+    #else
+        (void) CyWriteRowData(arrayId, rowNum, rowData);
+    #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing Flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * Flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from Flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h

@@ -1,169 +1,169 @@
-/*******************************************************************************
-* File Name: Bootloadable_1.h
-* Version 1.30
-*
-*  Description:
-*   Provides an API for the Bootloadable application. The API includes a
-*   single function for starting bootloader.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-********************************************************************************/
-
-
-#ifndef CY_BOOTLOADABLE_Bootloadable_1_H
-#define CY_BOOTLOADABLE_Bootloadable_1_H
-
-#include "cydevice_trm.h"
-#include "CyFlash.h"
-
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later
-#endif /* !defined (CY_PSOC5LP) */
-
-
-#ifndef CYDEV_FLASH_BASE
-    #define CYDEV_FLASH_BASE                            CYDEV_FLS_BASE
-    #define CYDEV_FLASH_SIZE                            CYDEV_FLS_SIZE
-#endif /* CYDEV_FLASH_BASE */
-
-#if(CY_PSOC3)
-    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  CYCODE *) (idx)))
-#else
-    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  *)(CYDEV_FLASH_BASE + (idx))))
-#endif /* (CY_PSOC3) */
-
-
-/*******************************************************************************
-* This variable is used by Bootloader/Bootloadable components to schedule what
-* application will be started after software reset.
-*******************************************************************************/
-#if (CY_PSOC4)
-    #if defined(__ARMCC_VERSION)
-        __attribute__ ((section(".bootloaderruntype"), zero_init))
-    #elif defined (__GNUC__)
-        __attribute__ ((section(".bootloaderruntype")))
-   #elif defined (__ICCARM__)
-        #pragma location=".bootloaderruntype"
-    #endif  /* defined(__ARMCC_VERSION) */
-    extern volatile uint32 cyBtldrRunType;
-#endif  /* (CY_PSOC4) */
-
-
-/*******************************************************************************
-* Get the reason of the device reset
-*******************************************************************************/
-#if(CY_PSOC4)
-    #define Bootloadable_1_RES_CAUSE_RESET_SOFT   (0x10u)
-    #define Bootloadable_1_GET_RUN_TYPE           \
-                        (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \
-                            ? (cyBtldrRunType) \
-                            : 0u)
-#else
-    #define Bootloadable_1_GET_RUN_TYPE           (CY_GET_REG8(CYREG_RESET_SR0) & \
-                                                    (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP))
-#endif  /* (CY_PSOC4) */
-
-
-/*******************************************************************************
-* Schedule Bootloader/Bootloadable to be run after software reset
-*******************************************************************************/
-#if(CY_PSOC4)
-    #define Bootloadable_1_SET_RUN_TYPE(x)        (cyBtldrRunType = (x))
-#else
-    #define Bootloadable_1_SET_RUN_TYPE(x)        CY_SET_REG8(CYREG_RESET_SR0, (x))
-#endif  /* (CY_PSOC4) */
-
-
-
-/***************************************
-*     Function Prototypes
-***************************************/
-extern void Bootloadable_1_Load(void) ;
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used starting from version 1.10
-*******************************************************************************/
-#define CYBTDLR_SET_RUN_TYPE(x)     Bootloadable_1_SET_RUN_TYPE(x)
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used starting from version 1.20
-*******************************************************************************/
-#define Bootloadable_1_START_APP                      (0x80u)
-#define Bootloadable_1_START_BTLDR                    (0x40u)
-#define Bootloadable_1_META_DATA_SIZE                 (64u)
-#define Bootloadable_1_META_APP_CHECKSUM_OFFSET       (0u)
-
-#if(CY_PSOC3)
-
-    #define Bootloadable_1_APP_ADDRESS                    uint16
-    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 CYCODE *) (idx)))
-
-    /* Offset by 2 from 32 bit start because only need 16 bits */
-    #define Bootloadable_1_META_APP_ADDR_OFFSET           (3u)
-    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (7u)
-    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (11u)
-    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (15u)
-
-#else
-
-    #define Bootloadable_1_APP_ADDRESS                    uint32
-    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 *)(CYDEV_FLASH_BASE + (idx))))
-
-    #define Bootloadable_1_META_APP_ADDR_OFFSET           (1u)
-    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (5u)
-    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (9u)
-    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (13u)
-
-#endif /* (CY_PSOC3) */
-
-#define Bootloadable_1_META_APP_ACTIVE_OFFSET             (16u)
-#define Bootloadable_1_META_APP_VERIFIED_OFFSET           (17u)
-
-#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET       (18u)
-#define Bootloadable_1_META_APP_ID_OFFSET                 (20u)
-#define Bootloadable_1_META_APP_VER_OFFSET                (22u)
-#define Bootloadable_1_META_APP_CUST_ID_OFFSET            (24u)
-
-#define Bootloadable_1_SetFlashRunType(runType)           \
-                        Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used.
-*
-* If the obsoleted macro definitions intended for use in the application use the
-* following scheme, redefine your own versions of these definitions:
-*    #ifdef <OBSOLETED_DEFINE>
-*        #undef  <OBSOLETED_DEFINE>
-*        #define <OBSOLETED_DEFINE>      (<New Value>)
-*    #endif
-*
-* Note: Redefine obsoleted macro definitions with caution. They might still be
-*       used in the application and their modification might lead to unexpected
-*       consequences.
-*******************************************************************************/
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
-#if(CY_PSOC4)
-    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
-#else
-    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
-#endif  /* (CY_PSOC4) */
-
-#if(CY_PSOC4)
-    extern uint8 appRunType;
-#endif  /* (CY_PSOC4) */
-
-
-#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Bootloadable_1.h
+* Version 1.30
+*
+*  Description:
+*   Provides an API for the Bootloadable application. The API includes a
+*   single function for starting bootloader.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+
+#ifndef CY_BOOTLOADABLE_Bootloadable_1_H
+#define CY_BOOTLOADABLE_Bootloadable_1_H
+
+#include "cydevice_trm.h"
+#include "CyFlash.h"
+
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later
+#endif /* !defined (CY_PSOC5LP) */
+
+
+#ifndef CYDEV_FLASH_BASE
+    #define CYDEV_FLASH_BASE                            CYDEV_FLS_BASE
+    #define CYDEV_FLASH_SIZE                            CYDEV_FLS_SIZE
+#endif /* CYDEV_FLASH_BASE */
+
+#if(CY_PSOC3)
+    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  CYCODE *) (idx)))
+#else
+    #define Bootloadable_1_GET_CODE_DATA(idx)         (*((uint8  *)(CYDEV_FLASH_BASE + (idx))))
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* This variable is used by Bootloader/Bootloadable components to schedule what
+* application will be started after software reset.
+*******************************************************************************/
+#if (CY_PSOC4)
+    #if defined(__ARMCC_VERSION)
+        __attribute__ ((section(".bootloaderruntype"), zero_init))
+    #elif defined (__GNUC__)
+        __attribute__ ((section(".bootloaderruntype")))
+   #elif defined (__ICCARM__)
+        #pragma location=".bootloaderruntype"
+    #endif  /* defined(__ARMCC_VERSION) */
+    extern volatile uint32 cyBtldrRunType;
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* Get the reason of the device reset
+*******************************************************************************/
+#if(CY_PSOC4)
+    #define Bootloadable_1_RES_CAUSE_RESET_SOFT   (0x10u)
+    #define Bootloadable_1_GET_RUN_TYPE           \
+                        (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \
+                            ? (cyBtldrRunType) \
+                            : 0u)
+#else
+    #define Bootloadable_1_GET_RUN_TYPE           (CY_GET_REG8(CYREG_RESET_SR0) & \
+                                                    (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP))
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* Schedule Bootloader/Bootloadable to be run after software reset
+*******************************************************************************/
+#if(CY_PSOC4)
+    #define Bootloadable_1_SET_RUN_TYPE(x)        (cyBtldrRunType = (x))
+#else
+    #define Bootloadable_1_SET_RUN_TYPE(x)        CY_SET_REG8(CYREG_RESET_SR0, (x))
+#endif  /* (CY_PSOC4) */
+
+
+
+/***************************************
+*     Function Prototypes
+***************************************/
+extern void Bootloadable_1_Load(void) ;
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting from version 1.10
+*******************************************************************************/
+#define CYBTDLR_SET_RUN_TYPE(x)     Bootloadable_1_SET_RUN_TYPE(x)
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting from version 1.20
+*******************************************************************************/
+#define Bootloadable_1_START_APP                      (0x80u)
+#define Bootloadable_1_START_BTLDR                    (0x40u)
+#define Bootloadable_1_META_DATA_SIZE                 (64u)
+#define Bootloadable_1_META_APP_CHECKSUM_OFFSET       (0u)
+
+#if(CY_PSOC3)
+
+    #define Bootloadable_1_APP_ADDRESS                    uint16
+    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 CYCODE *) (idx)))
+
+    /* Offset by 2 from 32 bit start because only need 16 bits */
+    #define Bootloadable_1_META_APP_ADDR_OFFSET           (3u)
+    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (7u)
+    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (11u)
+    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (15u)
+
+#else
+
+    #define Bootloadable_1_APP_ADDRESS                    uint32
+    #define Bootloadable_1_GET_CODE_WORD(idx)             (*((uint32 *)(CYDEV_FLASH_BASE + (idx))))
+
+    #define Bootloadable_1_META_APP_ADDR_OFFSET           (1u)
+    #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET    (5u)
+    #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET       (9u)
+    #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET       (13u)
+
+#endif /* (CY_PSOC3) */
+
+#define Bootloadable_1_META_APP_ACTIVE_OFFSET             (16u)
+#define Bootloadable_1_META_APP_VERIFIED_OFFSET           (17u)
+
+#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET       (18u)
+#define Bootloadable_1_META_APP_ID_OFFSET                 (20u)
+#define Bootloadable_1_META_APP_VER_OFFSET                (22u)
+#define Bootloadable_1_META_APP_CUST_ID_OFFSET            (24u)
+
+#define Bootloadable_1_SetFlashRunType(runType)           \
+                        Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
+#if(CY_PSOC4)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
+#else
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
+#endif  /* (CY_PSOC4) */
+
+#if(CY_PSOC4)
+    extern uint8 appRunType;
+#endif  /* (CY_PSOC4) */
+
+
+#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c

@@ -1,730 +1,730 @@
-/*******************************************************************************
-* File Name: CFG_EEPROM.c
-* Version 3.0
-*
-*  Description:
-*   Provides the source code to the API for the EEPROM component.
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "CFG_EEPROM.h"
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_Enable
-********************************************************************************
-*
-* Summary:
-*  Enable the EEPROM block. Also reads the temperature and stores it for
-*  future writes.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CFG_EEPROM_Enable(void) 
-{
-    /* Read temperature value */
-    (void)CySetTemp();
-
-    /* Start EEPROM block */
-    CyEEPROM_Start();
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_Start
-********************************************************************************
-*
-* Summary:
-*  Starts EEPROM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CFG_EEPROM_Start(void) 
-{
-    CFG_EEPROM_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_Stop
-********************************************************************************
-*
-* Summary:
-*  Stops and powers down EEPROM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CFG_EEPROM_Stop (void) 
-{
-    /* Stop and power down EEPROM block */
-    CyEEPROM_Stop();
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_WriteByte
-********************************************************************************
-*
-* Summary:
-*  Writes a byte of data to the EEPROM. This function blocks until
-*  the function is complete. For a reliable write procedure to occur you should
-*  call CFG_EEPROM_UpdateTemperature() function if the temperature of the
-*  silicon has been changed for more than 10C since the component was started.
-*
-* Parameters:
-*  dataByte:  The byte of data to write to the EEPROM
-*  address:   The address of data to be written. The maximum address is dependent
-*             on the EEPROM size.
-*
-* Return:
-*  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) 
-{
-    cystatus status;
-    uint16 rowNumber;
-    uint16 byteNumber;
-    
-    CySpcStart();
-
-    if (address < CY_EEPROM_SIZE)
-    {
-        rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
-        byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
-        if(CYRET_SUCCESS == CySpcLock())
-        {
-            status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
-                                                                    CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
-            if (CYRET_STARTED == status)
-            {
-                /* Plan for failure */
-                status = CYRET_UNKNOWN;
-
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait until SPC becomes idle */
-                }
-
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-                /* Command to erase and program the row. */
-                if(CYRET_SUCCESS == status)
-                {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
-                    dieTemperature[1u]) == CYRET_STARTED)
-                    {
-                        /* Plan for failure */
-                        status = CYRET_UNKNOWN;
-
-                        while(CY_SPC_BUSY)
-                        {
-                            /* Wait until SPC becomes idle */
-                        }
-
-                        /* SPC is idle now */
-                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                        {
-                            status = CYRET_SUCCESS;
-                        }
-                    }
-                    else
-                    {
-                        status = CYRET_UNKNOWN;
-                    }
-                }
-                else
-                {
-                    status = CYRET_UNKNOWN;
-                }
-            }
-            else
-            {
-                if (CYRET_BAD_PARAM != status)
-                {
-                    status = CYRET_UNKNOWN;
-                }
-            }
-            CySpcUnlock();
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_ReadByte
-********************************************************************************
-*
-* Summary:
-*  Reads and returns a byte of data from the on-chip EEPROM memory. Although
-*  the data is present in the CPU memory space, this function provides an
-*  intuitive user interface, addressing the EEPROM memory as a separate block with
-*  the first EERPOM byte address equal to 0x0000.
-*
-* Parameters:
-*  address:   The address of data to be read. The maximum address is limited by the
-*             size of the EEPROM array on a specific device.
-*
-* Return:
-*  Data located at an address.
-*
-*******************************************************************************/
-uint8 CFG_EEPROM_ReadByte(uint16 address) 
-{
-    uint8 retByte;
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    /* Request access to EEPROM for reading.
-    This is needed to reserve PHUB for read operation from EEPROM */
-    CyEEPROM_ReadReserve();
-    
-    retByte = *((reg8 *) (CYDEV_EE_BASE + address));
-
-    /* Release EEPROM array */
-    CyEEPROM_ReadRelease();
-    
-    CyExitCriticalSection(interruptState);
-
-    return (retByte);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_UpdateTemperature
-********************************************************************************
-*
-* Summary:
-*  Updates and stores the temperature value. This function should be called
-*  before EEPROM writes if the temperature may have been changed by more than
-*  10 degrees Celsius.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  Status of operation, 0 if operation complete, non-zero value if error
-*  was detected.
-*
-*******************************************************************************/
-uint8 CFG_EEPROM_UpdateTemperature(void) 
-{
-    return ((uint8)CySetTemp());
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_EraseSector
-********************************************************************************
-*
-* Summary:
-*  Erase an EEPROM sector (64 rows). This function blocks until the erase
-*  operation is complete. Using this API helps to erase the EEPROM sector at
-*  a time. This is faster than using individual writes but affects a cycle
-*  recourse of the whole EEPROM row.
-*
-* Parameters:
-*  sectorNumber:  The sector number to erase.
-*
-* Return:
-*  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
-{
-    cystatus status;
-    
-    CySpcStart();
-
-    if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
-    {
-        /* See if we can get SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
-            {
-                /* Plan for failure */
-                status = CYRET_UNKNOWN;
-
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait until SPC becomes idle */
-                }
-
-                /* SPC is idle now */
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-            }
-            else
-            {
-                status = CYRET_UNKNOWN;
-            }
-
-            /* Unlock SPC so that someone else can use it. */
-            CySpcUnlock();
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_Write
-********************************************************************************
-*
-* Summary:
-*  Writes a row (16 bytes) of data to the EEPROM. This function blocks until
-*  the write operation is complete. Compared to functions that write one byte,
-*  this function allows writing a whole row (16 bytes) at a time. For
-*  a reliable write procedure to occur you should call the
-*  CFG_EEPROM_UpdateTemperature() function if the temperature of the
-*  silicon has changed for more than 10C since component was started.
-*
-* Parameters:
-*  rowData:    The address of the data to write to the EEPROM.
-*  rowNumber:  The row number to write.
-*
-* Return:
-*  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) 
-{
-    cystatus status;
-    
-    CySpcStart();
-
-    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
-    {
-        /* See if we can get SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            /* Plan for failure */
-            status = CYRET_UNKNOWN;
-
-            /* Command to load a row of data */
-            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
-            {
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait until SPC becomes idle */
-                }
-
-                /* SPC is idle now */
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-
-                /* Command to erase and program the row. */
-                if(status == CYRET_SUCCESS)
-                {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
-                    dieTemperature[1u]) == CYRET_STARTED)
-                    {
-                        /* Plan for failure */
-                        status = CYRET_UNKNOWN;
-
-                        while(CY_SPC_BUSY)
-                        {
-                            /* Wait until SPC becomes idle */
-                        }
-
-                        /* SPC is idle now */
-                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                        {
-                            status = CYRET_SUCCESS;
-                        }
-                    }
-                    else
-                    {
-                        status = CYRET_UNKNOWN;
-                    }
-                }
-                else
-                {
-                    status = CYRET_UNKNOWN;
-                }
-            }
-
-            /* Unlock SPC so that someone else can use it. */
-            CySpcUnlock();
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_StartWrite
-********************************************************************************
-*
-* Summary:
-*  Starts a write of a row (16 bytes) of data to the EEPROM.
-*  This function does not block. The function returns once the SPC has begun
-*  writing the data. This function must be used in combination with
-*  CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
-*  until it returns a status other than CYRET_STARTED. That indicates that the
-*  write has completed. Until CFG_EEPROM_Query() detects that
-*  the write is complete, the SPC is marked as locked to prevent another
-*  SPC operation from being performed. For a reliable write procedure to occur
-*  you should call CFG_EEPROM_UpdateTemperature() API if the temperature
-*  of the silicon has changed for more than 10C since component was started.
-*
-* Parameters:
-*  rowData:    The address of the data to write to the EEPROM.
-*  rowNumber:  The row number to write.
-*
-* Return:
-*  CYRET_STARTED, if the SPC command to write was successfully started.
-*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-* Side effects:
-*  After calling this API, the device should not be powered down, reset or switched
-*  to low power modes until EEPROM operation is complete. 
-*  Ignoring this recommendation may lead to data corruption or silicon
-*  unexpected behavior.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
-
-{
-    cystatus status;
-    
-    CySpcStart();
-
-    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
-    {
-        /* See if we can get SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            /* Plan for failure */
-            status = CYRET_UNKNOWN;
-
-            /* Command to load a row of data */
-            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
-            {
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait until SPC becomes idle */
-                }
-
-                /* SPC is idle now */
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-
-                /* Command to erase and program the row. */
-                if(status == CYRET_SUCCESS)
-                {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
-                    dieTemperature[1u]) == CYRET_STARTED)
-                    {
-                        status = CYRET_STARTED;
-                    }
-                    else
-                    {
-                        status = CYRET_UNKNOWN;
-                    }
-                }
-                else
-                {
-                    status = CYRET_UNKNOWN;
-                }
-            }
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_StartErase
-********************************************************************************
-*
-* Summary:
-*  Starts the EEPROM sector erase. This function does not block.
-*  The function returns once the SPC has begun writing the data. This function
-*  must be used in combination with CFG_EEPROM_Query().
-*  CFG_EEPROM_Query() must be called until it returns a status
-*  other than CYRET_STARTED. That indicates the erase has been completed.
-*  Until CFG_EEPROM_Query() detects that the erase is
-*  complete, the SPC is marked as locked to prevent another SPC operation
-*  from being performed.
-*
-* Parameters:
-*  sectorNumber:  The sector number to erase.
-*
-* Return:
-*  CYRET_STARTED, if the SPC command to erase was successfully started.
-*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-* Side effects:
-*  After calling this API, the device should not be powered down, reset or switched
-*  to low power modes until EEPROM operation is complete.
-*  Ignoring this recommendation may lead to data corruption or silicon
-*  unexpected behavior.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) 
-{
-    cystatus status;
-    
-    CySpcStart();
-
-    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
-    {
-        /* See if we can get SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            /* Plan for failure */
-            status = CYRET_UNKNOWN;
-
-            /* Command to load a row of data */
-            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
-            {
-                status = CYRET_SUCCESS;
-            }
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_Query
-********************************************************************************
-*
-* Summary:
-*  Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
-*  CFG_EEPROM_StartErase().
-*  This function must be called until it returns a value other than
-*  CYRET_STARTED. Once that occurs, the write or erase has been completed and
-*  the SPC is unlocked.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  CYRET_STARTED, if the SPC command is still processing.
-*  CYRET_SUCCESS, if the operation was completed successfully.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_Query(void) 
-{
-    cystatus status;
-    
-    CySpcStart();
-
-    /* Check if SPC is idle */
-    if(CY_SPC_IDLE)
-    {
-        /* SPC is idle now */
-        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-        {
-            status = CYRET_SUCCESS;
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
-
-        /* Unlock SPC so that someone else can use it. */
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_STARTED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CFG_EEPROM_ByteWritePos
-********************************************************************************
-*
-* Summary:
-*  Writes a byte of data to the EEPROM. This is a blocking call. It will not
-*  return until the write operation succeeds or fails.
-*
-* Parameters:
-*  dataByte:   The byte of data to write to the EEPROM.
-*  rowNumber:  The EEPROM row number to program.
-*  byteNumber: The byte number within the row to program.
-*
-* Return:
-*  CYRET_SUCCESS, if the operation was successful.
-*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
-*  CYRET_LOCKED, if the SPC is being used.
-*  CYRET_UNKNOWN, if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
-
-{
-    cystatus status;
-
-    /* Start SPC */
-    CySpcStart();
-
-    if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
-    {
-        /* See if we can get SPC. */
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            /* Plan for failure */
-            status = CYRET_UNKNOWN;
-
-            /* Command to load byte of data */
-            if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
-                                                                CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
-            {
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait until SPC becomes idle */
-                }
-
-                /* SPC is idle now */
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-
-                /* Command to erase and program the row. */
-                if(status == CYRET_SUCCESS)
-                {
-                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
-                    dieTemperature[1u]) == CYRET_STARTED)
-                    {
-                        /* Plan for failure */
-                        status = CYRET_UNKNOWN;
-
-                        while(CY_SPC_BUSY)
-                        {
-                            /* Wait until SPC becomes idle */
-                        }
-
-                        /* SPC is idle now */
-                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                        {
-                            status = CYRET_SUCCESS;
-                        }
-                    }
-                    else
-                    {
-                        status = CYRET_UNKNOWN;
-                    }
-                }
-                else
-                {
-                    status = CYRET_UNKNOWN;
-                }
-            }
-
-            /* Unlock SPC so that someone else can use it. */
-            CySpcUnlock();
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CFG_EEPROM.c
+* Version 3.0
+*
+*  Description:
+*   Provides the source code to the API for the EEPROM component.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CFG_EEPROM.h"
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Enable
+********************************************************************************
+*
+* Summary:
+*  Enable the EEPROM block. Also reads the temperature and stores it for
+*  future writes.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Enable(void) 
+{
+    /* Read temperature value */
+    (void)CySetTemp();
+
+    /* Start EEPROM block */
+    CyEEPROM_Start();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Start
+********************************************************************************
+*
+* Summary:
+*  Starts EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Start(void) 
+{
+    CFG_EEPROM_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops and powers down EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CFG_EEPROM_Stop (void) 
+{
+    /* Stop and power down EEPROM block */
+    CyEEPROM_Stop();
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_WriteByte
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This function blocks until
+*  the function is complete. For a reliable write procedure to occur you should
+*  call CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has been changed for more than 10C since the component was started.
+*
+* Parameters:
+*  dataByte:  The byte of data to write to the EEPROM
+*  address:   The address of data to be written. The maximum address is dependent
+*             on the EEPROM size.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) 
+{
+    cystatus status;
+    uint16 rowNumber;
+    uint16 byteNumber;
+    
+    CySpcStart();
+
+    if (address < CY_EEPROM_SIZE)
+    {
+        rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;
+        byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));
+        if(CYRET_SUCCESS == CySpcLock())
+        {
+            status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \
+                                                                    CFG_EEPROM_SPC_BYTE_WRITE_SIZE);
+            if (CYRET_STARTED == status)
+            {
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+                /* Command to erase and program the row. */
+                if(CYRET_SUCCESS == status)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+            else
+            {
+                if (CYRET_BAD_PARAM != status)
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ReadByte
+********************************************************************************
+*
+* Summary:
+*  Reads and returns a byte of data from the on-chip EEPROM memory. Although
+*  the data is present in the CPU memory space, this function provides an
+*  intuitive user interface, addressing the EEPROM memory as a separate block with
+*  the first EERPOM byte address equal to 0x0000.
+*
+* Parameters:
+*  address:   The address of data to be read. The maximum address is limited by the
+*             size of the EEPROM array on a specific device.
+*
+* Return:
+*  Data located at an address.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_ReadByte(uint16 address) 
+{
+    uint8 retByte;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Request access to EEPROM for reading.
+    This is needed to reserve PHUB for read operation from EEPROM */
+    CyEEPROM_ReadReserve();
+    
+    retByte = *((reg8 *) (CYDEV_EE_BASE + address));
+
+    /* Release EEPROM array */
+    CyEEPROM_ReadRelease();
+    
+    CyExitCriticalSection(interruptState);
+
+    return (retByte);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_UpdateTemperature
+********************************************************************************
+*
+* Summary:
+*  Updates and stores the temperature value. This function should be called
+*  before EEPROM writes if the temperature may have been changed by more than
+*  10 degrees Celsius.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Status of operation, 0 if operation complete, non-zero value if error
+*  was detected.
+*
+*******************************************************************************/
+uint8 CFG_EEPROM_UpdateTemperature(void) 
+{
+    return ((uint8)CySetTemp());
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_EraseSector
+********************************************************************************
+*
+* Summary:
+*  Erase an EEPROM sector (64 rows). This function blocks until the erase
+*  operation is complete. Using this API helps to erase the EEPROM sector at
+*  a time. This is faster than using individual writes but affects a cycle
+*  recourse of the whole EEPROM row.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+            }
+            else
+            {
+                status = CYRET_UNKNOWN;
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Write
+********************************************************************************
+*
+* Summary:
+*  Writes a row (16 bytes) of data to the EEPROM. This function blocks until
+*  the write operation is complete. Compared to functions that write one byte,
+*  this function allows writing a whole row (16 bytes) at a time. For
+*  a reliable write procedure to occur you should call the
+*  CFG_EEPROM_UpdateTemperature() function if the temperature of the
+*  silicon has changed for more than 10C since component was started.
+*
+* Parameters:
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_StartWrite
+********************************************************************************
+*
+* Summary:
+*  Starts a write of a row (16 bytes) of data to the EEPROM.
+*  This function does not block. The function returns once the SPC has begun
+*  writing the data. This function must be used in combination with
+*  CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called
+*  until it returns a status other than CYRET_STARTED. That indicates that the
+*  write has completed. Until CFG_EEPROM_Query() detects that
+*  the write is complete, the SPC is marked as locked to prevent another
+*  SPC operation from being performed. For a reliable write procedure to occur
+*  you should call CFG_EEPROM_UpdateTemperature() API if the temperature
+*  of the silicon has changed for more than 10C since component was started.
+*
+* Parameters:
+*  rowData:    The address of the data to write to the EEPROM.
+*  rowNumber:  The row number to write.
+*
+* Return:
+*  CYRET_STARTED, if the SPC command to write was successfully started.
+*  CYRET_BAD_PARAM, if the parameter rowNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete. 
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        status = CYRET_STARTED;
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_StartErase
+********************************************************************************
+*
+* Summary:
+*  Starts the EEPROM sector erase. This function does not block.
+*  The function returns once the SPC has begun writing the data. This function
+*  must be used in combination with CFG_EEPROM_Query().
+*  CFG_EEPROM_Query() must be called until it returns a status
+*  other than CYRET_STARTED. That indicates the erase has been completed.
+*  Until CFG_EEPROM_Query() detects that the erase is
+*  complete, the SPC is marked as locked to prevent another SPC operation
+*  from being performed.
+*
+* Parameters:
+*  sectorNumber:  The sector number to erase.
+*
+* Return:
+*  CYRET_STARTED, if the SPC command to erase was successfully started.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+* Side effects:
+*  After calling this API, the device should not be powered down, reset or switched
+*  to low power modes until EEPROM operation is complete.
+*  Ignoring this recommendation may lead to data corruption or silicon
+*  unexpected behavior.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Query
+********************************************************************************
+*
+* Summary:
+*  Checks the status of an earlier call to CFG_EEPROM_StartWrite() or
+*  CFG_EEPROM_StartErase().
+*  This function must be called until it returns a value other than
+*  CYRET_STARTED. Once that occurs, the write or erase has been completed and
+*  the SPC is unlocked.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED, if the SPC command is still processing.
+*  CYRET_SUCCESS, if the operation was completed successfully.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_Query(void) 
+{
+    cystatus status;
+    
+    CySpcStart();
+
+    /* Check if SPC is idle */
+    if(CY_SPC_IDLE)
+    {
+        /* SPC is idle now */
+        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+        {
+            status = CYRET_SUCCESS;
+        }
+        else
+        {
+            status = CYRET_UNKNOWN;
+        }
+
+        /* Unlock SPC so that someone else can use it. */
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_STARTED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ByteWritePos
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This is a blocking call. It will not
+*  return until the write operation succeeds or fails.
+*
+* Parameters:
+*  dataByte:   The byte of data to write to the EEPROM.
+*  rowNumber:  The EEPROM row number to program.
+*  byteNumber: The byte number within the row to program.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.
+*  CYRET_LOCKED, if the SPC is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+
+{
+    cystatus status;
+
+    /* Start SPC */
+    CySpcStart();
+
+    if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
+    {
+        /* See if we can get SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load byte of data */
+            if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
+                                                                CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],
+                    dieTemperature[1u]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock SPC so that someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h

@@ -1,79 +1,79 @@
-/*******************************************************************************
-* File Name: CFG_EEPROM.h
-* Version 3.0
-*
-*  Description:
-*   Provides the function definitions for the EEPROM APIs.
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_EEPROM_CFG_EEPROM_H)
-#define CY_EEPROM_CFG_EEPROM_H
-
-#include "cydevice_trm.h"
-#include "CyFlash.h"
-
-#if !defined(CY_PSOC5LP)
-    #error Component EEPROM_v3_0 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5LP) */
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void CFG_EEPROM_Enable(void) ;
-void CFG_EEPROM_Start(void) ;
-void CFG_EEPROM_Stop (void) ;
-cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
-                                            ;
-uint8 CFG_EEPROM_ReadByte(uint16 address) ;
-uint8 CFG_EEPROM_UpdateTemperature(void) ;
-cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
-cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
-cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
-                                                ;
-cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
-cystatus CFG_EEPROM_Query(void) ;
-cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
-                                                ;
-
-
-/****************************************
-*           API Constants
-****************************************/
-
-#define CFG_EEPROM_EEPROM_SIZE            CYDEV_EE_SIZE
-#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)
-
-#define CFG_EEPROM_SECTORS_NUMBER         (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
-
-#define CFG_EEPROM_AHB_REQ_SHIFT          (0x00u)
-#define CFG_EEPROM_AHB_REQ                ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
-#define CFG_EEPROM_AHB_ACK_SHIFT          (0x01u)
-#define CFG_EEPROM_AHB_ACK_MASK           ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
-
-
-/***************************************
-* Registers
-***************************************/
-#define CFG_EEPROM_SPC_EE_SCR_REG                 (*(reg8 *) CYREG_SPC_EE_SCR)
-#define CFG_EEPROM_SPC_EE_SCR_PTR                 ( (reg8 *) CYREG_SPC_EE_SCR)
-
-
-
-/***************************************
-* The following code is DEPRECATED and
-* should not be used in new projects.
-***************************************/
-#define CFG_EEPROM_ByteWrite                  CFG_EEPROM_ByteWritePos
-#define CFG_EEPROM_QueryWrite                 CFG_EEPROM_Query
-
-#endif /* CY_EEPROM_CFG_EEPROM_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CFG_EEPROM.h
+* Version 3.0
+*
+*  Description:
+*   Provides the function definitions for the EEPROM APIs.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_EEPROM_CFG_EEPROM_H)
+#define CY_EEPROM_CFG_EEPROM_H
+
+#include "cydevice_trm.h"
+#include "CyFlash.h"
+
+#if !defined(CY_PSOC5LP)
+    #error Component EEPROM_v3_0 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void CFG_EEPROM_Enable(void) ;
+void CFG_EEPROM_Start(void) ;
+void CFG_EEPROM_Stop (void) ;
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \
+                                            ;
+uint8 CFG_EEPROM_ReadByte(uint16 address) ;
+uint8 CFG_EEPROM_UpdateTemperature(void) ;
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+                                                ;
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Query(void) ;
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+                                                ;
+
+
+/****************************************
+*           API Constants
+****************************************/
+
+#define CFG_EEPROM_EEPROM_SIZE            CYDEV_EE_SIZE
+#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)
+
+#define CFG_EEPROM_SECTORS_NUMBER         (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+
+#define CFG_EEPROM_AHB_REQ_SHIFT          (0x00u)
+#define CFG_EEPROM_AHB_REQ                ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))
+#define CFG_EEPROM_AHB_ACK_SHIFT          (0x01u)
+#define CFG_EEPROM_AHB_ACK_MASK           ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+#define CFG_EEPROM_SPC_EE_SCR_REG                 (*(reg8 *) CYREG_SPC_EE_SCR)
+#define CFG_EEPROM_SPC_EE_SCR_PTR                 ( (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+* The following code is DEPRECATED and
+* should not be used in new projects.
+***************************************/
+#define CFG_EEPROM_ByteWrite                  CFG_EEPROM_ByteWritePos
+#define CFG_EEPROM_QueryWrite                 CFG_EEPROM_Query
+
+#endif /* CY_EEPROM_CFG_EEPROM_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf

@@ -1,123 +1,123 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x0;
-define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
-define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__   = 0x0400;
-/**** End of ICF editor section. ###ICF###*/
-
-
-/******** Definitions ********/
-define symbol CY_APPL_LOADABLE  = 1;
-define symbol CY_APPL_LOADER    = 0;
-define symbol CY_APPL_NUM       = 1;
-define symbol CY_APPL_MAX       = 1;
-define symbol CY_METADATA_SIZE  = 64;
-define symbol CY_EE_IN_BTLDR    = 0x00;
-define symbol CY_EE_SIZE        = 2048;
-include "cybootloader.icf";
-if (!CY_APPL_LOADABLE) {
-    define symbol CYDEV_BTLDR_SIZE = 0;
-}
-
-define symbol CY_FLASH_SIZE     = 131072;
-define symbol CY_APPL_ORIGIN    = 0; 
-define symbol CY_FLASH_ROW_SIZE = 256;
-define symbol CY_ECC_ROW_SIZE   = 32;
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
-define block HSTACK      {block HEAP, last block CSTACK};
-
-if (CY_APPL_LOADABLE)
-{
-define block LOADER     { readonly section .cybootloader };
-}
-define block APPL       with fixed order {readonly section .romvectors, readonly};
-
-/* The address of Flash row next after Bootloader image */
-define symbol CY_BTLDR_END      = CYDEV_BTLDR_SIZE +
-                                    ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
-                                    (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
-
-/* The start address of Standard/Loader/Loadable#1 image */
-define symbol CY_APPL1_START    = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
-
-/* The number of metadata records located at the end of Flash */
-define symbol CY_METADATA_CNT   = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
-
-/* The application area size measured in rows */
-define symbol CY_APPL_ROW_CNT   = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
-
-/* The start address of Loadable#2 image if any */
-define symbol CY_APPL2_START    = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
-
-/* The current image (Standard/Loader/Loadable) start address */
-define symbol CY_APPL_START     = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
-
-/* The ECC data placement address */
-define exported symbol CY_ECC_OFFSET     = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
-
-/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
-define symbol CY_EE_OFFSET      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
-define symbol CY_EE_IN_USE      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
-
-/* Define EEPROM region */
-define region EEPROM_region     = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
-
-/* Define APPL region that will limit application size */
-define region APPL_region       = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
-
-
-/****** Initializations ******/
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-do not initialize  { readwrite section .ramvectors };
-
-/******** Placements *********/
-if (CY_APPL_LOADABLE)
-{
-".cybootloader"    : place at start of ROM_region {block LOADER};
-}
-
-"APPL"             : place at start of APPL_region {block APPL};
-
-"RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
-"readwrite"        : place in RAM_region          { readwrite };
-"HSTACK"           : place at end of RAM_region   { block HSTACK};
-
-keep {  section .cybootloader, 
-        section .cyloadermeta, 
-        section .cyloadablemeta,
-        section .cyconfigecc, 
-        section .cycustnvl, 
-        section .cywolatch,
-        section .cyeeprom, 
-        section .cyflashprotect,
-        section .cymeta };
-
-".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
-if (CY_APPL_LOADABLE)
-{
-".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
-}
-".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
-".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
-".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
-".cyeeprom"       : place in EEPROM_region { readonly section .cyeeprom };
-".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
-".cymeta"         : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-/* EOF */
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
+define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x0400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+/******** Definitions ********/
+define symbol CY_APPL_LOADABLE  = 1;
+define symbol CY_APPL_LOADER    = 0;
+define symbol CY_APPL_NUM       = 1;
+define symbol CY_APPL_MAX       = 1;
+define symbol CY_METADATA_SIZE  = 64;
+define symbol CY_EE_IN_BTLDR    = 0x00;
+define symbol CY_EE_SIZE        = 2048;
+include "cybootloader.icf";
+if (!CY_APPL_LOADABLE) {
+    define symbol CYDEV_BTLDR_SIZE = 0;
+}
+
+define symbol CY_FLASH_SIZE     = 131072;
+define symbol CY_APPL_ORIGIN    = 0; 
+define symbol CY_FLASH_ROW_SIZE = 256;
+define symbol CY_ECC_ROW_SIZE   = 32;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
+define block HSTACK      {block HEAP, last block CSTACK};
+
+if (CY_APPL_LOADABLE)
+{
+define block LOADER     { readonly section .cybootloader };
+}
+define block APPL       with fixed order {readonly section .romvectors, readonly};
+
+/* The address of Flash row next after Bootloader image */
+define symbol CY_BTLDR_END      = CYDEV_BTLDR_SIZE +
+                                    ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
+                                    (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
+
+/* The start address of Standard/Loader/Loadable#1 image */
+define symbol CY_APPL1_START    = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
+
+/* The number of metadata records located at the end of Flash */
+define symbol CY_METADATA_CNT   = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
+
+/* The application area size measured in rows */
+define symbol CY_APPL_ROW_CNT   = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
+
+/* The start address of Loadable#2 image if any */
+define symbol CY_APPL2_START    = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
+
+/* The current image (Standard/Loader/Loadable) start address */
+define symbol CY_APPL_START     = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
+
+/* The ECC data placement address */
+define exported symbol CY_ECC_OFFSET     = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
+
+/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
+define symbol CY_EE_OFFSET      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
+define symbol CY_EE_IN_USE      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
+
+/* Define EEPROM region */
+define region EEPROM_region     = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
+
+/* Define APPL region that will limit application size */
+define region APPL_region       = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
+
+
+/****** Initializations ******/
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { readwrite section .ramvectors };
+
+/******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
+".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
+"APPL"             : place at start of APPL_region {block APPL};
+
+"RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
+"readwrite"        : place in RAM_region          { readwrite };
+"HSTACK"           : place at end of RAM_region   { block HSTACK};
+
+keep {  section .cybootloader, 
+        section .cyloadermeta, 
+        section .cyloadablemeta,
+        section .cyconfigecc, 
+        section .cycustnvl, 
+        section .cywolatch,
+        section .cyeeprom, 
+        section .cyflashprotect,
+        section .cymeta };
+
+".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
+".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
+".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
+".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
+".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
+".cyeeprom"       : place in EEPROM_region { readonly section .cyeeprom };
+".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
+".cymeta"         : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+/* EOF */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat

@@ -1,190 +1,190 @@
-#! armcc -E
-; The first line specifies a preprocessor command that the linker invokes 
-; to pass a scatter file through a C preprocessor.
-
-;********************************************************************************
-;* File Name: Cm3RealView.scat
-;* Version 4.20
-;*
-;*  Description:
-;*  This Linker Descriptor file describes the memory layout of the PSoC5
-;*  device. The memory layout of the final binary and hex images as well as
-;*  the placement in PSoC5 memory is described.
-;*
-;*
-;*  Note:
-;*
-;*  romvectors: Cypress default Interrupt service routine vector table.
-;*
-;*      This is the ISR vector table at bootup. Used only for the reset vector.
-;*
-;*
-;*  ramvectors: Cypress ram interrupt service routine vector table.
-;*
-;*      This is the ISR vector table used by the application.
-;*
-;*
-;********************************************************************************
-;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-;* You may use this file only in accordance with the license, terms, conditions,
-;* disclaimers, and limitations in the end user license agreement accompanying
-;* the software package with which this file was provided.
-;********************************************************************************/
-#include "cyfitter.h"
-
-#define CY_FLASH_SIZE       131072
-#define CY_APPL_ORIGIN      0
-#define CY_FLASH_ROW_SIZE   256
-#define CY_ECC_ROW_SIZE     32
-#define CY_EE_SIZE          2048
-#define CY_METADATA_SIZE    64
-
-
-; Define application base address
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
-    #define CY_APPL_NUM     1
-    #define CY_APPL_MAX     1
-    #define CY_EE_IN_BTLDR  0
-
-    #if CY_APPL_ORIGIN
-        #define APPL1_START     CY_APPL_ORIGIN
-    #else
-        #define APPL1_START     AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
-    #endif
-
-    #define APPL_START      (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
-    #define ECC_OFFSET      ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
-    #define EE_OFFSET       (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
-    #define EE_SIZE         (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
-
-#else
-
-    #define APPL_START      0
-    #define ECC_OFFSET      0
-    #define EE_OFFSET       0
-    #define EE_SIZE         CY_EE_SIZE
-
-#endif
-
-
-; Place Bootloader at the beginning of Flash
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
-
-    CYBOOTLOADER 0
-    {
-        .cybootloader +0
-        {
-            * (.cybootloader)
-        }
-    }
-
-    #if CY_APPL_ORIGIN
-        ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))
-    #endif
-
-#endif
-
-
-APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
-{
-    VECTORS +0
-    {
-        * (.romvectors)
-    }
-
-    CODE +0
-    {
-        * (+RO)
-    }
-
-    ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT
-    {
-        * (.ramvectors)
-    }
-
-    NOINIT_DATA +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    DATA +0
-    {
-        .ANY (+RW, +ZI)
-    }
-
-    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
-    {
-    }
-
-    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
-    {
-    }
-}
-
-
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)
-
-    CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
-    {
-        .cyloadermeta +0 { * (.cyloadermeta) }
-    }
-
-#else
-
-    #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
-
-        CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
-        {
-            .cyloadablemeta +0 { * (.cyloadablemeta) }
-        }
-    
-    #endif
-
-#endif
-
-#if (CYDEV_ECC_ENABLE == 0)
-
-    CYCONFIGECC (0x80000000 + ECC_OFFSET)
-    {
-        .cyconfigecc +0 { * (.cyconfigecc) }
-    }
-
-#endif
-
-CYCUSTNVL 0x90000000
-{
-    .cycustnvl +0 { * (.cycustnvl) }
-}
-
-CYWOLATCH 0x90100000
-{
-    .cywolatch +0 { * (.cywolatch) }
-}
-
-#if defined(CYDEV_ALLOCATE_EEPROM)
-
-    CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
-    {
-        .cyeeprom +0 { * (.cyeeprom) }
-    }
-
-#endif
-
-CYFLASHPROTECT 0x90400000
-{
-    .cyflashprotect +0 { * (.cyflashprotect) }
-}
-
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
-
-    CYLOADERMETA +0
-    {
-        .cyloadermeta +0 { * (.cyloadermeta) }
-    }
-
-#endif
+#! armcc -E
+; The first line specifies a preprocessor command that the linker invokes 
+; to pass a scatter file through a C preprocessor.
+
+;********************************************************************************
+;* File Name: Cm3RealView.scat
+;* Version 4.20
+;*
+;*  Description:
+;*  This Linker Descriptor file describes the memory layout of the PSoC5
+;*  device. The memory layout of the final binary and hex images as well as
+;*  the placement in PSoC5 memory is described.
+;*
+;*
+;*  Note:
+;*
+;*  romvectors: Cypress default Interrupt service routine vector table.
+;*
+;*      This is the ISR vector table at bootup. Used only for the reset vector.
+;*
+;*
+;*  ramvectors: Cypress ram interrupt service routine vector table.
+;*
+;*      This is the ISR vector table used by the application.
+;*
+;*
+;********************************************************************************
+;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+;* You may use this file only in accordance with the license, terms, conditions,
+;* disclaimers, and limitations in the end user license agreement accompanying
+;* the software package with which this file was provided.
+;********************************************************************************/
+#include "cyfitter.h"
+
+#define CY_FLASH_SIZE       131072
+#define CY_APPL_ORIGIN      0
+#define CY_FLASH_ROW_SIZE   256
+#define CY_ECC_ROW_SIZE     32
+#define CY_EE_SIZE          2048
+#define CY_METADATA_SIZE    64
+
+
+; Define application base address
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+    #define CY_APPL_NUM     1
+    #define CY_APPL_MAX     1
+    #define CY_EE_IN_BTLDR  0
+
+    #if CY_APPL_ORIGIN
+        #define APPL1_START     CY_APPL_ORIGIN
+    #else
+        #define APPL1_START     AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
+    #endif
+
+    #define APPL_START      (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
+    #define ECC_OFFSET      ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
+    #define EE_OFFSET       (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
+    #define EE_SIZE         (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
+
+#else
+
+    #define APPL_START      0
+    #define ECC_OFFSET      0
+    #define EE_OFFSET       0
+    #define EE_SIZE         CY_EE_SIZE
+
+#endif
+
+
+; Place Bootloader at the beginning of Flash
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+    CYBOOTLOADER 0
+    {
+        .cybootloader +0
+        {
+            * (.cybootloader)
+        }
+    }
+
+    #if CY_APPL_ORIGIN
+        ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))
+    #endif
+
+#endif
+
+
+APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
+{
+    VECTORS +0
+    {
+        * (.romvectors)
+    }
+
+    CODE +0
+    {
+        * (+RO)
+    }
+
+    ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT
+    {
+        * (.ramvectors)
+    }
+
+    NOINIT_DATA +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    DATA +0
+    {
+        .ANY (+RW, +ZI)
+    }
+
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
+    {
+    }
+
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
+    {
+    }
+}
+
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)
+
+    CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#else
+
+    #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+        CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
+        {
+            .cyloadablemeta +0 { * (.cyloadablemeta) }
+        }
+    
+    #endif
+
+#endif
+
+#if (CYDEV_ECC_ENABLE == 0)
+
+    CYCONFIGECC (0x80000000 + ECC_OFFSET)
+    {
+        .cyconfigecc +0 { * (.cyconfigecc) }
+    }
+
+#endif
+
+CYCUSTNVL 0x90000000
+{
+    .cycustnvl +0 { * (.cycustnvl) }
+}
+
+CYWOLATCH 0x90100000
+{
+    .cywolatch +0 { * (.cywolatch) }
+}
+
+#if defined(CYDEV_ALLOCATE_EEPROM)
+
+    CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
+    {
+        .cyeeprom +0 { * (.cyeeprom) }
+    }
+
+#endif
+
+CYFLASHPROTECT 0x90400000
+{
+    .cyflashprotect +0 { * (.cyflashprotect) }
+}
+
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+    CYLOADERMETA +0
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#endif

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c

@@ -1,539 +1,539 @@
-/*******************************************************************************
-* File Name: Cm3Start.c
-* Version 4.20
-*
-*  Description:
-*  Startup code for the ARM CM3.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include <limits.h>
-#include "cydevice_trm.h"
-#include "cytypes.h"
-#include "cyfitter_cfg.h"
-#include "CyLib.h"
-#include "CyDmac.h"
-#include "cyfitter.h"
-
-#define CY_NUM_INTERRUPTS           (32u)
-#define CY_NUM_VECTORS              (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
-#define CY_NUM_ROM_VECTORS          (4u)
-#define CY_NVIC_APINT_PTR           ((reg32 *) CYREG_NVIC_APPLN_INTR)
-#define CY_NVIC_CFG_CTRL_PTR        ((reg32 *) CYREG_NVIC_CFG_CONTROL)
-#define CY_NVIC_APINT_PRIGROUP_3_5  (0x00000400u)  /* Priority group 3.5 split */
-#define CY_NVIC_APINT_VECTKEY       (0x05FA0000u)  /* This key is required in order to write the NVIC_APINT register */
-#define CY_NVIC_CFG_STACKALIGN      (0x00000200u)  /* This specifies that the exception stack must be 8 byte aligned */
-
-
-/* Extern functions */
-extern void CyBtldr_CheckLaunch(void);
-
-/* Function prototypes */
-void initialize_psoc(void);
-CY_ISR(IntDefaultHandler);
-void Reset(void);
-CY_ISR(IntDefaultHandler);
-
-#if defined(__ARMCC_VERSION)
-    #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
-#elif defined (__GNUC__)
-    #define INITIAL_STACK_POINTER (&__cy_stack)
-#elif defined (__ICCARM__)
-    #pragma language=extended
-    #pragma segment="CSTACK"
-    #define INITIAL_STACK_POINTER  { .__ptr = __sfe( "CSTACK" ) }
-
-    extern void __iar_program_start( void );
-    extern void __iar_data_init3 (void);
-#endif  /* (__ARMCC_VERSION) */
-
-#if defined(__GNUC__)
-    #include <errno.h>
-    extern int  errno;
-    extern int  end;
-#endif  /* defined(__GNUC__) */
-
-/* Global variables */
-#if !defined (__ICCARM__)
-    CY_NOINIT static uint32 cySysNoInitDataValid;
-#endif  /* !defined (__ICCARM__) */
-
-
-/*******************************************************************************
-* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
-*******************************************************************************/
-#if defined (__ICCARM__)
-    #pragma location=".ramvectors"
-    #pragma data_alignment=256
-#else
-    CY_SECTION(".ramvectors")
-    CY_ALIGN(256)
-#endif  /* defined (__ICCARM__) */
-cyisraddress CyRamVectors[CY_NUM_VECTORS];
-
-
-/*******************************************************************************
-* Function Name: IntDefaultHandler
-********************************************************************************
-*
-* Summary:
-*  This function is called for all interrupts, other than a reset that gets
-*  called before the system is setup.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-* Theory:
-*  Any value other than zero is acceptable.
-*
-*******************************************************************************/
-CY_ISR(IntDefaultHandler)
-{
-
-    while(1)
-    {
-        /***********************************************************************
-        * We must not get here. If we do, a serious problem occurs, so go
-        * into an infinite loop.
-        ***********************************************************************/
-    }
-}
-
-
-#if defined(__ARMCC_VERSION)
-
-/* Local function for device reset. */
-extern void Reset(void);
-
-/* Application entry point. */
-extern void $Super$$main(void);
-
-/* Linker-generated Stack Base addresses, Two Region and One Region */
-extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;
-
-/* RealView C Library initialization. */
-extern int __main(void);
-
-
-/*******************************************************************************
-* Function Name: Reset
-********************************************************************************
-*
-* Summary:
-*  This function handles the reset interrupt for the RVDS/MDK toolchains.
-*  This is the first bit of code that is executed at startup.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void Reset(void)
-{
-    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
-
-        /* For PSoC 5LP, debugging is enabled by default */
-        #if(CYDEV_DEBUGGING_ENABLE == 0)
-            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
-        #endif /* (CYDEV_DEBUGGING_ENABLE) */
-
-        /* Reset Status Register has Read-to-clear SW access mode.
-        * Preserve current RESET_SR0 state to make it available for next reading.
-        */
-        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
-
-    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
-
-    #if(CYDEV_BOOTLOADER_ENABLE)
-        CyBtldr_CheckLaunch();
-    #endif /* (CYDEV_BOOTLOADER_ENABLE) */
-
-    __main();
-}
-
-
-/*******************************************************************************
-* Function Name: $Sub$$main
-********************************************************************************
-*
-* Summary:
-*  This function is called immediately before the users main
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void $Sub$$main(void)
-{
-    initialize_psoc();
-
-    /* Call original main */
-    $Super$$main();
-
-    while (1)
-    {
-        /* If main returns, it is undefined what we should do. */
-    }
-}
-
-#elif defined(__GNUC__)
-
-void Start_c(void);
-
-/* Stack Base address */
-extern void __cy_stack(void);
-
-/* Application entry point. */
-extern int main(void);
-
-/* Static objects constructors initializer */
-extern void __libc_init_array(void);
-
-typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
-
-struct __cy_region
-{
-    __cy_byte_align8 *init; /* Initial contents of this region.  */
-    __cy_byte_align8 *data; /* Start address of region.  */
-    size_t init_size;       /* Size of initial data.  */
-    size_t zero_size;       /* Additional size to be zeroed.  */
-};
-
-extern const struct __cy_region __cy_regions[];
-extern const char __cy_region_num __attribute__((weak));
-#define __cy_region_num ((size_t)&__cy_region_num)
-
-
-/*******************************************************************************
-* System Calls of the Red Hat newlib C Library
-*******************************************************************************/
-
-
-/*******************************************************************************
-* Function Name: _exit
-********************************************************************************
-*
-* Summary:
-*  Exit a program without cleaning up files. If your system doesn't provide
-*  this, it is best to avoid linking with subroutines that require it (exit,
-*  system).
-*
-* Parameters:
-*  status: Status caused program exit.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-__attribute__((weak))
-void _exit(int status)
-{
-    /* Cause divide by 0 exception */
-    int x = status / (int) INT_MAX;
-    x = 4 / x;
-
-    while(1)
-    {
-
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: _sbrk
-********************************************************************************
-*
-* Summary:
-*  Increase program data space. As malloc and related functions depend on this,
-*  it is useful to have a working implementation. The following suffices for a
-*  standalone system; it exploits the symbol end automatically defined by the
-*  GNU linker.
-*
-* Parameters:
-*  nbytes: The number of bytes requested (if the parameter value is positive)
-*  from the heap or returned back to the heap (if the parameter value is
-*  negative).
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-__attribute__((weak))
-void * _sbrk (int nbytes)
-{
-    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
-    void *      returnValue;
-
-    /* The statically held previous end of the heap, with its initialization. */
-    static void *heapPointer = (void *) &end;                 /* Previous end */
-
-    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
-    {
-        returnValue  = heapPointer;
-        heapPointer += nbytes;
-    }
-    else
-    {
-        errno = ENOMEM;
-        returnValue = (void *) -1;
-    }
-
-    return (returnValue);
-}
-
-
-/*******************************************************************************
-* Function Name: Reset
-********************************************************************************
-*
-* Summary:
-*  This function handles the reset interrupt for the GCC toolchain. This is the
-*  first bit of code that is executed at startup.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void Reset(void)
-{
-    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
-
-        /* For PSoC 5LP, debugging is enabled by default */
-        #if(CYDEV_DEBUGGING_ENABLE == 0)
-            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
-        #endif /* (CYDEV_DEBUGGING_ENABLE) */
-
-        /* Reset Status Register has Read-to-clear SW access mode.
-        * Preserve current RESET_SR0 state to make it available for next reading.
-        */
-        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
-
-    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
-
-    #if(CYDEV_BOOTLOADER_ENABLE)
-        CyBtldr_CheckLaunch();
-    #endif /* (CYDEV_BOOTLOADER_ENABLE) */
-
-    Start_c();
-}
-
-
-/*******************************************************************************
-* Function Name: Start_c
-********************************************************************************
-*
-* Summary:
-*  This function handles initializing the .data and .bss sections in
-*  preparation for running the standard C code.  Once initialization is complete
-*  it will call main(). This function will never return.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void Start_c(void)  __attribute__ ((noreturn));
-void Start_c(void)
-{
-    unsigned regions = __cy_region_num;
-    const struct __cy_region *rptr = __cy_regions;
-
-    /* Initialize memory */
-    for (regions = __cy_region_num; regions != 0u; regions--)
-    {
-        uint32 *src = (uint32 *)rptr->init;
-        uint32 *dst = (uint32 *)rptr->data;
-        unsigned limit = rptr->init_size;
-        unsigned count;
-
-        for (count = 0u; count != limit; count += sizeof (uint32))
-        {
-            *dst = *src;
-            dst++;
-            src++;
-        }
-        limit = rptr->zero_size;
-        for (count = 0u; count != limit; count += sizeof (uint32))
-        {
-            *dst = 0u;
-            dst++;
-        }
-
-        rptr++;
-    }
-
-    /* Invoke static objects constructors */
-    __libc_init_array();
-    (void) main();
-
-    while (1)
-    {
-        /* If main returns, make sure we don't return. */
-    }
-}
-
-
-#elif defined (__ICCARM__)
-
-/*******************************************************************************
-* Function Name: __low_level_init
-********************************************************************************
-*
-* Summary:
-*  This function performs early initializations for the IAR Embedded
-*  Workbench IDE. It is executed in the context of a reset interrupt handler
-*  before the data sections are initialized.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  The value that determines whether or not data sections should be initialized
-*  by the system startup code:
-*    0 - skip data sections initialization;
-*    1 - initialize data sections;
-*
-*******************************************************************************/
-int __low_level_init(void)
-{
-    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
-
-        /* For PSoC 5LP, debugging is enabled by default */
-        #if(CYDEV_DEBUGGING_ENABLE == 0)
-            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
-        #endif /* (CYDEV_DEBUGGING_ENABLE) */
-
-        /* Reset Status Register has Read-to-clear SW access mode.
-        * Preserve current RESET_SR0 state to make it available for next reading.
-        */
-        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
-
-    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
-
-    #if (CYDEV_BOOTLOADER_ENABLE)
-        CyBtldr_CheckLaunch();
-    #endif /* CYDEV_BOOTLOADER_ENABLE */
-
-    /* Initialize data sections */
-    __iar_data_init3();
-
-    initialize_psoc();
-
-    return 0;
-}
-
-#endif /* __GNUC__ */
-
-
-/*******************************************************************************
-*
-* Default Rom Interrupt Vector table.
-*
-*******************************************************************************/
-#if defined(__ARMCC_VERSION)
-    /* Suppress diagnostic message 1296-D: extended constant initialiser used */
-    #pragma diag_suppress 1296
-#endif  /* defined(__ARMCC_VERSION) */
-
-#if defined (__ICCARM__)
-    #pragma location=".romvectors"
-    const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
-#else
-    CY_SECTION(".romvectors")
-    const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
-#endif  /* defined (__ICCARM__) */
-{
-    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
-    #if defined (__ICCARM__) /* Reset handler          1 */
-        __iar_program_start,
-    #else
-        (cyisraddress)&Reset,
-    #endif  /* defined (__ICCARM__) */
-    &IntDefaultHandler,      /* NMI handler            2 */
-    &IntDefaultHandler,      /* Hard fault handler     3 */
-};
-
-#if defined(__ARMCC_VERSION)
-    #pragma diag_default 1296
-#endif  /* defined(__ARMCC_VERSION) */
-
-
-/*******************************************************************************
-* Function Name: initialize_psoc
-********************************************************************************
-*
-* Summary:
-*  This function used to initialize the PSoC chip before calling main.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
-__attribute__ ((constructor(101)))
-#endif
-void initialize_psoc(void)
-{
-    uint32 i;
-
-    /* Set Priority group 5. */
-
-    /* Writes to NVIC_APINT register require the VECTKEY in the upper half */
-    *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
-    *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
-
-    /* Set Ram interrupt vectors to default functions. */
-    for (i = 0u; i < CY_NUM_VECTORS; i++)
-    {
-        #if defined (__ICCARM__)
-            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
-        #else
-            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
-        #endif  /* defined (__ICCARM__) */
-    }
-
-    /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
-    CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
-
-    /* Point NVIC at RAM vector table. */
-    *CYINT_VECT_TABLE = CyRamVectors;
-
-    /* Initialize the configuration registers. */
-    cyfitter_cfg();
-
-    #if(0u != DMA_CHANNELS_USED__MASK0)
-
-        /* Setup DMA - only necessary if design contains DMA component. */
-        CyDmacConfigure();
-
-    #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
-
-    #if !defined (__ICCARM__)
-        /* Actually, no need to clean this variable, just to make compiler happy. */
-        cySysNoInitDataValid = 0u;
-    #endif  /* !defined (__ICCARM__) */
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Cm3Start.c
+* Version 4.20
+*
+*  Description:
+*  Startup code for the ARM CM3.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <limits.h>
+#include "cydevice_trm.h"
+#include "cytypes.h"
+#include "cyfitter_cfg.h"
+#include "CyLib.h"
+#include "CyDmac.h"
+#include "cyfitter.h"
+
+#define CY_NUM_INTERRUPTS           (32u)
+#define CY_NUM_VECTORS              (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
+#define CY_NUM_ROM_VECTORS          (4u)
+#define CY_NVIC_APINT_PTR           ((reg32 *) CYREG_NVIC_APPLN_INTR)
+#define CY_NVIC_CFG_CTRL_PTR        ((reg32 *) CYREG_NVIC_CFG_CONTROL)
+#define CY_NVIC_APINT_PRIGROUP_3_5  (0x00000400u)  /* Priority group 3.5 split */
+#define CY_NVIC_APINT_VECTKEY       (0x05FA0000u)  /* This key is required in order to write the NVIC_APINT register */
+#define CY_NVIC_CFG_STACKALIGN      (0x00000200u)  /* This specifies that the exception stack must be 8 byte aligned */
+
+
+/* Extern functions */
+extern void CyBtldr_CheckLaunch(void);
+
+/* Function prototypes */
+void initialize_psoc(void);
+CY_ISR(IntDefaultHandler);
+void Reset(void);
+CY_ISR(IntDefaultHandler);
+
+#if defined(__ARMCC_VERSION)
+    #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
+#elif defined (__GNUC__)
+    #define INITIAL_STACK_POINTER (&__cy_stack)
+#elif defined (__ICCARM__)
+    #pragma language=extended
+    #pragma segment="CSTACK"
+    #define INITIAL_STACK_POINTER  { .__ptr = __sfe( "CSTACK" ) }
+
+    extern void __iar_program_start( void );
+    extern void __iar_data_init3 (void);
+#endif  /* (__ARMCC_VERSION) */
+
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
+/* Global variables */
+#if !defined (__ICCARM__)
+    CY_NOINIT static uint32 cySysNoInitDataValid;
+#endif  /* !defined (__ICCARM__) */
+
+
+/*******************************************************************************
+* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
+*******************************************************************************/
+#if defined (__ICCARM__)
+    #pragma location=".ramvectors"
+    #pragma data_alignment=256
+#else
+    CY_SECTION(".ramvectors")
+    CY_ALIGN(256)
+#endif  /* defined (__ICCARM__) */
+cyisraddress CyRamVectors[CY_NUM_VECTORS];
+
+
+/*******************************************************************************
+* Function Name: IntDefaultHandler
+********************************************************************************
+*
+* Summary:
+*  This function is called for all interrupts, other than a reset that gets
+*  called before the system is setup.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+* Theory:
+*  Any value other than zero is acceptable.
+*
+*******************************************************************************/
+CY_ISR(IntDefaultHandler)
+{
+
+    while(1)
+    {
+        /***********************************************************************
+        * We must not get here. If we do, a serious problem occurs, so go
+        * into an infinite loop.
+        ***********************************************************************/
+    }
+}
+
+
+#if defined(__ARMCC_VERSION)
+
+/* Local function for device reset. */
+extern void Reset(void);
+
+/* Application entry point. */
+extern void $Super$$main(void);
+
+/* Linker-generated Stack Base addresses, Two Region and One Region */
+extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+/* RealView C Library initialization. */
+extern int __main(void);
+
+
+/*******************************************************************************
+* Function Name: Reset
+********************************************************************************
+*
+* Summary:
+*  This function handles the reset interrupt for the RVDS/MDK toolchains.
+*  This is the first bit of code that is executed at startup.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void Reset(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+
+    #if(CYDEV_BOOTLOADER_ENABLE)
+        CyBtldr_CheckLaunch();
+    #endif /* (CYDEV_BOOTLOADER_ENABLE) */
+
+    __main();
+}
+
+
+/*******************************************************************************
+* Function Name: $Sub$$main
+********************************************************************************
+*
+* Summary:
+*  This function is called immediately before the users main
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void $Sub$$main(void)
+{
+    initialize_psoc();
+
+    /* Call original main */
+    $Super$$main();
+
+    while (1)
+    {
+        /* If main returns, it is undefined what we should do. */
+    }
+}
+
+#elif defined(__GNUC__)
+
+void Start_c(void);
+
+/* Stack Base address */
+extern void __cy_stack(void);
+
+/* Application entry point. */
+extern int main(void);
+
+/* Static objects constructors initializer */
+extern void __libc_init_array(void);
+
+typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
+
+struct __cy_region
+{
+    __cy_byte_align8 *init; /* Initial contents of this region.  */
+    __cy_byte_align8 *data; /* Start address of region.  */
+    size_t init_size;       /* Size of initial data.  */
+    size_t zero_size;       /* Additional size to be zeroed.  */
+};
+
+extern const struct __cy_region __cy_regions[];
+extern const char __cy_region_num __attribute__((weak));
+#define __cy_region_num ((size_t)&__cy_region_num)
+
+
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+* Parameters:
+*  status: Status caused program exit.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause divide by 0 exception */
+    int x = status / (int) INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+* Parameters:
+*  nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static void *heapPointer = (void *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Reset
+********************************************************************************
+*
+* Summary:
+*  This function handles the reset interrupt for the GCC toolchain. This is the
+*  first bit of code that is executed at startup.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void Reset(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+
+    #if(CYDEV_BOOTLOADER_ENABLE)
+        CyBtldr_CheckLaunch();
+    #endif /* (CYDEV_BOOTLOADER_ENABLE) */
+
+    Start_c();
+}
+
+
+/*******************************************************************************
+* Function Name: Start_c
+********************************************************************************
+*
+* Summary:
+*  This function handles initializing the .data and .bss sections in
+*  preparation for running the standard C code.  Once initialization is complete
+*  it will call main(). This function will never return.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void Start_c(void)  __attribute__ ((noreturn));
+void Start_c(void)
+{
+    unsigned regions = __cy_region_num;
+    const struct __cy_region *rptr = __cy_regions;
+
+    /* Initialize memory */
+    for (regions = __cy_region_num; regions != 0u; regions--)
+    {
+        uint32 *src = (uint32 *)rptr->init;
+        uint32 *dst = (uint32 *)rptr->data;
+        unsigned limit = rptr->init_size;
+        unsigned count;
+
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst = *src;
+            dst++;
+            src++;
+        }
+        limit = rptr->zero_size;
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst = 0u;
+            dst++;
+        }
+
+        rptr++;
+    }
+
+    /* Invoke static objects constructors */
+    __libc_init_array();
+    (void) main();
+
+    while (1)
+    {
+        /* If main returns, make sure we don't return. */
+    }
+}
+
+
+#elif defined (__ICCARM__)
+
+/*******************************************************************************
+* Function Name: __low_level_init
+********************************************************************************
+*
+* Summary:
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
+*  before the data sections are initialized.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  The value that determines whether or not data sections should be initialized
+*  by the system startup code:
+*    0 - skip data sections initialization;
+*    1 - initialize data sections;
+*
+*******************************************************************************/
+int __low_level_init(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+
+    #if (CYDEV_BOOTLOADER_ENABLE)
+        CyBtldr_CheckLaunch();
+    #endif /* CYDEV_BOOTLOADER_ENABLE */
+
+    /* Initialize data sections */
+    __iar_data_init3();
+
+    initialize_psoc();
+
+    return 0;
+}
+
+#endif /* __GNUC__ */
+
+
+/*******************************************************************************
+*
+* Default Rom Interrupt Vector table.
+*
+*******************************************************************************/
+#if defined(__ARMCC_VERSION)
+    /* Suppress diagnostic message 1296-D: extended constant initialiser used */
+    #pragma diag_suppress 1296
+#endif  /* defined(__ARMCC_VERSION) */
+
+#if defined (__ICCARM__)
+    #pragma location=".romvectors"
+    const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
+#else
+    CY_SECTION(".romvectors")
+    const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
+#endif  /* defined (__ICCARM__) */
+{
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
+        __iar_program_start,
+    #else
+        (cyisraddress)&Reset,
+    #endif  /* defined (__ICCARM__) */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
+};
+
+#if defined(__ARMCC_VERSION)
+    #pragma diag_default 1296
+#endif  /* defined(__ARMCC_VERSION) */
+
+
+/*******************************************************************************
+* Function Name: initialize_psoc
+********************************************************************************
+*
+* Summary:
+*  This function used to initialize the PSoC chip before calling main.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
+__attribute__ ((constructor(101)))
+#endif
+void initialize_psoc(void)
+{
+    uint32 i;
+
+    /* Set Priority group 5. */
+
+    /* Writes to NVIC_APINT register require the VECTKEY in the upper half */
+    *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
+    *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
+
+    /* Set Ram interrupt vectors to default functions. */
+    for (i = 0u; i < CY_NUM_VECTORS; i++)
+    {
+        #if defined (__ICCARM__)
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
+        #else
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
+        #endif  /* defined (__ICCARM__) */
+    }
+
+    /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
+    CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
+
+    /* Point NVIC at RAM vector table. */
+    *CYINT_VECT_TABLE = CyRamVectors;
+
+    /* Initialize the configuration registers. */
+    cyfitter_cfg();
+
+    #if(0u != DMA_CHANNELS_USED__MASK0)
+
+        /* Setup DMA - only necessary if design contains DMA component. */
+        CyDmacConfigure();
+
+    #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
+
+    #if !defined (__ICCARM__)
+        /* Actually, no need to clean this variable, just to make compiler happy. */
+        cySysNoInitDataValid = 0u;
+    #endif  /* !defined (__ICCARM__) */
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s

@@ -1,174 +1,174 @@
-/*******************************************************************************
-* File Name: CyBootAsmGnu.s
-* Version 4.20
-*
-*  Description:
-*   Assembly routines for GNU as.
-*
-********************************************************************************
-* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-.include "cyfittergnu.inc"
-
-.syntax unified
-.text
-.thumb
-
-
-/*******************************************************************************
-* Function Name: CyDelayCycles
-********************************************************************************
-*
-* Summary:
-*  Delays for the specified number of cycles.
-*
-* Parameters:
-*  uint32 cycles: number of cycles to delay.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-/* void CyDelayCycles(uint32 cycles) */
-.align 3                    /* Align to 8 byte boundary (2^n) */
-.global CyDelayCycles
-.func CyDelayCycles, CyDelayCycles
-.type CyDelayCycles, %function
-.thumb_func
-CyDelayCycles:              /* cycles bytes */
-/* If ICache is enabled */
-.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
-
-    ADDS r0, r0, #2           /*  1    2   Round to nearest multiple of 4 */
-    LSRS r0, r0, #2           /*  1    2   Divide by 4 and set flags */
-    BEQ CyDelayCycles_done    /*  2    2   Skip if 0 */
-    NOP                       /*  1    2   Loop alignment padding */
-
-CyDelayCycles_loop:
-    SUBS r0, r0, #1           /*  1    2 */
-    MOV r0, r0                /*  1    2   Pad loop to power of two cycles */
-    BNE CyDelayCycles_loop    /*  2    2 */
-
-CyDelayCycles_done:
-    BX lr                     /*  3    2 */
-
-.else
-
-    CMP r0, #20               /*  1    2   If delay is short - jump to cycle */
-    BLS CyDelayCycles_short   /*  1    2  */
-    PUSH {r1}                 /*  2    2   PUSH r1 to stack */
-    MOVS r1, #1               /*  1    2  */
-
-    SUBS r0, r0, #20          /*  1    2   Subtract overhead */
-    LDR r1,=CYREG_CACHE_CC_CTL/*  2    2   Load flash wait cycles value */
-    LDRB r1, [r1, #0]         /*  2    2  */
-    ANDS r1, #0xC0            /*  1    2  */
-
-    LSRS r1, r1, #6           /*  1    2  */
-    PUSH {r2}                 /*  1    2   PUSH r2 to stack */
-    LDR r2, =cy_flash_cycles  /*  2    2  */
-    LDRB r1, [r2, r1]         /*  2    2  */
-
-    POP {r2}                  /*  2    2   POP r2 from stack */
-    NOP                       /*  1    2   Alignment padding */
-    NOP                       /*  1    2   Alignment padding */
-    NOP                       /*  1    2   Alignment padding */
-
-CyDelayCycles_loop:
-    SBCS r0, r0, r1           /*  1    2  */
-    BPL CyDelayCycles_loop    /*  3    2  */
-    NOP                       /*  1    2   Loop alignment padding */
-    NOP                       /*  1    2   Loop alignment padding */
-
-    POP {r1}                  /*  2    2   POP r1 from stack */
-CyDelayCycles_done:
-    BX lr                     /*  3    2  */
-    NOP                       /*  1    2   Alignment padding */
-    NOP                       /*  1    2   Alignment padding */
-
-CyDelayCycles_short:
-    SBCS r0, r0, #4           /*  1    2  */
-    BPL CyDelayCycles_short   /*  3    2  */
-    BX lr                     /*  3    2  */
-
-cy_flash_cycles:
-.byte 0x0B
-.byte 0x05
-.byte 0x07
-.byte 0x09
-.endif
-
-.endfunc
-
-
-/*******************************************************************************
-* Function Name: CyEnterCriticalSection
-********************************************************************************
-*
-* Summary:
-*  CyEnterCriticalSection disables interrupts and returns a value indicating
-*  whether interrupts were previously enabled (the actual value depends on
-*  whether the device is PSoC 3 or PSoC 5).
-*
-*  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
-*  with interrupts still enabled. The test and set of the interrupt bits is not
-*  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
-*  corrupting processor state, it must be the policy that all interrupt routines
-*  restore the interrupt enable bits as they were found on entry.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  uint8
-*   Returns 0 if interrupts were previously enabled or 1 if interrupts
-*   were previously disabled.
-*
-*******************************************************************************/
-/* uint8 CyEnterCriticalSection(void) */
-.global CyEnterCriticalSection
-.func CyEnterCriticalSection, CyEnterCriticalSection
-.type CyEnterCriticalSection, %function
-.thumb_func
-CyEnterCriticalSection:
-    MRS r0, PRIMASK         /* Save and return interrupt state */
-    CPSID I                 /* Disable interrupts */
-    BX lr
-.endfunc
-
-
-/*******************************************************************************
-* Function Name: CyExitCriticalSection
-********************************************************************************
-*
-* Summary:
-*  CyExitCriticalSection re-enables interrupts if they were enabled before
-*  CyEnterCriticalSection was called. The argument should be the value returned
-*  from CyEnterCriticalSection.
-*
-* Parameters:
-*  uint8 savedIntrStatus:
-*   Saved interrupt status returned by the CyEnterCriticalSection function.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-/* void CyExitCriticalSection(uint8 savedIntrStatus) */
-.global CyExitCriticalSection
-.func CyExitCriticalSection, CyExitCriticalSection
-.type CyExitCriticalSection, %function
-.thumb_func
-CyExitCriticalSection:
-    MSR PRIMASK, r0         /* Restore interrupt state */
-    BX lr
-.endfunc
-
-.end
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyBootAsmGnu.s
+* Version 4.20
+*
+*  Description:
+*   Assembly routines for GNU as.
+*
+********************************************************************************
+* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+.include "cyfittergnu.inc"
+
+.syntax unified
+.text
+.thumb
+
+
+/*******************************************************************************
+* Function Name: CyDelayCycles
+********************************************************************************
+*
+* Summary:
+*  Delays for the specified number of cycles.
+*
+* Parameters:
+*  uint32 cycles: number of cycles to delay.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+/* void CyDelayCycles(uint32 cycles) */
+.align 3                    /* Align to 8 byte boundary (2^n) */
+.global CyDelayCycles
+.func CyDelayCycles, CyDelayCycles
+.type CyDelayCycles, %function
+.thumb_func
+CyDelayCycles:              /* cycles bytes */
+/* If ICache is enabled */
+.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
+
+    ADDS r0, r0, #2           /*  1    2   Round to nearest multiple of 4 */
+    LSRS r0, r0, #2           /*  1    2   Divide by 4 and set flags */
+    BEQ CyDelayCycles_done    /*  2    2   Skip if 0 */
+    NOP                       /*  1    2   Loop alignment padding */
+
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           /*  1    2 */
+    MOV r0, r0                /*  1    2   Pad loop to power of two cycles */
+    BNE CyDelayCycles_loop    /*  2    2 */
+
+CyDelayCycles_done:
+    BX lr                     /*  3    2 */
+
+.else
+
+    CMP r0, #20               /*  1    2   If delay is short - jump to cycle */
+    BLS CyDelayCycles_short   /*  1    2  */
+    PUSH {r1}                 /*  2    2   PUSH r1 to stack */
+    MOVS r1, #1               /*  1    2  */
+
+    SUBS r0, r0, #20          /*  1    2   Subtract overhead */
+    LDR r1,=CYREG_CACHE_CC_CTL/*  2    2   Load flash wait cycles value */
+    LDRB r1, [r1, #0]         /*  2    2  */
+    ANDS r1, #0xC0            /*  1    2  */
+
+    LSRS r1, r1, #6           /*  1    2  */
+    PUSH {r2}                 /*  1    2   PUSH r2 to stack */
+    LDR r2, =cy_flash_cycles  /*  2    2  */
+    LDRB r1, [r2, r1]         /*  2    2  */
+
+    POP {r2}                  /*  2    2   POP r2 from stack */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
+CyDelayCycles_loop:
+    SBCS r0, r0, r1           /*  1    2  */
+    BPL CyDelayCycles_loop    /*  3    2  */
+    NOP                       /*  1    2   Loop alignment padding */
+    NOP                       /*  1    2   Loop alignment padding */
+
+    POP {r1}                  /*  2    2   POP r1 from stack */
+CyDelayCycles_done:
+    BX lr                     /*  3    2  */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
+CyDelayCycles_short:
+    SBCS r0, r0, #4           /*  1    2  */
+    BPL CyDelayCycles_short   /*  3    2  */
+    BX lr                     /*  3    2  */
+
+cy_flash_cycles:
+.byte 0x0B
+.byte 0x05
+.byte 0x07
+.byte 0x09
+.endif
+
+.endfunc
+
+
+/*******************************************************************************
+* Function Name: CyEnterCriticalSection
+********************************************************************************
+*
+* Summary:
+*  CyEnterCriticalSection disables interrupts and returns a value indicating
+*  whether interrupts were previously enabled (the actual value depends on
+*  whether the device is PSoC 3 or PSoC 5).
+*
+*  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+*  with interrupts still enabled. The test and set of the interrupt bits is not
+*  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+*  corrupting processor state, it must be the policy that all interrupt routines
+*  restore the interrupt enable bits as they were found on entry.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  uint8
+*   Returns 0 if interrupts were previously enabled or 1 if interrupts
+*   were previously disabled.
+*
+*******************************************************************************/
+/* uint8 CyEnterCriticalSection(void) */
+.global CyEnterCriticalSection
+.func CyEnterCriticalSection, CyEnterCriticalSection
+.type CyEnterCriticalSection, %function
+.thumb_func
+CyEnterCriticalSection:
+    MRS r0, PRIMASK         /* Save and return interrupt state */
+    CPSID I                 /* Disable interrupts */
+    BX lr
+.endfunc
+
+
+/*******************************************************************************
+* Function Name: CyExitCriticalSection
+********************************************************************************
+*
+* Summary:
+*  CyExitCriticalSection re-enables interrupts if they were enabled before
+*  CyEnterCriticalSection was called. The argument should be the value returned
+*  from CyEnterCriticalSection.
+*
+* Parameters:
+*  uint8 savedIntrStatus:
+*   Saved interrupt status returned by the CyEnterCriticalSection function.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+/* void CyExitCriticalSection(uint8 savedIntrStatus) */
+.global CyExitCriticalSection
+.func CyExitCriticalSection, CyExitCriticalSection
+.type CyExitCriticalSection, %function
+.thumb_func
+CyExitCriticalSection:
+    MSR PRIMASK, r0         /* Restore interrupt state */
+    BX lr
+.endfunc
+
+.end
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s

@@ -1,156 +1,156 @@
-;-------------------------------------------------------------------------------
-; FILENAME: CyBootAsmIar.s
-; Version 4.20
-;
-;  DESCRIPTION:
-;    Assembly routines for IAR Embedded Workbench IDE.
-;
-;-------------------------------------------------------------------------------
-; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
-; You may use this file only in accordance with the license, terms, conditions,
-; disclaimers, and limitations in the end user license agreement accompanying
-; the software package with which this file was provided.
-;-------------------------------------------------------------------------------
-
-    SECTION .text:CODE:ROOT(4)
-    PUBLIC CyDelayCycles
-    PUBLIC CyEnterCriticalSection
-    PUBLIC CyExitCriticalSection
-    INCLUDE cyfitteriar.inc
-    THUMB
-
-
-;-------------------------------------------------------------------------------
-; Function Name: CyEnterCriticalSection
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  CyEnterCriticalSection disables interrupts and returns a value indicating
-;  whether interrupts were previously enabled.
-;
-;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
-;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
-;  that all interrupt routines restore the interrupt enable bits as they were 
-;  found on entry.
-;
-; Parameters:
-;  None
-;
-; Return:
-;  uint8
-;   Returns 0 if interrupts were previously enabled or 1 if interrupts
-;   were previously disabled.
-;
-;-------------------------------------------------------------------------------
-; uint8 CyEnterCriticalSection(void)
-
-CyEnterCriticalSection:
-    MRS r0, PRIMASK         ; Save and return interrupt state
-    CPSID I                 ; Disable interrupts
-    BX lr
-
-
-;-------------------------------------------------------------------------------
-; Function Name: CyExitCriticalSection
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  CyExitCriticalSection re-enables interrupts if they were enabled before
-;  CyEnterCriticalSection was called. The argument should be the value returned
-;  from CyEnterCriticalSection.
-;
-; Parameters:
-;  uint8 savedIntrStatus:
-;   Saved interrupt status returned by the CyEnterCriticalSection function.
-;
-; Return:
-;  None
-;
-;-------------------------------------------------------------------------------
-; void CyExitCriticalSection(uint8 savedIntrStatus)
-
-CyExitCriticalSection:
-    MSR PRIMASK, r0         ; Restore interrupt state
-    BX lr
-
-
-;-------------------------------------------------------------------------------
-; Function Name: CyDelayCycles
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  Delays for the specified number of cycles.
-;
-; Parameters:
-;  uint32 cycles: number of cycles to delay.
-;
-; Return:
-;  None
-;
-;-------------------------------------------------------------------------------
-; void CyDelayCycles(uint32 cycles)
-
-CyDelayCycles: 
-    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
-                              ; cycles bytes
-    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
-    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
-    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
-    NOP                       ;   1   2  Loop alignment padding
-CyDelayCycles_loop:
-    SUBS r0, r0, #1           ;   1   2
-    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
-    BNE CyDelayCycles_loop    ;   2   2
-CyDelayCycles_done:
-    BX lr                     ;   3   2
-    
-    ELSE
-    
-    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
-    BLS CyDelayCycles_short   ;   1   2
-    PUSH {r1}                 ;   2   2  PUSH r1 to stack
-    MOVS r1, #1               ;   1   2
-
-    SUBS r0, r0, #20          ;   1   2  Subtract overhead
-    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
-    LDRB r1, [r1, #0]         ;   2   2
-    ANDS r1, r1, #0xC0        ;   1   2
-
-    LSRS r1, r1, #6           ;   1   2
-    PUSH {r2}                 ;   1   2  PUSH r2 to stack
-    LDR r2, =cy_flash_cycles  ;   2   2
-    LDRB r1, [r2, r1]         ;   2   2
-
-    POP {r2}                  ;   2   2  POP r2 from stack
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-
-CyDelayCycles_loop:
-    SBCS r0, r0, r1           ;   1   2
-    BPL CyDelayCycles_loop    ;   3   2
-    NOP                       ;   1   2  Loop alignment padding
-    NOP                       ;   1   2  Loop alignment padding
-
-    POP {r1}                  ;   2   2  POP r1 from stack
-CyDelayCycles_done:
-    BX lr                     ;   3   2
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-CyDelayCycles_short:
-    SBCS r0, r0, #4           ;   1   2
-    BPL CyDelayCycles_short   ;   3   2
-    BX lr                     ;   3   2
-    NOP                       ;   1   2   Loop alignment padding
-
-    DATA
-cy_flash_cycles:
-byte_1 DCB 0x0B
-byte_2 DCB 0x05
-byte_3 DCB 0x07
-byte_4 DCB 0x09
-
-    ENDIF
-
-    END
+;-------------------------------------------------------------------------------
+; FILENAME: CyBootAsmIar.s
+; Version 4.20
+;
+;  DESCRIPTION:
+;    Assembly routines for IAR Embedded Workbench IDE.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions,
+; disclaimers, and limitations in the end user license agreement accompanying
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+    SECTION .text:CODE:ROOT(4)
+    PUBLIC CyDelayCycles
+    PUBLIC CyEnterCriticalSection
+    PUBLIC CyExitCriticalSection
+    INCLUDE cyfitteriar.inc
+    THUMB
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyEnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyEnterCriticalSection disables interrupts and returns a value indicating
+;  whether interrupts were previously enabled.
+;
+;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+;  with interrupts still enabled. The test and set of the interrupt bits is not
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
+;  that all interrupt routines restore the interrupt enable bits as they were 
+;  found on entry.
+;
+; Parameters:
+;  None
+;
+; Return:
+;  uint8
+;   Returns 0 if interrupts were previously enabled or 1 if interrupts
+;   were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8 CyEnterCriticalSection(void)
+
+CyEnterCriticalSection:
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyExitCriticalSection re-enables interrupts if they were enabled before
+;  CyEnterCriticalSection was called. The argument should be the value returned
+;  from CyEnterCriticalSection.
+;
+; Parameters:
+;  uint8 savedIntrStatus:
+;   Saved interrupt status returned by the CyEnterCriticalSection function.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyExitCriticalSection(uint8 savedIntrStatus)
+
+CyExitCriticalSection:
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyDelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  Delays for the specified number of cycles.
+;
+; Parameters:
+;  uint32 cycles: number of cycles to delay.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyDelayCycles(uint32 cycles)
+
+CyDelayCycles: 
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    
+    ELSE
+    
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, r1, #0xC0        ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop:
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+CyDelayCycles_short:
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+    NOP                       ;   1   2   Loop alignment padding
+
+    DATA
+cy_flash_cycles:
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+
+    END

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s

@@ -1,161 +1,161 @@
-;-------------------------------------------------------------------------------
-; FILENAME: CyBootAsmRv.s
-; Version 4.20
-;
-;  DESCRIPTION:
-;    Assembly routines for RealView.
-;
-;-------------------------------------------------------------------------------
-; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
-; You may use this file only in accordance with the license, terms, conditions,
-; disclaimers, and limitations in the end user license agreement accompanying
-; the software package with which this file was provided.
-;-------------------------------------------------------------------------------
-
-    AREA |.text|,CODE,ALIGN=3
-    THUMB
-    EXTERN Reset
-
-    GET cyfitterrv.inc
-
-;-------------------------------------------------------------------------------
-; Function Name: CyDelayCycles
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  Delays for the specified number of cycles.
-;
-; Parameters:
-;  uint32 cycles: number of cycles to delay.
-;
-; Return:
-;  None
-;
-;-------------------------------------------------------------------------------
-; void CyDelayCycles(uint32 cycles)
-    ALIGN 8
-CyDelayCycles FUNCTION
-    EXPORT CyDelayCycles
-    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
-                              ; cycles bytes
-    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
-    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
-    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
-    NOP                       ;   1   2  Loop alignment padding
-CyDelayCycles_loop
-    SUBS r0, r0, #1           ;   1   2
-    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
-    BNE CyDelayCycles_loop    ;   2   2
-    NOP                       ;   1   2  Loop alignment padding
-CyDelayCycles_done
-    BX lr                     ;   3   2
-
-    ELSE
-
-    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
-    BLS CyDelayCycles_short   ;   1   2
-    PUSH {r1}                 ;   2   2  PUSH r1 to stack
-    MOVS r1, #1               ;   1   2
-
-    SUBS r0, r0, #20          ;   1   2  Subtract overhead
-    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
-    LDRB r1, [r1, #0]         ;   2   2
-    ANDS r1, #0xC0            ;   1   2
-
-    LSRS r1, r1, #6           ;   1   2
-    PUSH {r2}                 ;   1   2  PUSH r2 to stack
-    LDR r2, =cy_flash_cycles  ;   2   2
-    LDRB r1, [r2, r1]         ;   2   2
-
-    POP {r2}                  ;   2   2  POP r2 from stack
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-
-CyDelayCycles_loop
-    SBCS r0, r0, r1           ;   1   2
-    BPL CyDelayCycles_loop    ;   3   2
-    NOP                       ;   1   2  Loop alignment padding
-    NOP                       ;   1   2  Loop alignment padding
-
-    POP {r1}                  ;   2   2  POP r1 from stack
-CyDelayCycles_done
-    BX lr                     ;   3   2
-    NOP                       ;   1   2  Alignment padding
-    NOP                       ;   1   2  Alignment padding
-
-CyDelayCycles_short
-    SBCS r0, r0, #4           ;   1   2
-    BPL CyDelayCycles_short   ;   3   2
-    BX lr                     ;   3   2
-
-cy_flash_cycles
-byte_1 DCB 0x0B
-byte_2 DCB 0x05
-byte_3 DCB 0x07
-byte_4 DCB 0x09
-
-    ENDIF
-    ENDFUNC
-
-
-;-------------------------------------------------------------------------------
-; Function Name: CyEnterCriticalSection
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  CyEnterCriticalSection disables interrupts and returns a value indicating
-;  whether interrupts were previously enabled (the actual value depends on
-;  whether the device is PSoC 3 or PSoC 5).
-;
-;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
-;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
-;  corrupting processor state, it must be the policy that all interrupt routines
-;  restore the interrupt enable bits as they were found on entry.
-;
-; Parameters:
-;  None
-;
-; Return:
-;  uint8
-;   Returns 0 if interrupts were previously enabled or 1 if interrupts
-;   were previously disabled.
-;
-;-------------------------------------------------------------------------------
-; uint8 CyEnterCriticalSection(void)
-CyEnterCriticalSection FUNCTION
-    EXPORT CyEnterCriticalSection
-    MRS r0, PRIMASK         ; Save and return interrupt state
-    CPSID I                 ; Disable interrupts
-    BX lr
-    ENDFUNC
-
-
-;-------------------------------------------------------------------------------
-; Function Name: CyExitCriticalSection
-;-------------------------------------------------------------------------------
-;
-; Summary:
-;  CyExitCriticalSection re-enables interrupts if they were enabled before
-;  CyEnterCriticalSection was called. The argument should be the value returned
-;  from CyEnterCriticalSection.
-;
-; Parameters:
-;  uint8 savedIntrStatus:
-;   Saved interrupt status returned by the CyEnterCriticalSection function.
-;
-; Return:
-;  None
-;
-;-------------------------------------------------------------------------------
-; void CyExitCriticalSection(uint8 savedIntrStatus)
-CyExitCriticalSection FUNCTION
-    EXPORT CyExitCriticalSection
-    MSR PRIMASK, r0         ; Restore interrupt state
-    BX lr
-    ENDFUNC
-
-    END
-
-; [] END OF FILE
+;-------------------------------------------------------------------------------
+; FILENAME: CyBootAsmRv.s
+; Version 4.20
+;
+;  DESCRIPTION:
+;    Assembly routines for RealView.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions,
+; disclaimers, and limitations in the end user license agreement accompanying
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+    AREA |.text|,CODE,ALIGN=3
+    THUMB
+    EXTERN Reset
+
+    GET cyfitterrv.inc
+
+;-------------------------------------------------------------------------------
+; Function Name: CyDelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  Delays for the specified number of cycles.
+;
+; Parameters:
+;  uint32 cycles: number of cycles to delay.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyDelayCycles(uint32 cycles)
+    ALIGN 8
+CyDelayCycles FUNCTION
+    EXPORT CyDelayCycles
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_loop
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_done
+    BX lr                     ;   3   2
+
+    ELSE
+
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, #0xC0            ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_short
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+
+cy_flash_cycles
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+    ENDFUNC
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyEnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyEnterCriticalSection disables interrupts and returns a value indicating
+;  whether interrupts were previously enabled (the actual value depends on
+;  whether the device is PSoC 3 or PSoC 5).
+;
+;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+;  with interrupts still enabled. The test and set of the interrupt bits is not
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
+;  corrupting processor state, it must be the policy that all interrupt routines
+;  restore the interrupt enable bits as they were found on entry.
+;
+; Parameters:
+;  None
+;
+; Return:
+;  uint8
+;   Returns 0 if interrupts were previously enabled or 1 if interrupts
+;   were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8 CyEnterCriticalSection(void)
+CyEnterCriticalSection FUNCTION
+    EXPORT CyEnterCriticalSection
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+    ENDFUNC
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyExitCriticalSection re-enables interrupts if they were enabled before
+;  CyEnterCriticalSection was called. The argument should be the value returned
+;  from CyEnterCriticalSection.
+;
+; Parameters:
+;  uint8 savedIntrStatus:
+;   Saved interrupt status returned by the CyEnterCriticalSection function.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyExitCriticalSection(uint8 savedIntrStatus)
+CyExitCriticalSection FUNCTION
+    EXPORT CyExitCriticalSection
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+    ENDFUNC
+
+    END
+
+; [] END OF FILE

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c

@@ -1,1131 +1,1131 @@
-/*******************************************************************************
-* File Name: CyDmac.c
-* Version 4.20
-*
-* Description:
-*  Provides an API for the DMAC component. The API includes functions for the
-*  DMA controller, DMA channels and Transfer Descriptors.
-*
-*  This API is the library version not the auto generated code that gets
-*  generated when the user places a DMA component on the schematic.
-*
-*  The auto generated code would use the APi's in this module.
-*
-* Note:
-*  This code is endian agnostic.
-*
-*  The Transfer Descriptor memory can be used as regular memory if the TD's are
-*  not being used.
-*
-*  This code uses the first byte of each TD to manage the free list of TD's.
-*  The user can overwrite this once the TD is allocated.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "CyDmac.h"
-
-
-/*******************************************************************************
-* The following variables are initialized from CyDmacConfigure() function that
-* is executed from initialize_psoc() at the early initialization stage.
-* In case of IAR EW IDE, initialize_psoc() is executed before the data sections
-* are initialized. To avoid zeroing, these variables should be initialized
-* properly during segments initialization as well.
-*******************************************************************************/
-static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
-static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
-static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
-
-
-/*******************************************************************************
-* Function Name: CyDmacConfigure
-********************************************************************************
-*
-* Summary:
-*  Creates a linked list of all the TDs to be allocated. This function is called
-*  by the startup code; you do not normally need to call it. You can call this
-*  function if all of the DMA channels are inactive.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyDmacConfigure(void) 
-{
-    uint8 dmaIndex;
-
-    /* Set TD list variables. */
-    CyDmaTdFreeIndex     = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);
-    CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;
-
-    /* Make TD free list. */
-    for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)
-    {
-        CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
-    }
-
-    /* Make last one point to zero. */
-    CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmacError
-********************************************************************************
-*
-* Summary:
-*  Returns errors of the last failed DMA transaction.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  Errors of the last failed DMA transaction.
-*
-*  DMAC_PERIPH_ERR:
-*   Set to 1 when a peripheral responds to a bus transaction with an error
-*   response.
-*
-*  DMAC_UNPOP_ACC:
-*   Set to 1 when an access is attempted to an invalid address.
-*
-*  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
-*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
-*
-* Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by 
-*  writing 1 to the error register.
-*
-*******************************************************************************/
-uint8 CyDmacError(void) 
-{
-    return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR));
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmacClearError
-********************************************************************************
-*
-* Summary:
-*  Clears the error bits in the error register of the DMAC.
-*
-* Parameters:
-* error:
-*   Clears the error bits in the DMAC error register.
-*
-*  DMAC_PERIPH_ERR:
-*   Set to 1 when a peripheral responds to a bus transaction with an error
-*   response.
-*
-*  DMAC_UNPOP_ACC:
-*   Set to 1 when an access is attempted to an invalid address.
-*
-*  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
-*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
-*
-* Return:
-*  None
-*
-* Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by 
-*  writing 1 to the error register.
-*
-*******************************************************************************/
-void CyDmacClearError(uint8 error) 
-{
-    *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error));
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmacErrorAddress
-********************************************************************************
-*
-* Summary:
-*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
-*  address of the error is written to the error address register and can be read
-*  with this function.
-*
-*  If there are multiple errors, only the address of the first is saved.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  The address that caused the error.
-*
-*******************************************************************************/
-uint32 CyDmacErrorAddress(void) 
-{
-    return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR));
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChAlloc
-********************************************************************************
-*
-* Summary:
-*  Allocates a channel from the DMAC to be used in all functions that require a
-*  channel handle.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  The allocated channel number. Zero is a valid channel number.
-*  DMA_INVALID_CHANNEL is returned if there are no channels available.
-*
-*******************************************************************************/
-uint8 CyDmaChAlloc(void) 
-{
-    uint8 interruptState;
-    uint8 dmaIndex;
-    uint32 channel = 1u;
-
-
-    /* Enter critical section! */
-    interruptState = CyEnterCriticalSection();
-
-    /* Look for free channel. */
-    for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
-    {
-        if(0uL == (CyDmaChannels & channel))
-        {
-            /* Mark channel as used. */
-            CyDmaChannels |= channel;
-            break;
-        }
-
-        channel <<= 1u;
-    }
-
-    if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS)
-    {
-        dmaIndex = CY_DMA_INVALID_CHANNEL;
-    }
-
-    /* Exit critical section! */
-    CyExitCriticalSection(interruptState);
-
-    return(dmaIndex);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChFree
-********************************************************************************
-*
-* Summary:
-*  Frees a channel allocated by DmaChAlloc().
-*
-* Parameters:
-*  uint8 chHandle:
-*   The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChFree(uint8 chHandle) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-    uint8 interruptState;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        /* Enter critical section */
-        interruptState = CyEnterCriticalSection();
-
-        /* Clear bit mask that keeps track of ownership. */
-        CyDmaChannels &= ~(((uint32) 1u) << chHandle);
-
-        /* Exit critical section */
-        CyExitCriticalSection(interruptState);
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the DMA channel. A software or hardware request still must happen
-*  before the channel is executed.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-*  uint8 preserveTds:
-*   Preserves the original TD state when the TD has completed. This parameter
-*   applies to all TDs in the channel.
-*
-*   0 - When TD is completed, the DMAC leaves the TD configuration values in
-*   their current state, and does not restore them to their original state.
-*
-*   1 - When TD is completed, the DMAC restores the original configuration
-*   values of the TD.
-*
-*  When preserveTds is set, the TD slot that equals the channel number becomes
-*  RESERVED and that becomes where the working registers exist. So, for example,
-*  if you are using CH06 and preserveTds is set, you are not allowed to use TD
-*  slot 6. That is reclaimed by the DMA engine for its private use.
-*
-*  Note Do not chain back to a completed TD if the preserveTds for the channel
-*  is set to 0. When a TD has completed preserveTds for the channel set to 0,
-*  the transfer count will be at 0. If a TD with a transfer count of 0 is
-*  started, the TD will transfer an indefinite amount of data.
-*
-*  Take extra precautions when using the hardware request (DRQ) option when the
-*  preserveTds is set to 0, as you might be requesting the wrong data.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        if (0u != preserveTds)
-        {
-            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
-            *  preserve original TD chain
-            */
-            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
-        }
-        else
-        {
-            /* Store intermediate and final TD states on top of original TD chain */
-            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
-        }
-
-        /* Enable channel */
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the DMA channel. Once this function is called, CyDmaChStatus() may
-*  be called to determine when the channel is disabled and which TDs were being
-*  executed.
-*
-*  If it is currently executing it will allow the current burst to finish
-*  naturally.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChDisable(uint8 chHandle) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        /***********************************************************************
-        * Should not change configuration information of a DMA channel when it
-        * is active (or vulnerable to becoming active).
-        ***********************************************************************/
-
-        /* Disable channel */
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
-
-        /* Store intermediate and final TD states on top of original TD chain */
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaClearPendingDrq
-********************************************************************************
-*
-* Summary:
-*  Clears pending the DMA data request.
-*
-* Parameters:
-*  uint8 chHandle:
-*   Handle to the dma channel.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaClearPendingDrq(uint8 chHandle) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN;
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u;
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChPriority
-********************************************************************************
-*
-* Summary:
-*  Sets the priority of a DMA channel. You can use this function when you want
-*  to change the priority at run time. If the priority remains the same for a
-*  DMA channel, then you can configure the priority in the .cydwr file.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-*  uint8 priority:
-*   Priority to set the channel to, 0 - 7.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) 
-{
-    uint8 value;
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu)));
-
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u));
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChSetExtendedAddress
-********************************************************************************
-*
-* Summary:
-*  Sets the high 16 bits of the source and destination addresses for the DMA
-*  channel (valid for all TDs in the chain).
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-*  uint16 source:
-*   Upper 16 bit address of the DMA transfer source.
-*
-*  uint16 destination:
-*   Upper 16 bit address of the DMA transfer destination.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \
-    
-{
-    cystatus status = CYRET_BAD_PARAM;
-    reg16 *convert;
-
-    #if(CY_PSOC5)
-
-        /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */
-        if(source == 0x1FFFu)
-        {
-            source = 0x2000u;
-        }
-
-        if(destination == 0x1FFFu)
-        {
-            destination = 0x2000u;
-        }
-
-    #endif  /* (CY_PSOC5) */
-
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        /* Set source address */
-        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
-        CY_SET_REG16(convert, source);
-
-        /* Set destination address */
-        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];
-        CY_SET_REG16(convert, destination);
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChSetInitialTd
-********************************************************************************
-*
-* Summary:
-*  Sets the initial TD to be executed for the channel when the CyDmaChEnable()
-*  function is called.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
-*
-*  uint8 startTd:
-*   Set the TD index as the first TD associated with the channel. Zero is
-*   a valid TD index.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd;
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChSetRequest
-********************************************************************************
-*
-* Summary:
-*  Allows the caller to terminate a chain of TDs, terminate one TD, or create a
-*  direct request to start the DMA channel.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-*  uint8 request:
-*   One of the following constants. Each of the constants is a three-bit value.
-*
-*   CPU_REQ         - Create a direct request to start the DMA channel
-*   CPU_TERM_TD     - Terminate one TD
-*   CPU_TERM_CHAIN  - Terminate a chain of TDs
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN));
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChGetRequest
-********************************************************************************
-*
-* Summary:
-*  This function allows the caller of CyDmaChSetRequest() to determine if the
-*  request was completed.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-* Return:
-*  Returns a three-bit field, corresponding to the three bits of the request,
-*  which describes the state of the previously posted request. If the value is
-*  zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is
-*  invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChGetRequest(uint8 chHandle) 
-{
-    cystatus status = CY_DMA_INVALID_CHANNEL;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
-                            (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChStatus
-********************************************************************************
-*
-* Summary:
-*  Determines the status of the DMA channel.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
-*
-*  uint8 * currentTd:
-*   The address to store the index of the current TD. Can be NULL if the value
-*   is not needed.
-*
-*  uint8 * state:
-*   The address to store the state of the channel. Can be NULL if the value is
-*   not needed.
-*
-*   STATUS_TD_ACTIVE
-*    0: Channel is not currently being serviced by DMAC
-*    1: Channel is currently being serviced by DMAC
-*
-*   STATUS_CHAIN_ACTIVE
-*    0: TD chain is inactive; either no DMA requests have triggered a new chain
-*       or the previous chain has completed.
-*    1: TD chain has been triggered by a DMA request
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-* Theory:
-*   The caller can check on the activity of the Current TD and the Chain.
-*
-*******************************************************************************/
-cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        if(NULL != currentTd)
-        {
-            *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu;
-        }
-
-        if(NULL != state)
-        {
-            *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0];
-        }
-
-        status = CYRET_SUCCESS;
-    }
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChSetConfiguration
-********************************************************************************
-*
-* Summary:
-* Sets configuration information of the channel.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
-*
-*  uint8 burstCount:
-*   Specifies the size of bursts (1 to 127) the data transfer should be divided
-*   into. If this value is zero then the whole transfer is done in one burst.
-*
-*  uint8 requestPerBurst:
-*   The whole of the data can be split into multiple bursts, if this is
-*   required to complete the transaction:
-*    0: All subsequent bursts after the first burst will be automatically
-*       requested and carried out
-*    1: All subsequent bursts after the first burst must also be individually
-*       requested.
-*
-*  uint8 tdDone0:
-*   Selects one of the TERMOUT0 interrupt lines to signal completion. The line
-*   connected to the nrq terminal will determine the TERMOUT0_SEL definition and
-*   should be used as supplied by cyfitter.h
-*
-*  uint8 tdDone1:
-*   Selects one of the TERMOUT1 interrupt lines to signal completion. The line
-*   connected to the nrq terminal will determine the TERMOUT1_SEL definition and
-*   should be used as supplied by cyfitter.h
-*
-*  uint8 tdStop:
-*   Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD
-*   should terminate. The signal connected to the trq terminal will determine
-*   which TERMIN (termination request) is used.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst,
-                                 uint8 tdDone0, uint8 tdDone1, uint8 tdStop) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u));
-        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu);
-        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop;
-        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */
-
-        status = CYRET_SUCCESS;
-    }
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdAllocate
-********************************************************************************
-*
-* Summary:
-*  Allocates a TD for use with an allocated DMA channel.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  Zero-based index of the TD to be used by the caller. Since there are 128 TDs
-*  minus the reserved TDs (0 to 23), the value returned would range from 24 to
-*  127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs
-*  available.
-*
-*******************************************************************************/
-uint8 CyDmaTdAllocate(void) 
-{
-    uint8 interruptState;
-    uint8 element = CY_DMA_INVALID_TD;
-
-    /* Enter critical section! */
-    interruptState = CyEnterCriticalSection();
-
-    if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
-    {
-        /* Get pointer to Next available. */
-        element = CyDmaTdFreeIndex;
-
-        /* Decrement the count. */
-        CyDmaTdCurrentNumber--;
-
-        /* Update next available pointer. */
-        CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
-    }
-
-    /* Exit critical section! */
-    CyExitCriticalSection(interruptState);
-
-    return(element);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdFree
-********************************************************************************
-*
-* Summary:
-*  Returns a TD to the free list.
-*
-* Parameters:
-*  uint8 tdHandle:
-*   The TD handle returned by the CyDmaTdAllocate().
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyDmaTdFree(uint8 tdHandle) 
-{
-    if(tdHandle < CY_DMA_NUMBEROF_TDS)
-    {
-        /* Enter critical section! */
-        uint8 interruptState = CyEnterCriticalSection();
-
-        /* Get pointer to Next available. */
-        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
-
-        /* Set new Next Available. */
-        CyDmaTdFreeIndex = tdHandle;
-
-        /* Keep track of how many left. */
-        CyDmaTdCurrentNumber++;
-
-        /* Exit critical section! */
-        CyExitCriticalSection(interruptState);
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdFreeCount
-********************************************************************************
-*
-* Summary:
-*  Returns the number of free TDs available to be allocated.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  The number of free TDs.
-*
-*******************************************************************************/
-uint8 CyDmaTdFreeCount(void) 
-{
-    return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdSetConfiguration
-********************************************************************************
-*
-* Summary:
-*  Configures the TD.
-*
-* Parameters:
-*  uint8 tdHandle:
-*   A handle previously returned by CyDmaTdAlloc().
-*
-*  uint16 transferCount:
-*   The size of the data transfer (in bytes) for this TD. A size of zero will
-*   cause the transfer to continue indefinitely. This parameter is limited to
-*   4095 bytes; the TD is not initialized at all when a higher value is passed.
-*
-*  uint8 nextTd:
-*   Zero based index of the next Transfer Descriptor in the TD chain. Zero is a
-*   valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.
-*   DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No
-*   further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and
-*   PSoC 5LP silicons.
-*
-*  uint8 configuration:
-*   Stores the Bit field of configuration bits.
-*
-*   CY_DMA_TD_SWAP_EN        - Perform endian swap
-*
-*   CY_DMA_TD_SWAP_SIZE4     - Swap size = 4 bytes
-*
-*   CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger
-*                              automatically when the current TD completes.
-*
-*   CY_DMA_TD_TERMIN_EN      - Terminate this TD if a positive edge on the trq
-*                              input line occurs. The positive edge must occur
-*                              during a burst. That is the only time the DMAC
-*                              will listen for it.
-*
-*   DMA__TD_TERMOUT_EN       - When this TD completes, the TERMOUT signal will
-*                              generate a pulse. Note that this option is
-*                              instance specific with the instance name followed
-*                              by two underscores. In this example, the instance
-*                              name is DMA.
-*
-*   CY_DMA_TD_INC_DST_ADR    - Increment DST_ADR according to the size of each
-*                              data transaction in the burst.
-*
-*   CY_DMA_TD_INC_SRC_ADR    - Increment SRC_ADR according to the size of each
-*                              data transaction in the burst.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if tdHandle or transferCount is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \
-    
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount)))
-    {
-        /* Set 12 bits transfer count. */
-        reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u];
-        CY_SET_REG16(convert, transferCount);
-
-        /* Set Next TD pointer. */
-        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd;
-
-        /* Configure the TD */
-        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration;
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdGetConfiguration
-********************************************************************************
-*
-* Summary:
-*  Retrieves the configuration of the TD. If a NULL pointer is passed as a
-*  parameter, that parameter is skipped. You may request only the values you are
-*  interested in.
-*
-* Parameters:
-*  uint8 tdHandle:
-*   A handle previously returned by CyDmaTdAlloc().
-*
-*  uint16 * transferCount:
-*   The address to store the size of the data transfer (in bytes) for this TD.
-*   A size of zero could indicate that the TD has completed its transfer, or
-*   that the TD is doing an indefinite transfer.
-*
-*  uint8 * nextTd:
-*   The address to store the index of the next TD in the TD chain.
-*
-*  uint8 * configuration:
-*   The address to store the Bit field of configuration bits.
-*   See CyDmaTdSetConfiguration() function description.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if tdHandle is invalid.
-*
-* Side Effects:
-*  If TD has a transfer count of N and is executed, the transfer count becomes
-*  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-*  request for indefinite transfer. Be careful when requesting TD with a
-*  transfer count of zero.
-*
-*******************************************************************************/
-cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \
-    
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(tdHandle < CY_DMA_NUMBEROF_TDS)
-    {
-        /* If we have pointer */
-        if(NULL != transferCount)
-        {
-            /* Get 12 bits of transfer count */
-            reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
-            *transferCount = 0x0FFFu & CY_GET_REG16(convert);
-        }
-
-        /* If we have pointer */
-        if(NULL != nextTd)
-        {
-            /* Get Next TD pointer */
-            *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
-        }
-
-        /* If we have pointer */
-        if(NULL != configuration)
-        {
-            /* Get configuration TD */
-            *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
-        }
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdSetAddress
-********************************************************************************
-*
-* Summary:
-*  Sets the lower 16 bits of the source and destination addresses for this TD
-*  only.
-*
-* Parameters:
-*  uint8 tdHandle:
-*   A handle previously returned by CyDmaTdAlloc().
-*
-*  uint16 source:
-*   The lower 16 address bits of the source of the data transfer.
-*
-*  uint16 destination:
-*   The lower 16 address bits of the destination of the data transfer.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if tdHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-    reg16 *convert;
-
-    if(tdHandle < CY_DMA_NUMBEROF_TDS)
-    {
-        /* Set source address */
-        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
-        CY_SET_REG16(convert, source);
-
-        /* Set destination address */
-        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
-        CY_SET_REG16(convert, destination);
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaTdGetAddress
-********************************************************************************
-*
-* Summary:
-*  Retrieves the lower 16 bits of the source and/or destination addresses for
-*  this TD only. If NULL is passed for a pointer parameter, that value is
-*  skipped. You may request only the values of interest.
-*
-* Parameters:
-*  uint8 tdHandle:
-*   A handle previously returned by CyDmaTdAlloc().
-*
-*  uint16 * source:
-*   The address to store the lower 16 address bits of the source of the data
-*   transfer.
-*
-*  uint16 * destination:
-*   The address to store the lower 16 address bits of the destination of the
-*   data transfer.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if tdHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-    reg16 *convert;
-
-    if(tdHandle < CY_DMA_NUMBEROF_TDS)
-    {
-        /* If we have a pointer. */
-        if(NULL != source)
-        {
-            /* Get source address */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
-            *source = CY_GET_REG16(convert);
-        }
-
-        /* If we have a pointer. */
-        if(NULL != destination)
-        {
-            /* Get Destination address. */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
-            *destination = CY_GET_REG16(convert);
-        }
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDmaChRoundRobin
-********************************************************************************
-*
-* Summary:
-*  Either enables or disables the Round-Robin scheduling enforcement algorithm.
-*  Within a priority level a Round-Robin fairness algorithm is enforced.
-*
-* Parameters:
-*  uint8 chHandle:
-*   A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().
-*
-*  uint8 enableRR:
-*   0: Disable Round-Robin fairness algorithm
-*   1: Enable Round-Robin fairness algorithm
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_BAD_PARAM if chHandle is invalid.
-*
-*******************************************************************************/
-cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) 
-{
-    cystatus status = CYRET_BAD_PARAM;
-
-    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
-    {
-        if (0u != enableRR)
-        {
-            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;
-        }
-        else
-        {
-            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);
-        }
-
-        status = CYRET_SUCCESS;
-    }
-
-    return(status);
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyDmac.c
+* Version 4.20
+*
+* Description:
+*  Provides an API for the DMAC component. The API includes functions for the
+*  DMA controller, DMA channels and Transfer Descriptors.
+*
+*  This API is the library version not the auto generated code that gets
+*  generated when the user places a DMA component on the schematic.
+*
+*  The auto generated code would use the APi's in this module.
+*
+* Note:
+*  This code is endian agnostic.
+*
+*  The Transfer Descriptor memory can be used as regular memory if the TD's are
+*  not being used.
+*
+*  This code uses the first byte of each TD to manage the free list of TD's.
+*  The user can overwrite this once the TD is allocated.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyDmac.h"
+
+
+/*******************************************************************************
+* The following variables are initialized from CyDmacConfigure() function that
+* is executed from initialize_psoc() at the early initialization stage.
+* In case of IAR EW IDE, initialize_psoc() is executed before the data sections
+* are initialized. To avoid zeroing, these variables should be initialized
+* properly during segments initialization as well.
+*******************************************************************************/
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
+static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
+
+
+/*******************************************************************************
+* Function Name: CyDmacConfigure
+********************************************************************************
+*
+* Summary:
+*  Creates a linked list of all the TDs to be allocated. This function is called
+*  by the startup code; you do not normally need to call it. You can call this
+*  function if all of the DMA channels are inactive.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyDmacConfigure(void) 
+{
+    uint8 dmaIndex;
+
+    /* Set TD list variables. */
+    CyDmaTdFreeIndex     = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);
+    CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;
+
+    /* Make TD free list. */
+    for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)
+    {
+        CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
+    }
+
+    /* Make last one point to zero. */
+    CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacError
+********************************************************************************
+*
+* Summary:
+*  Returns errors of the last failed DMA transaction.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Errors of the last failed DMA transaction.
+*
+*  DMAC_PERIPH_ERR:
+*   Set to 1 when a peripheral responds to a bus transaction with an error
+*   response.
+*
+*  DMAC_UNPOP_ACC:
+*   Set to 1 when an access is attempted to an invalid address.
+*
+*  DMAC_BUS_TIMEOUT:
+*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
+*
+* Theory:
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
+*
+*******************************************************************************/
+uint8 CyDmacError(void) 
+{
+    return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacClearError
+********************************************************************************
+*
+* Summary:
+*  Clears the error bits in the error register of the DMAC.
+*
+* Parameters:
+* error:
+*   Clears the error bits in the DMAC error register.
+*
+*  DMAC_PERIPH_ERR:
+*   Set to 1 when a peripheral responds to a bus transaction with an error
+*   response.
+*
+*  DMAC_UNPOP_ACC:
+*   Set to 1 when an access is attempted to an invalid address.
+*
+*  DMAC_BUS_TIMEOUT:
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
+*   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
+*
+* Return:
+*  None
+*
+* Theory:
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
+*
+*******************************************************************************/
+void CyDmacClearError(uint8 error) 
+{
+    *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmacErrorAddress
+********************************************************************************
+*
+* Summary:
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
+*  address of the error is written to the error address register and can be read
+*  with this function.
+*
+*  If there are multiple errors, only the address of the first is saved.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  The address that caused the error.
+*
+*******************************************************************************/
+uint32 CyDmacErrorAddress(void) 
+{
+    return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR));
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChAlloc
+********************************************************************************
+*
+* Summary:
+*  Allocates a channel from the DMAC to be used in all functions that require a
+*  channel handle.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  The allocated channel number. Zero is a valid channel number.
+*  DMA_INVALID_CHANNEL is returned if there are no channels available.
+*
+*******************************************************************************/
+uint8 CyDmaChAlloc(void) 
+{
+    uint8 interruptState;
+    uint8 dmaIndex;
+    uint32 channel = 1u;
+
+
+    /* Enter critical section! */
+    interruptState = CyEnterCriticalSection();
+
+    /* Look for free channel. */
+    for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
+    {
+        if(0uL == (CyDmaChannels & channel))
+        {
+            /* Mark channel as used. */
+            CyDmaChannels |= channel;
+            break;
+        }
+
+        channel <<= 1u;
+    }
+
+    if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS)
+    {
+        dmaIndex = CY_DMA_INVALID_CHANNEL;
+    }
+
+    /* Exit critical section! */
+    CyExitCriticalSection(interruptState);
+
+    return(dmaIndex);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChFree
+********************************************************************************
+*
+* Summary:
+*  Frees a channel allocated by DmaChAlloc().
+*
+* Parameters:
+*  uint8 chHandle:
+*   The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChFree(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    uint8 interruptState;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /* Enter critical section */
+        interruptState = CyEnterCriticalSection();
+
+        /* Clear bit mask that keeps track of ownership. */
+        CyDmaChannels &= ~(((uint32) 1u) << chHandle);
+
+        /* Exit critical section */
+        CyExitCriticalSection(interruptState);
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the DMA channel. A software or hardware request still must happen
+*  before the channel is executed.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+*  uint8 preserveTds:
+*   Preserves the original TD state when the TD has completed. This parameter
+*   applies to all TDs in the channel.
+*
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
+*   their current state, and does not restore them to their original state.
+*
+*   1 - When TD is completed, the DMAC restores the original configuration
+*   values of the TD.
+*
+*  When preserveTds is set, the TD slot that equals the channel number becomes
+*  RESERVED and that becomes where the working registers exist. So, for example,
+*  if you are using CH06 and preserveTds is set, you are not allowed to use TD
+*  slot 6. That is reclaimed by the DMA engine for its private use.
+*
+*  Note Do not chain back to a completed TD if the preserveTds for the channel
+*  is set to 0. When a TD has completed preserveTds for the channel set to 0,
+*  the transfer count will be at 0. If a TD with a transfer count of 0 is
+*  started, the TD will transfer an indefinite amount of data.
+*
+*  Take extra precautions when using the hardware request (DRQ) option when the
+*  preserveTds is set to 0, as you might be requesting the wrong data.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if (0u != preserveTds)
+        {
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
+            */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
+        }
+        else
+        {
+            /* Store intermediate and final TD states on top of original TD chain */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
+        }
+
+        /* Enable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the DMA channel. Once this function is called, CyDmaChStatus() may
+*  be called to determine when the channel is disabled and which TDs were being
+*  executed.
+*
+*  If it is currently executing it will allow the current burst to finish
+*  naturally.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChDisable(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /***********************************************************************
+        * Should not change configuration information of a DMA channel when it
+        * is active (or vulnerable to becoming active).
+        ***********************************************************************/
+
+        /* Disable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
+
+        /* Store intermediate and final TD states on top of original TD chain */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaClearPendingDrq
+********************************************************************************
+*
+* Summary:
+*  Clears pending the DMA data request.
+*
+* Parameters:
+*  uint8 chHandle:
+*   Handle to the dma channel.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaClearPendingDrq(uint8 chHandle) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN;
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u;
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChPriority
+********************************************************************************
+*
+* Summary:
+*  Sets the priority of a DMA channel. You can use this function when you want
+*  to change the priority at run time. If the priority remains the same for a
+*  DMA channel, then you can configure the priority in the .cydwr file.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+*  uint8 priority:
+*   Priority to set the channel to, 0 - 7.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) 
+{
+    uint8 value;
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu)));
+
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u));
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetExtendedAddress
+********************************************************************************
+*
+* Summary:
+*  Sets the high 16 bits of the source and destination addresses for the DMA
+*  channel (valid for all TDs in the chain).
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+*  uint16 source:
+*   Upper 16 bit address of the DMA transfer source.
+*
+*  uint16 destination:
+*   Upper 16 bit address of the DMA transfer destination.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    #if(CY_PSOC5)
+
+        /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */
+        if(source == 0x1FFFu)
+        {
+            source = 0x2000u;
+        }
+
+        if(destination == 0x1FFFu)
+        {
+            destination = 0x2000u;
+        }
+
+    #endif  /* (CY_PSOC5) */
+
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        /* Set source address */
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
+        CY_SET_REG16(convert, source);
+
+        /* Set destination address */
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];
+        CY_SET_REG16(convert, destination);
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetInitialTd
+********************************************************************************
+*
+* Summary:
+*  Sets the initial TD to be executed for the channel when the CyDmaChEnable()
+*  function is called.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
+*
+*  uint8 startTd:
+*   Set the TD index as the first TD associated with the channel. Zero is
+*   a valid TD index.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd;
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetRequest
+********************************************************************************
+*
+* Summary:
+*  Allows the caller to terminate a chain of TDs, terminate one TD, or create a
+*  direct request to start the DMA channel.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+*  uint8 request:
+*   One of the following constants. Each of the constants is a three-bit value.
+*
+*   CPU_REQ         - Create a direct request to start the DMA channel
+*   CPU_TERM_TD     - Terminate one TD
+*   CPU_TERM_CHAIN  - Terminate a chain of TDs
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN));
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChGetRequest
+********************************************************************************
+*
+* Summary:
+*  This function allows the caller of CyDmaChSetRequest() to determine if the
+*  request was completed.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+* Return:
+*  Returns a three-bit field, corresponding to the three bits of the request,
+*  which describes the state of the previously posted request. If the value is
+*  zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is
+*  invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChGetRequest(uint8 chHandle) 
+{
+    cystatus status = CY_DMA_INVALID_CHANNEL;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
+                            (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChStatus
+********************************************************************************
+*
+* Summary:
+*  Determines the status of the DMA channel.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().
+*
+*  uint8 * currentTd:
+*   The address to store the index of the current TD. Can be NULL if the value
+*   is not needed.
+*
+*  uint8 * state:
+*   The address to store the state of the channel. Can be NULL if the value is
+*   not needed.
+*
+*   STATUS_TD_ACTIVE
+*    0: Channel is not currently being serviced by DMAC
+*    1: Channel is currently being serviced by DMAC
+*
+*   STATUS_CHAIN_ACTIVE
+*    0: TD chain is inactive; either no DMA requests have triggered a new chain
+*       or the previous chain has completed.
+*    1: TD chain has been triggered by a DMA request
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+* Theory:
+*   The caller can check on the activity of the Current TD and the Chain.
+*
+*******************************************************************************/
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if(NULL != currentTd)
+        {
+            *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu;
+        }
+
+        if(NULL != state)
+        {
+            *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0];
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChSetConfiguration
+********************************************************************************
+*
+* Summary:
+* Sets configuration information of the channel.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
+*
+*  uint8 burstCount:
+*   Specifies the size of bursts (1 to 127) the data transfer should be divided
+*   into. If this value is zero then the whole transfer is done in one burst.
+*
+*  uint8 requestPerBurst:
+*   The whole of the data can be split into multiple bursts, if this is
+*   required to complete the transaction:
+*    0: All subsequent bursts after the first burst will be automatically
+*       requested and carried out
+*    1: All subsequent bursts after the first burst must also be individually
+*       requested.
+*
+*  uint8 tdDone0:
+*   Selects one of the TERMOUT0 interrupt lines to signal completion. The line
+*   connected to the nrq terminal will determine the TERMOUT0_SEL definition and
+*   should be used as supplied by cyfitter.h
+*
+*  uint8 tdDone1:
+*   Selects one of the TERMOUT1 interrupt lines to signal completion. The line
+*   connected to the nrq terminal will determine the TERMOUT1_SEL definition and
+*   should be used as supplied by cyfitter.h
+*
+*  uint8 tdStop:
+*   Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD
+*   should terminate. The signal connected to the trq terminal will determine
+*   which TERMIN (termination request) is used.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst,
+                                 uint8 tdDone0, uint8 tdDone1, uint8 tdStop) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u));
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu);
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop;
+        CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */
+
+        status = CYRET_SUCCESS;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdAllocate
+********************************************************************************
+*
+* Summary:
+*  Allocates a TD for use with an allocated DMA channel.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Zero-based index of the TD to be used by the caller. Since there are 128 TDs
+*  minus the reserved TDs (0 to 23), the value returned would range from 24 to
+*  127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs
+*  available.
+*
+*******************************************************************************/
+uint8 CyDmaTdAllocate(void) 
+{
+    uint8 interruptState;
+    uint8 element = CY_DMA_INVALID_TD;
+
+    /* Enter critical section! */
+    interruptState = CyEnterCriticalSection();
+
+    if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
+    {
+        /* Get pointer to Next available. */
+        element = CyDmaTdFreeIndex;
+
+        /* Decrement the count. */
+        CyDmaTdCurrentNumber--;
+
+        /* Update next available pointer. */
+        CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
+    }
+
+    /* Exit critical section! */
+    CyExitCriticalSection(interruptState);
+
+    return(element);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdFree
+********************************************************************************
+*
+* Summary:
+*  Returns a TD to the free list.
+*
+* Parameters:
+*  uint8 tdHandle:
+*   The TD handle returned by the CyDmaTdAllocate().
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyDmaTdFree(uint8 tdHandle) 
+{
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* Enter critical section! */
+        uint8 interruptState = CyEnterCriticalSection();
+
+        /* Get pointer to Next available. */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
+
+        /* Set new Next Available. */
+        CyDmaTdFreeIndex = tdHandle;
+
+        /* Keep track of how many left. */
+        CyDmaTdCurrentNumber++;
+
+        /* Exit critical section! */
+        CyExitCriticalSection(interruptState);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdFreeCount
+********************************************************************************
+*
+* Summary:
+*  Returns the number of free TDs available to be allocated.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  The number of free TDs.
+*
+*******************************************************************************/
+uint8 CyDmaTdFreeCount(void) 
+{
+    return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdSetConfiguration
+********************************************************************************
+*
+* Summary:
+*  Configures the TD.
+*
+* Parameters:
+*  uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  uint16 transferCount:
+*   The size of the data transfer (in bytes) for this TD. A size of zero will
+*   cause the transfer to continue indefinitely. This parameter is limited to
+*   4095 bytes; the TD is not initialized at all when a higher value is passed.
+*
+*  uint8 nextTd:
+*   Zero based index of the next Transfer Descriptor in the TD chain. Zero is a
+*   valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.
+*   DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No
+*   further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and
+*   PSoC 5LP silicons.
+*
+*  uint8 configuration:
+*   Stores the Bit field of configuration bits.
+*
+*   CY_DMA_TD_SWAP_EN        - Perform endian swap
+*
+*   CY_DMA_TD_SWAP_SIZE4     - Swap size = 4 bytes
+*
+*   CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger
+*                              automatically when the current TD completes.
+*
+*   CY_DMA_TD_TERMIN_EN      - Terminate this TD if a positive edge on the trq
+*                              input line occurs. The positive edge must occur
+*                              during a burst. That is the only time the DMAC
+*                              will listen for it.
+*
+*   DMA__TD_TERMOUT_EN       - When this TD completes, the TERMOUT signal will
+*                              generate a pulse. Note that this option is
+*                              instance specific with the instance name followed
+*                              by two underscores. In this example, the instance
+*                              name is DMA.
+*
+*   CY_DMA_TD_INC_DST_ADR    - Increment DST_ADR according to the size of each
+*                              data transaction in the burst.
+*
+*   CY_DMA_TD_INC_SRC_ADR    - Increment SRC_ADR according to the size of each
+*                              data transaction in the burst.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle or transferCount is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount)))
+    {
+        /* Set 12 bits transfer count. */
+        reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u];
+        CY_SET_REG16(convert, transferCount);
+
+        /* Set Next TD pointer. */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd;
+
+        /* Configure the TD */
+        CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration;
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdGetConfiguration
+********************************************************************************
+*
+* Summary:
+*  Retrieves the configuration of the TD. If a NULL pointer is passed as a
+*  parameter, that parameter is skipped. You may request only the values you are
+*  interested in.
+*
+* Parameters:
+*  uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  uint16 * transferCount:
+*   The address to store the size of the data transfer (in bytes) for this TD.
+*   A size of zero could indicate that the TD has completed its transfer, or
+*   that the TD is doing an indefinite transfer.
+*
+*  uint8 * nextTd:
+*   The address to store the index of the next TD in the TD chain.
+*
+*  uint8 * configuration:
+*   The address to store the Bit field of configuration bits.
+*   See CyDmaTdSetConfiguration() function description.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+* Side Effects:
+*  If TD has a transfer count of N and is executed, the transfer count becomes
+*  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
+*  request for indefinite transfer. Be careful when requesting TD with a
+*  transfer count of zero.
+*
+*******************************************************************************/
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \
+    
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* If we have pointer */
+        if(NULL != transferCount)
+        {
+            /* Get 12 bits of transfer count */
+            reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
+            *transferCount = 0x0FFFu & CY_GET_REG16(convert);
+        }
+
+        /* If we have pointer */
+        if(NULL != nextTd)
+        {
+            /* Get Next TD pointer */
+            *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
+        }
+
+        /* If we have pointer */
+        if(NULL != configuration)
+        {
+            /* Get configuration TD */
+            *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdSetAddress
+********************************************************************************
+*
+* Summary:
+*  Sets the lower 16 bits of the source and destination addresses for this TD
+*  only.
+*
+* Parameters:
+*  uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  uint16 source:
+*   The lower 16 address bits of the source of the data transfer.
+*
+*  uint16 destination:
+*   The lower 16 address bits of the destination of the data transfer.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* Set source address */
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
+        CY_SET_REG16(convert, source);
+
+        /* Set destination address */
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+        CY_SET_REG16(convert, destination);
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaTdGetAddress
+********************************************************************************
+*
+* Summary:
+*  Retrieves the lower 16 bits of the source and/or destination addresses for
+*  this TD only. If NULL is passed for a pointer parameter, that value is
+*  skipped. You may request only the values of interest.
+*
+* Parameters:
+*  uint8 tdHandle:
+*   A handle previously returned by CyDmaTdAlloc().
+*
+*  uint16 * source:
+*   The address to store the lower 16 address bits of the source of the data
+*   transfer.
+*
+*  uint16 * destination:
+*   The address to store the lower 16 address bits of the destination of the
+*   data transfer.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if tdHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
+
+    if(tdHandle < CY_DMA_NUMBEROF_TDS)
+    {
+        /* If we have a pointer. */
+        if(NULL != source)
+        {
+            /* Get source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
+            *source = CY_GET_REG16(convert);
+        }
+
+        /* If we have a pointer. */
+        if(NULL != destination)
+        {
+            /* Get Destination address. */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+            *destination = CY_GET_REG16(convert);
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDmaChRoundRobin
+********************************************************************************
+*
+* Summary:
+*  Either enables or disables the Round-Robin scheduling enforcement algorithm.
+*  Within a priority level a Round-Robin fairness algorithm is enforced.
+*
+* Parameters:
+*  uint8 chHandle:
+*   A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().
+*
+*  uint8 enableRR:
+*   0: Disable Round-Robin fairness algorithm
+*   1: Enable Round-Robin fairness algorithm
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_BAD_PARAM if chHandle is invalid.
+*
+*******************************************************************************/
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) 
+{
+    cystatus status = CYRET_BAD_PARAM;
+
+    if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
+    {
+        if (0u != enableRR)
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;
+        }
+        else
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);
+        }
+
+        status = CYRET_SUCCESS;
+    }
+
+    return(status);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h

@@ -1,229 +1,229 @@
-/*******************************************************************************
-* File Name: CyDmac.h
-* Version 4.20
-*
-*  Description:
-*   Provides the function definitions for the DMA Controller.
-*
-*  Note:
-*   Documentation of the API's in this file is located in the
-*   System Reference Guide provided with PSoC Creator.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_BOOT_CYDMAC_H)
-#define CY_BOOT_CYDMAC_H
-
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cydevice_trm.h"
-#include "CyLib.h"
-
-
-/***************************************
-*    Function Prototypes
-***************************************/
-
-/* DMA Controller functions. */
-void    CyDmacConfigure(void) ;
-uint8   CyDmacError(void) ;
-void    CyDmacClearError(uint8 error) ;
-uint32  CyDmacErrorAddress(void) ;
-
-/* Channel specific functions. */
-uint8    CyDmaChAlloc(void) ;
-cystatus CyDmaChFree(uint8 chHandle) ;
-cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
-cystatus CyDmaChDisable(uint8 chHandle) ;
-cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
-cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
-cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
-;
-cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
-cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
-cystatus CyDmaChGetRequest(uint8 chHandle) ;
-cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
-cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
-                                 uint8 tdDone1, uint8 tdStop) ;
-cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
-
-/* Transfer Descriptor functions. */
-uint8    CyDmaTdAllocate(void) ;
-void     CyDmaTdFree(uint8 tdHandle) ;
-uint8    CyDmaTdFreeCount(void) ;
-cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
-;
-cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
-;
-cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
-cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
-
-
-/***************************************
-* Data Struct Definitions
-***************************************/
-
-typedef struct dmac_ch_struct
-{
-    volatile uint8 basic_cfg[4];
-    volatile uint8 action[4];
-    volatile uint8 basic_status[4];
-    volatile uint8 reserved[4];
-
-} dmac_ch;
-
-
-typedef struct dmac_cfgmem_struct
-{
-    volatile uint8 CFG0[4];
-    volatile uint8 CFG1[4];
-
-} dmac_cfgmem;
-
-
-typedef struct dmac_tdmem_struct
-{
-    volatile uint8  TD0[4];
-    volatile uint8  TD1[4];
-
-} dmac_tdmem;
-
-
-typedef struct dmac_tdmem2_struct
-{
-    volatile uint16 xfercnt;
-    volatile uint8  next_td_ptr;
-    volatile uint8  flags;
-    volatile uint16 src_adr;
-    volatile uint16 dst_adr;
-} dmac_tdmem2;
-
-
-/***************************************
-* API Constants
-***************************************/
-
-#define CY_DMA_INVALID_CHANNEL      0xFFu   /* Invalid Channel ID */
-#define CY_DMA_INVALID_TD           0xFFu   /* Invalid TD */
-#define CY_DMA_END_CHAIN_TD         0xFFu   /* End of chain TD */
-#define CY_DMA_DISABLE_TD           0xFEu
-
-#define CY_DMA_TD_SIZE              0x08u
-
-/* "u" was removed as workaround for Keil compiler bug */
-#define CY_DMA_TD_SWAP_EN           0x80
-#define CY_DMA_TD_SWAP_SIZE4        0x40
-#define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
-#define CY_DMA_TD_TERMIN_EN         0x10
-#define CY_DMA_TD_TERMOUT1_EN       0x08
-#define CY_DMA_TD_TERMOUT0_EN       0x04
-#define CY_DMA_TD_INC_DST_ADR       0x02
-#define CY_DMA_TD_INC_SRC_ADR       0x01
-
-#define CY_DMA_NUMBEROF_TDS         128u
-#define CY_DMA_NUMBEROF_CHANNELS    ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))
-
-/* Action register bits */
-#define CY_DMA_CPU_REQ              ((uint8)(1u << 0u))
-#define CY_DMA_CPU_TERM_TD          ((uint8)(1u << 1u))
-#define CY_DMA_CPU_TERM_CHAIN       ((uint8)(1u << 2u))
-
-/* Basic Status register bits */
-#define CY_DMA_STATUS_CHAIN_ACTIVE  ((uint8)(1u << 0u))
-#define CY_DMA_STATUS_TD_ACTIVE     ((uint8)(1u << 1u))
-
-/* DMA controller register error bits */
-#define CY_DMA_BUS_TIMEOUT          (1u << 1u)
-#define CY_DMA_UNPOP_ACC            (1u << 2u)
-#define CY_DMA_PERIPH_ERR           (1u << 3u)
-
-/* Round robin bits */
-#define CY_DMA_ROUND_ROBIN_ENABLE   ((uint8)(1u << 4u))
-
-
-/*******************************************************************************
-* CyDmaChEnable() / CyDmaChDisable() API constants
-*******************************************************************************/
-#define CY_DMA_CH_BASIC_CFG_EN           (0x01u)
-#define CY_DMA_CH_BASIC_CFG_WORK_SEP     (0x20u)
-
-
-/***************************************
-* Registers
-***************************************/
-
-#define CY_DMA_CFG_REG              (*(reg32 *) CYREG_PHUB_CFG)
-#define CY_DMA_CFG_PTR              ( (reg32 *) CYREG_PHUB_CFG)
-
-#define CY_DMA_ERR_REG              (*(reg32 *) CYREG_PHUB_ERR)
-#define CY_DMA_ERR_PTR              ( (reg32 *) CYREG_PHUB_ERR)
-
-#define CY_DMA_ERR_ADR_REG          (*(reg32 *) CYREG_PHUB_ERR_ADR)
-#define CY_DMA_ERR_ADR_PTR          ( (reg32 *) CYREG_PHUB_ERR_ADR)
-
-#define CY_DMA_CH_STRUCT_REG        (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
-#define CY_DMA_CH_STRUCT_PTR        ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
-
-#define CY_DMA_CFGMEM_STRUCT_REG    (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
-#define CY_DMA_CFGMEM_STRUCT_PTR    ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
-
-#define CY_DMA_TDMEM_STRUCT_REG     (*(dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
-#define CY_DMA_TDMEM_STRUCT_PTR     ( (dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used.
-*
-* If the obsoleted macro definitions intended for use in the application use the
-* following scheme, redefine your own versions of these definitions:
-*    #ifdef <OBSOLETED_DEFINE>
-*        #undef  <OBSOLETED_DEFINE>
-*        #define <OBSOLETED_DEFINE>      (<New Value>)
-*    #endif
-*
-* Note: Redefine obsoleted macro definitions with caution. They might still be
-*       used in the application and their modification might lead to unexpected
-*       consequences.
-*******************************************************************************/
-#define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
-#define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
-#define DMA_END_CHAIN_TD            (CY_DMA_END_CHAIN_TD)
-#define DMAC_TD_SIZE                (CY_DMA_TD_SIZE)
-#define TD_SWAP_EN                  (CY_DMA_TD_SWAP_EN)
-#define TD_SWAP_SIZE4               (CY_DMA_TD_SWAP_SIZE4)
-#define TD_AUTO_EXEC_NEXT           (CY_DMA_TD_AUTO_EXEC_NEXT)
-#define TD_TERMIN_EN                (CY_DMA_TD_TERMIN_EN)
-#define TD_TERMOUT1_EN              (CY_DMA_TD_TERMOUT1_EN)
-#define TD_TERMOUT0_EN              (CY_DMA_TD_TERMOUT0_EN)
-#define TD_INC_DST_ADR              (CY_DMA_TD_INC_DST_ADR)
-#define TD_INC_SRC_ADR              (CY_DMA_TD_INC_SRC_ADR)
-#define NUMBEROF_TDS                (CY_DMA_NUMBEROF_TDS)
-#define NUMBEROF_CHANNELS           (CY_DMA_NUMBEROF_CHANNELS)
-#define CPU_REQ                     (CY_DMA_CPU_REQ)
-#define CPU_TERM_TD                 (CY_DMA_CPU_TERM_TD)
-#define CPU_TERM_CHAIN              (CY_DMA_CPU_TERM_CHAIN)
-#define STATUS_CHAIN_ACTIVE         (CY_DMA_STATUS_CHAIN_ACTIVE)
-#define STATUS_TD_ACTIVE            (CY_DMA_STATUS_TD_ACTIVE)
-#define DMAC_BUS_TIMEOUT            (CY_DMA_BUS_TIMEOUT)
-#define DMAC_UNPOP_ACC              (CY_DMA_UNPOP_ACC)
-#define DMAC_PERIPH_ERR             (CY_DMA_PERIPH_ERR)
-#define ROUND_ROBIN_ENABLE          (CY_DMA_ROUND_ROBIN_ENABLE)
-#define DMA_DISABLE_TD              (CY_DMA_DISABLE_TD)
-
-#define DMAC_CFG                    (CY_DMA_CFG_PTR)
-#define DMAC_ERR                    (CY_DMA_ERR_PTR)
-#define DMAC_ERR_ADR                (CY_DMA_ERR_ADR_PTR)
-#define DMAC_CH                     (CY_DMA_CH_STRUCT_PTR)
-#define DMAC_CFGMEM                 (CY_DMA_CFGMEM_STRUCT_PTR)
-#define DMAC_TDMEM                  (CY_DMA_TDMEM_STRUCT_PTR)
-
-#endif  /* (CY_BOOT_CYDMAC_H) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyDmac.h
+* Version 4.20
+*
+*  Description:
+*   Provides the function definitions for the DMA Controller.
+*
+*  Note:
+*   Documentation of the API's in this file is located in the
+*   System Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYDMAC_H)
+#define CY_BOOT_CYDMAC_H
+
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cydevice_trm.h"
+#include "CyLib.h"
+
+
+/***************************************
+*    Function Prototypes
+***************************************/
+
+/* DMA Controller functions. */
+void    CyDmacConfigure(void) ;
+uint8   CyDmacError(void) ;
+void    CyDmacClearError(uint8 error) ;
+uint32  CyDmacErrorAddress(void) ;
+
+/* Channel specific functions. */
+uint8    CyDmaChAlloc(void) ;
+cystatus CyDmaChFree(uint8 chHandle) ;
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
+cystatus CyDmaChDisable(uint8 chHandle) ;
+cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
+;
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
+cystatus CyDmaChGetRequest(uint8 chHandle) ;
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
+                                 uint8 tdDone1, uint8 tdStop) ;
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
+
+/* Transfer Descriptor functions. */
+uint8    CyDmaTdAllocate(void) ;
+void     CyDmaTdFree(uint8 tdHandle) ;
+uint8    CyDmaTdFreeCount(void) ;
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
+;
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
+;
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
+
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+typedef struct dmac_ch_struct
+{
+    volatile uint8 basic_cfg[4];
+    volatile uint8 action[4];
+    volatile uint8 basic_status[4];
+    volatile uint8 reserved[4];
+
+} dmac_ch;
+
+
+typedef struct dmac_cfgmem_struct
+{
+    volatile uint8 CFG0[4];
+    volatile uint8 CFG1[4];
+
+} dmac_cfgmem;
+
+
+typedef struct dmac_tdmem_struct
+{
+    volatile uint8  TD0[4];
+    volatile uint8  TD1[4];
+
+} dmac_tdmem;
+
+
+typedef struct dmac_tdmem2_struct
+{
+    volatile uint16 xfercnt;
+    volatile uint8  next_td_ptr;
+    volatile uint8  flags;
+    volatile uint16 src_adr;
+    volatile uint16 dst_adr;
+} dmac_tdmem2;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define CY_DMA_INVALID_CHANNEL      0xFFu   /* Invalid Channel ID */
+#define CY_DMA_INVALID_TD           0xFFu   /* Invalid TD */
+#define CY_DMA_END_CHAIN_TD         0xFFu   /* End of chain TD */
+#define CY_DMA_DISABLE_TD           0xFEu
+
+#define CY_DMA_TD_SIZE              0x08u
+
+/* "u" was removed as workaround for Keil compiler bug */
+#define CY_DMA_TD_SWAP_EN           0x80
+#define CY_DMA_TD_SWAP_SIZE4        0x40
+#define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
+#define CY_DMA_TD_TERMIN_EN         0x10
+#define CY_DMA_TD_TERMOUT1_EN       0x08
+#define CY_DMA_TD_TERMOUT0_EN       0x04
+#define CY_DMA_TD_INC_DST_ADR       0x02
+#define CY_DMA_TD_INC_SRC_ADR       0x01
+
+#define CY_DMA_NUMBEROF_TDS         128u
+#define CY_DMA_NUMBEROF_CHANNELS    ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))
+
+/* Action register bits */
+#define CY_DMA_CPU_REQ              ((uint8)(1u << 0u))
+#define CY_DMA_CPU_TERM_TD          ((uint8)(1u << 1u))
+#define CY_DMA_CPU_TERM_CHAIN       ((uint8)(1u << 2u))
+
+/* Basic Status register bits */
+#define CY_DMA_STATUS_CHAIN_ACTIVE  ((uint8)(1u << 0u))
+#define CY_DMA_STATUS_TD_ACTIVE     ((uint8)(1u << 1u))
+
+/* DMA controller register error bits */
+#define CY_DMA_BUS_TIMEOUT          (1u << 1u)
+#define CY_DMA_UNPOP_ACC            (1u << 2u)
+#define CY_DMA_PERIPH_ERR           (1u << 3u)
+
+/* Round robin bits */
+#define CY_DMA_ROUND_ROBIN_ENABLE   ((uint8)(1u << 4u))
+
+
+/*******************************************************************************
+* CyDmaChEnable() / CyDmaChDisable() API constants
+*******************************************************************************/
+#define CY_DMA_CH_BASIC_CFG_EN           (0x01u)
+#define CY_DMA_CH_BASIC_CFG_WORK_SEP     (0x20u)
+
+
+/***************************************
+* Registers
+***************************************/
+
+#define CY_DMA_CFG_REG              (*(reg32 *) CYREG_PHUB_CFG)
+#define CY_DMA_CFG_PTR              ( (reg32 *) CYREG_PHUB_CFG)
+
+#define CY_DMA_ERR_REG              (*(reg32 *) CYREG_PHUB_ERR)
+#define CY_DMA_ERR_PTR              ( (reg32 *) CYREG_PHUB_ERR)
+
+#define CY_DMA_ERR_ADR_REG          (*(reg32 *) CYREG_PHUB_ERR_ADR)
+#define CY_DMA_ERR_ADR_PTR          ( (reg32 *) CYREG_PHUB_ERR_ADR)
+
+#define CY_DMA_CH_STRUCT_REG        (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
+#define CY_DMA_CH_STRUCT_PTR        ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)
+
+#define CY_DMA_CFGMEM_STRUCT_REG    (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
+#define CY_DMA_CFGMEM_STRUCT_PTR    ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)
+
+#define CY_DMA_TDMEM_STRUCT_REG     (*(dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
+#define CY_DMA_TDMEM_STRUCT_PTR     ( (dmac_tdmem  CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
+#define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
+#define DMA_END_CHAIN_TD            (CY_DMA_END_CHAIN_TD)
+#define DMAC_TD_SIZE                (CY_DMA_TD_SIZE)
+#define TD_SWAP_EN                  (CY_DMA_TD_SWAP_EN)
+#define TD_SWAP_SIZE4               (CY_DMA_TD_SWAP_SIZE4)
+#define TD_AUTO_EXEC_NEXT           (CY_DMA_TD_AUTO_EXEC_NEXT)
+#define TD_TERMIN_EN                (CY_DMA_TD_TERMIN_EN)
+#define TD_TERMOUT1_EN              (CY_DMA_TD_TERMOUT1_EN)
+#define TD_TERMOUT0_EN              (CY_DMA_TD_TERMOUT0_EN)
+#define TD_INC_DST_ADR              (CY_DMA_TD_INC_DST_ADR)
+#define TD_INC_SRC_ADR              (CY_DMA_TD_INC_SRC_ADR)
+#define NUMBEROF_TDS                (CY_DMA_NUMBEROF_TDS)
+#define NUMBEROF_CHANNELS           (CY_DMA_NUMBEROF_CHANNELS)
+#define CPU_REQ                     (CY_DMA_CPU_REQ)
+#define CPU_TERM_TD                 (CY_DMA_CPU_TERM_TD)
+#define CPU_TERM_CHAIN              (CY_DMA_CPU_TERM_CHAIN)
+#define STATUS_CHAIN_ACTIVE         (CY_DMA_STATUS_CHAIN_ACTIVE)
+#define STATUS_TD_ACTIVE            (CY_DMA_STATUS_TD_ACTIVE)
+#define DMAC_BUS_TIMEOUT            (CY_DMA_BUS_TIMEOUT)
+#define DMAC_UNPOP_ACC              (CY_DMA_UNPOP_ACC)
+#define DMAC_PERIPH_ERR             (CY_DMA_PERIPH_ERR)
+#define ROUND_ROBIN_ENABLE          (CY_DMA_ROUND_ROBIN_ENABLE)
+#define DMA_DISABLE_TD              (CY_DMA_DISABLE_TD)
+
+#define DMAC_CFG                    (CY_DMA_CFG_PTR)
+#define DMAC_ERR                    (CY_DMA_ERR_PTR)
+#define DMAC_ERR_ADR                (CY_DMA_ERR_ADR_PTR)
+#define DMAC_CH                     (CY_DMA_CH_STRUCT_PTR)
+#define DMAC_CFGMEM                 (CY_DMA_CFGMEM_STRUCT_PTR)
+#define DMAC_TDMEM                  (CY_DMA_TDMEM_STRUCT_PTR)
+
+#endif  /* (CY_BOOT_CYDMAC_H) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c

@@ -1,753 +1,753 @@
-/*******************************************************************************
-* File Name: CyFlash.c
-* Version 4.20
-*
-*  Description:
-*   Provides an API for the FLASH/EEPROM.
-*
-*  Note:
-*   This code is endian agnostic.
-*
-*  Note:
-*   Documentation of the API's in this file is located in the
-*   System Reference Guide provided with PSoC Creator.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "CyFlash.h"
-
-/*  The number of EEPROM arrays */
-#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
-
-
-/*******************************************************************************
-* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
-* The first byte is the sign of the temperature (0 = negative, 1 = positive).
-* The second byte is the magnitude.
-*******************************************************************************/
-uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
-
-#if(CYDEV_ECC_ENABLE == 0)
-    static uint8 * rowBuffer = 0;
-#endif  /* (CYDEV_ECC_ENABLE == 0) */
-
-
-static cystatus CySetTempInt(void);
-static cystatus CyFlashGetSpcAlgorithm(void);
-
-
-/*******************************************************************************
-* Function Name: CyFlash_Start
-********************************************************************************
-*
-* Summary:
-*  Enable the Flash.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyFlash_Start(void) 
-{
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-
-    /***************************************************************************
-    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
-    * is required for the SPC to function.
-    ***************************************************************************/
-    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
-    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
-
-
-    /***************************************************************************
-    * The wake count defines the number of Bus Clock cycles it takes for the
-    * flash or eeprom to wake up from a low power mode independent of the chip
-    * power mode. Wake up time for these blocks is 5 us.
-    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
-    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
-    * This register needs to be written with a value dependent on the Bus Clock
-    * frequency so that the duration of the cycles is equal to or greater than
-    * the 5 us delay required.
-    ***************************************************************************/
-    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
-
-
-    /***************************************************************************
-    * Enable flash. Active flash macros consume current, but re-enabling a
-    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
-    * macro during that time, it will be stalled. This bit allows the flash to
-    * be enabled even if the CPU is disabled, which allows a quicker return to
-    * code execution.
-    ***************************************************************************/
-    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
-    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
-
-    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
-    {
-        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
-    }
-
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyFlash_Stop
-********************************************************************************
-*
-* Summary:
-*  Disable the Flash.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  This setting is ignored as long as the CPU is currently running.  This will
-*  only take effect when the CPU is later disabled.
-*
-*******************************************************************************/
-void CyFlash_Stop(void) 
-{
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
-    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
-
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CySetTempInt
-********************************************************************************
-*
-* Summary:
-*  Sends a command to the SPC to read the die temperature. Sets a global value
-*  used by the Write function. This function must be called once before
-*  executing a series of Flash writing functions.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  status:
-*   CYRET_SUCCESS - if successful
-*   CYRET_LOCKED  - if Flash writing already in use
-*   CYRET_UNKNOWN - if there was an SPC error
-*
-*******************************************************************************/
-static cystatus CySetTempInt(void) 
-{
-    cystatus status;
-
-    /* Make sure SPC is powered */
-    CySpcStart();
-
-    /* Plan for failure. */
-    status = CYRET_UNKNOWN;
-
-    if(CySpcLock() == CYRET_SUCCESS)
-    {
-        /* Write the command. */
-        if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
-        {
-            do
-            {
-                if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
-                {
-                    status = CYRET_SUCCESS;
-
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Spin until idle. */
-                        CyDelayUs(1u);
-                    }
-                    break;
-                }
-
-            } while(CY_SPC_BUSY);
-        }
-
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyFlashGetSpcAlgorithm
-********************************************************************************
-*
-* Summary:
-*  Sends a command to the SPC to download code into RAM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  status:
-*   CYRET_SUCCESS - if successful
-*   CYRET_LOCKED  - if Flash writing already in use
-*   CYRET_UNKNOWN - if there was an SPC error
-*
-*******************************************************************************/
-static cystatus CyFlashGetSpcAlgorithm(void) 
-{
-    cystatus status;
-
-    /* Make sure SPC is powered */
-    CySpcStart();
-
-    if(CySpcLock() == CYRET_SUCCESS)
-    {
-        status = CySpcGetAlgorithm();
-
-        if(CYRET_STARTED == status)
-        {
-            while(CY_SPC_BUSY)
-            {
-                /* Spin until idle. */
-                CyDelayUs(1u);
-            }
-
-            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-            {
-                status = CYRET_SUCCESS;
-            }
-        }
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySetTemp
-********************************************************************************
-*
-* Summary:
-*  This is a wraparound for CySetTempInt(). It is used to return the second
-*  successful read of the temperature value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  status:
-*   CYRET_SUCCESS if successful.
-*   CYRET_LOCKED  if Flash writing already in use
-*   CYRET_UNKNOWN if there was an SPC error.
-*
-*  uint8 dieTemperature[2]:
-*   Holds the die temperature for the flash writing algorithm. The first byte is
-*   the sign of the temperature (0 = negative, 1 = positive). The second byte is
-*   the magnitude.
-*
-*******************************************************************************/
-cystatus CySetTemp(void) 
-{
-    cystatus status = CyFlashGetSpcAlgorithm();
-
-    if(status == CYRET_SUCCESS)
-    {
-        status = CySetTempInt();
-    }
-
-    return (status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySetFlashEEBuffer
-********************************************************************************
-*
-* Summary:
-*  Sets the user supplied temporary buffer to store SPC data while performing
-*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
-*  disabled.
-*
-* Parameters:
-*  buffer:
-*   The address of a block of memory to store temporary memory. The size of the block
-*   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
-*
-* Return:
-*  status:
-*   CYRET_SUCCESS if successful.
-*   CYRET_BAD_PARAM if the buffer is NULL
-*
-*******************************************************************************/
-cystatus CySetFlashEEBuffer(uint8 * buffer) 
-{
-    cystatus status = CYRET_SUCCESS;
-
-    CySpcStart();
-
-    #if(CYDEV_ECC_ENABLE == 0)
-
-        if(NULL == buffer)
-        {
-            rowBuffer = rowBuffer;
-            status = CYRET_BAD_PARAM;
-        }
-        else if(CySpcLock() != CYRET_SUCCESS)
-        {
-            rowBuffer = rowBuffer;
-            status = CYRET_LOCKED;
-        }
-        else
-        {
-            rowBuffer = buffer;
-            CySpcUnlock();
-        }
-
-    #else
-
-        /* To suppress warning */
-        buffer = buffer;
-
-    #endif  /* (CYDEV_ECC_ENABLE == 0u) */
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyWriteRowData
-********************************************************************************
-*
-* Summary:
-*  Sends a command to the SPC to load and program a row of data in
-*  Flash or EEPROM.
-*
-* Parameters:
-*  arrayID:    ID of the array to write.
-*   The type of write, Flash or EEPROM, is determined from the array ID.
-*   The arrays in the part are sequential starting at the first ID for the
-*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-*  rowAddress: rowAddress of flash row to program.
-*  rowData:    Array of bytes to write.
-*
-* Return:
-*  status:
-*   CYRET_SUCCESS if successful.
-*   CYRET_LOCKED if the SPC is already in use.
-*   CYRET_CANCELED if command not accepted
-*   CYRET_UNKNOWN if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-{
-    uint16 rowSize;
-    cystatus status;
-
-    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
-    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
-    return(status);
-}
-
-
-/*******************************************************************
-* If "Enable Error Correcting Code (ECC)" and "Store Configuration
-* Data in ECC" DWR options are disabled, ECC section is available
-* for user data.
-*******************************************************************/
-#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowConfig
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sends a command to the SPC to load and program a row of config data in the Flash.
-    *  This function is only valid for Flash array IDs (not for EEPROM).
-    *
-    * Parameters:
-    *  arrayId:      ID of the array to write
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts
-    *   from 0x00 to 0x3F.
-    *  rowAddress:   The address of the sector to erase.
-    *  rowECC:       The array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
-    
-    {
-        cystatus status;
-
-        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
-
-        return (status);
-    }
-
-#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
-
-
-
-/*******************************************************************************
-* Function Name: CyWriteRowFull
-********************************************************************************
-* Summary:
-*  Sends a command to the SPC to load and program a row of data in the Flash.
-*  rowData array is expected to contain Flash and ECC data if needed.
-*
-* Parameters:
-*  arrayId:    FLASH or EEPROM array id.
-*  rowData:    Pointer to a row of data to write.
-*  rowNumber:  Zero based number of the row.
-*  rowSize:    Size of the row.
-*
-* Return:
-*  CYRET_SUCCESS if successful.
-*  CYRET_LOCKED if the SPC is already in use.
-*  CYRET_CANCELED if command not accepted
-*  CYRET_UNKNOWN if there was an SPC error.
-*
-*******************************************************************************/
-cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
-        
-{
-    cystatus status = CYRET_SUCCESS;
-
-    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
-    {
-        /* Flash */
-        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
-        {
-            status = CYRET_BAD_PARAM;
-        }
-    }
-    else
-    {
-        /* EEPROM */
-        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
-        {
-            status = CYRET_BAD_PARAM;
-        }
-
-        if(CY_EEPROM_SIZEOF_ROW != rowSize)
-        {
-            status = CYRET_BAD_PARAM;
-        }
-    }
-
-    if(rowData == NULL)
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-
-    if(status == CYRET_SUCCESS)
-    {
-        if(CySpcLock() == CYRET_SUCCESS)
-        {
-            /* Load row data into SPC internal latch */
-            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
-
-            if(CYRET_STARTED == status)
-            {
-                while(CY_SPC_BUSY)
-                {
-                    /* Wait for SPC to finish and get SPC status */
-                    CyDelayUs(1u);
-                }
-
-                /* Hide SPC status */
-                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                {
-                    status = CYRET_SUCCESS;
-                }
-                else
-                {
-                    status = CYRET_UNKNOWN;
-                }
-
-                if(CYRET_SUCCESS == status)
-                {
-                    /* Erase and program flash with data from SPC interval latch */
-                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
-
-                    if(CYRET_STARTED == status)
-                    {
-                        while(CY_SPC_BUSY)
-                        {
-                            /* Wait for SPC to finish and get SPC status */
-                            CyDelayUs(1u);
-                        }
-
-                        /* Hide SPC status */
-                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                        {
-                            status = CYRET_SUCCESS;
-                        }
-                        else
-                        {
-                            status = CYRET_UNKNOWN;
-                        }
-                    }
-                }
-            }
-            CySpcUnlock();
-        }   /* if(CySpcLock() == CYRET_SUCCESS) */
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyFlash_SetWaitCycles
-********************************************************************************
-*
-* Summary:
-*  Sets the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash. This function must be called before increasing the CPU
-*  clock frequency. It can optionally be called after lowering the CPU clock
-*  frequency in order to improve the CPU performance.
-*
-* Parameters:
-*  uint8 freq:
-*   Frequency of operation in Megahertz.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyFlash_SetWaitCycles(uint8 freq) 
-{
-    uint8 interruptState;
-
-    /* Save current global interrupt enable and disable it */
-    interruptState = CyEnterCriticalSection();
-
-    /***************************************************************************
-    * The number of clock cycles the cache will wait before it samples data
-    * coming back from the Flash must be equal or greater to to the CPU frequency
-    * outlined in clock cycles.
-    ***************************************************************************/
-
-    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
-    {
-        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
-                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
-    }
-    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
-    {
-        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
-                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
-    }
-    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
-    {
-        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
-                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
-    }
-#if (CY_PSOC5)
-    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
-    {
-        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
-                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
-    }
-    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
-    {
-        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
-                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
-    }
-#endif  /* (CY_PSOC5) */
-    else
-    {
-        /* Halt CPU in debug mode if frequency is invalid */
-        CYASSERT(0u != 0u);
-    }
-
-    /* Restore global interrupt enable state */
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyEEPROM_Start
-********************************************************************************
-*
-* Summary:
-*  Enable the EEPROM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyEEPROM_Start(void) 
-{
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-
-    /***************************************************************************
-    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
-    * is required for the SPC to function.
-    ***************************************************************************/
-    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
-    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
-
-
-    /***************************************************************************
-    * The wake count defines the number of Bus Clock cycles it takes for the
-    * flash or EEPROM to wake up from a low power mode independent of the chip
-    * power mode. Wake up time for these blocks is 5 us.
-    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
-    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
-    * This register needs to be written with a value dependent on the Bus Clock
-    * frequency so that the duration of the cycles is equal to or greater than
-    * the 5 us delay required.
-    ***************************************************************************/
-    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
-
-
-    /***************************************************************************
-    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
-    * the EE will not acknowledge a PHUB request.
-    ***************************************************************************/
-    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
-    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
-
-    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
-    {
-        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
-    }
-
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyEEPROM_Stop
-********************************************************************************
-*
-* Summary:
-*  Disable the EEPROM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyEEPROM_Stop (void) 
-{
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
-    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
-
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyEEPROM_ReadReserve
-********************************************************************************
-*
-* Summary:
-*  Request access to the EEPROM for reading and wait until access is available.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyEEPROM_ReadReserve(void) 
-{
-    /* Make request for PHUB to have access */
-    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
-
-    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
-    {
-        /* Wait for acknowledgment from PHUB */
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyEEPROM_ReadRelease
-********************************************************************************
-*
-* Summary:
-*  Release the read reservation of the EEPROM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyEEPROM_ReadRelease(void) 
-{
-    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyFlash.c
+* Version 4.20
+*
+*  Description:
+*   Provides an API for the FLASH/EEPROM.
+*
+*  Note:
+*   This code is endian agnostic.
+*
+*  Note:
+*   Documentation of the API's in this file is located in the
+*   System Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyFlash.h"
+
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
+
+/*******************************************************************************
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
+* The first byte is the sign of the temperature (0 = negative, 1 = positive).
+* The second byte is the magnitude.
+*******************************************************************************/
+uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
+
+#if(CYDEV_ECC_ENABLE == 0)
+    static uint8 * rowBuffer = 0;
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
+
+
+static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
+
+
+/*******************************************************************************
+* Function Name: CyFlash_Start
+********************************************************************************
+*
+* Summary:
+*  Enable the Flash.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyFlash_Start(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlash_Stop
+********************************************************************************
+*
+* Summary:
+*  Disable the Flash.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  This setting is ignored as long as the CPU is currently running.  This will
+*  only take effect when the CPU is later disabled.
+*
+*******************************************************************************/
+void CyFlash_Stop(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetTempInt
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to read the die temperature. Sets a global value
+*  used by the Write function. This function must be called once before
+*  executing a series of Flash writing functions.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CySetTempInt(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    /* Plan for failure. */
+    status = CYRET_UNKNOWN;
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        /* Write the command. */
+        if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
+        {
+            do
+            {
+                if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
+                {
+                    status = CYRET_SUCCESS;
+
+                    while(CY_SPC_BUSY)
+                    {
+                        /* Spin until idle. */
+                        CyDelayUs(1u);
+                    }
+                    break;
+                }
+
+            } while(CY_SPC_BUSY);
+        }
+
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetTemp
+********************************************************************************
+*
+* Summary:
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED  if Flash writing already in use
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*  uint8 dieTemperature[2]:
+*   Holds the die temperature for the flash writing algorithm. The first byte is
+*   the sign of the temperature (0 = negative, 1 = positive). The second byte is
+*   the magnitude.
+*
+*******************************************************************************/
+cystatus CySetTemp(void) 
+{
+    cystatus status = CyFlashGetSpcAlgorithm();
+
+    if(status == CYRET_SUCCESS)
+    {
+        status = CySetTempInt();
+    }
+
+    return (status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySetFlashEEBuffer
+********************************************************************************
+*
+* Summary:
+*  Sets the user supplied temporary buffer to store SPC data while performing
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
+*  disabled.
+*
+* Parameters:
+*  buffer:
+*   The address of a block of memory to store temporary memory. The size of the block
+*   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_BAD_PARAM if the buffer is NULL
+*
+*******************************************************************************/
+cystatus CySetFlashEEBuffer(uint8 * buffer) 
+{
+    cystatus status = CYRET_SUCCESS;
+
+    CySpcStart();
+
+    #if(CYDEV_ECC_ENABLE == 0)
+
+        if(NULL == buffer)
+        {
+            rowBuffer = rowBuffer;
+            status = CYRET_BAD_PARAM;
+        }
+        else if(CySpcLock() != CYRET_SUCCESS)
+        {
+            rowBuffer = rowBuffer;
+            status = CYRET_LOCKED;
+        }
+        else
+        {
+            rowBuffer = buffer;
+            CySpcUnlock();
+        }
+
+    #else
+
+        /* To suppress warning */
+        buffer = buffer;
+
+    #endif  /* (CYDEV_ECC_ENABLE == 0u) */
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+* Parameters:
+*  arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  rowAddress: rowAddress of flash row to program.
+*  rowData:    Array of bytes to write.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
+
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
+
+    return(status);
+}
+
+
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+    /*******************************************************************************
+    * Function Name: CyWriteRowConfig
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sends a command to the SPC to load and program a row of config data in the Flash.
+    *  This function is only valid for Flash array IDs (not for EEPROM).
+    *
+    * Parameters:
+    *  arrayId:      ID of the array to write
+    *   The arrays in the part are sequential starting at the first ID for the
+    *   specific memory type. The array ID for the Flash memory lasts
+    *   from 0x00 to 0x3F.
+    *  rowAddress:   The address of the sector to erase.
+    *  rowECC:       The array of bytes to write.
+    *
+    * Return:
+    *  status:
+    *   CYRET_SUCCESS if successful.
+    *   CYRET_LOCKED if the SPC is already in use.
+    *   CYRET_CANCELED if command not accepted
+    *   CYRET_UNKNOWN if there was an SPC error.
+    *
+    *******************************************************************************/
+    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
+    
+    {
+        cystatus status;
+
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
+
+        return (status);
+    }
+
+#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+
+/*******************************************************************************
+* Function Name: CyWriteRowFull
+********************************************************************************
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in the Flash.
+*  rowData array is expected to contain Flash and ECC data if needed.
+*
+* Parameters:
+*  arrayId:    FLASH or EEPROM array id.
+*  rowData:    Pointer to a row of data to write.
+*  rowNumber:  Zero based number of the row.
+*  rowSize:    Size of the row.
+*
+* Return:
+*  CYRET_SUCCESS if successful.
+*  CYRET_LOCKED if the SPC is already in use.
+*  CYRET_CANCELED if command not accepted
+*  CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
+        
+{
+    cystatus status = CYRET_SUCCESS;
+
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
+
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
+
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
+
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
+                    {
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
+                    }
+                }
+            }
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyFlash_SetWaitCycles
+********************************************************************************
+*
+* Summary:
+*  Sets the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash. This function must be called before increasing the CPU
+*  clock frequency. It can optionally be called after lowering the CPU clock
+*  frequency in order to improve the CPU performance.
+*
+* Parameters:
+*  uint8 freq:
+*   Frequency of operation in Megahertz.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyFlash_SetWaitCycles(uint8 freq) 
+{
+    uint8 interruptState;
+
+    /* Save current global interrupt enable and disable it */
+    interruptState = CyEnterCriticalSection();
+
+    /***************************************************************************
+    * The number of clock cycles the cache will wait before it samples data
+    * coming back from the Flash must be equal or greater to to the CPU frequency
+    * outlined in clock cycles.
+    ***************************************************************************/
+
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
+
+    /* Restore global interrupt enable state */
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_Start
+********************************************************************************
+*
+* Summary:
+*  Enable the EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_Start(void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_Stop
+********************************************************************************
+*
+* Summary:
+*  Disable the EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_Stop (void) 
+{
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_ReadReserve
+********************************************************************************
+*
+* Summary:
+*  Request access to the EEPROM for reading and wait until access is available.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_ReadReserve(void) 
+{
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    {
+        /* Wait for acknowledgment from PHUB */
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyEEPROM_ReadRelease
+********************************************************************************
+*
+* Summary:
+*  Release the read reservation of the EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_ReadRelease(void) 
+{
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h

@@ -1,323 +1,323 @@
-/*******************************************************************************
-* File Name: CyFlash.h
-* Version 4.20
-*
-*  Description:
-*   Provides the function definitions for the FLASH/EEPROM.
-*
-*  Note:
-*   Documentation of the API's in this file is located in the
-*   System Reference Guide provided with PSoC Creator.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_BOOT_CYFLASH_H)
-#define CY_BOOT_CYFLASH_H
-
-#include "cydevice_trm.h"
-#include "cytypes.h"
-#include "CyLib.h"
-#include "CySpc.h"
-
-#define CY_FLASH_DIE_TEMP_DATA_SIZE      (2u)    /* Die temperature data size */
-
-extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
-
-
-/***************************************
-*    API Constants
-***************************************/
-
-#define CY_FLASH_BASE               (CYDEV_FLASH_BASE)
-#define CY_FLASH_SIZE               (CYDEV_FLS_SIZE)
-#define CY_FLASH_SIZEOF_ARRAY       (CYDEV_FLS_SECTOR_SIZE)
-#define CY_FLASH_SIZEOF_ROW         (CYDEV_FLS_ROW_SIZE)
-#define CY_FLASH_SIZEOF_ECC_ROW     (CYDEV_ECC_ROW_SIZE)
-#define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
-#define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
-
-#if(CYDEV_ECC_ENABLE == 0)
-    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
-#else
-    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
-#endif  /* (CYDEV_ECC_ENABLE == 0) */
-#define CY_EEPROM_BASE              (CYDEV_EE_BASE)
-#define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
-#define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
-#define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
-#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
-
-#if !defined(CYDEV_FLS_BASE)
-    #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
-#endif  /* !defined(CYDEV_FLS_BASE) */
-
-
-/***************************************
-*     Function Prototypes
-***************************************/
-
-/* Flash Functions */
-void     CyFlash_Start(void);
-void     CyFlash_Stop(void);
-cystatus CySetTemp(void);
-cystatus CySetFlashEEBuffer(uint8 * buffer);
-cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \
-            ;
-cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);
-
-#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
-    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \
-            ;
-#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
-
-void CyFlash_SetWaitCycles(uint8 freq) ;
-
-/* EEPROM Functions */
-void CyEEPROM_Start(void) ;
-void CyEEPROM_Stop(void) ;
-
-void CyEEPROM_ReadReserve(void) ;
-void CyEEPROM_ReadRelease(void) ;
-
-
-/***************************************
-*     Registers
-***************************************/
-/* Active Power Mode Configuration Register 0 */
-#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
-#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
-
-/* Alternate Active Power Mode Configuration Register 0 */
-#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
-#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
-
-/* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
-
-/* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
-
-/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
-#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
-#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
-
-/* Flash macro control register */
-#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
-#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
-
-
-/* Cache Control Register */
-#if (CY_PSOC3)
-
-    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CR )
-    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CR )
-
-#else
-
-    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CC_CTL )
-    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CC_CTL )
-
-#endif  /* (CY_PSOC3) */
-
-
-/* EEPROM Status & Control Register */
-#define CY_FLASH_EE_SCR_REG                     (* (reg8 *) CYREG_SPC_EE_SCR)
-#define CY_FLASH_EE_SCR_PTR                     (  (reg8 *) CYREG_SPC_EE_SCR)
-
-
-
-/***************************************
-*     Register Constants
-***************************************/
-
-/* Power Mode Masks */
-
-/* Enable EEPROM */
-#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
-#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
-
-/* Enable Flash */
-#if (CY_PSOC3)
-    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
-    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
-#else
-    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
-    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
-#endif  /* (CY_PSOC3) */
-
-
-
-/* Frequency Constants */
-#if (CY_PSOC3)
-    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
-    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
-    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
-    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
-
-    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
-    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
-    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
-#endif  /* (CY_PSOC3) */
-
-#if (CY_PSOC5)
-    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
-    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
-    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
-    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
-    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
-    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
-
-    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
-    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
-    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
-    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
-    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
-#endif  /* (CY_PSOC5) */
-
-#define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
-#define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-
-#define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
-#define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
-
-
-#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
-
-/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
-#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
-
-/* Enable clk_spc. This also internally enables the 36MHz IMO. */
-#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
-#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
-
-/* Default values for getting temperature. */
-
-#define CY_TEMP_NUMBER_OF_SAMPLES               (0x1u)
-#define CY_TEMP_TIMER_PERIOD                    (0xFFFu)
-#define CY_TEMP_CLK_DIV_SELECT                  (0x4u)
-#define CY_TEMP_NUM_SAMPLES                     (1 << (CY_TEMP_NUMBER_OF_SAMPLES))
-#define CY_SPC_CLK_PERIOD                       (120u)      /* nS */
-#define CY_SYS_ns_PER_TICK                      (1000u)
-#define CY_FRM_EXEC_TIME                        (1000u)     /* nS */
-
-#define CY_GET_TEMP_TIME                        ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \
-                                                    (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \
-                                                    CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)
-
-#define CY_TEMP_MAX_WAIT                        ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK)    /* In system ticks. */
-
-
-/*******************************************************************************
-* Thne following code is OBSOLETE and must not be used starting with cy_boot
-* 4.20.
-*
-* If the obsoleted macro definitions intended for use in the application use the
-* following scheme, redefine your own versions of these definitions:
-*    #ifdef <OBSOLETED_DEFINE>
-*        #undef  <OBSOLETED_DEFINE>
-*        #define <OBSOLETED_DEFINE>      (<New Value>)
-*    #endif
-*
-* Note: Redefine obsoleted macro definitions with caution. They might still be
-*       used in the application and their modification might lead to unexpected
-*       consequences.
-*******************************************************************************/
-#if (CY_PSOC5)
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-#endif  /* (CY_PSOC5) */
-
-#if (CY_PSOC3)
-    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
-    #define CY_FLASH_GREATER_44MHz              (0x03u)
-#endif  /* (CY_PSOC3) */
-
-#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_EE_MASK                 (0x10u)
-#define CY_FLASH_PM_FLASH_MASK              (0x01u)
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
-*******************************************************************************/
-#define FLASH_SIZE                  (CY_FLASH_SIZE)
-#define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
-#define FLASH_NUMBER_ROWS           (CY_FLASH_NUMBER_ROWS)
-#define FLASH_NUMBER_SECTORS        (CY_FLASH_NUMBER_ARRAYS)
-#define EEPROM_SIZE                 (CY_EEPROM_SIZE)
-#define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
-#define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
-#define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
-*******************************************************************************/
-#define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
-
-#define TEMP_NUMBER_OF_SAMPLES      (CY_TEMP_NUMBER_OF_SAMPLES)
-#define TEMP_TIMER_PERIOD           (CY_TEMP_TIMER_PERIOD)
-#define TEMP_CLK_DIV_SELECT         (CY_TEMP_CLK_DIV_SELECT)
-#define NUM_SAMPLES                 (CY_TEMP_NUM_SAMPLES)
-#define SPC_CLK_PERIOD              (CY_SPC_CLK_PERIOD)
-#define FRM_EXEC_TIME               (CY_FRM_EXEC_TIME)
-#define GET_TEMP_TIME               (CY_GET_TEMP_TIME)
-#define TEMP_MAX_WAIT               (CY_TEMP_MAX_WAIT)
-
-#define ECC_ADDR                    (0x80u)
-
-
-#define PM_ACT_EE_PTR           (CY_FLASH_PM_ACT_EEFLASH_PTR)
-#define PM_ACT_FLASH_PTR        (CY_FLASH_PM_ACT_EEFLASH_PTR)
-
-#define PM_STBY_EE_PTR          (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
-#define PM_STBY_FLASH_PTR       (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
-
-#define PM_EE_MASK              (CY_FLASH_PM_EE_MASK)
-#define PM_FLASH_MASK           (CY_FLASH_PM_FLASH_MASK)
-
-#define FLASH_CYCLES_MASK_SHIFT     (CY_FLASH_CYCLES_MASK_SHIFT)
-#define FLASH_CYCLES_MASK           (CY_FLASH_CYCLES_MASK)
-
-
-#if (CY_PSOC3)
-
-    #define LESSER_OR_EQUAL_22MHz   (CY_FLASH_LESSER_OR_EQUAL_22MHz)
-    #define LESSER_OR_EQUAL_44MHz   (CY_FLASH_LESSER_OR_EQUAL_44MHz)
-    #define GREATER_44MHz           (CY_FLASH_GREATER_44MHz)
-
-#endif  /* (CY_PSOC3) */
-
-#if (CY_PSOC5)
-
-    #define LESSER_OR_EQUAL_16MHz   (CY_FLASH_LESSER_OR_EQUAL_16MHz)
-    #define LESSER_OR_EQUAL_33MHz   (CY_FLASH_LESSER_OR_EQUAL_33MHz)
-    #define LESSER_OR_EQUAL_50MHz   (CY_FLASH_LESSER_OR_EQUAL_50MHz)
-    #define LESSER_OR_EQUAL_67MHz   (CY_FLASH_LESSER_OR_EQUAL_67MHz)
-    #define GREATER_67MHz           (CY_FLASH_GREATER_67MHz)
-    #define GREATER_51MHz           (CY_FLASH_GREATER_51MHz)
-
-#endif  /* (CY_PSOC5) */
-
-#define AHUB_EE_REQ_ACK_PTR         (CY_FLASH_EE_SCR_PTR)
-
-
-#endif  /* (CY_BOOT_CYFLASH_H) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyFlash.h
+* Version 4.20
+*
+*  Description:
+*   Provides the function definitions for the FLASH/EEPROM.
+*
+*  Note:
+*   Documentation of the API's in this file is located in the
+*   System Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYFLASH_H)
+#define CY_BOOT_CYFLASH_H
+
+#include "cydevice_trm.h"
+#include "cytypes.h"
+#include "CyLib.h"
+#include "CySpc.h"
+
+#define CY_FLASH_DIE_TEMP_DATA_SIZE      (2u)    /* Die temperature data size */
+
+extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
+
+
+/***************************************
+*    API Constants
+***************************************/
+
+#define CY_FLASH_BASE               (CYDEV_FLASH_BASE)
+#define CY_FLASH_SIZE               (CYDEV_FLS_SIZE)
+#define CY_FLASH_SIZEOF_ARRAY       (CYDEV_FLS_SECTOR_SIZE)
+#define CY_FLASH_SIZEOF_ROW         (CYDEV_FLS_ROW_SIZE)
+#define CY_FLASH_SIZEOF_ECC_ROW     (CYDEV_ECC_ROW_SIZE)
+#define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
+#define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
+
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
+#define CY_EEPROM_BASE              (CYDEV_EE_BASE)
+#define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
+#define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
+
+#if !defined(CYDEV_FLS_BASE)
+    #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
+#endif  /* !defined(CYDEV_FLS_BASE) */
+
+
+/***************************************
+*     Function Prototypes
+***************************************/
+
+/* Flash Functions */
+void     CyFlash_Start(void);
+void     CyFlash_Stop(void);
+cystatus CySetTemp(void);
+cystatus CySetFlashEEBuffer(uint8 * buffer);
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \
+            ;
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);
+
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \
+            ;
+#endif  /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+void CyFlash_SetWaitCycles(uint8 freq) ;
+
+/* EEPROM Functions */
+void CyEEPROM_Start(void) ;
+void CyEEPROM_Stop(void) ;
+
+void CyEEPROM_ReadReserve(void) ;
+void CyEEPROM_ReadRelease(void) ;
+
+
+/***************************************
+*     Registers
+***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
+/* Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
+
+/* Alternate Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
+
+
+/* Cache Control Register */
+#if (CY_PSOC3)
+
+    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CR )
+    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CR )
+
+#else
+
+    #define CY_FLASH_CONTROL_REG                (* (reg8 *) CYREG_CACHE_CC_CTL )
+    #define CY_FLASH_CONTROL_PTR                (  (reg8 *) CYREG_CACHE_CC_CTL )
+
+#endif  /* (CY_PSOC3) */
+
+
+/* EEPROM Status & Control Register */
+#define CY_FLASH_EE_SCR_REG                     (* (reg8 *) CYREG_SPC_EE_SCR)
+#define CY_FLASH_EE_SCR_PTR                     (  (reg8 *) CYREG_SPC_EE_SCR)
+
+
+
+/***************************************
+*     Register Constants
+***************************************/
+
+/* Power Mode Masks */
+
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
+#if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
+
+
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
+#endif  /* (CY_PSOC3) */
+
+#if (CY_PSOC5)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
+#endif  /* (CY_PSOC5) */
+
+#define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
+#define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
+
+#define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
+#define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
+
+
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
+
+/* Default values for getting temperature. */
+
+#define CY_TEMP_NUMBER_OF_SAMPLES               (0x1u)
+#define CY_TEMP_TIMER_PERIOD                    (0xFFFu)
+#define CY_TEMP_CLK_DIV_SELECT                  (0x4u)
+#define CY_TEMP_NUM_SAMPLES                     (1 << (CY_TEMP_NUMBER_OF_SAMPLES))
+#define CY_SPC_CLK_PERIOD                       (120u)      /* nS */
+#define CY_SYS_ns_PER_TICK                      (1000u)
+#define CY_FRM_EXEC_TIME                        (1000u)     /* nS */
+
+#define CY_GET_TEMP_TIME                        ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \
+                                                    (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \
+                                                    CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)
+
+#define CY_TEMP_MAX_WAIT                        ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK)    /* In system ticks. */
+
+
+/*******************************************************************************
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
+*******************************************************************************/
+#define FLASH_SIZE                  (CY_FLASH_SIZE)
+#define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
+#define FLASH_NUMBER_ROWS           (CY_FLASH_NUMBER_ROWS)
+#define FLASH_NUMBER_SECTORS        (CY_FLASH_NUMBER_ARRAYS)
+#define EEPROM_SIZE                 (CY_EEPROM_SIZE)
+#define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
+#define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
+#define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*******************************************************************************/
+#define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
+
+#define TEMP_NUMBER_OF_SAMPLES      (CY_TEMP_NUMBER_OF_SAMPLES)
+#define TEMP_TIMER_PERIOD           (CY_TEMP_TIMER_PERIOD)
+#define TEMP_CLK_DIV_SELECT         (CY_TEMP_CLK_DIV_SELECT)
+#define NUM_SAMPLES                 (CY_TEMP_NUM_SAMPLES)
+#define SPC_CLK_PERIOD              (CY_SPC_CLK_PERIOD)
+#define FRM_EXEC_TIME               (CY_FRM_EXEC_TIME)
+#define GET_TEMP_TIME               (CY_GET_TEMP_TIME)
+#define TEMP_MAX_WAIT               (CY_TEMP_MAX_WAIT)
+
+#define ECC_ADDR                    (0x80u)
+
+
+#define PM_ACT_EE_PTR           (CY_FLASH_PM_ACT_EEFLASH_PTR)
+#define PM_ACT_FLASH_PTR        (CY_FLASH_PM_ACT_EEFLASH_PTR)
+
+#define PM_STBY_EE_PTR          (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
+#define PM_STBY_FLASH_PTR       (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
+
+#define PM_EE_MASK              (CY_FLASH_PM_EE_MASK)
+#define PM_FLASH_MASK           (CY_FLASH_PM_FLASH_MASK)
+
+#define FLASH_CYCLES_MASK_SHIFT     (CY_FLASH_CYCLES_MASK_SHIFT)
+#define FLASH_CYCLES_MASK           (CY_FLASH_CYCLES_MASK)
+
+
+#if (CY_PSOC3)
+
+    #define LESSER_OR_EQUAL_22MHz   (CY_FLASH_LESSER_OR_EQUAL_22MHz)
+    #define LESSER_OR_EQUAL_44MHz   (CY_FLASH_LESSER_OR_EQUAL_44MHz)
+    #define GREATER_44MHz           (CY_FLASH_GREATER_44MHz)
+
+#endif  /* (CY_PSOC3) */
+
+#if (CY_PSOC5)
+
+    #define LESSER_OR_EQUAL_16MHz   (CY_FLASH_LESSER_OR_EQUAL_16MHz)
+    #define LESSER_OR_EQUAL_33MHz   (CY_FLASH_LESSER_OR_EQUAL_33MHz)
+    #define LESSER_OR_EQUAL_50MHz   (CY_FLASH_LESSER_OR_EQUAL_50MHz)
+    #define LESSER_OR_EQUAL_67MHz   (CY_FLASH_LESSER_OR_EQUAL_67MHz)
+    #define GREATER_67MHz           (CY_FLASH_GREATER_67MHz)
+    #define GREATER_51MHz           (CY_FLASH_GREATER_51MHz)
+
+#endif  /* (CY_PSOC5) */
+
+#define AHUB_EE_REQ_ACK_PTR         (CY_FLASH_EE_SCR_PTR)
+
+
+#endif  /* (CY_BOOT_CYFLASH_H) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c

@@ -1,3105 +1,3105 @@
-/*******************************************************************************
-* File Name: CyLib.c
-* Version 4.20
-*
-*  Description:
-*   Provides a system API for the clocking, interrupts and watchdog timer.
-*
-*  Note:
-*   Documentation of the API's in this file is located in the
-*   System Reference Guide provided with PSoC Creator.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "CyLib.h"
-
-
-/*******************************************************************************
-* The CyResetStatus variable is used to obtain value of RESET_SR0 register after
-* a device reset. It is set from initialize_psoc() at the early initialization
-* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data
-* sections are initialized. To avoid zeroing, CyResetStatus should be placed
-* to the .noinit section.
-*******************************************************************************/
-CY_NOINIT uint8 CYXDATA CyResetStatus;
-
-
-/* Variable Vdda */
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-/* Do not use these definitions directly in your application */
-uint32 cydelay_freq_hz  = BCLK__BUS_CLK__HZ;
-uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u;
-uint8  cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u);
-uint32 cydelay_32k_ms   = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u);
-
-
-/* Function Prototypes */
-static uint8 CyUSB_PowerOnCheck(void)  ;
-static void CyIMO_SetTrimValue(uint8 freq) ;
-static void CyBusClk_Internal_SetDivider(uint16 divider);
-
-#if(CY_PSOC5)
-	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
-    static void CySysTickServiceCallbacks(void);
-    uint32 CySysTickInitVar = 0u;
-#endif  /* (CY_PSOC5) */
-
-
-/*******************************************************************************
-* Function Name: CyPLL_OUT_Start
-********************************************************************************
-*
-* Summary:
-*   Enables the PLL.  Optionally waits for it to become stable.
-*   Waits at least 250 us or until it is detected that the PLL is stable.
-*
-* Parameters:
-*   wait:
-*    0: Return immediately after configuration
-*    1: Wait for PLL lock or timeout.
-*
-* Return:
-*   Status
-*    CYRET_SUCCESS - Completed successfully
-*    CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.
-*     If the input source of the clock is jittery, then the lock indication
-*     may not occur.  However, after the timeout has expired the generated PLL
-*     clock can still be used.
-*
-* Side Effects:
-*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
-*  Any other use of the Fast Time Wheel will be stopped during the period of
-*  this function and then restored. This function also uses the 100 KHz ILO.
-*  If not enabled, this function will enable the 100 KHz ILO for the period of
-*  this function.
-*
-*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
-*  Once Per Second interrupt may be made by interrupt routines during the period
-*  of this function execution. The current operation of the ILO, Central Time
-*  Wheel and Once Per Second interrupt are maintained during the operation of
-*  this function provided the reading of the Power Manager Interrupt Status
-*  Register is only done using the CyPmReadStatus() function.
-*
-*******************************************************************************/
-cystatus CyPLL_OUT_Start(uint8 wait) 
-{
-    cystatus status = CYRET_SUCCESS;
-
-    uint8 iloEnableState;
-    uint8 pmTwCfg0State;
-    uint8 pmTwCfg2State;
-
-
-    /* Enables PLL circuit  */
-    CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
-
-    if(wait != 0u)
-    {
-        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
-        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
-        pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG;
-        pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG;
-
-        CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL);
-
-        status = CYRET_TIMEOUT;
-
-        while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
-        {
-            /* Wait for interrupt status */
-            if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
-            {
-                if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
-                {
-                    status = CYRET_SUCCESS;
-                    break;
-                }
-            }
-        }
-
-        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
-        if(0u == iloEnableState)
-        {
-            CyILO_Stop100K();
-        }
-
-        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State;
-        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyPLL_OUT_Stop
-********************************************************************************
-*
-* Summary:
-*  Disables the PLL.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyPLL_OUT_Stop(void) 
-{
-    CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE));
-}
-
-
-/*******************************************************************************
-* Function Name: CyPLL_OUT_SetPQ
-********************************************************************************
-*
-* Summary:
-*  Sets the P and Q dividers and the charge pump current.
-*  The Frequency Out will be P/Q * Frequency In.
-*  The PLL must be disabled before calling this function.
-*
-* Parameters:
-*  uint8 pDiv:
-*   Valid range [8 - 255].
-*
-*  uint8 qDiv:
-*   Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.
-
-*  uint8 current:
-*   Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and
-*   datasheet for more information.
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution results in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*******************************************************************************/
-void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) 
-{
-    /* Halt CPU in debug mode if PLL is enabled */
-    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
-
-    if((pDiv    >= CY_CLK_PLL_MIN_P_VALUE  ) &&
-       (qDiv    <= CY_CLK_PLL_MAX_Q_VALUE  ) && (qDiv    >= CY_CLK_PLL_MIN_Q_VALUE  ) &&
-       (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE))
-    {
-        /* Set new values */
-        CY_CLK_PLL_P_REG = pDiv;
-        CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u));
-        CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) |
-                                ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION));
-    }
-    else
-    {
-        /***********************************************************************
-        * Halt CPU in debug mode if:
-        * - P divider is less than required
-        * - Q divider is out of range
-        * - pump current is out of range
-        ***********************************************************************/
-        CYASSERT(0u != 0u);
-    }
-
-}
-
-
-/*******************************************************************************
-* Function Name: CyPLL_OUT_SetSource
-********************************************************************************
-*
-* Summary:
-*  Sets the input clock source to the PLL. The PLL must be disabled before
-*  calling this function.
-*
-* Parameters:
-*   source: One of the three available PLL clock sources
-*    CY_PLL_SOURCE_IMO  :   IMO
-*    CY_PLL_SOURCE_XTAL :   MHz Crystal
-*    CY_PLL_SOURCE_DSI  :   DSI
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution results in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*******************************************************************************/
-void CyPLL_OUT_SetSource(uint8 source) 
-{
-    /* Halt CPU in debug mode if PLL is enabled */
-    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
-
-    switch(source)
-    {
-        case CY_PLL_SOURCE_IMO:
-        case CY_PLL_SOURCE_XTAL:
-        case CY_PLL_SOURCE_DSI:
-            CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source);
-        break;
-
-        default:
-            CYASSERT(0u != 0u);
-        break;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_Start
-********************************************************************************
-*
-* Summary:
-*  Enables the IMO. Optionally waits at least 6 us for it to settle.
-*
-* Parameters:
-*  uint8 wait:
-*   0: Return immediately after configuration
-*   1: Wait for at least 6 us for the IMO to settle.
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
-*  Any other use of the Fast Time Wheel will be stopped during the period of
-*  this function and then restored. This function also uses the 100 KHz ILO.
-*  If not enabled, this function will enable the 100 KHz ILO for the period of
-*  this function.
-*
-*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
-*  Once Per Second interrupt may be made by interrupt routines during the period
-*  of this function execution. The current operation of the ILO, Central Time
-*  Wheel and Once Per Second interrupt are maintained during the operation of
-*  this function provided the reading of the Power Manager Interrupt Status
-*  Register is only done using the CyPmReadStatus() function.
-*
-*******************************************************************************/
-void CyIMO_Start(uint8 wait) 
-{
-    uint8 pmFtwCfg2Reg;
-    uint8 pmFtwCfg0Reg;
-    uint8 ilo100KhzEnable;
-
-
-    CY_LIB_PM_ACT_CFG0_REG  |= CY_LIB_PM_ACT_CFG0_IMO_EN;
-    CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN;
-
-    if(0u != wait)
-    {
-        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
-        ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
-        pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
-        pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
-
-        CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT);
-
-        while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
-        {
-            /* Wait for interrupt status */
-        }
-
-        if(0u == ilo100KhzEnable)
-        {
-            CyILO_Stop100K();
-        }
-
-        CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg;
-        CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables the IMO.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyIMO_Stop(void) 
-{
-    CY_LIB_PM_ACT_CFG0_REG  &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN));
-    CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN));
-}
-
-
-/*******************************************************************************
-* Function Name: CyUSB_PowerOnCheck
-********************************************************************************
-*
-* Summary:
-*  Returns the USB power status value. A private function to cy_boot.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   uint8: one if the USB is enabled, 0 if not enabled.
-*
-*******************************************************************************/
-static uint8 CyUSB_PowerOnCheck(void)  
-{
-    uint8 poweredOn = 0u;
-
-    /* Check whether device is in Active or AltActiv and if USB is powered on */
-    if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&
-       (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED     )))  ||
-       (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&
-       (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))
-    {
-        poweredOn = 1u;
-    }
-
-    return (poweredOn);
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_SetTrimValue
-********************************************************************************
-*
-* Summary:
-*  Sets the IMO factory trim values.
-*
-* Parameters:
-*  uint8 freq - frequency for which trims must be set
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-static void CyIMO_SetTrimValue(uint8 freq) 
-{
-    uint8 usbPowerOn = CyUSB_PowerOnCheck();
-
-    /* If USB is powered */
-    if(usbPowerOn == 1u)
-    {
-        /* Unlock USB write */
-        CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN));
-    }
-    switch(freq)
-    {
-    case CY_IMO_FREQ_3MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR);
-        break;
-
-    case CY_IMO_FREQ_6MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR);
-        break;
-
-    case CY_IMO_FREQ_12MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR);
-        break;
-
-    case CY_IMO_FREQ_24MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR);
-        break;
-
-    case CY_IMO_FREQ_48MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR);
-        break;
-
-    case CY_IMO_FREQ_62MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR);
-        break;
-
-#if(CY_PSOC5)
-    case CY_IMO_FREQ_74MHZ:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR);
-        break;
-#endif  /* (CY_PSOC5) */
-
-    case CY_IMO_FREQ_USB:
-        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR);
-
-        /* If USB is powered */
-        if(usbPowerOn == 1u)
-        {
-            /* Lock USB Oscillator */
-            CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
-        }
-        break;
-
-    default:
-            CYASSERT(0u != 0u);
-        break;
-    }
-
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_SetFreq
-********************************************************************************
-*
-* Summary:
-*  Sets the frequency of the IMO. Changes may be made while the IMO is running.
-*
-* Parameters:
-*  freq: Frequency of IMO operation
-*       CY_IMO_FREQ_3MHZ  to set  3   MHz
-*       CY_IMO_FREQ_6MHZ  to set  6   MHz
-*       CY_IMO_FREQ_12MHZ to set 12   MHz
-*       CY_IMO_FREQ_24MHZ to set 24   MHz
-*       CY_IMO_FREQ_48MHZ to set 48   MHz
-*       CY_IMO_FREQ_62MHZ to set 62.6 MHz
-*       CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)
-*       CY_IMO_FREQ_USB   to set 24   MHz (Trimmed for USB operation)
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution results in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*  When the USB setting is chosen, the USB clock locking circuit is enabled.
-*  Otherwise this circuit is disabled. The USB block must be powered before
-*  selecting the USB setting.
-*
-*******************************************************************************/
-void CyIMO_SetFreq(uint8 freq) 
-{
-    uint8 currentFreq;
-    uint8 nextFreq;
-
-    /***************************************************************************
-    * If the IMO frequency is changed,the Trim values must also be set
-    * accordingly.This requires reading the current frequency. If the new
-    * frequency is faster, then set a new trim and then change the frequency,
-    * otherwise change the frequency and then set new trim values.
-    ***************************************************************************/
-
-    currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
-
-    /* Check if requested frequency is USB. */
-    nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
-
-    switch (currentFreq)
-    {
-    case 0u:
-        currentFreq = CY_IMO_FREQ_12MHZ;
-        break;
-
-    case 1u:
-        currentFreq = CY_IMO_FREQ_6MHZ;
-        break;
-
-    case 2u:
-        currentFreq = CY_IMO_FREQ_24MHZ;
-        break;
-
-    case 3u:
-        currentFreq = CY_IMO_FREQ_3MHZ;
-        break;
-
-    case 4u:
-        currentFreq = CY_IMO_FREQ_48MHZ;
-        break;
-
-    case 5u:
-        currentFreq = CY_IMO_FREQ_62MHZ;
-        break;
-
-#if(CY_PSOC5)
-    case 6u:
-        currentFreq = CY_IMO_FREQ_74MHZ;
-        break;
-#endif  /* (CY_PSOC5) */
-
-    default:
-        CYASSERT(0u != 0u);
-        break;
-    }
-
-    if (nextFreq >= currentFreq)
-    {
-        /* Set new trim first */
-        CyIMO_SetTrimValue(freq);
-    }
-
-    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
-    switch(freq)
-    {
-    case CY_IMO_FREQ_3MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-    case CY_IMO_FREQ_6MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-    case CY_IMO_FREQ_12MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-    case CY_IMO_FREQ_24MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-    case CY_IMO_FREQ_48MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-    case CY_IMO_FREQ_62MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-
-#if(CY_PSOC5)
-    case CY_IMO_FREQ_74MHZ:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
-        break;
-#endif  /* (CY_PSOC5) */
-
-    case CY_IMO_FREQ_USB:
-        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
-            CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET;
-        break;
-
-    default:
-        CYASSERT(0u != 0u);
-        break;
-    }
-
-    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
-    if (freq == CY_IMO_FREQ_USB)
-    {
-        CyIMO_EnableDoubler();
-    }
-    else
-    {
-        CyIMO_DisableDoubler();
-    }
-
-    if (nextFreq < currentFreq)
-    {
-        /* Set the trim after setting frequency */
-        CyIMO_SetTrimValue(freq);
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_SetSource
-********************************************************************************
-*
-* Summary:
-*  Sets the source of the clock output from the IMO block.
-*
-*  The output from the IMO is by default the IMO itself. Optionally the MHz
-*  Crystal or DSI input can be the source of the IMO output instead.
-*
-* Parameters:
-*   source: CY_IMO_SOURCE_DSI to set the DSI as source.
-*           CY_IMO_SOURCE_XTAL to set the MHz as source.
-*           CY_IMO_SOURCE_IMO to set the IMO itself.
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution resulted in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*******************************************************************************/
-void CyIMO_SetSource(uint8 source) 
-{
-    switch(source)
-    {
-    case CY_IMO_SOURCE_DSI:
-        CY_LIB_CLKDIST_CR_REG     &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X));
-        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
-        break;
-
-    case CY_IMO_SOURCE_XTAL:
-        CY_LIB_CLKDIST_CR_REG     |= CY_LIB_CLKDIST_CR_IMO2X;
-        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
-        break;
-
-    case CY_IMO_SOURCE_IMO:
-        CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO));
-        break;
-
-    default:
-        /* Incorrect source value */
-        CYASSERT(0u != 0u);
-        break;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_EnableDoubler
-********************************************************************************
-*
-* Summary:
-*  Enables the IMO doubler.  The 2x frequency clock is used to convert a 24 MHz
-*  input to a 48 MHz output for use by the USB block.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyIMO_EnableDoubler(void) 
-{
-    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
-    CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
-}
-
-
-/*******************************************************************************
-* Function Name: CyIMO_DisableDoubler
-********************************************************************************
-*
-* Summary:
-*   Disables the IMO doubler.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyIMO_DisableDoubler(void) 
-{
-    CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER));
-}
-
-
-/*******************************************************************************
-* Function Name: CyMasterClk_SetSource
-********************************************************************************
-*
-* Summary:
-*  Sets the source of the master clock.
-*
-* Parameters:
-*   source: One of the four available Master clock sources.
-*     CY_MASTER_SOURCE_IMO
-*     CY_MASTER_SOURCE_PLL
-*     CY_MASTER_SOURCE_XTAL
-*     CY_MASTER_SOURCE_DSI
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  The current source and the new source must both be running and stable before
-*  calling this function.
-*
-*  If this function execution resulted in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*******************************************************************************/
-void CyMasterClk_SetSource(uint8 source) 
-{
-    CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) |
-                                (source & ((uint8)(~MASTER_CLK_SRC_CLEAR)));
-}
-
-
-/*******************************************************************************
-* Function Name: CyMasterClk_SetDivider
-********************************************************************************
-*
-* Summary:
-*  Sets the divider value used to generate Master Clock.
-*
-* Parameters:
-*  uint8 divider:
-*   The valid range is [0-255]. The clock will be divided by this value + 1.
-*   For example to divide this parameter by two should be set to 1.
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution resulted in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*  When changing the Master or Bus clock divider value from div-by-n to div-by-1
-*  the first clock cycle output after the div-by-1 can be up to 4 ns shorter
-*  than the final/expected div-by-1 period.
-*
-*******************************************************************************/
-void CyMasterClk_SetDivider(uint8 divider) 
-{
-    CY_LIB_CLKDIST_MSTR0_REG = divider;
-}
-
-
-/*******************************************************************************
-* Function Name: CyBusClk_Internal_SetDivider
-********************************************************************************
-*
-* Summary:
-*  The function used by CyBusClk_SetDivider(). For internal use only.
-*
-* Parameters:
-*   divider: Valid range [0-65535].
-*   The clock will be divided by this value + 1.
-*   For example, to divide this parameter by two should be set to 1.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-static void CyBusClk_Internal_SetDivider(uint16 divider)
-{
-    /* Mask bits to enable shadow loads  */
-    CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK;
-    CY_LIB_CLKDIST_DMASK_REG  = CY_LIB_CLKDIST_DMASK_MASK;
-
-    /* Enable mask bits to enable shadow loads */
-    CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
-
-    /* Update Shadow Divider Value Register with new divider */
-    CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
-    CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
-
-
-    /***************************************************************************
-    * Copy shadow value defined in Shadow Divider Value Register
-    * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all
-    * dividers selected in Analog and Digital Clock Mask Registers
-    * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG).
-    ***************************************************************************/
-    CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD;
-}
-
-
-/*******************************************************************************
-* Function Name: CyBusClk_SetDivider
-********************************************************************************
-*
-* Summary:
-*  Sets the divider value used to generate the Bus Clock.
-*
-* Parameters:
-*  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-*  For example, to divide this parameter by two should be set to 1.
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  If this function execution resulted in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-*  See CyFlash_SetWaitCycles() description for more information.
-*
-*******************************************************************************/
-void CyBusClk_SetDivider(uint16 divider) 
-{
-    uint8  masterClkDiv;
-    uint16 busClkDiv;
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    /* Work around to set bus clock divider value */
-    busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
-    busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
-
-    if ((divider == 0u) || (busClkDiv == 0u))
-    {
-        /* Save away master clock divider value */
-        masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
-
-        if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
-        {
-            /* Set master clock divider to 7 */
-            CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV);
-        }
-
-        if (divider == 0u)
-        {
-            /* Set SSS bit and divider register desired value */
-            CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
-            CyBusClk_Internal_SetDivider(divider);
-        }
-        else
-        {
-            CyBusClk_Internal_SetDivider(divider);
-            CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
-        }
-
-        /* Restore master clock */
-        CyMasterClk_SetDivider(masterClkDiv);
-    }
-    else
-    {
-        CyBusClk_Internal_SetDivider(divider);
-    }
-
-    CyExitCriticalSection(interruptState);
-}
-
-
-#if(CY_PSOC3)
-
-    /*******************************************************************************
-    * Function Name: CyCpuClk_SetDivider
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the divider value used to generate the CPU Clock. Only applicable for
-    *  PSoC 3 parts.
-    *
-    * Parameters:
-    *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
-    *  For example, to divide this parameter by two should be set to 1.
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  If this function execution resulted in the CPU clock frequency increasing,
-*  then the number of clock cycles the cache will wait before it samples data
-*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with an appropriate parameter. It can be optionally called if the CPU clock
-*  frequency is lowered in order to improve the CPU performance.
-    *  See CyFlash_SetWaitCycles() description for more information.
-    *
-    *******************************************************************************/
-    void CyCpuClk_SetDivider(uint8 divider) 
-    {
-            CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) |
-                                ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION));
-    }
-
-#endif /* (CY_PSOC3) */
-
-
-/*******************************************************************************
-* Function Name: CyUsbClk_SetSource
-********************************************************************************
-*
-* Summary:
-*  Sets the source of the USB clock.
-*
-* Parameters:
-*  source: One of the four available USB clock sources
-*    CY_LIB_USB_CLK_IMO2X     - IMO 2x
-*    CY_LIB_USB_CLK_IMO       - IMO
-*    CY_LIB_USB_CLK_PLL       - PLL
-*    CY_LIB_USB_CLK_DSI       - DSI
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyUsbClk_SetSource(uint8 source) 
-{
-    CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) |
-                        (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source);
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Start1K
-********************************************************************************
-*
-* Summary:
-*  Enables the ILO 1 KHz oscillator.
-*
-*  Note The ILO 1 KHz oscillator is always enabled by default, regardless of the
-*  selection in the Clock Editor. Therefore, this API is only needed if the
-*  oscillator was turned off manually.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_Start1K(void) 
-{
-    /* Set bit 1 of ILO RS */
-    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Stop1K
-********************************************************************************
-*
-* Summary:
-*  Disables the ILO 1 KHz oscillator.
-*
-*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
-*  mode APIs are expected to be used. For more information, refer to the Power
-*  Management section of this document.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.
-*
-*******************************************************************************/
-void CyILO_Stop1K(void) 
-{
-    /* Clear bit 1 of ILO RS */
-    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Start100K
-********************************************************************************
-*
-* Summary:
-*  Enables the ILO 100 KHz oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_Start100K(void) 
-{
-    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Stop100K
-********************************************************************************
-*
-* Summary:
-*  Disables the ILO 100 KHz oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_Stop100K(void) 
-{
-    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ));
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Enable33K
-********************************************************************************
-*
-* Summary:
-*  Enables the ILO 33 KHz divider.
-*
-*  Note that the 33 KHz clock is generated from the 100 KHz oscillator,
-*  so it must also be running in order to generate the 33 KHz output.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_Enable33K(void) 
-{
-    /* Set bit 5 of ILO RS */
-    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_Disable33K
-********************************************************************************
-*
-* Summary:
-*  Disables the ILO 33 KHz divider.
-*
-*  Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this
-*  API does not disable the 100 KHz clock.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_Disable33K(void) 
-{
-    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ));
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_SetSource
-********************************************************************************
-*
-* Summary:
-*  Sets the source of the clock output from the ILO block.
-*
-* Parameters:
-*  source: One of the three available ILO output sources
-*       Value        Define                Source
-*       0            CY_ILO_SOURCE_100K    ILO 100 KHz
-*       1            CY_ILO_SOURCE_33K     ILO 33 KHz
-*       2            CY_ILO_SOURCE_1K      ILO 1 KHz
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyILO_SetSource(uint8 source) 
-{
-    CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) |
-                    (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR)));
-}
-
-
-/*******************************************************************************
-* Function Name: CyILO_SetPowerMode
-********************************************************************************
-*
-* Summary:
-*  Sets the power mode used by the ILO during power down. Allows for lower power
-*  down power usage resulting in a slower startup time.
-*
-* Parameters:
-*  uint8 mode
-*   CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down
-*   CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down
-*
-* Return:
-*   Prevous power mode state.
-*
-*******************************************************************************/
-uint8 CyILO_SetPowerMode(uint8 mode) 
-{
-    uint8 state;
-
-    /* Get current state. */
-    state = CY_LIB_SLOWCLK_ILO_CR0_REG;
-
-    /* Set the oscillator power mode. */
-    if(mode != CY_ILO_FAST_START)
-    {
-        CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
-    }
-    else
-    {
-        CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
-    }
-
-    /* Return old mode. */
-    return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_32KHZ_Start
-********************************************************************************
-*
-* Summary:
-*  Enables the 32 KHz Crystal Oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_32KHZ_Start(void) 
-{
-    volatile uint16 i;
-
-    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
-    CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_STARTUP;
-    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
-                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
-
-    #if(CY_PSOC3)
-        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
-    #endif  /* (CY_PSOC3) */
-
-    /* Enable operation of 32K Crystal Oscillator */
-    CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
-
-    for (i = 1000u; i > 0u; i--)
-    {
-        if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
-        {
-            /* Ready - switch to high power mode */
-            (void) CyXTAL_32KHZ_SetPowerMode(0u);
-
-            break;
-        }
-        CyDelayUs(1u);
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_32KHZ_Stop
-********************************************************************************
-*
-* Summary:
-*  Disables the 32KHz Crystal Oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_32KHZ_Stop(void) 
-{
-    CY_CLK_XTAL32_TST_REG  = CY_CLK_XTAL32_TST_DEFAULT;
-    CY_CLK_XTAL32_TR_REG   = CY_CLK_XTAL32_TR_POWERDOWN;
-    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
-                             CY_CLK_XTAL32_CFG_LP_DEFAULT;
-    CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM)));
-
-    #if(CY_PSOC3)
-        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN));
-    #endif  /* (CY_PSOC3) */
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_32KHZ_ReadStatus
-********************************************************************************
-*
-* Summary:
-*  Returns status of the 32 KHz oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  Value     Define                    Source
-*  20        CY_XTAL32K_ANA_STAT       Analog measurement
-*                                       1: Stable
-*                                       0: Not stable
-*
-*******************************************************************************/
-uint8 CyXTAL_32KHZ_ReadStatus(void) 
-{
-    return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT);
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_32KHZ_SetPowerMode
-********************************************************************************
-*
-* Summary:
-*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
-*  Allows for lower power during sleep when there are fewer sources of noise.
-*  During the active mode the oscillator is always run in the high power mode.
-*
-* Parameters:
-*  uint8 mode
-*       0: High power mode
-*       1: Low power mode during sleep
-*
-* Return:
-*  Previous power mode.
-*
-*******************************************************************************/
-uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) 
-{
-    uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u;
-
-    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
-
-    if(1u == mode)
-    {
-        /* Low power mode during Sleep */
-        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_LOW_POWER;
-        CyDelayUs(10u);
-        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
-                                CY_CLK_XTAL32_CFG_LP_LOWPOWER;
-        CyDelayUs(20u);
-        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM;
-    }
-    else
-    {
-        /* High power mode */
-        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_HIGH_POWER;
-        CyDelayUs(10u);
-        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
-                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
-        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM));
-    }
-
-    return(state);
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_Start
-********************************************************************************
-*
-* Summary:
-*  Enables the megahertz crystal.
-*
-*  PSoC 3:
-*  Waits until the XERR bit is low (no error) for a millisecond or until the
-*  number of milliseconds specified by the wait parameter has expired.
-*
-* Parameters:
-*   wait: Valid range [0-255].
-*   This is the timeout value in milliseconds.
-*   The appropriate value is crystal specific.
-*
-* Return:
-*   CYRET_SUCCESS - Completed successfully
-*   CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.
-*
-* Side Effects and Restrictions:
-*  If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait.
-*  Any other use of the Fast Timewheel (FTW) will be stopped during the period
-*  of this function and then restored.
-*
-*  Uses the 100KHz ILO.  If not enabled, this function will enable the 100KHz
-*  ILO for the period of this function. No changes to the setup of the ILO,
-*  Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made
-*  by interrupt routines during the period of this function.
-*
-*  The current operation of the ILO, Central Timewheel and Once Per Second
-*  interrupt are maintained during the operation of this function provided the
-*  reading of the Power Manager Interrupt Status Register is only done using the
-*  CyPmReadStatus() function.
-*
-*******************************************************************************/
-cystatus CyXTAL_Start(uint8 wait) 
-{
-    cystatus status = CYRET_SUCCESS;
-    volatile uint8  timeout = wait;
-    volatile uint8 count;
-    uint8 iloEnableState;
-    uint8 pmTwCfg0Tmp;
-    uint8 pmTwCfg2Tmp;
-
-
-    /* Enables MHz crystal oscillator circuit  */
-    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
-
-
-    if(wait > 0u)
-    {
-        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
-        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG;
-        pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG;
-        pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG;
-
-        /* Set 250 us interval */
-        CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL);
-        status = CYRET_TIMEOUT;
-
-
-        for( ; timeout > 0u; timeout--)
-        {
-            /* Read XERR bit to clear it */
-            (void) CY_CLK_XMHZ_CSR_REG;
-
-            /* Wait for 1 millisecond - 4 x 250 us */
-            for(count = 4u; count > 0u; count--)
-            {
-                while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
-                {
-                    /* Wait for FTW interrupt event */
-                }
-            }
-
-
-            /*******************************************************************
-            * High output indicates an oscillator failure.
-            * Only can be used after a start-up interval (1 ms) is completed.
-            *******************************************************************/
-            if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
-            {
-                status = CYRET_SUCCESS;
-                break;
-            }
-        }
-
-
-        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
-        if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ))
-        {
-            CyILO_Stop100K();
-        }
-        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp;
-        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_Stop
-********************************************************************************
-*
-* Summary:
-*  Disables the megahertz crystal oscillator.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_Stop(void) 
-{
-    /* Disable oscillator. */
-    FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_EnableErrStatus
-********************************************************************************
-*
-* Summary:
-*  Enables the generation of the XERR status bit for the megahertz crystal.
-*  This function is not available for PSoC5.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_EnableErrStatus(void) 
-{
-    /* If oscillator has insufficient amplitude, XERR bit will be high. */
-    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_DisableErrStatus
-********************************************************************************
-*
-* Summary:
-*  Disables the generation of the XERR status bit for the megahertz crystal.
-*  This function is not available for PSoC5.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_DisableErrStatus(void) 
-{
-    /* If oscillator has insufficient amplitude, XERR bit will be high. */
-    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_ReadStatus
-********************************************************************************
-*
-* Summary:
-*  Reads the XERR status bit for the megahertz crystal. This status bit is a
-*  sticky, clear on read. This function is not available for PSoC5.
-*
-* Parameters:
-*  None
-*
-* Return:
-*   Status
-*    0: No error
-*    1: Error
-*
-*******************************************************************************/
-uint8 CyXTAL_ReadStatus(void) 
-{
-    /***************************************************************************
-    * High output indicates an oscillator failure. Only use this after a start-up
-    * interval is completed. This can be used for the status and failure recovery.
-    ***************************************************************************/
-    return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_EnableFaultRecovery
-********************************************************************************
-*
-* Summary:
-*  Enables the fault recovery circuit which will switch to the IMO in the case
-*  of a fault in the megahertz crystal circuit. The crystal must be up and
-*  running with the XERR bit at 0, before calling this function to prevent
-*  an immediate fault switchover. This function is not available for PSoC5.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_EnableFaultRecovery(void) 
-{
-    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_DisableFaultRecovery
-********************************************************************************
-*
-* Summary:
-*  Disables the fault recovery circuit which will switch to the IMO in the case
-*  of a fault in the megahertz crystal circuit. This function is not available
-*  for PSoC5.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_DisableFaultRecovery(void) 
-{
-    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_SetStartup
-********************************************************************************
-*
-* Summary:
-*  Sets the startup settings for the crystal. The logic model outputs a frequency
-*  (setting + 4) MHz when enabled.
-*
-*  This is artificial as the actual frequency is determined by an attached
-*  external crystal.
-*
-* Parameters:
-*  setting: Valid range [0-31].
-*   The value is dependent on the frequency and quality of the crystal being used.
-*   Refer to the device TRM and datasheet for more information.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_SetStartup(uint8 setting) 
-{
-    CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) |
-                           (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK);
-}
-
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_SetFbVoltage
-********************************************************************************
-*
-* Summary:
-*  Sets the feedback reference voltage to use for the crystal circuit.
-*  This function is only available for PSoC3 and PSoC 5LP.
-*
-* Parameters:
-*  setting: Valid range [0-15].
-*  Refer to the device TRM and datasheet for more information.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_SetFbVoltage(uint8 setting) 
-{
-    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |
-                            (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));
-}
-
-
-/*******************************************************************************
-* Function Name: CyXTAL_SetWdVoltage
-********************************************************************************
-*
-* Summary:
-*  Sets the reference voltage used by the watchdog to detect a failure in the
-*  crystal circuit. This function is only available for PSoC3 and PSoC 5LP.
-*
-* Parameters:
-*  setting: Valid range [0-7].
-*  Refer to the device TRM and datasheet for more information.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyXTAL_SetWdVoltage(uint8 setting) 
-{
-    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |
-                            (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));
-}
-
-
-/*******************************************************************************
-* Function Name: CyHalt
-********************************************************************************
-*
-* Summary:
-*  Halts the CPU.
-*
-* Parameters:
-*  uint8 reason: Value to be used during debugging.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyHalt(uint8 reason) CYREENTRANT
-{
-    if(0u != reason)
-    {
-        /* To remove unreferenced local variable warning */
-    }
-
-    #if defined (__ARMCC_VERSION)
-        __breakpoint(0x0);
-    #elif defined(__GNUC__) || defined (__ICCARM__)
-        __asm("    bkpt    1");
-    #elif defined(__C51__)
-        CYDEV_HALT_CPU;
-    #endif  /* (__ARMCC_VERSION) */
-}
-
-
-/*******************************************************************************
-* Function Name: CySoftwareReset
-********************************************************************************
-*
-* Summary:
-*  Forces a device software reset.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CySoftwareReset(void) 
-{
-    CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET;
-}
-
-
-/*******************************************************************************
-* Function Name: CyDelay
-********************************************************************************
-*
-* Summary:
-*  Blocks for milliseconds.
-*
-*  Note:
-*  CyDelay has been implemented with the instruction cache assumed enabled. When
-*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
-*  For example, with instruction cache disabled CyDelay(100) would result in
-*  about 200 ms delay instead of 100 ms.
-*
-* Parameters:
-*  milliseconds: number of milliseconds to delay.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void CyDelay(uint32 milliseconds) CYREENTRANT
-{
-    while (milliseconds > 32768u)
-    {
-        /***********************************************************************
-        * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz
-        * overflows at about 42 seconds.
-        ***********************************************************************/
-        CyDelayCycles(cydelay_32k_ms);
-        milliseconds = ((uint32)(milliseconds - 32768u));
-    }
-
-    CyDelayCycles(milliseconds * cydelay_freq_khz);
-}
-
-
-#if(!CY_PSOC3)
-
-    /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */
-
-    /*******************************************************************************
-    * Function Name: CyDelayUs
-    ********************************************************************************
-    *
-    * Summary:
-    *  Blocks for microseconds.
-    *
-    *  Note:
-    *   CyDelay has been implemented with the instruction cache assumed enabled.
-    *   When instruction cache is disabled on PSoC5, CyDelayUs will be two times
-    *   larger. Ex: With instruction cache disabled CyDelayUs(100) would result
-    *   in about 200us delay instead of 100us.
-    *
-    * Parameters:
-    *  uint16 microseconds: number of microseconds to delay.
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  CyDelayUS has been implemented with the instruction cache assumed enabled.
-    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
-    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
-    *  result in about 200 us delay instead of 100 us.
-    *
-    *  If the bus clock frequency is a small non-integer number, the actual delay
-    *  can be up to twice as long as the nominal value. The actual delay cannot be
-    *  shorter than the nominal one.
-    *******************************************************************************/
-    void CyDelayUs(uint16 microseconds) CYREENTRANT
-    {
-        CyDelayCycles((uint32)microseconds * cydelay_freq_mhz);
-    }
-
-#endif  /* (!CY_PSOC3) */
-
-
-/*******************************************************************************
-* Function Name: CyDelayFreq
-********************************************************************************
-*
-* Summary:
-*  Sets the clock frequency for CyDelay.
-*
-* Parameters:
-*  freq: The frequency of the bus clock in Hertz.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyDelayFreq(uint32 freq) CYREENTRANT
-{
-    if (freq != 0u)
-    {
-        cydelay_freq_hz = freq;
-    }
-    else
-    {
-        cydelay_freq_hz = BCLK__BUS_CLK__HZ;
-    }
-
-    cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u);
-    cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u;
-    cydelay_32k_ms   = 32768u * cydelay_freq_khz;
-}
-
-
-/*******************************************************************************
-* Function Name: CyWdtStart
-********************************************************************************
-*
-* Summary:
-*  Enables the watchdog timer.
-*
-*  The timer is configured for the specified count interval, the central
-*  timewheel is cleared, the setting for the low power mode is configured and the
-*  watchdog timer is enabled.
-*
-*  Once enabled the watchdog cannot be disabled. The watchdog counts each time
-*  the Central Time Wheel (CTW) reaches the period specified. The watchdog must
-*  be cleared using the CyWdtClear() function before three ticks of the watchdog
-*  timer occur. The CTW is free running, so this will occur after between 2 and
-*  3 timer periods elapse.
-*
-*  PSoC5: The watchdog timer should not be used during sleep modes. Since the
-*  WDT cannot be disabled after it is enabled, the WDT timeout period can be
-*  set to be greater than the sleep wakeup period, then feed the dog on each
-*  wakeup from Sleep.
-*
-* Parameters:
-*  ticks: One of the four available timer periods. Once WDT enabled, the
-   interval cannot be changed.
-*         CYWDT_2_TICKS     -     4 - 6     ms
-*         CYWDT_16_TICKS    -    32 - 48    ms
-*         CYWDT_128_TICKS   -   256 - 384   ms
-*         CYWDT_1024_TICKS  - 2.048 - 3.072 s
-*
-*  lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.
-*          The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.
-*
-*          CYWDT_LPMODE_NOCHANGE - No Change
-*          CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power
-*                                 mode
-*          CYWDT_LPMODE_DISABLED - Disable WDT during low power mode
-*
-* Return:
-*  None
-*
-* Side Effects:
-*  PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the
-*  ILO 1 kHz could break the active WDT functionality.
-*
-*******************************************************************************/
-void CyWdtStart(uint8 ticks, uint8 lpMode) 
-{
-    /* Set WDT interval */
-    CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK);
-
-    /* Reset CTW to ensure that first watchdog period is full */
-    CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
-    CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
-
-    /* Setting low power mode */
-    CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
-                       (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
-
-    /* Enables watchdog reset */
-    CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
-}
-
-
-/*******************************************************************************
-* Function Name: CyWdtClear
-********************************************************************************
-*
-* Summary:
-*  Clears (feeds) the watchdog timer.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyWdtClear(void) 
-{
-    CY_WDT_CR_REG = CY_WDT_CR_FEED;
-}
-
-
-
-/*******************************************************************************
-* Function Name: CyVdLvDigitEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the digital low voltage monitors to generate interrupt on Vddd
-*   archives specified threshold and optionally resets the device.
-*
-* Parameters:
-*  reset: The option to reset the device at a specified Vddd threshold:
-*           0 - Device is not reset.
-*           1 - Device is reset.
-*
-*  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
-*  250 mV.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdLvDigitEnable(uint8 reset, uint8 threshold) 
-{
-    *CY_INT_CLEAR_PTR = 0x01u;
-
-    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
-
-    CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) |
-                            (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
-    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
-
-    /* Timeout to eliminate glitches on LVI/HVI when enabling */
-    CyDelayUs(1u);
-
-    (void)CY_VD_PERSISTENT_STATUS_REG;
-
-    if(0u != reset)
-    {
-        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;
-    }
-    else
-    {
-        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
-    }
-
-    *CY_INT_CLR_PEND_PTR = 0x01u;
-    *CY_INT_ENABLE_PTR   = 0x01u;
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdLvAnalogEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the analog low voltage monitors to generate interrupt on Vdda
-*   archives specified threshold and optionally resets the device.
-*
-* Parameters:
-*  reset: The option to reset the device at a specified Vdda threshold:
-*           0 - Device is not reset.
-*           1 - Device is reset.
-*
-*  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-*  interval.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) 
-{
-    *CY_INT_CLEAR_PTR = 0x01u;
-
-    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
-
-    CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
-    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
-
-    /* Timeout to eliminate glitches on LVI/HVI when enabling */
-    CyDelayUs(1u);
-
-    (void)CY_VD_PERSISTENT_STATUS_REG;
-
-    if(0u != reset)
-    {
-        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;
-    }
-    else
-    {
-        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
-    }
-
-    *CY_INT_CLR_PEND_PTR = 0x01u;
-    *CY_INT_ENABLE_PTR   = 0x01u;
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdLvDigitDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the digital low voltage monitor (interrupt and device reset are
-*  disabled).
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdLvDigitDisable(void) 
-{
-    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));
-
-    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
-
-    while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))
-    {
-
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdLvAnalogDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the analog low voltage monitor (interrupt and device reset are
-*  disabled).
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdLvAnalogDisable(void) 
-{
-    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));
-
-    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
-
-    while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))
-    {
-
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdHvAnalogEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the analog high voltage monitors to generate interrupt on
-*  Vdda archives 5.75 V threshold and optionally resets device.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdHvAnalogEnable(void) 
-{
-    *CY_INT_CLEAR_PTR = 0x01u;
-
-    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
-
-    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;
-
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
-    CyDelayUs(1u);
-
-    (void) CY_VD_PERSISTENT_STATUS_REG;
-
-    *CY_INT_CLR_PEND_PTR = 0x01u;
-    *CY_INT_ENABLE_PTR   = 0x01u;
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdHvAnalogDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the analog low voltage monitor
-*  (interrupt and device reset are disabled).
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyVdHvAnalogDisable(void) 
-{
-    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdStickyStatus
-********************************************************************************
-*
-* Summary:
-*  Manages the Reset and Voltage Detection Status Register 0.
-*  This register has the interrupt status for the HVIA, LVID and LVIA.
-*  This hardware register clears on read.
-*
-* Parameters:
-*  mask: Bits in the shadow register to clear.
-*   Define                  Definition
-*   CY_VD_LVID            Persistent status of digital LVI.
-*   CY_VD_LVIA            Persistent status of analog LVI.
-*   CY_VD_HVIA            Persistent status of analog HVI.
-*
-* Return:
-*  Status.  Same enumerated bit values as used for the mask parameter.
-*
-*******************************************************************************/
-uint8 CyVdStickyStatus(uint8 mask) 
-{
-    uint8 status;
-
-    status = CY_VD_PERSISTENT_STATUS_REG;
-    CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask));
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CyVdRealTimeStatus
-********************************************************************************
-*
-* Summary:
-*  Returns the real time voltage detection status.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  Status:
-*   Define                  Definition
-*   CY_VD_LVID            Persistent status of digital LVI.
-*   CY_VD_LVIA            Persistent status of analog LVI.
-*   CY_VD_HVIA            Persistent status of analog HVI.
-*
-*******************************************************************************/
-uint8 CyVdRealTimeStatus(void) 
-{
-    uint8 interruptState;
-    uint8 vdFlagsState;
-
-    interruptState = CyEnterCriticalSection();
-    vdFlagsState = CY_VD_RT_STATUS_REG;
-    CyExitCriticalSection(interruptState);
-
-    return(vdFlagsState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyDisableInts
-********************************************************************************
-*
-* Summary:
-*  Disables the interrupt enable for each interrupt.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  32 bit mask of previously enabled interrupts.
-*
-*******************************************************************************/
-uint32 CyDisableInts(void) 
-{
-    uint32 intState;
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    #if(CY_PSOC3)
-
-        /* Get the current interrupt state. */
-        intState  = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR));
-        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u));
-        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u));
-        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u));
-
-
-        /* Disable all of the interrupts. */
-        CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu);
-        CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu);
-        CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu);
-        CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu);
-
-    #else
-
-        /* Get the current interrupt state. */
-        intState = CY_GET_REG32(CY_INT_CLEAR_PTR);
-
-        /* Disable all of the interrupts. */
-        CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu);
-
-    #endif /* (CY_PSOC3) */
-
-    CyExitCriticalSection(interruptState);
-
-    return (intState);
-}
-
-
-/*******************************************************************************
-* Function Name: CyEnableInts
-********************************************************************************
-*
-* Summary:
-*  Enables interrupts to a given state.
-*
-* Parameters:
-*  uint32 mask: 32 bit mask of interrupts to enable.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CyEnableInts(uint32 mask) 
-{
-
-    uint8 interruptState;
-
-    interruptState = CyEnterCriticalSection();
-
-    #if(CY_PSOC3)
-
-        /* Set interrupts as enabled. */
-        CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u)));
-        CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u)));
-        CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u )));
-        CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask )));
-
-    #else
-
-        CY_SET_REG32(CY_INT_ENABLE_PTR, mask);
-
-    #endif /* (CY_PSOC3) */
-
-    CyExitCriticalSection(interruptState);
-
-}
-
-#if(CY_PSOC5)
-
-    /*******************************************************************************
-    * Function Name: CyFlushCache
-    ********************************************************************************
-    * Summary:
-    *  Flushes the PSoC 5/5LP cache by invalidating all entries.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CyFlushCache(void)
-    {
-        uint8 interruptState;
-
-        /* Save current global interrupt enable and disable it */
-        interruptState = CyEnterCriticalSection();
-
-        /* Fill instruction prefectch unit to insure data integrity */
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-
-        /* All entries in cache are invalidated on next clock cycle. */
-        CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
-
-        /* Once this is executed it's guaranteed the cache has been flushed */
-        (void) CY_CACHE_CONTROL_REG;
-
-        /* Flush the pipeline */
-        CY_SYS_ISB;
-
-        /* Restore global interrupt enable state */
-        CyExitCriticalSection(interruptState);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntSetSysVector
-    ********************************************************************************
-    * Summary:
-    *  Sets the interrupt vector of the specified system interrupt number. System
-    *  interrupts are present only for the ARM platform. These interrupts are for
-    *  SysTick, PendSV and others.
-    *
-    * Parameters:
-    *  number: System interrupt number:
-    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
-    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
-    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
-    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
-    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
-    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
-    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
-    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
-    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
-    *
-    *  address: Pointer to an interrupt service routine.
-    *
-    * Return:
-    *   The old ISR vector at this location.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)
-    {
-        cyisraddress oldIsr;
-        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
-
-        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
-
-        /* Save old Interrupt service routine. */
-        oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
-
-        /* Set new Interrupt service routine. */
-        ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address;
-
-        return (oldIsr);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetSysVector
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets the interrupt vector of the specified system interrupt number. System
-    *  interrupts are present only for the ARM platform. These interrupts are for
-    *  SysTick, PendSV and others.
-    *
-    * Parameters:
-    *  number: System interrupt number:
-    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
-    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
-    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
-    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
-    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
-    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
-    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
-    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
-    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
-    *
-    * Return:
-    *   Address of the ISR in the interrupt vector table.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntGetSysVector(uint8 number)
-    {
-        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
-        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
-
-        return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntSetVector
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the interrupt vector of the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number
-    *  address: Pointer to an interrupt service routine
-    *
-    * Return:
-    *   Previous interrupt vector value.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntSetVector(uint8 number, cyisraddress address)
-    {
-        cyisraddress oldIsr;
-        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        /* Save old Interrupt service routine. */
-        oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)];
-
-        /* Set new Interrupt service routine. */
-        ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address;
-
-        return (oldIsr);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetVector
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets the interrupt vector of the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number
-    *
-    * Return:
-    *  The address of the ISR in the interrupt vector table.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntGetVector(uint8 number)
-    {
-        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntSetPriority
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the Priority of the Interrupt.
-    *
-    * Parameters:
-    *  priority: Priority of the interrupt. 0 - 7, 0 being the highest.
-    *  number: The number of the interrupt, 0 - 31.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CyIntSetPriority(uint8 number, uint8 priority)
-    {
-        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetPriority
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets the Priority of the Interrupt.
-    *
-    * Parameters:
-    *  number: The number of the interrupt, 0 - 31.
-    *
-    * Return:
-    *  Priority of the interrupt. 0 - 7, 0 being the highest.
-    *
-    *******************************************************************************/
-    uint8 CyIntGetPriority(uint8 number)
-    {
-        uint8 priority;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
-
-        return (priority);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetState
-    ********************************************************************************
-    *
-    * Summary:
-    *   Gets the enable state of the specified interrupt number.
-    *
-    * Parameters:
-    *   number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *   Enable status: 1 if enabled, 0 if disabled
-    *
-    *******************************************************************************/
-    uint8 CyIntGetState(uint8 number)
-    {
-        reg32 * stateReg;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        /* Get pointer to Interrupt enable register. */
-        stateReg = CY_INT_ENABLE_PTR;
-
-        /* Get state of interrupt. */
-        return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
-    }
-
-
-#else   /* PSoC3 */
-
-
-    /*******************************************************************************
-    * Function Name: CyIntSetVector
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the interrupt vector of the specified interrupt number.
-    *
-    * Parameters:
-    *  number:  Valid range [0-31].  Interrupt number
-    *  address: Pointer to an interrupt service routine
-    *
-    * Return:
-    *  Previous interrupt vector value.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntSetVector(uint8 number, cyisraddress address) 
-    {
-        cyisraddress oldIsr;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        /* Save old Interrupt service routine. */
-        oldIsr = (cyisraddress) \
-                    CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]);
-
-        /* Set new Interrupt service routine. */
-        CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address);
-
-        return (oldIsr);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetVector
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets the interrupt vector of the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number
-    *
-    * Return:
-    *  Address of the ISR in the interrupt vector table.
-    *
-    *******************************************************************************/
-    cyisraddress CyIntGetVector(uint8 number) 
-    {
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        return ((cyisraddress) \
-                CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]));
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntSetPriority
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the Priority of the Interrupt.
-    *
-    * Parameters:
-    *  priority: Priority of the interrupt. 0 - 7, 0 being the highest.
-    *  number:   The number of the interrupt, 0 - 31.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CyIntSetPriority(uint8 number, uint8 priority) 
-    {
-        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] =
-                    (priority & CY_INT_PRIORITY_MASK) << 5;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetPriority
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets the Priority of the Interrupt.
-    *
-    * Parameters:
-    *  number: The number of the interrupt, 0 - 31.
-    *
-    * Return:
-    *  Priority of the interrupt. 0 - 7, 0 being the highest.
-    *
-    *******************************************************************************/
-    uint8 CyIntGetPriority(uint8 number) 
-    {
-        uint8 priority;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
-
-        return (priority);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CyIntGetState
-    ********************************************************************************
-    *
-    * Summary:
-    *   Gets the enable state of the specified interrupt number.
-    *
-    * Parameters:
-    *   number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *   Enable status: 1 if enabled, 0 if disabled
-    *
-    *******************************************************************************/
-    uint8 CyIntGetState(uint8 number) 
-    {
-        reg8 * stateReg;
-
-        CYASSERT(number <= CY_INT_NUMBER_MAX);
-
-        /* Get pointer to Interrupt enable register. */
-        stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
-
-        /* Get state of interrupt. */
-        return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
-    }
-
-
-#endif  /* (CY_PSOC5) */
-
-
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    /*******************************************************************************
-    * Function Name: CySetScPumps
-    ********************************************************************************
-    *
-    * Summary:
-    *  If 1 is passed as a parameter:
-    *   - if any of the SC blocks are used - enable pumps for the SC blocks and
-    *     start boost clock.
-    *   - For each enabled SC block set a boost clock index and enable the boost
-    *     clock.
-    *
-    *  If non-1 value is passed as a parameter:
-    *   - If all SC blocks are not used - disable pumps for the SC blocks and
-    *     stop the boost clock.
-    *   - For each enabled SC block clear the boost clock index and disable the  boost
-    *     clock.
-    *
-    *  The global variable CyScPumpEnabled is updated to be equal to passed the
-    *  parameter.
-    *
-    * Parameters:
-    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
-    *                 1 - Enable
-    *                 0 - Disable
-    *
-    * Return:
-    *   None
-    *
-    *******************************************************************************/
-    void CySetScPumps(uint8 enable) 
-    {
-        if(1u == enable)
-        {
-            /* The SC pumps should be enabled */
-            CyScPumpEnabled = 1u;
-            /* Enable pumps if any of SC blocks are used */
-            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))
-            {
-                CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;
-                CyScBoostClk_Start();
-            }
-            /* Set positive pump for each enabled SC block: set clock index and enable it */
-            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))
-            {
-                CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
-                CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;
-            }
-            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))
-            {
-                CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
-                CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;
-            }
-            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))
-            {
-                CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
-                CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;
-            }
-            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))
-            {
-                CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
-                CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;
-            }
-        }
-        else
-        {
-            /* The SC pumps should be disabled */
-            CyScPumpEnabled = 0u;
-            /* Disable pumps for all SC blocks and stop boost clock */
-            CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));
-            CyScBoostClk_Stop();
-            /* Disable boost clock and clear clock index for each SC block */
-            CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
-            CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
-            CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
-            CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
-            CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
-            CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
-            CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
-            CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
-        }
-    }
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-#if(CY_PSOC5)
-    /*******************************************************************************
-    * Function Name: CySysTickStart
-    ********************************************************************************
-    *
-    * Summary:
-    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
-    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
-    *  Refer to the corresponding function description for the details.
-
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set
-    *
-    *******************************************************************************/
-    void CySysTickStart(void)
-    {
-        if (0u == CySysTickInitVar)
-        {
-            CySysTickInit();
-            CySysTickInitVar = 1u;
-        }
-
-        CySysTickEnable();
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickInit
-    ********************************************************************************
-    *
-    * Summary:
-    *  Initializes the callback addresses with pointers to NULL, associates the
-    *  SysTick system vector with the function that is responsible for calling
-    *  registered callback functions, configures SysTick timer to generate interrupt
-    * every 1 ms.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set.
-    *
-    *  The 1 ms interrupt interval is configured based on the frequency determined
-    *  by PSoC Creator at build time. If System clock frequency is changed in
-    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
-    *
-    *******************************************************************************/
-    void CySysTickInit(void)
-    {
-        uint32 i;
-
-        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
-        {
-            CySysTickCallbacks[i] = (void *) 0;
-        }
-
-    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
-        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
-        CySysTickSetReload(cydelay_freq_hz/1000u);
-        CySysTickClear();
-        CyIntEnable(CY_INT_SYSTICK_IRQN);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickEnable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enables the SysTick timer and its interrupt.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set
-    *
-    *******************************************************************************/
-    void CySysTickEnable(void)
-    {
-        CySysTickEnableInterrupt();
-        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickStop
-    ********************************************************************************
-    *
-    * Summary:
-    *  Stops the system timer (SysTick).
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set
-    *
-    *******************************************************************************/
-    void CySysTickStop(void)
-    {
-        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickEnableInterrupt
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enables the SysTick interrupt.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set
-    *
-    *******************************************************************************/
-    void CySysTickEnableInterrupt(void)
-    {
-        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickDisableInterrupt
-    ********************************************************************************
-    *
-    * Summary:
-    *  Disables the SysTick interrupt.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set
-    *
-    *******************************************************************************/
-    void CySysTickDisableInterrupt(void)
-    {
-        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickSetReload
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets value the counter is set to on startup and after it reaches zero. This
-    *  function do not change or reset current sysTick counter value, so it should
-    *  be cleared using CySysTickClear() API.
-    *
-    * Parameters:
-    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CySysTickSetReload(uint32 value)
-    {
-        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickGetReload
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets value the counter is set to on startup and after it reaches zero.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  Counter reset value
-    *
-    *******************************************************************************/
-    uint32 CySysTickGetReload(void)
-    {
-        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickGetValue
-    ********************************************************************************
-    *
-    * Summary:
-    *  Gets current SysTick counter value.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  Current SysTick counter value
-    *
-    *******************************************************************************/
-    uint32 CySysTickGetValue(void)
-    {
-        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickSetClockSource
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sets the clock source for the SysTick counter.
-    *
-    * Parameters:
-    *  clockSource: Clock source for SysTick counter
-    *         Define                     Clock Source
-    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
-    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
-    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
-    *
-    * Return:
-    *  None
-    *
-    * Side Effects:
-    *  Clears SysTick count flag if it was set. If clock source is not ready this
-    *  function call will have no effect. After changing clock source to the low frequency
-    *  clock the counter and reload register values will remain unchanged so time to
-    *  the interrupt will be significantly bigger and vice versa.
-    *
-    *******************************************************************************/
-    void CySysTickSetClockSource(uint32 clockSource)
-    {
-        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
-        {
-            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
-        }
-        else
-        {
-            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
-        }
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickGetCountFlag
-    ********************************************************************************
-    *
-    * Summary:
-    *  The count flag is set once SysTick counter reaches zero.
-    *   The flag cleared on read.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  Returns non-zero value if counter is set, otherwise zero is returned.
-    *
-    *******************************************************************************/
-    uint32 CySysTickGetCountFlag(void)
-    {
-        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickClear
-    ********************************************************************************
-    *
-    * Summary:
-    *  Clears the SysTick counter for well-defined startup.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CySysTickClear(void)
-    {
-        CY_SYS_SYST_CVR_REG = 0u;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickSetCallback
-    ********************************************************************************
-    *
-    * Summary:
-    *  The function set the pointers to the functions that will be called on
-    *  SysTick interrupt.
-    *
-    * Parameters:
-    *  number:  The number of callback function address to be set.
-    *           The valid range is from 0 to 4.
-    *  CallbackFunction: Function address.
-    *
-    * Return:
-    *  Returns the address of the previous callback function.
-    *  The NULL is returned if the specified address in not set.
-    *
-    *******************************************************************************/
-    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
-    {
-        cySysTickCallback retVal;
-
-        retVal = CySysTickCallbacks[number];
-        CySysTickCallbacks[number] = function;
-        return (retVal);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickGetCallback
-    ********************************************************************************
-    *
-    * Summary:
-    *  The function get the specified callback pointer.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    cySysTickCallback CySysTickGetCallback(uint32 number)
-    {
-        return ((cySysTickCallback) CySysTickCallbacks[number]);
-    }
-
-
-    /*******************************************************************************
-    * Function Name: CySysTickServiceCallbacks
-    ********************************************************************************
-    *
-    * Summary:
-    *  System Tick timer interrupt routine
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    static void CySysTickServiceCallbacks(void)
-    {
-        uint32 i;
-
-        /* Verify that tick timer flag was set */
-        if (1u == CySysTickGetCountFlag())
-        {
-            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
-            {
-                if (CySysTickCallbacks[i] != (void *) 0)
-                {
-                    (void)(CySysTickCallbacks[i])();
-                }
-            }
-        }
-    }
-#endif /* (CY_PSOC5) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyLib.c
+* Version 4.20
+*
+*  Description:
+*   Provides a system API for the clocking, interrupts and watchdog timer.
+*
+*  Note:
+*   Documentation of the API's in this file is located in the
+*   System Reference Guide provided with PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CyLib.h"
+
+
+/*******************************************************************************
+* The CyResetStatus variable is used to obtain value of RESET_SR0 register after
+* a device reset. It is set from initialize_psoc() at the early initialization
+* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data
+* sections are initialized. To avoid zeroing, CyResetStatus should be placed
+* to the .noinit section.
+*******************************************************************************/
+CY_NOINIT uint8 CYXDATA CyResetStatus;
+
+
+/* Variable Vdda */
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Do not use these definitions directly in your application */
+uint32 cydelay_freq_hz  = BCLK__BUS_CLK__HZ;
+uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u;
+uint8  cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u);
+uint32 cydelay_32k_ms   = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u);
+
+
+/* Function Prototypes */
+static uint8 CyUSB_PowerOnCheck(void)  ;
+static void CyIMO_SetTrimValue(uint8 freq) ;
+static void CyBusClk_Internal_SetDivider(uint16 divider);
+
+#if(CY_PSOC5)
+	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_Start
+********************************************************************************
+*
+* Summary:
+*   Enables the PLL.  Optionally waits for it to become stable.
+*   Waits at least 250 us or until it is detected that the PLL is stable.
+*
+* Parameters:
+*   wait:
+*    0: Return immediately after configuration
+*    1: Wait for PLL lock or timeout.
+*
+* Return:
+*   Status
+*    CYRET_SUCCESS - Completed successfully
+*    CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.
+*     If the input source of the clock is jittery, then the lock indication
+*     may not occur.  However, after the timeout has expired the generated PLL
+*     clock can still be used.
+*
+* Side Effects:
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
+*  Any other use of the Fast Time Wheel will be stopped during the period of
+*  this function and then restored. This function also uses the 100 KHz ILO.
+*  If not enabled, this function will enable the 100 KHz ILO for the period of
+*  this function.
+*
+*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
+*  Once Per Second interrupt may be made by interrupt routines during the period
+*  of this function execution. The current operation of the ILO, Central Time
+*  Wheel and Once Per Second interrupt are maintained during the operation of
+*  this function provided the reading of the Power Manager Interrupt Status
+*  Register is only done using the CyPmReadStatus() function.
+*
+*******************************************************************************/
+cystatus CyPLL_OUT_Start(uint8 wait) 
+{
+    cystatus status = CYRET_SUCCESS;
+
+    uint8 iloEnableState;
+    uint8 pmTwCfg0State;
+    uint8 pmTwCfg2State;
+
+
+    /* Enables PLL circuit  */
+    CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
+
+    if(wait != 0u)
+    {
+        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
+        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+        pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG;
+        pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG;
+
+        CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL);
+
+        status = CYRET_TIMEOUT;
+
+        while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+        {
+            /* Wait for interrupt status */
+            if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
+            {
+                if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
+                {
+                    status = CYRET_SUCCESS;
+                    break;
+                }
+            }
+        }
+
+        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
+        if(0u == iloEnableState)
+        {
+            CyILO_Stop100K();
+        }
+
+        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State;
+        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_Stop
+********************************************************************************
+*
+* Summary:
+*  Disables the PLL.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyPLL_OUT_Stop(void) 
+{
+    CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE));
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_SetPQ
+********************************************************************************
+*
+* Summary:
+*  Sets the P and Q dividers and the charge pump current.
+*  The Frequency Out will be P/Q * Frequency In.
+*  The PLL must be disabled before calling this function.
+*
+* Parameters:
+*  uint8 pDiv:
+*   Valid range [8 - 255].
+*
+*  uint8 qDiv:
+*   Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.
+
+*  uint8 current:
+*   Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and
+*   datasheet for more information.
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) 
+{
+    /* Halt CPU in debug mode if PLL is enabled */
+    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
+
+    if((pDiv    >= CY_CLK_PLL_MIN_P_VALUE  ) &&
+       (qDiv    <= CY_CLK_PLL_MAX_Q_VALUE  ) && (qDiv    >= CY_CLK_PLL_MIN_Q_VALUE  ) &&
+       (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE))
+    {
+        /* Set new values */
+        CY_CLK_PLL_P_REG = pDiv;
+        CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u));
+        CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) |
+                                ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION));
+    }
+    else
+    {
+        /***********************************************************************
+        * Halt CPU in debug mode if:
+        * - P divider is less than required
+        * - Q divider is out of range
+        * - pump current is out of range
+        ***********************************************************************/
+        CYASSERT(0u != 0u);
+    }
+
+}
+
+
+/*******************************************************************************
+* Function Name: CyPLL_OUT_SetSource
+********************************************************************************
+*
+* Summary:
+*  Sets the input clock source to the PLL. The PLL must be disabled before
+*  calling this function.
+*
+* Parameters:
+*   source: One of the three available PLL clock sources
+*    CY_PLL_SOURCE_IMO  :   IMO
+*    CY_PLL_SOURCE_XTAL :   MHz Crystal
+*    CY_PLL_SOURCE_DSI  :   DSI
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyPLL_OUT_SetSource(uint8 source) 
+{
+    /* Halt CPU in debug mode if PLL is enabled */
+    CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));
+
+    switch(source)
+    {
+        case CY_PLL_SOURCE_IMO:
+        case CY_PLL_SOURCE_XTAL:
+        case CY_PLL_SOURCE_DSI:
+            CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source);
+        break;
+
+        default:
+            CYASSERT(0u != 0u);
+        break;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_Start
+********************************************************************************
+*
+* Summary:
+*  Enables the IMO. Optionally waits at least 6 us for it to settle.
+*
+* Parameters:
+*  uint8 wait:
+*   0: Return immediately after configuration
+*   1: Wait for at least 6 us for the IMO to settle.
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
+*  Any other use of the Fast Time Wheel will be stopped during the period of
+*  this function and then restored. This function also uses the 100 KHz ILO.
+*  If not enabled, this function will enable the 100 KHz ILO for the period of
+*  this function.
+*
+*  No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or
+*  Once Per Second interrupt may be made by interrupt routines during the period
+*  of this function execution. The current operation of the ILO, Central Time
+*  Wheel and Once Per Second interrupt are maintained during the operation of
+*  this function provided the reading of the Power Manager Interrupt Status
+*  Register is only done using the CyPmReadStatus() function.
+*
+*******************************************************************************/
+void CyIMO_Start(uint8 wait) 
+{
+    uint8 pmFtwCfg2Reg;
+    uint8 pmFtwCfg0Reg;
+    uint8 ilo100KhzEnable;
+
+
+    CY_LIB_PM_ACT_CFG0_REG  |= CY_LIB_PM_ACT_CFG0_IMO_EN;
+    CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN;
+
+    if(0u != wait)
+    {
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
+        ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+        pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
+        pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
+
+        CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT);
+
+        while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+        {
+            /* Wait for interrupt status */
+        }
+
+        if(0u == ilo100KhzEnable)
+        {
+            CyILO_Stop100K();
+        }
+
+        CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg;
+        CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables the IMO.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyIMO_Stop(void) 
+{
+    CY_LIB_PM_ACT_CFG0_REG  &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN));
+    CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN));
+}
+
+
+/*******************************************************************************
+* Function Name: CyUSB_PowerOnCheck
+********************************************************************************
+*
+* Summary:
+*  Returns the USB power status value. A private function to cy_boot.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   uint8: one if the USB is enabled, 0 if not enabled.
+*
+*******************************************************************************/
+static uint8 CyUSB_PowerOnCheck(void)  
+{
+    uint8 poweredOn = 0u;
+
+    /* Check whether device is in Active or AltActiv and if USB is powered on */
+    if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&
+       (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED     )))  ||
+       (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&
+       (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))
+    {
+        poweredOn = 1u;
+    }
+
+    return (poweredOn);
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetTrimValue
+********************************************************************************
+*
+* Summary:
+*  Sets the IMO factory trim values.
+*
+* Parameters:
+*  uint8 freq - frequency for which trims must be set
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+static void CyIMO_SetTrimValue(uint8 freq) 
+{
+    uint8 usbPowerOn = CyUSB_PowerOnCheck();
+
+    /* If USB is powered */
+    if(usbPowerOn == 1u)
+    {
+        /* Unlock USB write */
+        CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN));
+    }
+    switch(freq)
+    {
+    case CY_IMO_FREQ_3MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_6MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_12MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_24MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR);
+        break;
+
+    case CY_IMO_FREQ_48MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR);
+        break;
+
+    case CY_IMO_FREQ_62MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR);
+        break;
+
+#if(CY_PSOC5)
+    case CY_IMO_FREQ_74MHZ:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR);
+        break;
+#endif  /* (CY_PSOC5) */
+
+    case CY_IMO_FREQ_USB:
+        CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR);
+
+        /* If USB is powered */
+        if(usbPowerOn == 1u)
+        {
+            /* Lock USB Oscillator */
+            CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
+        }
+        break;
+
+    default:
+            CYASSERT(0u != 0u);
+        break;
+    }
+
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetFreq
+********************************************************************************
+*
+* Summary:
+*  Sets the frequency of the IMO. Changes may be made while the IMO is running.
+*
+* Parameters:
+*  freq: Frequency of IMO operation
+*       CY_IMO_FREQ_3MHZ  to set  3   MHz
+*       CY_IMO_FREQ_6MHZ  to set  6   MHz
+*       CY_IMO_FREQ_12MHZ to set 12   MHz
+*       CY_IMO_FREQ_24MHZ to set 24   MHz
+*       CY_IMO_FREQ_48MHZ to set 48   MHz
+*       CY_IMO_FREQ_62MHZ to set 62.6 MHz
+*       CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)
+*       CY_IMO_FREQ_USB   to set 24   MHz (Trimmed for USB operation)
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution results in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*  When the USB setting is chosen, the USB clock locking circuit is enabled.
+*  Otherwise this circuit is disabled. The USB block must be powered before
+*  selecting the USB setting.
+*
+*******************************************************************************/
+void CyIMO_SetFreq(uint8 freq) 
+{
+    uint8 currentFreq;
+    uint8 nextFreq;
+
+    /***************************************************************************
+    * If the IMO frequency is changed,the Trim values must also be set
+    * accordingly.This requires reading the current frequency. If the new
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
+    ***************************************************************************/
+
+    currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
+
+    /* Check if requested frequency is USB. */
+    nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
+
+    switch (currentFreq)
+    {
+    case 0u:
+        currentFreq = CY_IMO_FREQ_12MHZ;
+        break;
+
+    case 1u:
+        currentFreq = CY_IMO_FREQ_6MHZ;
+        break;
+
+    case 2u:
+        currentFreq = CY_IMO_FREQ_24MHZ;
+        break;
+
+    case 3u:
+        currentFreq = CY_IMO_FREQ_3MHZ;
+        break;
+
+    case 4u:
+        currentFreq = CY_IMO_FREQ_48MHZ;
+        break;
+
+    case 5u:
+        currentFreq = CY_IMO_FREQ_62MHZ;
+        break;
+
+#if(CY_PSOC5)
+    case 6u:
+        currentFreq = CY_IMO_FREQ_74MHZ;
+        break;
+#endif  /* (CY_PSOC5) */
+
+    default:
+        CYASSERT(0u != 0u);
+        break;
+    }
+
+    if (nextFreq >= currentFreq)
+    {
+        /* Set new trim first */
+        CyIMO_SetTrimValue(freq);
+    }
+
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    switch(freq)
+    {
+    case CY_IMO_FREQ_3MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_6MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_12MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_24MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_48MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+    case CY_IMO_FREQ_62MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+
+#if(CY_PSOC5)
+    case CY_IMO_FREQ_74MHZ:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));
+        break;
+#endif  /* (CY_PSOC5) */
+
+    case CY_IMO_FREQ_USB:
+        CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |
+            CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET;
+        break;
+
+    default:
+        CYASSERT(0u != 0u);
+        break;
+    }
+
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
+    if (freq == CY_IMO_FREQ_USB)
+    {
+        CyIMO_EnableDoubler();
+    }
+    else
+    {
+        CyIMO_DisableDoubler();
+    }
+
+    if (nextFreq < currentFreq)
+    {
+        /* Set the trim after setting frequency */
+        CyIMO_SetTrimValue(freq);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_SetSource
+********************************************************************************
+*
+* Summary:
+*  Sets the source of the clock output from the IMO block.
+*
+*  The output from the IMO is by default the IMO itself. Optionally the MHz
+*  Crystal or DSI input can be the source of the IMO output instead.
+*
+* Parameters:
+*   source: CY_IMO_SOURCE_DSI to set the DSI as source.
+*           CY_IMO_SOURCE_XTAL to set the MHz as source.
+*           CY_IMO_SOURCE_IMO to set the IMO itself.
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyIMO_SetSource(uint8 source) 
+{
+    switch(source)
+    {
+    case CY_IMO_SOURCE_DSI:
+        CY_LIB_CLKDIST_CR_REG     &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X));
+        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
+        break;
+
+    case CY_IMO_SOURCE_XTAL:
+        CY_LIB_CLKDIST_CR_REG     |= CY_LIB_CLKDIST_CR_IMO2X;
+        CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;
+        break;
+
+    case CY_IMO_SOURCE_IMO:
+        CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO));
+        break;
+
+    default:
+        /* Incorrect source value */
+        CYASSERT(0u != 0u);
+        break;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_EnableDoubler
+********************************************************************************
+*
+* Summary:
+*  Enables the IMO doubler.  The 2x frequency clock is used to convert a 24 MHz
+*  input to a 48 MHz output for use by the USB block.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyIMO_EnableDoubler(void) 
+{
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
+}
+
+
+/*******************************************************************************
+* Function Name: CyIMO_DisableDoubler
+********************************************************************************
+*
+* Summary:
+*   Disables the IMO doubler.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyIMO_DisableDoubler(void) 
+{
+    CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER));
+}
+
+
+/*******************************************************************************
+* Function Name: CyMasterClk_SetSource
+********************************************************************************
+*
+* Summary:
+*  Sets the source of the master clock.
+*
+* Parameters:
+*   source: One of the four available Master clock sources.
+*     CY_MASTER_SOURCE_IMO
+*     CY_MASTER_SOURCE_PLL
+*     CY_MASTER_SOURCE_XTAL
+*     CY_MASTER_SOURCE_DSI
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  The current source and the new source must both be running and stable before
+*  calling this function.
+*
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyMasterClk_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) |
+                                (source & ((uint8)(~MASTER_CLK_SRC_CLEAR)));
+}
+
+
+/*******************************************************************************
+* Function Name: CyMasterClk_SetDivider
+********************************************************************************
+*
+* Summary:
+*  Sets the divider value used to generate Master Clock.
+*
+* Parameters:
+*  uint8 divider:
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*  When changing the Master or Bus clock divider value from div-by-n to div-by-1
+*  the first clock cycle output after the div-by-1 can be up to 4 ns shorter
+*  than the final/expected div-by-1 period.
+*
+*******************************************************************************/
+void CyMasterClk_SetDivider(uint8 divider) 
+{
+    CY_LIB_CLKDIST_MSTR0_REG = divider;
+}
+
+
+/*******************************************************************************
+* Function Name: CyBusClk_Internal_SetDivider
+********************************************************************************
+*
+* Summary:
+*  The function used by CyBusClk_SetDivider(). For internal use only.
+*
+* Parameters:
+*   divider: Valid range [0-65535].
+*   The clock will be divided by this value + 1.
+*   For example, to divide this parameter by two should be set to 1.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+static void CyBusClk_Internal_SetDivider(uint16 divider)
+{
+    /* Mask bits to enable shadow loads  */
+    CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK;
+    CY_LIB_CLKDIST_DMASK_REG  = CY_LIB_CLKDIST_DMASK_MASK;
+
+    /* Enable mask bits to enable shadow loads */
+    CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
+
+    /* Update Shadow Divider Value Register with new divider */
+    CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
+    CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
+
+
+    /***************************************************************************
+    * Copy shadow value defined in Shadow Divider Value Register
+    * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all
+    * dividers selected in Analog and Digital Clock Mask Registers
+    * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG).
+    ***************************************************************************/
+    CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD;
+}
+
+
+/*******************************************************************************
+* Function Name: CyBusClk_SetDivider
+********************************************************************************
+*
+* Summary:
+*  Sets the divider value used to generate the Bus Clock.
+*
+* Parameters:
+*  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
+*  For example, to divide this parameter by two should be set to 1.
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+*  See CyFlash_SetWaitCycles() description for more information.
+*
+*******************************************************************************/
+void CyBusClk_SetDivider(uint16 divider) 
+{
+    uint8  masterClkDiv;
+    uint16 busClkDiv;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    /* Work around to set bus clock divider value */
+    busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
+    busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
+
+    if ((divider == 0u) || (busClkDiv == 0u))
+    {
+        /* Save away master clock divider value */
+        masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
+
+        if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
+        {
+            /* Set master clock divider to 7 */
+            CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV);
+        }
+
+        if (divider == 0u)
+        {
+            /* Set SSS bit and divider register desired value */
+            CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
+            CyBusClk_Internal_SetDivider(divider);
+        }
+        else
+        {
+            CyBusClk_Internal_SetDivider(divider);
+            CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
+        }
+
+        /* Restore master clock */
+        CyMasterClk_SetDivider(masterClkDiv);
+    }
+    else
+    {
+        CyBusClk_Internal_SetDivider(divider);
+    }
+
+    CyExitCriticalSection(interruptState);
+}
+
+
+#if(CY_PSOC3)
+
+    /*******************************************************************************
+    * Function Name: CyCpuClk_SetDivider
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the divider value used to generate the CPU Clock. Only applicable for
+    *  PSoC 3 parts.
+    *
+    * Parameters:
+    *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
+    *  For example, to divide this parameter by two should be set to 1.
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
+    *  See CyFlash_SetWaitCycles() description for more information.
+    *
+    *******************************************************************************/
+    void CyCpuClk_SetDivider(uint8 divider) 
+    {
+            CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) |
+                                ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION));
+    }
+
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Function Name: CyUsbClk_SetSource
+********************************************************************************
+*
+* Summary:
+*  Sets the source of the USB clock.
+*
+* Parameters:
+*  source: One of the four available USB clock sources
+*    CY_LIB_USB_CLK_IMO2X     - IMO 2x
+*    CY_LIB_USB_CLK_IMO       - IMO
+*    CY_LIB_USB_CLK_PLL       - PLL
+*    CY_LIB_USB_CLK_DSI       - DSI
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyUsbClk_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) |
+                        (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source);
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Start1K
+********************************************************************************
+*
+* Summary:
+*  Enables the ILO 1 KHz oscillator.
+*
+*  Note The ILO 1 KHz oscillator is always enabled by default, regardless of the
+*  selection in the Clock Editor. Therefore, this API is only needed if the
+*  oscillator was turned off manually.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_Start1K(void) 
+{
+    /* Set bit 1 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Stop1K
+********************************************************************************
+*
+* Summary:
+*  Disables the ILO 1 KHz oscillator.
+*
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
+*  mode APIs are expected to be used. For more information, refer to the Power
+*  Management section of this document.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.
+*
+*******************************************************************************/
+void CyILO_Stop1K(void) 
+{
+    /* Clear bit 1 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Start100K
+********************************************************************************
+*
+* Summary:
+*  Enables the ILO 100 KHz oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_Start100K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Stop100K
+********************************************************************************
+*
+* Summary:
+*  Disables the ILO 100 KHz oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_Stop100K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Enable33K
+********************************************************************************
+*
+* Summary:
+*  Enables the ILO 33 KHz divider.
+*
+*  Note that the 33 KHz clock is generated from the 100 KHz oscillator,
+*  so it must also be running in order to generate the 33 KHz output.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_Enable33K(void) 
+{
+    /* Set bit 5 of ILO RS */
+    CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_Disable33K
+********************************************************************************
+*
+* Summary:
+*  Disables the ILO 33 KHz divider.
+*
+*  Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this
+*  API does not disable the 100 KHz clock.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_Disable33K(void) 
+{
+    CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_SetSource
+********************************************************************************
+*
+* Summary:
+*  Sets the source of the clock output from the ILO block.
+*
+* Parameters:
+*  source: One of the three available ILO output sources
+*       Value        Define                Source
+*       0            CY_ILO_SOURCE_100K    ILO 100 KHz
+*       1            CY_ILO_SOURCE_33K     ILO 33 KHz
+*       2            CY_ILO_SOURCE_1K      ILO 1 KHz
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyILO_SetSource(uint8 source) 
+{
+    CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) |
+                    (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR)));
+}
+
+
+/*******************************************************************************
+* Function Name: CyILO_SetPowerMode
+********************************************************************************
+*
+* Summary:
+*  Sets the power mode used by the ILO during power down. Allows for lower power
+*  down power usage resulting in a slower startup time.
+*
+* Parameters:
+*  uint8 mode
+*   CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down
+*   CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down
+*
+* Return:
+*   Prevous power mode state.
+*
+*******************************************************************************/
+uint8 CyILO_SetPowerMode(uint8 mode) 
+{
+    uint8 state;
+
+    /* Get current state. */
+    state = CY_LIB_SLOWCLK_ILO_CR0_REG;
+
+    /* Set the oscillator power mode. */
+    if(mode != CY_ILO_FAST_START)
+    {
+        CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
+    }
+    else
+    {
+        CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
+    }
+
+    /* Return old mode. */
+    return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_Start
+********************************************************************************
+*
+* Summary:
+*  Enables the 32 KHz Crystal Oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_32KHZ_Start(void) 
+{
+    volatile uint16 i;
+
+    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
+    CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_STARTUP;
+    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
+
+    #if(CY_PSOC3)
+        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
+    #endif  /* (CY_PSOC3) */
+
+    /* Enable operation of 32K Crystal Oscillator */
+    CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
+
+    for (i = 1000u; i > 0u; i--)
+    {
+        if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
+        {
+            /* Ready - switch to high power mode */
+            (void) CyXTAL_32KHZ_SetPowerMode(0u);
+
+            break;
+        }
+        CyDelayUs(1u);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_Stop
+********************************************************************************
+*
+* Summary:
+*  Disables the 32KHz Crystal Oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_32KHZ_Stop(void) 
+{
+    CY_CLK_XTAL32_TST_REG  = CY_CLK_XTAL32_TST_DEFAULT;
+    CY_CLK_XTAL32_TR_REG   = CY_CLK_XTAL32_TR_POWERDOWN;
+    CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                             CY_CLK_XTAL32_CFG_LP_DEFAULT;
+    CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM)));
+
+    #if(CY_PSOC3)
+        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN));
+    #endif  /* (CY_PSOC3) */
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_ReadStatus
+********************************************************************************
+*
+* Summary:
+*  Returns status of the 32 KHz oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Value     Define                    Source
+*  20        CY_XTAL32K_ANA_STAT       Analog measurement
+*                                       1: Stable
+*                                       0: Not stable
+*
+*******************************************************************************/
+uint8 CyXTAL_32KHZ_ReadStatus(void) 
+{
+    return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_32KHZ_SetPowerMode
+********************************************************************************
+*
+* Summary:
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
+*  Allows for lower power during sleep when there are fewer sources of noise.
+*  During the active mode the oscillator is always run in the high power mode.
+*
+* Parameters:
+*  uint8 mode
+*       0: High power mode
+*       1: Low power mode during sleep
+*
+* Return:
+*  Previous power mode.
+*
+*******************************************************************************/
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) 
+{
+    uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u;
+
+    CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;
+
+    if(1u == mode)
+    {
+        /* Low power mode during Sleep */
+        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_LOW_POWER;
+        CyDelayUs(10u);
+        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_LOWPOWER;
+        CyDelayUs(20u);
+        CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM;
+    }
+    else
+    {
+        /* High power mode */
+        CY_CLK_XTAL32_TR_REG  = CY_CLK_XTAL32_TR_HIGH_POWER;
+        CyDelayUs(10u);
+        CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |
+                                CY_CLK_XTAL32_CFG_LP_DEFAULT;
+        CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM));
+    }
+
+    return(state);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_Start
+********************************************************************************
+*
+* Summary:
+*  Enables the megahertz crystal.
+*
+*  PSoC 3:
+*  Waits until the XERR bit is low (no error) for a millisecond or until the
+*  number of milliseconds specified by the wait parameter has expired.
+*
+* Parameters:
+*   wait: Valid range [0-255].
+*   This is the timeout value in milliseconds.
+*   The appropriate value is crystal specific.
+*
+* Return:
+*   CYRET_SUCCESS - Completed successfully
+*   CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.
+*
+* Side Effects and Restrictions:
+*  If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait.
+*  Any other use of the Fast Timewheel (FTW) will be stopped during the period
+*  of this function and then restored.
+*
+*  Uses the 100KHz ILO.  If not enabled, this function will enable the 100KHz
+*  ILO for the period of this function. No changes to the setup of the ILO,
+*  Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made
+*  by interrupt routines during the period of this function.
+*
+*  The current operation of the ILO, Central Timewheel and Once Per Second
+*  interrupt are maintained during the operation of this function provided the
+*  reading of the Power Manager Interrupt Status Register is only done using the
+*  CyPmReadStatus() function.
+*
+*******************************************************************************/
+cystatus CyXTAL_Start(uint8 wait) 
+{
+    cystatus status = CYRET_SUCCESS;
+    volatile uint8  timeout = wait;
+    volatile uint8 count;
+    uint8 iloEnableState;
+    uint8 pmTwCfg0Tmp;
+    uint8 pmTwCfg2Tmp;
+
+
+    /* Enables MHz crystal oscillator circuit  */
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
+
+
+    if(wait > 0u)
+    {
+        /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */
+        iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG;
+        pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG;
+        pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG;
+
+        /* Set 250 us interval */
+        CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL);
+        status = CYRET_TIMEOUT;
+
+
+        for( ; timeout > 0u; timeout--)
+        {
+            /* Read XERR bit to clear it */
+            (void) CY_CLK_XMHZ_CSR_REG;
+
+            /* Wait for 1 millisecond - 4 x 250 us */
+            for(count = 4u; count > 0u; count--)
+            {
+                while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
+                {
+                    /* Wait for FTW interrupt event */
+                }
+            }
+
+
+            /*******************************************************************
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
+            *******************************************************************/
+            if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+
+        /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */
+        if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ))
+        {
+            CyILO_Stop100K();
+        }
+        CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp;
+        CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_Stop
+********************************************************************************
+*
+* Summary:
+*  Disables the megahertz crystal oscillator.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_Stop(void) 
+{
+    /* Disable oscillator. */
+    FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_EnableErrStatus
+********************************************************************************
+*
+* Summary:
+*  Enables the generation of the XERR status bit for the megahertz crystal.
+*  This function is not available for PSoC5.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_EnableErrStatus(void) 
+{
+    /* If oscillator has insufficient amplitude, XERR bit will be high. */
+    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_DisableErrStatus
+********************************************************************************
+*
+* Summary:
+*  Disables the generation of the XERR status bit for the megahertz crystal.
+*  This function is not available for PSoC5.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_DisableErrStatus(void) 
+{
+    /* If oscillator has insufficient amplitude, XERR bit will be high. */
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_ReadStatus
+********************************************************************************
+*
+* Summary:
+*  Reads the XERR status bit for the megahertz crystal. This status bit is a
+*  sticky, clear on read. This function is not available for PSoC5.
+*
+* Parameters:
+*  None
+*
+* Return:
+*   Status
+*    0: No error
+*    1: Error
+*
+*******************************************************************************/
+uint8 CyXTAL_ReadStatus(void) 
+{
+    /***************************************************************************
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
+    ***************************************************************************/
+    return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_EnableFaultRecovery
+********************************************************************************
+*
+* Summary:
+*  Enables the fault recovery circuit which will switch to the IMO in the case
+*  of a fault in the megahertz crystal circuit. The crystal must be up and
+*  running with the XERR bit at 0, before calling this function to prevent
+*  an immediate fault switchover. This function is not available for PSoC5.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_EnableFaultRecovery(void) 
+{
+    CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_DisableFaultRecovery
+********************************************************************************
+*
+* Summary:
+*  Disables the fault recovery circuit which will switch to the IMO in the case
+*  of a fault in the megahertz crystal circuit. This function is not available
+*  for PSoC5.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_DisableFaultRecovery(void) 
+{
+    CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetStartup
+********************************************************************************
+*
+* Summary:
+*  Sets the startup settings for the crystal. The logic model outputs a frequency
+*  (setting + 4) MHz when enabled.
+*
+*  This is artificial as the actual frequency is determined by an attached
+*  external crystal.
+*
+* Parameters:
+*  setting: Valid range [0-31].
+*   The value is dependent on the frequency and quality of the crystal being used.
+*   Refer to the device TRM and datasheet for more information.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_SetStartup(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) |
+                           (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK);
+}
+
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetFbVoltage
+********************************************************************************
+*
+* Summary:
+*  Sets the feedback reference voltage to use for the crystal circuit.
+*  This function is only available for PSoC3 and PSoC 5LP.
+*
+* Parameters:
+*  setting: Valid range [0-15].
+*  Refer to the device TRM and datasheet for more information.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_SetFbVoltage(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |
+                            (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: CyXTAL_SetWdVoltage
+********************************************************************************
+*
+* Summary:
+*  Sets the reference voltage used by the watchdog to detect a failure in the
+*  crystal circuit. This function is only available for PSoC3 and PSoC 5LP.
+*
+* Parameters:
+*  setting: Valid range [0-7].
+*  Refer to the device TRM and datasheet for more information.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyXTAL_SetWdVoltage(uint8 setting) 
+{
+    CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |
+                            (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: CyHalt
+********************************************************************************
+*
+* Summary:
+*  Halts the CPU.
+*
+* Parameters:
+*  uint8 reason: Value to be used during debugging.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyHalt(uint8 reason) CYREENTRANT
+{
+    if(0u != reason)
+    {
+        /* To remove unreferenced local variable warning */
+    }
+
+    #if defined (__ARMCC_VERSION)
+        __breakpoint(0x0);
+    #elif defined(__GNUC__) || defined (__ICCARM__)
+        __asm("    bkpt    1");
+    #elif defined(__C51__)
+        CYDEV_HALT_CPU;
+    #endif  /* (__ARMCC_VERSION) */
+}
+
+
+/*******************************************************************************
+* Function Name: CySoftwareReset
+********************************************************************************
+*
+* Summary:
+*  Forces a device software reset.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CySoftwareReset(void) 
+{
+    CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET;
+}
+
+
+/*******************************************************************************
+* Function Name: CyDelay
+********************************************************************************
+*
+* Summary:
+*  Blocks for milliseconds.
+*
+*  Note:
+*  CyDelay has been implemented with the instruction cache assumed enabled. When
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
+*
+* Parameters:
+*  milliseconds: number of milliseconds to delay.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void CyDelay(uint32 milliseconds) CYREENTRANT
+{
+    while (milliseconds > 32768u)
+    {
+        /***********************************************************************
+        * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz
+        * overflows at about 42 seconds.
+        ***********************************************************************/
+        CyDelayCycles(cydelay_32k_ms);
+        milliseconds = ((uint32)(milliseconds - 32768u));
+    }
+
+    CyDelayCycles(milliseconds * cydelay_freq_khz);
+}
+
+
+#if(!CY_PSOC3)
+
+    /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */
+
+    /*******************************************************************************
+    * Function Name: CyDelayUs
+    ********************************************************************************
+    *
+    * Summary:
+    *  Blocks for microseconds.
+    *
+    *  Note:
+    *   CyDelay has been implemented with the instruction cache assumed enabled.
+    *   When instruction cache is disabled on PSoC5, CyDelayUs will be two times
+    *   larger. Ex: With instruction cache disabled CyDelayUs(100) would result
+    *   in about 200us delay instead of 100us.
+    *
+    * Parameters:
+    *  uint16 microseconds: number of microseconds to delay.
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  CyDelayUS has been implemented with the instruction cache assumed enabled.
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
+    *  result in about 200 us delay instead of 100 us.
+    *
+    *  If the bus clock frequency is a small non-integer number, the actual delay
+    *  can be up to twice as long as the nominal value. The actual delay cannot be
+    *  shorter than the nominal one.
+    *******************************************************************************/
+    void CyDelayUs(uint16 microseconds) CYREENTRANT
+    {
+        CyDelayCycles((uint32)microseconds * cydelay_freq_mhz);
+    }
+
+#endif  /* (!CY_PSOC3) */
+
+
+/*******************************************************************************
+* Function Name: CyDelayFreq
+********************************************************************************
+*
+* Summary:
+*  Sets the clock frequency for CyDelay.
+*
+* Parameters:
+*  freq: The frequency of the bus clock in Hertz.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyDelayFreq(uint32 freq) CYREENTRANT
+{
+    if (freq != 0u)
+    {
+        cydelay_freq_hz = freq;
+    }
+    else
+    {
+        cydelay_freq_hz = BCLK__BUS_CLK__HZ;
+    }
+
+    cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u);
+    cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u;
+    cydelay_32k_ms   = 32768u * cydelay_freq_khz;
+}
+
+
+/*******************************************************************************
+* Function Name: CyWdtStart
+********************************************************************************
+*
+* Summary:
+*  Enables the watchdog timer.
+*
+*  The timer is configured for the specified count interval, the central
+*  timewheel is cleared, the setting for the low power mode is configured and the
+*  watchdog timer is enabled.
+*
+*  Once enabled the watchdog cannot be disabled. The watchdog counts each time
+*  the Central Time Wheel (CTW) reaches the period specified. The watchdog must
+*  be cleared using the CyWdtClear() function before three ticks of the watchdog
+*  timer occur. The CTW is free running, so this will occur after between 2 and
+*  3 timer periods elapse.
+*
+*  PSoC5: The watchdog timer should not be used during sleep modes. Since the
+*  WDT cannot be disabled after it is enabled, the WDT timeout period can be
+*  set to be greater than the sleep wakeup period, then feed the dog on each
+*  wakeup from Sleep.
+*
+* Parameters:
+*  ticks: One of the four available timer periods. Once WDT enabled, the
+   interval cannot be changed.
+*         CYWDT_2_TICKS     -     4 - 6     ms
+*         CYWDT_16_TICKS    -    32 - 48    ms
+*         CYWDT_128_TICKS   -   256 - 384   ms
+*         CYWDT_1024_TICKS  - 2.048 - 3.072 s
+*
+*  lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.
+*          The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.
+*
+*          CYWDT_LPMODE_NOCHANGE - No Change
+*          CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power
+*                                 mode
+*          CYWDT_LPMODE_DISABLED - Disable WDT during low power mode
+*
+* Return:
+*  None
+*
+* Side Effects:
+*  PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the
+*  ILO 1 kHz could break the active WDT functionality.
+*
+*******************************************************************************/
+void CyWdtStart(uint8 ticks, uint8 lpMode) 
+{
+    /* Set WDT interval */
+    CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK);
+
+    /* Reset CTW to ensure that first watchdog period is full */
+    CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
+    CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
+
+    /* Setting low power mode */
+    CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
+                       (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
+
+    /* Enables watchdog reset */
+    CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
+}
+
+
+/*******************************************************************************
+* Function Name: CyWdtClear
+********************************************************************************
+*
+* Summary:
+*  Clears (feeds) the watchdog timer.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyWdtClear(void) 
+{
+    CY_WDT_CR_REG = CY_WDT_CR_FEED;
+}
+
+
+
+/*******************************************************************************
+* Function Name: CyVdLvDigitEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the digital low voltage monitors to generate interrupt on Vddd
+*   archives specified threshold and optionally resets the device.
+*
+* Parameters:
+*  reset: The option to reset the device at a specified Vddd threshold:
+*           0 - Device is not reset.
+*           1 - Device is reset.
+*
+*  threshold: Sets the trip level for the voltage monitor.
+*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
+*  250 mV.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) 
+{
+    *CY_INT_CLEAR_PTR = 0x01u;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+
+    CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) |
+                            (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
+
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
+    CyDelayUs(1u);
+
+    (void)CY_VD_PERSISTENT_STATUS_REG;
+
+    if(0u != reset)
+    {
+        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;
+    }
+    else
+    {
+        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+    }
+
+    *CY_INT_CLR_PEND_PTR = 0x01u;
+    *CY_INT_ENABLE_PTR   = 0x01u;
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvAnalogEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the analog low voltage monitors to generate interrupt on Vdda
+*   archives specified threshold and optionally resets the device.
+*
+* Parameters:
+*  reset: The option to reset the device at a specified Vdda threshold:
+*           0 - Device is not reset.
+*           1 - Device is reset.
+*
+*  threshold: Sets the trip level for the voltage monitor.
+*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
+*  interval.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) 
+{
+    *CY_INT_CLEAR_PTR = 0x01u;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+
+    CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
+
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
+    CyDelayUs(1u);
+
+    (void)CY_VD_PERSISTENT_STATUS_REG;
+
+    if(0u != reset)
+    {
+        CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;
+    }
+    else
+    {
+        CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+    }
+
+    *CY_INT_CLR_PEND_PTR = 0x01u;
+    *CY_INT_ENABLE_PTR   = 0x01u;
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvDigitDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the digital low voltage monitor (interrupt and device reset are
+*  disabled).
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdLvDigitDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));
+
+    while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdLvAnalogDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the analog low voltage monitor (interrupt and device reset are
+*  disabled).
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdLvAnalogDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+
+    while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdHvAnalogEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the analog high voltage monitors to generate interrupt on
+*  Vdda archives 5.75 V threshold and optionally resets device.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdHvAnalogEnable(void) 
+{
+    *CY_INT_CLEAR_PTR = 0x01u;
+
+    CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));
+
+    CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;
+
+    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    CyDelayUs(1u);
+
+    (void) CY_VD_PERSISTENT_STATUS_REG;
+
+    *CY_INT_CLR_PEND_PTR = 0x01u;
+    *CY_INT_ENABLE_PTR   = 0x01u;
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdHvAnalogDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the analog low voltage monitor
+*  (interrupt and device reset are disabled).
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyVdHvAnalogDisable(void) 
+{
+    CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdStickyStatus
+********************************************************************************
+*
+* Summary:
+*  Manages the Reset and Voltage Detection Status Register 0.
+*  This register has the interrupt status for the HVIA, LVID and LVIA.
+*  This hardware register clears on read.
+*
+* Parameters:
+*  mask: Bits in the shadow register to clear.
+*   Define                  Definition
+*   CY_VD_LVID            Persistent status of digital LVI.
+*   CY_VD_LVIA            Persistent status of analog LVI.
+*   CY_VD_HVIA            Persistent status of analog HVI.
+*
+* Return:
+*  Status.  Same enumerated bit values as used for the mask parameter.
+*
+*******************************************************************************/
+uint8 CyVdStickyStatus(uint8 mask) 
+{
+    uint8 status;
+
+    status = CY_VD_PERSISTENT_STATUS_REG;
+    CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask));
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CyVdRealTimeStatus
+********************************************************************************
+*
+* Summary:
+*  Returns the real time voltage detection status.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  Status:
+*   Define                  Definition
+*   CY_VD_LVID            Persistent status of digital LVI.
+*   CY_VD_LVIA            Persistent status of analog LVI.
+*   CY_VD_HVIA            Persistent status of analog HVI.
+*
+*******************************************************************************/
+uint8 CyVdRealTimeStatus(void) 
+{
+    uint8 interruptState;
+    uint8 vdFlagsState;
+
+    interruptState = CyEnterCriticalSection();
+    vdFlagsState = CY_VD_RT_STATUS_REG;
+    CyExitCriticalSection(interruptState);
+
+    return(vdFlagsState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyDisableInts
+********************************************************************************
+*
+* Summary:
+*  Disables the interrupt enable for each interrupt.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  32 bit mask of previously enabled interrupts.
+*
+*******************************************************************************/
+uint32 CyDisableInts(void) 
+{
+    uint32 intState;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    #if(CY_PSOC3)
+
+        /* Get the current interrupt state. */
+        intState  = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u));
+        intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u));
+
+
+        /* Disable all of the interrupts. */
+        CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu);
+        CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu);
+
+    #else
+
+        /* Get the current interrupt state. */
+        intState = CY_GET_REG32(CY_INT_CLEAR_PTR);
+
+        /* Disable all of the interrupts. */
+        CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu);
+
+    #endif /* (CY_PSOC3) */
+
+    CyExitCriticalSection(interruptState);
+
+    return (intState);
+}
+
+
+/*******************************************************************************
+* Function Name: CyEnableInts
+********************************************************************************
+*
+* Summary:
+*  Enables interrupts to a given state.
+*
+* Parameters:
+*  uint32 mask: 32 bit mask of interrupts to enable.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEnableInts(uint32 mask) 
+{
+
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    #if(CY_PSOC3)
+
+        /* Set interrupts as enabled. */
+        CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u)));
+        CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u)));
+        CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u )));
+        CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask )));
+
+    #else
+
+        CY_SET_REG32(CY_INT_ENABLE_PTR, mask);
+
+    #endif /* (CY_PSOC3) */
+
+    CyExitCriticalSection(interruptState);
+
+}
+
+#if(CY_PSOC5)
+
+    /*******************************************************************************
+    * Function Name: CyFlushCache
+    ********************************************************************************
+    * Summary:
+    *  Flushes the PSoC 5/5LP cache by invalidating all entries.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CyFlushCache(void)
+    {
+        uint8 interruptState;
+
+        /* Save current global interrupt enable and disable it */
+        interruptState = CyEnterCriticalSection();
+
+        /* Fill instruction prefectch unit to insure data integrity */
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+        CY_NOP;
+
+        /* All entries in cache are invalidated on next clock cycle. */
+        CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
+
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
+
+        /* Flush the pipeline */
+        CY_SYS_ISB;
+
+        /* Restore global interrupt enable state */
+        CyExitCriticalSection(interruptState);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetSysVector
+    ********************************************************************************
+    * Summary:
+    *  Sets the interrupt vector of the specified system interrupt number. System
+    *  interrupts are present only for the ARM platform. These interrupts are for
+    *  SysTick, PendSV and others.
+    *
+    * Parameters:
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  address: Pointer to an interrupt service routine.
+    *
+    * Return:
+    *   The old ISR vector at this location.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)
+    {
+        cyisraddress oldIsr;
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+
+        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
+
+        /* Set new Interrupt service routine. */
+        ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address;
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetSysVector
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets the interrupt vector of the specified system interrupt number. System
+    *  interrupts are present only for the ARM platform. These interrupts are for
+    *  SysTick, PendSV and others.
+    *
+    * Parameters:
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    * Return:
+    *   Address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetSysVector(uint8 number)
+    {
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+        CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);
+
+        return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetVector
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the interrupt vector of the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number
+    *  address: Pointer to an interrupt service routine
+    *
+    * Return:
+    *   Previous interrupt vector value.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetVector(uint8 number, cyisraddress address)
+    {
+        cyisraddress oldIsr;
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)];
+
+        /* Set new Interrupt service routine. */
+        ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address;
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetVector
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets the interrupt vector of the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number
+    *
+    * Return:
+    *  The address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetVector(uint8 number)
+    {
+        cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetPriority
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the Priority of the Interrupt.
+    *
+    * Parameters:
+    *  priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+    *  number: The number of the interrupt, 0 - 31.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CyIntSetPriority(uint8 number, uint8 priority)
+    {
+        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetPriority
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets the Priority of the Interrupt.
+    *
+    * Parameters:
+    *  number: The number of the interrupt, 0 - 31.
+    *
+    * Return:
+    *  Priority of the interrupt. 0 - 7, 0 being the highest.
+    *
+    *******************************************************************************/
+    uint8 CyIntGetPriority(uint8 number)
+    {
+        uint8 priority;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
+
+        return (priority);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetState
+    ********************************************************************************
+    *
+    * Summary:
+    *   Gets the enable state of the specified interrupt number.
+    *
+    * Parameters:
+    *   number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *   Enable status: 1 if enabled, 0 if disabled
+    *
+    *******************************************************************************/
+    uint8 CyIntGetState(uint8 number)
+    {
+        reg32 * stateReg;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Get pointer to Interrupt enable register. */
+        stateReg = CY_INT_ENABLE_PTR;
+
+        /* Get state of interrupt. */
+        return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
+    }
+
+
+#else   /* PSoC3 */
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetVector
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the interrupt vector of the specified interrupt number.
+    *
+    * Parameters:
+    *  number:  Valid range [0-31].  Interrupt number
+    *  address: Pointer to an interrupt service routine
+    *
+    * Return:
+    *  Previous interrupt vector value.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntSetVector(uint8 number, cyisraddress address) 
+    {
+        cyisraddress oldIsr;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Save old Interrupt service routine. */
+        oldIsr = (cyisraddress) \
+                    CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]);
+
+        /* Set new Interrupt service routine. */
+        CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address);
+
+        return (oldIsr);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetVector
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets the interrupt vector of the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number
+    *
+    * Return:
+    *  Address of the ISR in the interrupt vector table.
+    *
+    *******************************************************************************/
+    cyisraddress CyIntGetVector(uint8 number) 
+    {
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        return ((cyisraddress) \
+                CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntSetPriority
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the Priority of the Interrupt.
+    *
+    * Parameters:
+    *  priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+    *  number:   The number of the interrupt, 0 - 31.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CyIntSetPriority(uint8 number, uint8 priority) 
+    {
+        CYASSERT(priority <= CY_INT_PRIORITY_MAX);
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] =
+                    (priority & CY_INT_PRIORITY_MASK) << 5;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetPriority
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets the Priority of the Interrupt.
+    *
+    * Parameters:
+    *  number: The number of the interrupt, 0 - 31.
+    *
+    * Return:
+    *  Priority of the interrupt. 0 - 7, 0 being the highest.
+    *
+    *******************************************************************************/
+    uint8 CyIntGetPriority(uint8 number) 
+    {
+        uint8 priority;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;
+
+        return (priority);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CyIntGetState
+    ********************************************************************************
+    *
+    * Summary:
+    *   Gets the enable state of the specified interrupt number.
+    *
+    * Parameters:
+    *   number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *   Enable status: 1 if enabled, 0 if disabled
+    *
+    *******************************************************************************/
+    uint8 CyIntGetState(uint8 number) 
+    {
+        reg8 * stateReg;
+
+        CYASSERT(number <= CY_INT_NUMBER_MAX);
+
+        /* Get pointer to Interrupt enable register. */
+        stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
+
+        /* Get state of interrupt. */
+        return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
+    }
+
+
+#endif  /* (CY_PSOC5) */
+
+
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    /*******************************************************************************
+    * Function Name: CySetScPumps
+    ********************************************************************************
+    *
+    * Summary:
+    *  If 1 is passed as a parameter:
+    *   - if any of the SC blocks are used - enable pumps for the SC blocks and
+    *     start boost clock.
+    *   - For each enabled SC block set a boost clock index and enable the boost
+    *     clock.
+    *
+    *  If non-1 value is passed as a parameter:
+    *   - If all SC blocks are not used - disable pumps for the SC blocks and
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the  boost
+    *     clock.
+    *
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
+    *  parameter.
+    *
+    * Parameters:
+    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
+    *                 1 - Enable
+    *                 0 - Disable
+    *
+    * Return:
+    *   None
+    *
+    *******************************************************************************/
+    void CySetScPumps(uint8 enable) 
+    {
+        if(1u == enable)
+        {
+            /* The SC pumps should be enabled */
+            CyScPumpEnabled = 1u;
+            /* Enable pumps if any of SC blocks are used */
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))
+            {
+                CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;
+                CyScBoostClk_Start();
+            }
+            /* Set positive pump for each enabled SC block: set clock index and enable it */
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))
+            {
+                CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))
+            {
+                CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))
+            {
+                CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+            if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))
+            {
+                CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;
+                CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;
+            }
+        }
+        else
+        {
+            /* The SC pumps should be disabled */
+            CyScPumpEnabled = 0u;
+            /* Disable pumps for all SC blocks and stop boost clock */
+            CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));
+            CyScBoostClk_Stop();
+            /* Disable boost clock and clear clock index for each SC block */
+            CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+            CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));
+            CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;
+        }
+    }
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ********************************************************************************
+    *
+    * Summary:
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ********************************************************************************
+    *
+    * Summary:
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops the system timer (SysTick).
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    * Parameters:
+    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets current SysTick counter value.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the clock source for the SysTick counter.
+    *
+    * Parameters:
+    *  clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low frequency
+    *  clock the counter and reload register values will remain unchanged so time to
+    *  the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ********************************************************************************
+    *
+    * Summary:
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Returns non-zero value if counter is set, otherwise zero is returned.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ********************************************************************************
+    *
+    * Summary:
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function set the pointers to the functions that will be called on
+    *  SysTick interrupt.
+    *
+    * Parameters:
+    *  number:  The number of callback function address to be set.
+    *           The valid range is from 0 to 4.
+    *  CallbackFunction: Function address.
+    *
+    * Return:
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function get the specified callback pointer.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ********************************************************************************
+    *
+    * Summary:
+    *  System Tick timer interrupt routine
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h

@@ -1,1361 +1,1361 @@
-/*******************************************************************************
-* File Name: CyLib.h
-* Version 4.20
-*
-* Description:
-*  Provides the function definitions for the system, clocking, interrupts and
-*  watchdog timer API.
-*
-* Note:
-*  Documentation of the API's in this file is located in the System Reference
-*  Guide provided with PSoC Creator.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_BOOT_CYLIB_H)
-#define CY_BOOT_CYLIB_H
-
-#include <string.h>
-#include <limits.h>
-#include <ctype.h>
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cydevice_trm.h"
-#include "cyPm.h"
-
-#if(CY_PSOC3)
-    #include <PSoC3_8051.h>
-#endif  /* (CY_PSOC3) */
-
-
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    #include "CyScBoostClk.h"
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-/* Global variable with preserved reset status */
-extern uint8 CYXDATA CyResetStatus;
-
-
-/* Variable Vdda */
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    extern uint8 CyScPumpEnabled;
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-/* Do not use these definitions directly in your application */
-extern uint32 cydelay_freq_hz;
-extern uint32 cydelay_freq_khz;
-extern uint8  cydelay_freq_mhz;
-extern uint32 cydelay_32k_ms;
-
-
-/***************************************
-*    Function Prototypes
-***************************************/
-cystatus CyPLL_OUT_Start(uint8 wait) ;
-void  CyPLL_OUT_Stop(void) ;
-void  CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ;
-void  CyPLL_OUT_SetSource(uint8 source) ;
-
-void  CyIMO_Start(uint8 wait) ;
-void  CyIMO_Stop(void) ;
-void  CyIMO_SetFreq(uint8 freq) ;
-void  CyIMO_SetSource(uint8 source) ;
-void  CyIMO_EnableDoubler(void) ;
-void  CyIMO_DisableDoubler(void) ;
-
-void  CyMasterClk_SetSource(uint8 source) ;
-void  CyMasterClk_SetDivider(uint8 divider) ;
-void  CyBusClk_SetDivider(uint16 divider) ;
-
-#if(CY_PSOC3)
-    void  CyCpuClk_SetDivider(uint8 divider) ;
-#endif  /* (CY_PSOC3) */
-
-void  CyUsbClk_SetSource(uint8 source) ;
-
-void  CyILO_Start1K(void) ;
-void  CyILO_Stop1K(void) ;
-void  CyILO_Start100K(void) ;
-void  CyILO_Stop100K(void) ;
-void  CyILO_Enable33K(void) ;
-void  CyILO_Disable33K(void) ;
-void  CyILO_SetSource(uint8 source) ;
-uint8 CyILO_SetPowerMode(uint8 mode) ;
-
-uint8 CyXTAL_32KHZ_ReadStatus(void) ;
-uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ;
-void  CyXTAL_32KHZ_Start(void) ;
-void  CyXTAL_32KHZ_Stop(void) ;
-
-cystatus CyXTAL_Start(uint8 wait) ;
-void  CyXTAL_Stop(void) ;
-void  CyXTAL_SetStartup(uint8 setting) ;
-
-void  CyXTAL_EnableErrStatus(void) ;
-void  CyXTAL_DisableErrStatus(void) ;
-uint8 CyXTAL_ReadStatus(void) ;
-void  CyXTAL_EnableFaultRecovery(void) ;
-void  CyXTAL_DisableFaultRecovery(void) ;
-
-void CyXTAL_SetFbVoltage(uint8 setting) ;
-void CyXTAL_SetWdVoltage(uint8 setting) ;
-
-void CyWdtStart(uint8 ticks, uint8 lpMode) ;
-void CyWdtClear(void) ;
-
-/* System Function Prototypes */
-void CyDelay(uint32 milliseconds) CYREENTRANT;
-void CyDelayUs(uint16 microseconds);
-void CyDelayFreq(uint32 freq) CYREENTRANT;
-void CyDelayCycles(uint32 cycles);
-
-void CySoftwareReset(void) ;
-
-uint8 CyEnterCriticalSection(void);
-void CyExitCriticalSection(uint8 savedIntrStatus);
-void CyHalt(uint8 reason) CYREENTRANT;
-
-
-/* Interrupt Function Prototypes */
-#if(CY_PSOC5)
-    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)  ;
-    cyisraddress CyIntGetSysVector(uint8 number) ;
-#endif  /* (CY_PSOC5) */
-
-cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ;
-cyisraddress CyIntGetVector(uint8 number) ;
-
-void  CyIntSetPriority(uint8 number, uint8 priority) ;
-uint8 CyIntGetPriority(uint8 number) ;
-
-uint8 CyIntGetState(uint8 number) ;
-
-uint32 CyDisableInts(void) ;
-void CyEnableInts(uint32 mask) ;
-
-
-#if(CY_PSOC5)
-    void CyFlushCache(void);
-#endif  /* (CY_PSOC5) */
-
-
-/* Voltage Detection Function Prototypes */
-void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ;
-void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ;
-void CyVdLvDigitDisable(void) ;
-void CyVdLvAnalogDisable(void) ;
-void CyVdHvAnalogEnable(void) ;
-void CyVdHvAnalogDisable(void) ;
-uint8 CyVdStickyStatus(uint8 mask) ;
-uint8 CyVdRealTimeStatus(void) ;
-
-void CySetScPumps(uint8 enable) ;
-
-#if(CY_PSOC5)
-    /* Default interrupt handler */
-    CY_ISR_PROTO(IntDefaultHandler);
-#endif  /* (CY_PSOC5) */
-
-#if(CY_PSOC5)
-    /* System tick timer APIs */
-    typedef void (*cySysTickCallback)(void);
-
-    void CySysTickStart(void);
-    void CySysTickInit(void);
-    void CySysTickEnable(void);
-    void CySysTickStop(void);
-    void CySysTickEnableInterrupt(void);
-    void CySysTickDisableInterrupt(void);
-    void CySysTickSetReload(uint32 value);
-    uint32 CySysTickGetReload(void);
-    uint32 CySysTickGetValue(void);
-    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
-    cySysTickCallback CySysTickGetCallback(uint32 number);
-    void CySysTickSetClockSource(uint32 clockSource);
-    uint32 CySysTickGetCountFlag(void);
-    void CySysTickClear(void);
-#endif  /* (CY_PSOC5) */
-
-/***************************************
-* API Constants
-***************************************/
-
-
-/*******************************************************************************
-* PLL API Constants
-*******************************************************************************/
-#define CY_CLK_PLL_ENABLE               (0x01u)
-#define CY_CLK_PLL_LOCK_STATUS          (0x01u)
-
-#define CY_CLK_PLL_FTW_INTERVAL         (24u)
-
-#define CY_CLK_PLL_MAX_Q_VALUE          (16u)
-#define CY_CLK_PLL_MIN_Q_VALUE          (1u)
-#define CY_CLK_PLL_MIN_P_VALUE          (8u)
-#define CY_CLK_PLL_MIN_CUR_VALUE        (1u)
-#define CY_CLK_PLL_MAX_CUR_VALUE        (7u)
-
-#define CY_CLK_PLL_CURRENT_POSITION     (4u)
-#define CY_CLK_PLL_CURRENT_MASK         (0x8Fu)
-
-
-/*******************************************************************************
-* External 32kHz Crystal Oscillator API Constants
-*******************************************************************************/
-#define CY_XTAL32K_ANA_STAT             (0x20u)
-
-#define CY_CLK_XTAL32_CR_LPM            (0x02u)
-#define CY_CLK_XTAL32_CR_EN             (0x01u)
-#if(CY_PSOC3)
-    #define CY_CLK_XTAL32_CR_PDBEN      (0x04u)
-#endif  /* (CY_PSOC3) */
-
-#define CY_CLK_XTAL32_TR_MASK           (0x07u)
-#define CY_CLK_XTAL32_TR_STARTUP        (0x03u)
-#define CY_CLK_XTAL32_TR_HIGH_POWER     (0x06u)
-#define CY_CLK_XTAL32_TR_LOW_POWER      (0x01u)
-#define CY_CLK_XTAL32_TR_POWERDOWN      (0x00u)
-
-#define CY_CLK_XTAL32_TST_DEFAULT       (0xF3u)
-
-#define CY_CLK_XTAL32_CFG_LP_DEFAULT    (0x04u)
-#define CY_CLK_XTAL32_CFG_LP_LOWPOWER   (0x08u)
-#define CY_CLK_XTAL32_CFG_LP_MASK       (0x0Cu)
-
-#define CY_CLK_XTAL32_CFG_LP_ALLOW      (0x80u)
-
-
-/*******************************************************************************
-* External MHz Crystal Oscillator API Constants
-*******************************************************************************/
-#define CY_CLK_XMHZ_FTW_INTERVAL        (24u)
-#define CY_CLK_XMHZ_MIN_TIMEOUT         (130u)
-
-#define CY_CLK_XMHZ_CSR_ENABLE          (0x01u)
-#define CY_CLK_XMHZ_CSR_XERR            (0x80u)
-#define CY_CLK_XMHZ_CSR_XFB             (0x04u)
-#define CY_CLK_XMHZ_CSR_XPROT           (0x40u)
-
-#define CY_CLK_XMHZ_CFG0_XCFG_MASK      (0x1Fu)
-#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK   (0x0Fu)
-#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK   (0x70u)
-
-
-/*******************************************************************************
-* Watchdog Timer API Constants
-*******************************************************************************/
-#define CYWDT_2_TICKS               (0x0u)     /*    4 -    6 ms */
-#define CYWDT_16_TICKS              (0x1u)     /*   32 -   48 ms */
-#define CYWDT_128_TICKS             (0x2u)     /*  256 -  384 ms */
-#define CYWDT_1024_TICKS            (0x3u)     /* 2048 - 3072 ms */
-
-#define CYWDT_LPMODE_NOCHANGE       (0x00u)
-#define CYWDT_LPMODE_MAXINTER       (0x01u)
-#define CYWDT_LPMODE_DISABLED       (0x03u)
-
-#define CY_WDT_CFG_INTERVAL_MASK    (0x03u)
-#define CY_WDT_CFG_CTW_RESET        (0x80u)
-#define CY_WDT_CFG_LPMODE_SHIFT     (5u)
-#define CY_WDT_CFG_LPMODE_MASK      (0x60u)
-#define CY_WDT_CFG_WDR_EN           (0x10u)
-#define CY_WDT_CFG_CLEAR_ALL        (0x00u)
-#define CY_WDT_CR_FEED              (0x01u)
-
-
-/*******************************************************************************
-*    Voltage Detection API Constants
-*******************************************************************************/
-
-#define CY_VD_LVID_EN                (0x01u)
-#define CY_VD_LVIA_EN                (0x02u)
-#define CY_VD_HVIA_EN                (0x04u)
-
-#define CY_VD_PRESD_EN               (0x40u)
-#define CY_VD_PRESA_EN               (0x80u)
-
-#define CY_VD_LVID                   (0x01u)
-#define CY_VD_LVIA                   (0x02u)
-#define CY_VD_HVIA                   (0x04u)
-
-#define CY_VD_LVI_TRIP_LVID_MASK     (0x0Fu)
-
-
-/*******************************************************************************
-*    Variable VDDA API Constants
-*******************************************************************************/
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    /* Active Power Mode Configuration Register 9 */
-    #define CY_LIB_ACT_CFG9_SWCAP0_EN        (0x01u)
-    #define CY_LIB_ACT_CFG9_SWCAP1_EN        (0x02u)
-    #define CY_LIB_ACT_CFG9_SWCAP2_EN        (0x04u)
-    #define CY_LIB_ACT_CFG9_SWCAP3_EN        (0x08u)
-    #define CY_LIB_ACT_CFG9_SWCAPS_MASK      (0x0Fu)
-
-    /* Switched Cap Miscellaneous Control Register */
-    #define CY_LIB_SC_MISC_PUMP_FORCE        (0x20u)
-
-    /* Switched Capacitor 0 Boost Clock Selection Register */
-    #define CY_LIB_SC_BST_CLK_EN             (0x08u)
-    #define CY_LIB_SC_BST_CLK_INDEX_MASK     (0xF8u)
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-/*******************************************************************************
-* Clock Distribution API Constants
-*******************************************************************************/
-#define CY_LIB_CLKDIST_AMASK_MASK       (0xF0u)
-#define CY_LIB_CLKDIST_DMASK_MASK       (0x00u)
-#define CY_LIB_CLKDIST_LD_LOAD          (0x01u)
-#define CY_LIB_CLKDIST_BCFG2_MASK       (0x80u)
-#define CY_LIB_CLKDIST_MASTERCLK_DIV    (7u)
-#define CY_LIB_CLKDIST_BCFG2_SSS        (0x40u)
-#define CY_LIB_CLKDIST_MSTR1_SRC_MASK   (0xFCu)
-#define CY_LIB_FASTCLK_IMO_DOUBLER      (0x10u)
-#define CY_LIB_FASTCLK_IMO_IMO          (0x20u)
-#define CY_LIB_CLKDIST_CR_IMO2X         (0x40u)
-#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)
-
-#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK  (0xFCu)
-
-
-/* CyILO_SetPowerMode() */
-#define CY_ILO_CONTROL_PD_MODE          (0x10u)
-#define CY_ILO_CONTROL_PD_POSITION      (4u)
-
-#define CY_ILO_SOURCE_100K              (0u)
-#define CY_ILO_SOURCE_33K               (1u)
-#define CY_ILO_SOURCE_1K                (2u)
-
-#define CY_ILO_FAST_START               (0u)
-#define CY_ILO_SLOW_START               (1u)
-
-#define CY_ILO_SOURCE_BITS_CLEAR        (0xF3u)
-#define CY_ILO_SOURCE_1K_SET            (0x08u)
-#define CY_ILO_SOURCE_33K_SET           (0x04u)
-#define CY_ILO_SOURCE_100K_SET          (0x00u)
-
-#define CY_MASTER_SOURCE_IMO            (0u)
-#define CY_MASTER_SOURCE_PLL            (1u)
-#define CY_MASTER_SOURCE_XTAL           (2u)
-#define CY_MASTER_SOURCE_DSI            (3u)
-
-#define CY_IMO_SOURCE_IMO               (0u)
-#define CY_IMO_SOURCE_XTAL              (1u)
-#define CY_IMO_SOURCE_DSI               (2u)
-
-
-/* CyIMO_Start() */
-#define CY_LIB_PM_ACT_CFG0_IMO_EN       (0x10u)
-#define CY_LIB_PM_STBY_CFG0_IMO_EN      (0x10u)
-#define CY_LIB_CLK_IMO_FTW_TIMEOUT      (0x00u)
-
-#define CY_LIB_IMO_3MHZ_VALUE           (0x03u)
-#define CY_LIB_IMO_6MHZ_VALUE           (0x01u)
-#define CY_LIB_IMO_12MHZ_VALUE          (0x00u)
-#define CY_LIB_IMO_24MHZ_VALUE          (0x02u)
-#define CY_LIB_IMO_48MHZ_VALUE          (0x04u)
-#define CY_LIB_IMO_62MHZ_VALUE          (0x05u)
-#define CY_LIB_IMO_74MHZ_VALUE          (0x06u)
-
-
-/* CyIMO_SetFreq() */
-#define CY_IMO_FREQ_3MHZ                (0u)
-#define CY_IMO_FREQ_6MHZ                (1u)
-#define CY_IMO_FREQ_12MHZ               (2u)
-#define CY_IMO_FREQ_24MHZ               (3u)
-#define CY_IMO_FREQ_48MHZ               (4u)
-#define CY_IMO_FREQ_62MHZ               (5u)
-#if(CY_PSOC5)
-    #define CY_IMO_FREQ_74MHZ           (6u)
-#endif  /* (CY_PSOC5) */
-#define CY_IMO_FREQ_USB                 (8u)
-
-#define CY_LIB_IMO_USBCLK_ON_SET        (0x40u)
-
-
-/* CyCpuClk_SetDivider() */
-#define CY_LIB_CLKDIST_DIV_POSITION     (4u)
-#define CY_LIB_CLKDIST_MSTR1_DIV_MASK   (0x0Fu)
-
-
-/* CyIMO_SetTrimValue() */
-#define CY_LIB_USB_CLK_EN               (0x02u)
-
-
-/* CyPLL_OUT_SetSource() - parameters */
-#define CY_PLL_SOURCE_IMO               (0u)
-#define CY_PLL_SOURCE_XTAL              (1u)
-#define CY_PLL_SOURCE_DSI               (2u)
-
-
-/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */
-#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ   (0x02u)
-#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ  (0x20u)
-#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)
-
-
-/* CyUsbClk_SetSource() */
-#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)
-
-
-/* CyUsbClk_SetSource() - parameters */
-#define CY_LIB_USB_CLK_IMO2X            (0x00u)
-#define CY_LIB_USB_CLK_IMO              (0x01u)
-#define CY_LIB_USB_CLK_PLL              (0x02u)
-#define CY_LIB_USB_CLK_DSI              (0x03u)
-
-
-/* CyUSB_PowerOnCheck() */
-#define CY_ACT_USB_ENABLED              (0x01u)
-#define CY_ALT_ACT_USB_ENABLED          (0x01u)
-
-
-#if(CY_PSOC5)
-
-    /***************************************************************************
-    * Instruction Synchronization Barrier flushes the pipeline in the processor,
-    * so that all instructions following the ISB are fetched from cache or
-    * memory, after the instruction has been completed.
-    ***************************************************************************/
-
-    #if defined(__ARMCC_VERSION)
-        #define CY_SYS_ISB       __isb(0x0f)
-    #else   /* ASM for GCC & IAR */
-        #define CY_SYS_ISB       asm volatile ("isb \n")
-    #endif /* (__ARMCC_VERSION) */
-
-#endif /* (CY_PSOC5) */
-
-
-/***************************************
-* Registers
-***************************************/
-
-
-/*******************************************************************************
-* System Registers
-*******************************************************************************/
-
-/* Software Reset Control Register */
-#define CY_LIB_RESET_CR2_REG         (* (reg8 *) CYREG_RESET_CR2)
-#define CY_LIB_RESET_CR2_PTR         (  (reg8 *) CYREG_RESET_CR2)
-
-/* Timewheel Configuration Register 0 */
-#define CY_LIB_PM_TW_CFG0_REG           (*(reg8 *) CYREG_PM_TW_CFG0)
-#define CY_LIB_PM_TW_CFG0_PTR           ( (reg8 *) CYREG_PM_TW_CFG0)
-
-/* Timewheel Configuration Register 2 */
-#define CY_LIB_PM_TW_CFG2_REG           (*(reg8 *) CYREG_PM_TW_CFG2)
-#define CY_LIB_PM_TW_CFG2_PTR           ( (reg8 *) CYREG_PM_TW_CFG2)
-
-/* USB Configuration Register */
-#define CY_LIB_CLKDIST_UCFG_REG         (*(reg8 *) CYREG_CLKDIST_UCFG)
-#define CY_LIB_CLKDIST_UCFG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
-
-/* Internal Main Oscillator Trim Register 1 */
-#define CY_LIB_IMO_TR1_REG              (*(reg8 *) CYREG_IMO_TR1)
-#define CY_LIB_IMO_TR1_PTR              ( (reg8 *) CYREG_IMO_TR1)
-
-/* USB control 1 Register */
-#define CY_LIB_USB_CR1_REG              (*(reg8 *) CYREG_USB_CR1 )
-#define CY_LIB_USB_CR1_PTR              ( (reg8 *) CYREG_USB_CR1 )
-
-/* Active Power Mode Configuration Register 0 */
-#define CY_LIB_PM_ACT_CFG0_REG          (*(reg8 *) CYREG_PM_ACT_CFG0)
-#define CY_LIB_PM_ACT_CFG0_PTR          ( (reg8 *) CYREG_PM_ACT_CFG0)
-
-/* Standby Power Mode Configuration Register 0 */
-#define CY_LIB_PM_STBY_CFG0_REG          (*(reg8 *) CYREG_PM_STBY_CFG0)
-#define CY_LIB_PM_STBY_CFG0_PTR          ( (reg8 *) CYREG_PM_STBY_CFG0)
-
-/* Active Power Mode Configuration Register 5 */
-#define CY_LIB_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
-#define CY_LIB_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
-
-/* Standby Power Mode Configuration Register 5 */
-#define CY_LIB_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
-#define CY_LIB_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
-
-/* CyIMO_SetTrimValue() */
-#if(CY_PSOC3)
-    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define CY_LIB_TRIM_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
-    #define CY_LIB_TRIM_IMO_TR1_PTR          ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
- #else
-    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define CY_LIB_TRIM_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
-    #define CY_LIB_TRIM_IMO_TR1_PTR          ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
-#endif  /* (CY_PSOC3) */
-
-
-/*******************************************************************************
-* PLL Registers
-*******************************************************************************/
-
-/* PLL Configuration Register 0 */
-#define CY_CLK_PLL_CFG0_REG         (*(reg8 *) CYREG_FASTCLK_PLL_CFG0)
-#define CY_CLK_PLL_CFG0_PTR         ( (reg8 *) CYREG_FASTCLK_PLL_CFG0)
-
-/* PLL Configuration Register 1 */
-#define CY_CLK_PLL_CFG1_REG         (*(reg8 *) CYREG_FASTCLK_PLL_CFG1)
-#define CY_CLK_PLL_CFG1_PTR         ( (reg8 *) CYREG_FASTCLK_PLL_CFG1)
-
-/* PLL Status Register */
-#define CY_CLK_PLL_SR_REG           (*(reg8 *) CYREG_FASTCLK_PLL_SR)
-#define CY_CLK_PLL_SR_PTR           ( (reg8 *) CYREG_FASTCLK_PLL_SR)
-
-/* PLL Q-Counter Configuration Register */
-#define CY_CLK_PLL_Q_REG            (*(reg8 *) CYREG_FASTCLK_PLL_Q)
-#define CY_CLK_PLL_Q_PTR            ( (reg8 *) CYREG_FASTCLK_PLL_Q)
-
-/* PLL P-Counter Configuration Register */
-#define CY_CLK_PLL_P_REG            (*(reg8 *) CYREG_FASTCLK_PLL_P)
-#define CY_CLK_PLL_P_PTR            ( (reg8 *) CYREG_FASTCLK_PLL_P)
-
-
-/*******************************************************************************
-* External MHz Crystal Oscillator Registers
-*******************************************************************************/
-
-/* External MHz Crystal Oscillator Status and Control Register */
-#define CY_CLK_XMHZ_CSR_REG         (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
-#define CY_CLK_XMHZ_CSR_PTR         ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
-
-/* External MHz Crystal Oscillator Configuration Register 0 */
-#define CY_CLK_XMHZ_CFG0_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
-#define CY_CLK_XMHZ_CFG0_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
-
-/* External MHz Crystal Oscillator Configuration Register 1 */
-#define CY_CLK_XMHZ_CFG1_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
-#define CY_CLK_XMHZ_CFG1_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
-
-
-/*******************************************************************************
-* External 32kHz Crystal Oscillator Registers
-*******************************************************************************/
-
-/* 32 kHz Watch Crystal Oscillator Trim Register */
-#define CY_CLK_XTAL32_TR_REG        (*(reg8 *) CYREG_X32_TR)
-#define CY_CLK_XTAL32_TR_PTR        ( (reg8 *) CYREG_X32_TR)
-
-/* External 32kHz Crystal Oscillator Test Register */
-#define CY_CLK_XTAL32_TST_REG       (*(reg8 *) CYREG_SLOWCLK_X32_TST)
-#define CY_CLK_XTAL32_TST_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_TST)
-
-/* External 32kHz Crystal Oscillator Control Register */
-#define CY_CLK_XTAL32_CR_REG        (*(reg8 *) CYREG_SLOWCLK_X32_CR)
-#define CY_CLK_XTAL32_CR_PTR        ( (reg8 *) CYREG_SLOWCLK_X32_CR)
-
-/* External 32kHz Crystal Oscillator Configuration Register */
-#define CY_CLK_XTAL32_CFG_REG       (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
-#define CY_CLK_XTAL32_CFG_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
-
-
-/*******************************************************************************
-* Watchdog Timer Registers
-*******************************************************************************/
-
-/* Watchdog Timer Configuration Register */
-#define CY_WDT_CFG_REG              (*(reg8 *) CYREG_PM_WDT_CFG)
-#define CY_WDT_CFG_PTR              ( (reg8 *) CYREG_PM_WDT_CFG)
-
-/* Watchdog Timer Control Register */
-#define CY_WDT_CR_REG               (*(reg8 *) CYREG_PM_WDT_CR)
-#define CY_WDT_CR_PTR               ( (reg8 *) CYREG_PM_WDT_CR)
-
-
-/*******************************************************************************
-*    LVI/HVI Registers
-*******************************************************************************/
-
-#define CY_VD_LVI_TRIP_REG          (* (reg8 *) CYREG_RESET_CR0)
-#define CY_VD_LVI_TRIP_PTR          (  (reg8 *) CYREG_RESET_CR0)
-
-#define CY_VD_LVI_HVI_CONTROL_REG   (* (reg8 *) CYREG_RESET_CR1)
-#define CY_VD_LVI_HVI_CONTROL_PTR   (  (reg8 *) CYREG_RESET_CR1)
-
-#define CY_VD_PRES_CONTROL_REG      (* (reg8 *) CYREG_RESET_CR3)
-#define CY_VD_PRES_CONTROL_PTR      (  (reg8 *) CYREG_RESET_CR3)
-
-#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0)
-#define CY_VD_PERSISTENT_STATUS_PTR (  (reg8 *) CYREG_RESET_SR0)
-
-#define CY_VD_RT_STATUS_REG         (* (reg8 *) CYREG_RESET_SR2)
-#define CY_VD_RT_STATUS_PTR         (  (reg8 *) CYREG_RESET_SR2)
-
-
-/*******************************************************************************
-*    Variable VDDA
-*******************************************************************************/
-#if(CYDEV_VARIABLE_VDDA == 1)
-
-    /* Active Power Mode Configuration Register 9 */
-    #define CY_LIB_ACT_CFG9_REG            (* (reg8 *) CYREG_PM_ACT_CFG9 )
-    #define CY_LIB_ACT_CFG9_PTR            (  (reg8 *) CYREG_PM_ACT_CFG9 )
-
-    /* Switched Capacitor 0 Boost Clock Selection Register */
-    #define CY_LIB_SC0_BST_REG             (* (reg8 *) CYREG_SC0_BST )
-    #define CY_LIB_SC0_BST_PTR             (  (reg8 *) CYREG_SC0_BST )
-
-    /* Switched Capacitor 1 Boost Clock Selection Register */
-    #define CY_LIB_SC1_BST_REG             (* (reg8 *) CYREG_SC1_BST )
-    #define CY_LIB_SC1_BST_PTR             (  (reg8 *) CYREG_SC1_BST )
-
-    /* Switched Capacitor 2 Boost Clock Selection Register */
-    #define CY_LIB_SC2_BST_REG             (* (reg8 *) CYREG_SC2_BST )
-    #define CY_LIB_SC2_BST_PTR             (  (reg8 *) CYREG_SC2_BST )
-
-    /* Switched Capacitor 3 Boost Clock Selection Register */
-    #define CY_LIB_SC3_BST_REG             (* (reg8 *) CYREG_SC3_BST )
-    #define CY_LIB_SC3_BST_PTR             (  (reg8 *) CYREG_SC3_BST )
-
-    /* Switched Cap Miscellaneous Control Register */
-    #define CY_LIB_SC_MISC_REG             (* (reg8 *) CYREG_SC_MISC )
-    #define CY_LIB_SC_MISC_PTR             (  (reg8 *) CYREG_SC_MISC )
-
-#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-
-/*******************************************************************************
-*    Clock Distribution Registers
-*******************************************************************************/
-
-/* Analog Clock Mask Register */
-#define CY_LIB_CLKDIST_AMASK_REG       (* (reg8 *) CYREG_CLKDIST_AMASK )
-#define CY_LIB_CLKDIST_AMASK_PTR       (  (reg8 *) CYREG_CLKDIST_AMASK )
-
-/* Digital Clock Mask Register */
-#define CY_LIB_CLKDIST_DMASK_REG        (*(reg8 *) CYREG_CLKDIST_DMASK)
-#define CY_LIB_CLKDIST_DMASK_PTR        ( (reg8 *) CYREG_CLKDIST_DMASK)
-
-/* CLK_BUS Configuration Register */
-#define CY_LIB_CLKDIST_BCFG2_REG        (*(reg8 *) CYREG_CLKDIST_BCFG2)
-#define CY_LIB_CLKDIST_BCFG2_PTR        ( (reg8 *) CYREG_CLKDIST_BCFG2)
-
-/* LSB Shadow Divider Value Register */
-#define CY_LIB_CLKDIST_WRK_LSB_REG      (*(reg8 *) CYREG_CLKDIST_WRK0)
-#define CY_LIB_CLKDIST_WRK_LSB_PTR      ( (reg8 *) CYREG_CLKDIST_WRK0)
-
-/* MSB Shadow Divider Value Register */
-#define CY_LIB_CLKDIST_WRK_MSB_REG      (*(reg8 *) CYREG_CLKDIST_WRK1)
-#define CY_LIB_CLKDIST_WRK_MSB_PTR      ( (reg8 *) CYREG_CLKDIST_WRK1)
-
-/* LOAD Register */
-#define CY_LIB_CLKDIST_LD_REG           (*(reg8 *) CYREG_CLKDIST_LD)
-#define CY_LIB_CLKDIST_LD_PTR           ( (reg8 *) CYREG_CLKDIST_LD)
-
-/* CLK_BUS LSB Divider Value Register */
-#define CY_LIB_CLKDIST_BCFG_LSB_REG     (*(reg8 *) CYREG_CLKDIST_BCFG0)
-#define CY_LIB_CLKDIST_BCFG_LSB_PTR     ( (reg8 *) CYREG_CLKDIST_BCFG0)
-
-/* CLK_BUS MSB Divider Value Register */
-#define CY_LIB_CLKDIST_BCFG_MSB_REG     (*(reg8 *) CYREG_CLKDIST_BCFG1)
-#define CY_LIB_CLKDIST_BCFG_MSB_PTR     ( (reg8 *) CYREG_CLKDIST_BCFG1)
-
-/* Master clock (clk_sync_d) Divider Value Register */
-#define CY_LIB_CLKDIST_MSTR0_REG        (*(reg8 *) CYREG_CLKDIST_MSTR0)
-#define CY_LIB_CLKDIST_MSTR0_PTR        ( (reg8 *) CYREG_CLKDIST_MSTR0)
-
-/* Master (clk_sync_d) Configuration Register/CPU Divider Value */
-#define CY_LIB_CLKDIST_MSTR1_REG        (*(reg8 *) CYREG_CLKDIST_MSTR1)
-#define CY_LIB_CLKDIST_MSTR1_PTR        ( (reg8 *) CYREG_CLKDIST_MSTR1)
-
-/* Internal Main Oscillator Control Register */
-#define CY_LIB_FASTCLK_IMO_CR_REG       (*(reg8 *) CYREG_FASTCLK_IMO_CR)
-#define CY_LIB_FASTCLK_IMO_CR_PTR       ( (reg8 *) CYREG_FASTCLK_IMO_CR)
-
-/* Configuration Register CR */
-#define CY_LIB_CLKDIST_CR_REG           (*(reg8 *) CYREG_CLKDIST_CR)
-#define CY_LIB_CLKDIST_CR_PTR           ( (reg8 *) CYREG_CLKDIST_CR)
-
-/* Internal Low-speed Oscillator Control Register 0 */
-#define CY_LIB_SLOWCLK_ILO_CR0_REG      (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
-#define CY_LIB_SLOWCLK_ILO_CR0_PTR      ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
-
-
-/*******************************************************************************
-* Interrupt Registers
-*******************************************************************************/
-
-#if(CY_PSOC5)
-
-    /* Interrupt Vector Table Offset */
-    #define CY_INT_VECT_TABLE           ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-
-    /* Interrupt Priority 0-31 */
-    #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_NVIC_PRI_0)
-    #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_NVIC_PRI_0)
-
-    /* Interrupt Enable Set 0-31 */
-    #define CY_INT_ENABLE_REG           (* (reg32 *) CYREG_NVIC_SETENA0)
-    #define CY_INT_ENABLE_PTR           (  (reg32 *) CYREG_NVIC_SETENA0)
-
-    /* Interrupt Enable Clear 0-31 */
-    #define CY_INT_CLEAR_REG            (* (reg32 *) CYREG_NVIC_CLRENA0)
-    #define CY_INT_CLEAR_PTR            (  (reg32 *) CYREG_NVIC_CLRENA0)
-
-    /* Interrupt Pending Set 0-31 */
-    #define CY_INT_SET_PEND_REG         (* (reg32 *) CYREG_NVIC_SETPEND0)
-    #define CY_INT_SET_PEND_PTR         (  (reg32 *) CYREG_NVIC_SETPEND0)
-
-    /* Interrupt Pending Clear 0-31 */
-    #define CY_INT_CLR_PEND_REG         (* (reg32 *) CYREG_NVIC_CLRPEND0)
-    #define CY_INT_CLR_PEND_PTR         (  (reg32 *) CYREG_NVIC_CLRPEND0)
-
-    /* Cache Control Register */
-    #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
-    #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
-
-    /* System tick registers */
-    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
-    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
-
-    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
-    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
-
-    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
-    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
-
-    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
-    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
-
-#elif (CY_PSOC3)
-
-    /* Interrupt Address Vector registers */
-    #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
-
-    /* Interrupt Controller Priority Registers */
-    #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
-    #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
-
-    /* Interrupt Controller Set Enable Registers */
-    #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
-    #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
-
-    #define CY_INT_SET_EN0_REG          (* (reg8 *) CYREG_INTC_SET_EN0)
-    #define CY_INT_SET_EN0_PTR          (  (reg8 *) CYREG_INTC_SET_EN0)
-
-    #define CY_INT_SET_EN1_REG          (* (reg8 *) CYREG_INTC_SET_EN1)
-    #define CY_INT_SET_EN1_PTR          (  (reg8 *) CYREG_INTC_SET_EN1)
-
-    #define CY_INT_SET_EN2_REG          (* (reg8 *) CYREG_INTC_SET_EN2)
-    #define CY_INT_SET_EN2_PTR          (  (reg8 *) CYREG_INTC_SET_EN2)
-
-    #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
-    #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
-
-    /* Interrupt Controller Clear Enable Registers */
-    #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
-    #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
-
-    #define CY_INT_CLR_EN0_REG          (* (reg8 *) CYREG_INTC_CLR_EN0)
-    #define CY_INT_CLR_EN0_PTR          (  (reg8 *) CYREG_INTC_CLR_EN0)
-
-    #define CY_INT_CLR_EN1_REG          (* (reg8 *) CYREG_INTC_CLR_EN1)
-    #define CY_INT_CLR_EN1_PTR          (  (reg8 *) CYREG_INTC_CLR_EN1)
-
-    #define CY_INT_CLR_EN2_REG          (* (reg8 *) CYREG_INTC_CLR_EN2)
-    #define CY_INT_CLR_EN2_PTR          (  (reg8 *) CYREG_INTC_CLR_EN2)
-
-    #define CY_INT_CLR_EN3_REG          (* (reg8 *) CYREG_INTC_CLR_EN3)
-    #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
-
-
-    /* Interrupt Controller Set Pend Registers */
-    #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
-    #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
-
-    /* Interrupt Controller Clear Pend Registers */
-    #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
-    #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
-
-
-    /* Access Interrupt Controller Registers based on interrupt number */
-    #define CY_INT_SET_EN_INDX_PTR(number)    ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
-    #define CY_INT_CLR_EN_INDX_PTR(number)    ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
-    #define CY_INT_CLR_PEND_INDX_PTR(number)  ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
-    #define CY_INT_SET_PEND_INDX_PTR(number)  ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
-
-#endif  /* (CY_PSOC5) */
-
-
-/*******************************************************************************
-* Macro Name: CyAssert
-********************************************************************************
-* Summary:
-*  The macro that evaluates the expression and if it is false (evaluates to 0)
-*  then the processor is halted.
-*
-*  This macro is evaluated unless NDEBUG is defined.
-*
-*  If NDEBUG is defined, then no code is generated for this macro. NDEBUG is
-*  defined by default for a Release build setting and not defined for a Debug
-*  build setting.
-*
-* Parameters:
-*  expr: Logical expression.  Asserts if false.
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-#if !defined(NDEBUG)
-    #define CYASSERT(x)     { \
-                                if(!(x)) \
-                                { \
-                                    CyHalt((uint8) 0u); \
-                                } \
-                            }
-#else
-    #define CYASSERT(x)
-#endif /* !defined(NDEBUG) */
-
-
-/* Reset register fields of RESET_SR0 (CyResetStatus) */
-#define CY_RESET_LVID               (0x01u)
-#define CY_RESET_LVIA               (0x02u)
-#define CY_RESET_HVIA               (0x04u)
-#define CY_RESET_WD                 (0x08u)
-#define CY_RESET_SW                 (0x20u)
-#define CY_RESET_GPIO0              (0x40u)
-#define CY_RESET_GPIO1              (0x80u)
-
-
-/* Interrupt Controller Configuration and Status Register */
-#if(CY_PSOC3)
-    #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
-    #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
-    #define INTERRUPT_DISABLE_IRQ       {*INTERRUPT_CSR |= DISABLE_IRQ_SET;}
-    #define INTERRUPT_ENABLE_IRQ        {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);}
-#endif  /* (CY_PSOC3) */
-
-
-#if defined(__ARMCC_VERSION)
-    #define CyGlobalIntEnable           {__enable_irq();}
-    #define CyGlobalIntDisable          {__disable_irq();}
-#elif defined(__GNUC__) || defined (__ICCARM__)
-    #define CyGlobalIntEnable           {__asm("CPSIE   i");}
-    #define CyGlobalIntDisable          {__asm("CPSID   i");}
-#elif defined(__C51__)
-    #define CyGlobalIntEnable           {\
-                                            EA = 1u; \
-                                            INTERRUPT_ENABLE_IRQ\
-                                        }
-
-    #define CyGlobalIntDisable          {\
-                                            INTERRUPT_DISABLE_IRQ; \
-                                            CY_NOP; \
-                                            EA = 0u;\
-                                        }
-#else
-    #error No compiler toolchain defined
-    #define CyGlobalIntEnable
-    #define CyGlobalIntDisable
-#endif  /* (__ARMCC_VERSION) */
-
-
-#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR
-    #define CYDEV_HALT_CPU      CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u)
-#else
-    #define CYDEV_HALT_CPU      CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u)
-#endif  /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */
-
-
-#ifdef CYREG_MLOGIC_REV_ID_REV_ID
-    #define CYDEV_CHIP_REV_ACTUAL       (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID))
-#else
-    #define CYDEV_CHIP_REV_ACTUAL       (CY_GET_REG8(CYREG_MLOGIC_REV_ID))
-#endif  /* (CYREG_MLOGIC_REV_ID_REV_ID) */
-
-
-/*******************************************************************************
-* System API constants
-*******************************************************************************/
-#define CY_CACHE_CONTROL_FLUSH          (0x0004u)
-#define CY_LIB_RESET_CR2_RESET          (0x01u)
-
-#if(CY_PSOC5)
-    /* System tick API constants */
-    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
-    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
-    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
-    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
-    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
-    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
-    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
-    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
-#endif /* (CY_PSOC5) */
-
-
-
-/*******************************************************************************
-* Interrupt API constants
-*******************************************************************************/
-#if(CY_PSOC5)
-
-    #define CY_INT_IRQ_BASE             (16u)
-
-#elif (CY_PSOC3)
-
-    #define CY_INT_IRQ_BASE             (0u)
-
-#endif  /* (CY_PSOC5) */
-
-/* Valid range of interrupt 0-31 */
-#define CY_INT_NUMBER_MAX               (31u)
-
-/* Valid range of system interrupt 0-15 */
-#define CY_INT_SYS_NUMBER_MAX           (15u)
-
-/* Valid range of system priority 0-7 */
-#define CY_INT_PRIORITY_MAX             (7u)
-
-/* Mask to get valid range of interrupt 0-31 */
-#define CY_INT_NUMBER_MASK              (0x1Fu)
-
-/* Mask to get valid range of system priority 0-7 */
-#define CY_INT_PRIORITY_MASK            (0x7u)
-
-/* Mask to get valid range of system interrupt 0-15 */
-#define CY_INT_SYS_NUMBER_MASK          (0xFu)
-
-#if(CY_PSOC5)
-
-    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
-    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
-    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
-    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
-    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
-    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
-    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
-    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
-    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
-    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
-
-#endif  /* (CY_PSOC5) */
-
-/*******************************************************************************
-* Interrupt Macros
-*******************************************************************************/
-
-#if(CY_PSOC5)
-
-    /*******************************************************************************
-    * Macro Name: CyIntEnable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enables the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntEnable(number)     CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
-
-    /*******************************************************************************
-    * Macro Name: CyIntDisable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Disables the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntDisable(number)     CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntSetPending
-    ********************************************************************************
-    *
-    * Summary:
-    *   Forces the specified interrupt number to be pending.
-    *
-    * Parameters:
-    *   number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntSetPending(number)     CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntClearPending
-    ********************************************************************************
-    *
-    * Summary:
-    *   Clears any pending interrupt for the specified interrupt number.
-    *
-    * Parameters:
-    *   number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntClearPending(number)   CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
-
-
-#else   /* PSoC3 */
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntEnable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enables the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntEnable(number)   CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \
-                                          ((uint8)(1u << (0x07u & (number)))))
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntDisable
-    ********************************************************************************
-    *
-    * Summary:
-    *  Disables the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntDisable(number)   CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \
-                                          ((uint8)(1u << (0x07u & (number)))))
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntSetPending
-    ********************************************************************************
-    *
-    * Summary:
-    *  Forces the specified interrupt number to be pending.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntSetPending(number)   CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \
-                                                  ((uint8)(1u << (0x07u & (number)))))
-
-
-    /*******************************************************************************
-    * Macro Name: CyIntClearPending
-    ********************************************************************************
-    * Summary:
-    *  Clears any pending interrupt for the specified interrupt number.
-    *
-    * Parameters:
-    *  number: Valid range [0-31].  Interrupt number.
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    #define CyIntClearPending(number)   CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \
-                                                    ((uint8)(1u << (0x07u & (number)))))
-
-#endif  /* (CY_PSOC5) */
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used.
-*
-* If the obsoleted macro definitions intended for use in the application use the
-* following scheme, redefine your own versions of these definitions:
-*    #ifdef <OBSOLETED_DEFINE>
-*        #undef  <OBSOLETED_DEFINE>
-*        #define <OBSOLETED_DEFINE>      (<New Value>)
-*    #endif
-*
-* Note: Redefine obsoleted macro definitions with caution. They might still be
-*       used in the application and their modification might lead to unexpected
-*       consequences.
-*******************************************************************************/
-
-#define CYGlobalIntEnable       CyGlobalIntEnable
-#define CYGlobalIntDisable      CyGlobalIntDisable
-
-#define cymemset(s,c,n)         memset((s),(c),(n))
-#define cymemcpy(d,s,n)         memcpy((d),(s),(n))
-
-#define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
-#define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
-#define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
-#define SLOWCLK_X32_TST                 (CY_CLK_XTAL32_TST_REG)
-#define SLOWCLK_X32_CR_PTR              (CY_CLK_XTAL32_CR_PTR)
-#define SLOWCLK_X32_CR                  (CY_CLK_XTAL32_CR_REG)
-#define SLOWCLK_X32_CFG_PTR             (CY_CLK_XTAL32_CFG_PTR)
-#define SLOWCLK_X32_CFG                 (CY_CLK_XTAL32_CFG_REG)
-
-#define X32_CONTROL_ANA_STAT            (CY_CLK_XTAL32_CR_ANA_STAT)
-#define X32_CONTROL_DIG_STAT            (0x10u)
-#define X32_CONTROL_LPM                 (CY_CLK_XTAL32_CR_LPM)
-#define X32_CONTROL_LPM_POSITION        (1u)
-#define X32_CONTROL_X32EN               (CY_CLK_XTAL32_CR_EN)
-#define X32_CONTROL_PDBEN           (CY_CLK_XTAL32_CR_PDBEN)
-#define X32_TR_DPMODE                   (CY_CLK_XTAL32_TR_STARTUP)
-#define X32_TR_CLEAR                    (CY_CLK_XTAL32_TR_POWERDOWN)
-#define X32_TR_HPMODE                   (CY_CLK_XTAL32_TR_HIGH_POWER)
-#define X32_TR_LPMODE                   (CY_CLK_XTAL32_TR_LOW_POWER)
-#define X32_TST_SETALL                  (CY_CLK_XTAL32_TST_DEFAULT)
-#define X32_CFG_LP_BITS_MASK            (CY_CLK_XTAL32_CFG_LP_MASK)
-#define X32_CFG_LP_DEFAULT              (CY_CLK_XTAL32_CFG_LP_DEFAULT)
-#define X32_CFG_LOWPOWERMODE            (0x80u)
-#define X32_CFG_LP_LOWPOWER             (0x8u)
-#define CY_X32_HIGHPOWER_MODE           (0u)
-#define CY_X32_LOWPOWER_MODE            (1u)
-#define CY_XTAL32K_DIG_STAT             (0x10u)
-#define CY_XTAL32K_STAT_FIELDS          (0x30u)
-#define CY_XTAL32K_DIG_STAT_UNSTABLE    (0u)
-#define CY_XTAL32K_ANA_STAT_UNSTABLE    (0x0u)
-#define CY_XTAL32K_STATUS               (0x20u)
-
-#define FASTCLK_XMHZ_CSR_PTR            (CY_CLK_XMHZ_CSR_PTR)
-#define FASTCLK_XMHZ_CSR                (CY_CLK_XMHZ_CSR_REG)
-#define FASTCLK_XMHZ_CFG0_PTR           (CY_CLK_XMHZ_CFG0_PTR)
-#define FASTCLK_XMHZ_CFG0               (CY_CLK_XMHZ_CFG0_REG)
-#define FASTCLK_XMHZ_CFG1_PTR           (CY_CLK_XMHZ_CFG1_PTR)
-#define FASTCLK_XMHZ_CFG1               (CY_CLK_XMHZ_CFG1_REG)
-#define FASTCLK_XMHZ_GAINMASK           (CY_CLK_XMHZ_CFG0_XCFG_MASK)
-#define FASTCLK_XMHZ_VREFMASK           (CY_CLK_XMHZ_CFG1_VREF_FB_MASK)
-#define FASTCLK_XMHZ_VREF_WD_MASK       (CY_CLK_XMHZ_CFG1_VREF_WD_MASK)
-#define XMHZ_CONTROL_ENABLE             (CY_CLK_XMHZ_CSR_ENABLE)
-#define X32_CONTROL_XERR_MASK           (CY_CLK_XMHZ_CSR_XERR)
-#define X32_CONTROL_XERR_DIS            (CY_CLK_XMHZ_CSR_XFB)
-#define X32_CONTROL_XERR_POSITION       (7u)
-#define X32_CONTROL_FAULT_RECOVER       (CY_CLK_XMHZ_CSR_XPROT)
-
-#define CYWDT_CFG                       (CY_WDT_CFG_PTR)
-#define CYWDT_CR                        (CY_WDT_CR_PTR)
-
-#define CYWDT_TICKS_MASK                (CY_WDT_CFG_INTERVAL_MASK)
-#define CYWDT_RESET                     (CY_WDT_CFG_CTW_RESET)
-#define CYWDT_LPMODE_SHIFT              (CY_WDT_CFG_LPMODE_SHIFT)
-#define CYWDT_LPMODE_MASK               (CY_WDT_CFG_LPMODE_MASK)
-#define CYWDT_ENABLE_BIT                (CY_WDT_CFG_WDR_EN)
-
-#define FASTCLK_PLL_CFG0_PTR            (CY_CLK_PLL_CFG0_PTR)
-#define FASTCLK_PLL_CFG0                (CY_CLK_PLL_CFG0_REG)
-#define FASTCLK_PLL_SR_PTR              (CY_CLK_PLL_SR_PTR)
-#define FASTCLK_PLL_SR                  (CY_CLK_PLL_SR_REG)
-
-#define MAX_FASTCLK_PLL_Q_VALUE         (CY_CLK_PLL_MAX_Q_VALUE)
-#define MIN_FASTCLK_PLL_Q_VALUE         (CY_CLK_PLL_MIN_Q_VALUE)
-#define MIN_FASTCLK_PLL_P_VALUE         (CY_CLK_PLL_MIN_P_VALUE)
-#define MIN_FASTCLK_PLL_CUR_VALUE       (CY_CLK_PLL_MIN_CUR_VALUE)
-#define MAX_FASTCLK_PLL_CUR_VALUE       (CY_CLK_PLL_MAX_CUR_VALUE)
-
-#define PLL_CONTROL_ENABLE              (CY_CLK_PLL_ENABLE)
-#define PLL_STATUS_LOCK                 (CY_CLK_PLL_LOCK_STATUS)
-#define PLL_STATUS_ENABLED              (CY_CLK_PLL_ENABLE)
-#define PLL_CURRENT_POSITION            (CY_CLK_PLL_CURRENT_POSITION)
-#define PLL_VCO_GAIN_2                  (2u)
-
-#define FASTCLK_PLL_Q_PTR              (CY_CLK_PLL_Q_PTR)
-#define FASTCLK_PLL_Q                  (CY_CLK_PLL_Q_REG)
-#define FASTCLK_PLL_P_PTR              (CY_CLK_PLL_P_PTR)
-#define FASTCLK_PLL_P                  (CY_CLK_PLL_P_REG)
-#define FASTCLK_PLL_CFG1_PTR           (CY_CLK_PLL_CFG1_REG)
-#define FASTCLK_PLL_CFG1               (CY_CLK_PLL_CFG1_REG)
-
-#define CY_VD_PRESISTENT_STATUS_REG    (CY_VD_PERSISTENT_STATUS_REG)
-#define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
-
-
-#if(CY_PSOC5)
-
-    #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
-
-    #define CYINT_VECT_TABLE    (CY_INT_VECT_TABLE)
-    #define CYINT_PRIORITY      (CY_INT_PRIORITY_PTR)
-    #define CYINT_ENABLE        (CY_INT_ENABLE_PTR)
-    #define CYINT_CLEAR         (CY_INT_CLEAR_PTR)
-    #define CYINT_SET_PEND      (CY_INT_SET_PEND_PTR)
-    #define CYINT_CLR_PEND      (CY_INT_CLR_PEND_PTR)
-    #define CACHE_CC_CTL        (CY_CACHE_CONTROL_PTR)
-
-#elif (CY_PSOC3)
-
-    #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
-
-    #define CYINT_VECT_TABLE    (CY_INT_VECT_TABLE)
-    #define CYINT_PRIORITY      (CY_INT_PRIORITY_PTR)
-    #define CYINT_ENABLE        (CY_INT_ENABLE_PTR)
-    #define CYINT_CLEAR         (CY_INT_CLEAR_PTR)
-    #define CYINT_SET_PEND      (CY_INT_SET_PEND_PTR)
-    #define CYINT_CLR_PEND      (CY_INT_CLR_PEND_PTR)
-
-#endif  /* (CY_PSOC5) */
-
-
-
-#define BUS_AMASK_CLEAR                 (0xF0u)
-#define BUS_DMASK_CLEAR                 (0x00u)
-#define CLKDIST_LD_LOAD_SET             (0x01u)
-#define CLKDIST_WRK0_MASK_SET           (0x80u) /* Enable shadow loads */
-#define MASTERCLK_DIVIDER_VALUE         (7u)
-#define CLKDIST_BCFG2_SSS_SET           (0x40u) /* Sync source is same frequency */
-#define MASTER_CLK_SRC_CLEAR            (0xFCu)
-#define IMO_DOUBLER_ENABLE              (0x10u)
-#define CLOCK_IMO_IMO                   (0x20u)
-#define CLOCK_IMO2X_XTAL                (0x40u)
-#define CLOCK_IMO_RANGE_CLEAR           (0xF8u)
-#define CLOCK_CONTROL_DIST_MASK         (0xFCu)
-
-
-#define CLKDIST_AMASK                  (*(reg8 *) CYREG_CLKDIST_AMASK)
-#define CLKDIST_AMASK_PTR              ( (reg8 *) CYREG_CLKDIST_AMASK)
-#define CLKDIST_DMASK_PTR              ( (reg8 *) CYREG_CLKDIST_DMASK)
-#define CLKDIST_DMASK                  (*(reg8 *) CYREG_CLKDIST_DMASK)
-#define CLKDIST_BCFG2_PTR              ( (reg8 *) CYREG_CLKDIST_BCFG2)
-#define CLKDIST_BCFG2                  (*(reg8 *) CYREG_CLKDIST_BCFG2)
-#define CLKDIST_WRK0_PTR               ( (reg8 *) CYREG_CLKDIST_WRK0)
-#define CLKDIST_WRK0                   (*(reg8 *) CYREG_CLKDIST_WRK0)
-#define CLKDIST_LD_PTR                 ( (reg8 *) CYREG_CLKDIST_LD)
-#define CLKDIST_LD                     (*(reg8 *) CYREG_CLKDIST_LD)
-#define CLKDIST_BCFG0_PTR              ( (reg8 *) CYREG_CLKDIST_BCFG0)
-#define CLKDIST_BCFG0                  (*(reg8 *) CYREG_CLKDIST_BCFG0)
-#define CLKDIST_MSTR0_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR0)
-#define CLKDIST_MSTR0                  (*(reg8 *) CYREG_CLKDIST_MSTR0)
-#define FASTCLK_IMO_CR_PTR             ( (reg8 *) CYREG_FASTCLK_IMO_CR)
-#define FASTCLK_IMO_CR                 (*(reg8 *) CYREG_FASTCLK_IMO_CR)
-#define CLKDIST_CR_PTR                 ( (reg8 *) CYREG_CLKDIST_CR)
-#define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
-
-
-#define IMO_PM_ENABLE                   (0x10u)
-#define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
-#define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
-#define SLOWCLK_ILO_CR0_PTR            ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
-#define SLOWCLK_ILO_CR0                (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
-#define ILO_CONTROL_PD_MODE             (0x10u)
-#define ILO_CONTROL_PD_POSITION         (4u)
-#define ILO_CONTROL_1KHZ_ON             (0x02u)
-#define ILO_CONTROL_100KHZ_ON           (0x04u)
-#define ILO_CONTROL_33KHZ_ON            (0x20u)
-#define PM_TW_CFG0_PTR                 ( (reg8 *) CYREG_PM_TW_CFG0)
-#define PM_TW_CFG0                     (*(reg8 *) CYREG_PM_TW_CFG0)
-#define PM_TW_CFG2_PTR                 ( (reg8 *) CYREG_PM_TW_CFG2)
-#define PM_TW_CFG2                     (*(reg8 *) CYREG_PM_TW_CFG2)
-#define RESET_CR2               ((reg8 *) CYREG_RESET_CR2)
-#define FASTCLK_IMO_USBCLK_ON_SET       (0x40u)
-#define CLOCK_IMO_3MHZ_VALUE            (0x03u)
-#define CLOCK_IMO_6MHZ_VALUE            (0x01u)
-#define CLOCK_IMO_12MHZ_VALUE           (0x00u)
-#define CLOCK_IMO_24MHZ_VALUE           (0x02u)
-#define CLOCK_IMO_48MHZ_VALUE           (0x04u)
-#define CLOCK_IMO_62MHZ_VALUE           (0x05u)
-#define CLOCK_IMO_74MHZ_VALUE           (0x06u)
-#define CLKDIST_DIV_POSITION            (4u)
-#define CLKDIST_MSTR1_DIV_CLEAR         (0x0Fu)
-#define SFR_USER_CPUCLK_DIV_MASK        (0x0Fu)
-#define CLOCK_USB_ENABLE                (0x02u)
-#define CLOCK_IMO_OUT_X2                (0x10u)
-#define CLOCK_IMO_OUT_X1                ((uint8)(~CLOCK_IMO_OUT_X2))
-#define CLOCK_IMO2X_ECO                 ((uint8)(~CLOCK_IMO2X_DSI))
-#define USB_CLKDIST_CONFIG_MASK         (0x03u)
-#define USB_CLK_IMO2X                   (0x00u)
-#define USB_CLK_IMO                     (0x01u)
-#define USB_CLK_PLL                     (0x02u)
-#define USB_CLK_DSI                     (0x03u)
-#define USB_CLK_DIV2_ON                 (0x04u)
-#define USB_CLK_STOP_FLAG               (0x00u)
-#define USB_CLK_START_FLAG              (0x01u)
-#define FTW_CLEAR_ALL_BITS              (0x00u)
-#define FTW_CLEAR_FTW_BITS              (0xFCu)
-#define FTW_ENABLE                      (0x01u)
-#define PM_STBY_CFG0_PTR               ( (reg8 *) CYREG_PM_STBY_CFG0)
-#define PM_STBY_CFG0                   (*(reg8 *) CYREG_PM_STBY_CFG0)
-#define PM_AVAIL_CR2_PTR               ( (reg8 *) CYREG_PM_AVAIL_CR2)
-#define PM_AVAIL_CR2                   (*(reg8 *) CYREG_PM_AVAIL_CR2)
-#define CLKDIST_UCFG_PTR               ( (reg8 *) CYREG_CLKDIST_UCFG)
-#define CLKDIST_UCFG                   (*(reg8 *) CYREG_CLKDIST_UCFG)
-#define CLKDIST_MSTR1_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR1)
-#define CLKDIST_MSTR1                  (*(reg8 *) CYREG_CLKDIST_MSTR1)
-#define SFR_USER_CPUCLK_DIV_PTR        ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
-#define IMO_TR1_PTR                    ( (reg8 *) CYREG_IMO_TR1)
-#define IMO_TR1                        (*(reg8 *) CYREG_IMO_TR1)
-#define CLOCK_CONTROL                  ( (reg8 *) CYREG_CLKDIST_CR)
-#define CY_USB_CR1_PTR                 ( (reg8 *) CYREG_USB_CR1 )
-#define CY_USB_CR1                     (*(reg8 *) CYREG_USB_CR1 )
-#define USB_CLKDIST_CONFIG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
-#define USB_CLKDIST_CONFIG             (*(reg8 *) CYREG_CLKDIST_UCFG)
-#define CY_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
-#define CY_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
-#define CY_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
-#define CY_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
-#if(CY_PSOC3)
-    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
-    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
- #else
-    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
-    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
-#endif  /* (CY_PSOC3) */
-
-
-#endif  /* (CY_BOOT_CYLIB_H) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CyLib.h
+* Version 4.20
+*
+* Description:
+*  Provides the function definitions for the system, clocking, interrupts and
+*  watchdog timer API.
+*
+* Note:
+*  Documentation of the API's in this file is located in the System Reference
+*  Guide provided with PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYLIB_H)
+#define CY_BOOT_CYLIB_H
+
+#include <string.h>
+#include <limits.h>
+#include <ctype.h>
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cydevice_trm.h"
+#include "cyPm.h"
+
+#if(CY_PSOC3)
+    #include <PSoC3_8051.h>
+#endif  /* (CY_PSOC3) */
+
+
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    #include "CyScBoostClk.h"
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Global variable with preserved reset status */
+extern uint8 CYXDATA CyResetStatus;
+
+
+/* Variable Vdda */
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    extern uint8 CyScPumpEnabled;
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/* Do not use these definitions directly in your application */
+extern uint32 cydelay_freq_hz;
+extern uint32 cydelay_freq_khz;
+extern uint8  cydelay_freq_mhz;
+extern uint32 cydelay_32k_ms;
+
+
+/***************************************
+*    Function Prototypes
+***************************************/
+cystatus CyPLL_OUT_Start(uint8 wait) ;
+void  CyPLL_OUT_Stop(void) ;
+void  CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ;
+void  CyPLL_OUT_SetSource(uint8 source) ;
+
+void  CyIMO_Start(uint8 wait) ;
+void  CyIMO_Stop(void) ;
+void  CyIMO_SetFreq(uint8 freq) ;
+void  CyIMO_SetSource(uint8 source) ;
+void  CyIMO_EnableDoubler(void) ;
+void  CyIMO_DisableDoubler(void) ;
+
+void  CyMasterClk_SetSource(uint8 source) ;
+void  CyMasterClk_SetDivider(uint8 divider) ;
+void  CyBusClk_SetDivider(uint16 divider) ;
+
+#if(CY_PSOC3)
+    void  CyCpuClk_SetDivider(uint8 divider) ;
+#endif  /* (CY_PSOC3) */
+
+void  CyUsbClk_SetSource(uint8 source) ;
+
+void  CyILO_Start1K(void) ;
+void  CyILO_Stop1K(void) ;
+void  CyILO_Start100K(void) ;
+void  CyILO_Stop100K(void) ;
+void  CyILO_Enable33K(void) ;
+void  CyILO_Disable33K(void) ;
+void  CyILO_SetSource(uint8 source) ;
+uint8 CyILO_SetPowerMode(uint8 mode) ;
+
+uint8 CyXTAL_32KHZ_ReadStatus(void) ;
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ;
+void  CyXTAL_32KHZ_Start(void) ;
+void  CyXTAL_32KHZ_Stop(void) ;
+
+cystatus CyXTAL_Start(uint8 wait) ;
+void  CyXTAL_Stop(void) ;
+void  CyXTAL_SetStartup(uint8 setting) ;
+
+void  CyXTAL_EnableErrStatus(void) ;
+void  CyXTAL_DisableErrStatus(void) ;
+uint8 CyXTAL_ReadStatus(void) ;
+void  CyXTAL_EnableFaultRecovery(void) ;
+void  CyXTAL_DisableFaultRecovery(void) ;
+
+void CyXTAL_SetFbVoltage(uint8 setting) ;
+void CyXTAL_SetWdVoltage(uint8 setting) ;
+
+void CyWdtStart(uint8 ticks, uint8 lpMode) ;
+void CyWdtClear(void) ;
+
+/* System Function Prototypes */
+void CyDelay(uint32 milliseconds) CYREENTRANT;
+void CyDelayUs(uint16 microseconds);
+void CyDelayFreq(uint32 freq) CYREENTRANT;
+void CyDelayCycles(uint32 cycles);
+
+void CySoftwareReset(void) ;
+
+uint8 CyEnterCriticalSection(void);
+void CyExitCriticalSection(uint8 savedIntrStatus);
+void CyHalt(uint8 reason) CYREENTRANT;
+
+
+/* Interrupt Function Prototypes */
+#if(CY_PSOC5)
+    cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)  ;
+    cyisraddress CyIntGetSysVector(uint8 number) ;
+#endif  /* (CY_PSOC5) */
+
+cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ;
+cyisraddress CyIntGetVector(uint8 number) ;
+
+void  CyIntSetPriority(uint8 number, uint8 priority) ;
+uint8 CyIntGetPriority(uint8 number) ;
+
+uint8 CyIntGetState(uint8 number) ;
+
+uint32 CyDisableInts(void) ;
+void CyEnableInts(uint32 mask) ;
+
+
+#if(CY_PSOC5)
+    void CyFlushCache(void);
+#endif  /* (CY_PSOC5) */
+
+
+/* Voltage Detection Function Prototypes */
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ;
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ;
+void CyVdLvDigitDisable(void) ;
+void CyVdLvAnalogDisable(void) ;
+void CyVdHvAnalogEnable(void) ;
+void CyVdHvAnalogDisable(void) ;
+uint8 CyVdStickyStatus(uint8 mask) ;
+uint8 CyVdRealTimeStatus(void) ;
+
+void CySetScPumps(uint8 enable) ;
+
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /* System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
+
+/***************************************
+* API Constants
+***************************************/
+
+
+/*******************************************************************************
+* PLL API Constants
+*******************************************************************************/
+#define CY_CLK_PLL_ENABLE               (0x01u)
+#define CY_CLK_PLL_LOCK_STATUS          (0x01u)
+
+#define CY_CLK_PLL_FTW_INTERVAL         (24u)
+
+#define CY_CLK_PLL_MAX_Q_VALUE          (16u)
+#define CY_CLK_PLL_MIN_Q_VALUE          (1u)
+#define CY_CLK_PLL_MIN_P_VALUE          (8u)
+#define CY_CLK_PLL_MIN_CUR_VALUE        (1u)
+#define CY_CLK_PLL_MAX_CUR_VALUE        (7u)
+
+#define CY_CLK_PLL_CURRENT_POSITION     (4u)
+#define CY_CLK_PLL_CURRENT_MASK         (0x8Fu)
+
+
+/*******************************************************************************
+* External 32kHz Crystal Oscillator API Constants
+*******************************************************************************/
+#define CY_XTAL32K_ANA_STAT             (0x20u)
+
+#define CY_CLK_XTAL32_CR_LPM            (0x02u)
+#define CY_CLK_XTAL32_CR_EN             (0x01u)
+#if(CY_PSOC3)
+    #define CY_CLK_XTAL32_CR_PDBEN      (0x04u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_CLK_XTAL32_TR_MASK           (0x07u)
+#define CY_CLK_XTAL32_TR_STARTUP        (0x03u)
+#define CY_CLK_XTAL32_TR_HIGH_POWER     (0x06u)
+#define CY_CLK_XTAL32_TR_LOW_POWER      (0x01u)
+#define CY_CLK_XTAL32_TR_POWERDOWN      (0x00u)
+
+#define CY_CLK_XTAL32_TST_DEFAULT       (0xF3u)
+
+#define CY_CLK_XTAL32_CFG_LP_DEFAULT    (0x04u)
+#define CY_CLK_XTAL32_CFG_LP_LOWPOWER   (0x08u)
+#define CY_CLK_XTAL32_CFG_LP_MASK       (0x0Cu)
+
+#define CY_CLK_XTAL32_CFG_LP_ALLOW      (0x80u)
+
+
+/*******************************************************************************
+* External MHz Crystal Oscillator API Constants
+*******************************************************************************/
+#define CY_CLK_XMHZ_FTW_INTERVAL        (24u)
+#define CY_CLK_XMHZ_MIN_TIMEOUT         (130u)
+
+#define CY_CLK_XMHZ_CSR_ENABLE          (0x01u)
+#define CY_CLK_XMHZ_CSR_XERR            (0x80u)
+#define CY_CLK_XMHZ_CSR_XFB             (0x04u)
+#define CY_CLK_XMHZ_CSR_XPROT           (0x40u)
+
+#define CY_CLK_XMHZ_CFG0_XCFG_MASK      (0x1Fu)
+#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK   (0x0Fu)
+#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK   (0x70u)
+
+
+/*******************************************************************************
+* Watchdog Timer API Constants
+*******************************************************************************/
+#define CYWDT_2_TICKS               (0x0u)     /*    4 -    6 ms */
+#define CYWDT_16_TICKS              (0x1u)     /*   32 -   48 ms */
+#define CYWDT_128_TICKS             (0x2u)     /*  256 -  384 ms */
+#define CYWDT_1024_TICKS            (0x3u)     /* 2048 - 3072 ms */
+
+#define CYWDT_LPMODE_NOCHANGE       (0x00u)
+#define CYWDT_LPMODE_MAXINTER       (0x01u)
+#define CYWDT_LPMODE_DISABLED       (0x03u)
+
+#define CY_WDT_CFG_INTERVAL_MASK    (0x03u)
+#define CY_WDT_CFG_CTW_RESET        (0x80u)
+#define CY_WDT_CFG_LPMODE_SHIFT     (5u)
+#define CY_WDT_CFG_LPMODE_MASK      (0x60u)
+#define CY_WDT_CFG_WDR_EN           (0x10u)
+#define CY_WDT_CFG_CLEAR_ALL        (0x00u)
+#define CY_WDT_CR_FEED              (0x01u)
+
+
+/*******************************************************************************
+*    Voltage Detection API Constants
+*******************************************************************************/
+
+#define CY_VD_LVID_EN                (0x01u)
+#define CY_VD_LVIA_EN                (0x02u)
+#define CY_VD_HVIA_EN                (0x04u)
+
+#define CY_VD_PRESD_EN               (0x40u)
+#define CY_VD_PRESA_EN               (0x80u)
+
+#define CY_VD_LVID                   (0x01u)
+#define CY_VD_LVIA                   (0x02u)
+#define CY_VD_HVIA                   (0x04u)
+
+#define CY_VD_LVI_TRIP_LVID_MASK     (0x0Fu)
+
+
+/*******************************************************************************
+*    Variable VDDA API Constants
+*******************************************************************************/
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    /* Active Power Mode Configuration Register 9 */
+    #define CY_LIB_ACT_CFG9_SWCAP0_EN        (0x01u)
+    #define CY_LIB_ACT_CFG9_SWCAP1_EN        (0x02u)
+    #define CY_LIB_ACT_CFG9_SWCAP2_EN        (0x04u)
+    #define CY_LIB_ACT_CFG9_SWCAP3_EN        (0x08u)
+    #define CY_LIB_ACT_CFG9_SWCAPS_MASK      (0x0Fu)
+
+    /* Switched Cap Miscellaneous Control Register */
+    #define CY_LIB_SC_MISC_PUMP_FORCE        (0x20u)
+
+    /* Switched Capacitor 0 Boost Clock Selection Register */
+    #define CY_LIB_SC_BST_CLK_EN             (0x08u)
+    #define CY_LIB_SC_BST_CLK_INDEX_MASK     (0xF8u)
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/*******************************************************************************
+* Clock Distribution API Constants
+*******************************************************************************/
+#define CY_LIB_CLKDIST_AMASK_MASK       (0xF0u)
+#define CY_LIB_CLKDIST_DMASK_MASK       (0x00u)
+#define CY_LIB_CLKDIST_LD_LOAD          (0x01u)
+#define CY_LIB_CLKDIST_BCFG2_MASK       (0x80u)
+#define CY_LIB_CLKDIST_MASTERCLK_DIV    (7u)
+#define CY_LIB_CLKDIST_BCFG2_SSS        (0x40u)
+#define CY_LIB_CLKDIST_MSTR1_SRC_MASK   (0xFCu)
+#define CY_LIB_FASTCLK_IMO_DOUBLER      (0x10u)
+#define CY_LIB_FASTCLK_IMO_IMO          (0x20u)
+#define CY_LIB_CLKDIST_CR_IMO2X         (0x40u)
+#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)
+
+#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK  (0xFCu)
+
+
+/* CyILO_SetPowerMode() */
+#define CY_ILO_CONTROL_PD_MODE          (0x10u)
+#define CY_ILO_CONTROL_PD_POSITION      (4u)
+
+#define CY_ILO_SOURCE_100K              (0u)
+#define CY_ILO_SOURCE_33K               (1u)
+#define CY_ILO_SOURCE_1K                (2u)
+
+#define CY_ILO_FAST_START               (0u)
+#define CY_ILO_SLOW_START               (1u)
+
+#define CY_ILO_SOURCE_BITS_CLEAR        (0xF3u)
+#define CY_ILO_SOURCE_1K_SET            (0x08u)
+#define CY_ILO_SOURCE_33K_SET           (0x04u)
+#define CY_ILO_SOURCE_100K_SET          (0x00u)
+
+#define CY_MASTER_SOURCE_IMO            (0u)
+#define CY_MASTER_SOURCE_PLL            (1u)
+#define CY_MASTER_SOURCE_XTAL           (2u)
+#define CY_MASTER_SOURCE_DSI            (3u)
+
+#define CY_IMO_SOURCE_IMO               (0u)
+#define CY_IMO_SOURCE_XTAL              (1u)
+#define CY_IMO_SOURCE_DSI               (2u)
+
+
+/* CyIMO_Start() */
+#define CY_LIB_PM_ACT_CFG0_IMO_EN       (0x10u)
+#define CY_LIB_PM_STBY_CFG0_IMO_EN      (0x10u)
+#define CY_LIB_CLK_IMO_FTW_TIMEOUT      (0x00u)
+
+#define CY_LIB_IMO_3MHZ_VALUE           (0x03u)
+#define CY_LIB_IMO_6MHZ_VALUE           (0x01u)
+#define CY_LIB_IMO_12MHZ_VALUE          (0x00u)
+#define CY_LIB_IMO_24MHZ_VALUE          (0x02u)
+#define CY_LIB_IMO_48MHZ_VALUE          (0x04u)
+#define CY_LIB_IMO_62MHZ_VALUE          (0x05u)
+#define CY_LIB_IMO_74MHZ_VALUE          (0x06u)
+
+
+/* CyIMO_SetFreq() */
+#define CY_IMO_FREQ_3MHZ                (0u)
+#define CY_IMO_FREQ_6MHZ                (1u)
+#define CY_IMO_FREQ_12MHZ               (2u)
+#define CY_IMO_FREQ_24MHZ               (3u)
+#define CY_IMO_FREQ_48MHZ               (4u)
+#define CY_IMO_FREQ_62MHZ               (5u)
+#if(CY_PSOC5)
+    #define CY_IMO_FREQ_74MHZ           (6u)
+#endif  /* (CY_PSOC5) */
+#define CY_IMO_FREQ_USB                 (8u)
+
+#define CY_LIB_IMO_USBCLK_ON_SET        (0x40u)
+
+
+/* CyCpuClk_SetDivider() */
+#define CY_LIB_CLKDIST_DIV_POSITION     (4u)
+#define CY_LIB_CLKDIST_MSTR1_DIV_MASK   (0x0Fu)
+
+
+/* CyIMO_SetTrimValue() */
+#define CY_LIB_USB_CLK_EN               (0x02u)
+
+
+/* CyPLL_OUT_SetSource() - parameters */
+#define CY_PLL_SOURCE_IMO               (0u)
+#define CY_PLL_SOURCE_XTAL              (1u)
+#define CY_PLL_SOURCE_DSI               (2u)
+
+
+/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ   (0x02u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ  (0x20u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)
+
+
+/* CyUsbClk_SetSource() */
+#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)
+
+
+/* CyUsbClk_SetSource() - parameters */
+#define CY_LIB_USB_CLK_IMO2X            (0x00u)
+#define CY_LIB_USB_CLK_IMO              (0x01u)
+#define CY_LIB_USB_CLK_PLL              (0x02u)
+#define CY_LIB_USB_CLK_DSI              (0x03u)
+
+
+/* CyUSB_PowerOnCheck() */
+#define CY_ACT_USB_ENABLED              (0x01u)
+#define CY_ALT_ACT_USB_ENABLED          (0x01u)
+
+
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+
+/*******************************************************************************
+* System Registers
+*******************************************************************************/
+
+/* Software Reset Control Register */
+#define CY_LIB_RESET_CR2_REG         (* (reg8 *) CYREG_RESET_CR2)
+#define CY_LIB_RESET_CR2_PTR         (  (reg8 *) CYREG_RESET_CR2)
+
+/* Timewheel Configuration Register 0 */
+#define CY_LIB_PM_TW_CFG0_REG           (*(reg8 *) CYREG_PM_TW_CFG0)
+#define CY_LIB_PM_TW_CFG0_PTR           ( (reg8 *) CYREG_PM_TW_CFG0)
+
+/* Timewheel Configuration Register 2 */
+#define CY_LIB_PM_TW_CFG2_REG           (*(reg8 *) CYREG_PM_TW_CFG2)
+#define CY_LIB_PM_TW_CFG2_PTR           ( (reg8 *) CYREG_PM_TW_CFG2)
+
+/* USB Configuration Register */
+#define CY_LIB_CLKDIST_UCFG_REG         (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CY_LIB_CLKDIST_UCFG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
+
+/* Internal Main Oscillator Trim Register 1 */
+#define CY_LIB_IMO_TR1_REG              (*(reg8 *) CYREG_IMO_TR1)
+#define CY_LIB_IMO_TR1_PTR              ( (reg8 *) CYREG_IMO_TR1)
+
+/* USB control 1 Register */
+#define CY_LIB_USB_CR1_REG              (*(reg8 *) CYREG_USB_CR1 )
+#define CY_LIB_USB_CR1_PTR              ( (reg8 *) CYREG_USB_CR1 )
+
+/* Active Power Mode Configuration Register 0 */
+#define CY_LIB_PM_ACT_CFG0_REG          (*(reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_LIB_PM_ACT_CFG0_PTR          ( (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Standby Power Mode Configuration Register 0 */
+#define CY_LIB_PM_STBY_CFG0_REG          (*(reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_LIB_PM_STBY_CFG0_PTR          ( (reg8 *) CYREG_PM_STBY_CFG0)
+
+/* Active Power Mode Configuration Register 5 */
+#define CY_LIB_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_LIB_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
+
+/* Standby Power Mode Configuration Register 5 */
+#define CY_LIB_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
+#define CY_LIB_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
+
+/* CyIMO_SetTrimValue() */
+#if(CY_PSOC3)
+    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define CY_LIB_TRIM_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define CY_LIB_TRIM_IMO_TR1_PTR          ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+ #else
+    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define CY_LIB_TRIM_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define CY_LIB_TRIM_IMO_TR1_PTR          ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+#endif  /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* PLL Registers
+*******************************************************************************/
+
+/* PLL Configuration Register 0 */
+#define CY_CLK_PLL_CFG0_REG         (*(reg8 *) CYREG_FASTCLK_PLL_CFG0)
+#define CY_CLK_PLL_CFG0_PTR         ( (reg8 *) CYREG_FASTCLK_PLL_CFG0)
+
+/* PLL Configuration Register 1 */
+#define CY_CLK_PLL_CFG1_REG         (*(reg8 *) CYREG_FASTCLK_PLL_CFG1)
+#define CY_CLK_PLL_CFG1_PTR         ( (reg8 *) CYREG_FASTCLK_PLL_CFG1)
+
+/* PLL Status Register */
+#define CY_CLK_PLL_SR_REG           (*(reg8 *) CYREG_FASTCLK_PLL_SR)
+#define CY_CLK_PLL_SR_PTR           ( (reg8 *) CYREG_FASTCLK_PLL_SR)
+
+/* PLL Q-Counter Configuration Register */
+#define CY_CLK_PLL_Q_REG            (*(reg8 *) CYREG_FASTCLK_PLL_Q)
+#define CY_CLK_PLL_Q_PTR            ( (reg8 *) CYREG_FASTCLK_PLL_Q)
+
+/* PLL P-Counter Configuration Register */
+#define CY_CLK_PLL_P_REG            (*(reg8 *) CYREG_FASTCLK_PLL_P)
+#define CY_CLK_PLL_P_PTR            ( (reg8 *) CYREG_FASTCLK_PLL_P)
+
+
+/*******************************************************************************
+* External MHz Crystal Oscillator Registers
+*******************************************************************************/
+
+/* External MHz Crystal Oscillator Status and Control Register */
+#define CY_CLK_XMHZ_CSR_REG         (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
+#define CY_CLK_XMHZ_CSR_PTR         ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
+
+/* External MHz Crystal Oscillator Configuration Register 0 */
+#define CY_CLK_XMHZ_CFG0_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
+#define CY_CLK_XMHZ_CFG0_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
+
+/* External MHz Crystal Oscillator Configuration Register 1 */
+#define CY_CLK_XMHZ_CFG1_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
+#define CY_CLK_XMHZ_CFG1_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
+
+
+/*******************************************************************************
+* External 32kHz Crystal Oscillator Registers
+*******************************************************************************/
+
+/* 32 kHz Watch Crystal Oscillator Trim Register */
+#define CY_CLK_XTAL32_TR_REG        (*(reg8 *) CYREG_X32_TR)
+#define CY_CLK_XTAL32_TR_PTR        ( (reg8 *) CYREG_X32_TR)
+
+/* External 32kHz Crystal Oscillator Test Register */
+#define CY_CLK_XTAL32_TST_REG       (*(reg8 *) CYREG_SLOWCLK_X32_TST)
+#define CY_CLK_XTAL32_TST_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_TST)
+
+/* External 32kHz Crystal Oscillator Control Register */
+#define CY_CLK_XTAL32_CR_REG        (*(reg8 *) CYREG_SLOWCLK_X32_CR)
+#define CY_CLK_XTAL32_CR_PTR        ( (reg8 *) CYREG_SLOWCLK_X32_CR)
+
+/* External 32kHz Crystal Oscillator Configuration Register */
+#define CY_CLK_XTAL32_CFG_REG       (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
+#define CY_CLK_XTAL32_CFG_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
+
+
+/*******************************************************************************
+* Watchdog Timer Registers
+*******************************************************************************/
+
+/* Watchdog Timer Configuration Register */
+#define CY_WDT_CFG_REG              (*(reg8 *) CYREG_PM_WDT_CFG)
+#define CY_WDT_CFG_PTR              ( (reg8 *) CYREG_PM_WDT_CFG)
+
+/* Watchdog Timer Control Register */
+#define CY_WDT_CR_REG               (*(reg8 *) CYREG_PM_WDT_CR)
+#define CY_WDT_CR_PTR               ( (reg8 *) CYREG_PM_WDT_CR)
+
+
+/*******************************************************************************
+*    LVI/HVI Registers
+*******************************************************************************/
+
+#define CY_VD_LVI_TRIP_REG          (* (reg8 *) CYREG_RESET_CR0)
+#define CY_VD_LVI_TRIP_PTR          (  (reg8 *) CYREG_RESET_CR0)
+
+#define CY_VD_LVI_HVI_CONTROL_REG   (* (reg8 *) CYREG_RESET_CR1)
+#define CY_VD_LVI_HVI_CONTROL_PTR   (  (reg8 *) CYREG_RESET_CR1)
+
+#define CY_VD_PRES_CONTROL_REG      (* (reg8 *) CYREG_RESET_CR3)
+#define CY_VD_PRES_CONTROL_PTR      (  (reg8 *) CYREG_RESET_CR3)
+
+#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0)
+#define CY_VD_PERSISTENT_STATUS_PTR (  (reg8 *) CYREG_RESET_SR0)
+
+#define CY_VD_RT_STATUS_REG         (* (reg8 *) CYREG_RESET_SR2)
+#define CY_VD_RT_STATUS_PTR         (  (reg8 *) CYREG_RESET_SR2)
+
+
+/*******************************************************************************
+*    Variable VDDA
+*******************************************************************************/
+#if(CYDEV_VARIABLE_VDDA == 1)
+
+    /* Active Power Mode Configuration Register 9 */
+    #define CY_LIB_ACT_CFG9_REG            (* (reg8 *) CYREG_PM_ACT_CFG9 )
+    #define CY_LIB_ACT_CFG9_PTR            (  (reg8 *) CYREG_PM_ACT_CFG9 )
+
+    /* Switched Capacitor 0 Boost Clock Selection Register */
+    #define CY_LIB_SC0_BST_REG             (* (reg8 *) CYREG_SC0_BST )
+    #define CY_LIB_SC0_BST_PTR             (  (reg8 *) CYREG_SC0_BST )
+
+    /* Switched Capacitor 1 Boost Clock Selection Register */
+    #define CY_LIB_SC1_BST_REG             (* (reg8 *) CYREG_SC1_BST )
+    #define CY_LIB_SC1_BST_PTR             (  (reg8 *) CYREG_SC1_BST )
+
+    /* Switched Capacitor 2 Boost Clock Selection Register */
+    #define CY_LIB_SC2_BST_REG             (* (reg8 *) CYREG_SC2_BST )
+    #define CY_LIB_SC2_BST_PTR             (  (reg8 *) CYREG_SC2_BST )
+
+    /* Switched Capacitor 3 Boost Clock Selection Register */
+    #define CY_LIB_SC3_BST_REG             (* (reg8 *) CYREG_SC3_BST )
+    #define CY_LIB_SC3_BST_PTR             (  (reg8 *) CYREG_SC3_BST )
+
+    /* Switched Cap Miscellaneous Control Register */
+    #define CY_LIB_SC_MISC_REG             (* (reg8 *) CYREG_SC_MISC )
+    #define CY_LIB_SC_MISC_PTR             (  (reg8 *) CYREG_SC_MISC )
+
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+
+
+/*******************************************************************************
+*    Clock Distribution Registers
+*******************************************************************************/
+
+/* Analog Clock Mask Register */
+#define CY_LIB_CLKDIST_AMASK_REG       (* (reg8 *) CYREG_CLKDIST_AMASK )
+#define CY_LIB_CLKDIST_AMASK_PTR       (  (reg8 *) CYREG_CLKDIST_AMASK )
+
+/* Digital Clock Mask Register */
+#define CY_LIB_CLKDIST_DMASK_REG        (*(reg8 *) CYREG_CLKDIST_DMASK)
+#define CY_LIB_CLKDIST_DMASK_PTR        ( (reg8 *) CYREG_CLKDIST_DMASK)
+
+/* CLK_BUS Configuration Register */
+#define CY_LIB_CLKDIST_BCFG2_REG        (*(reg8 *) CYREG_CLKDIST_BCFG2)
+#define CY_LIB_CLKDIST_BCFG2_PTR        ( (reg8 *) CYREG_CLKDIST_BCFG2)
+
+/* LSB Shadow Divider Value Register */
+#define CY_LIB_CLKDIST_WRK_LSB_REG      (*(reg8 *) CYREG_CLKDIST_WRK0)
+#define CY_LIB_CLKDIST_WRK_LSB_PTR      ( (reg8 *) CYREG_CLKDIST_WRK0)
+
+/* MSB Shadow Divider Value Register */
+#define CY_LIB_CLKDIST_WRK_MSB_REG      (*(reg8 *) CYREG_CLKDIST_WRK1)
+#define CY_LIB_CLKDIST_WRK_MSB_PTR      ( (reg8 *) CYREG_CLKDIST_WRK1)
+
+/* LOAD Register */
+#define CY_LIB_CLKDIST_LD_REG           (*(reg8 *) CYREG_CLKDIST_LD)
+#define CY_LIB_CLKDIST_LD_PTR           ( (reg8 *) CYREG_CLKDIST_LD)
+
+/* CLK_BUS LSB Divider Value Register */
+#define CY_LIB_CLKDIST_BCFG_LSB_REG     (*(reg8 *) CYREG_CLKDIST_BCFG0)
+#define CY_LIB_CLKDIST_BCFG_LSB_PTR     ( (reg8 *) CYREG_CLKDIST_BCFG0)
+
+/* CLK_BUS MSB Divider Value Register */
+#define CY_LIB_CLKDIST_BCFG_MSB_REG     (*(reg8 *) CYREG_CLKDIST_BCFG1)
+#define CY_LIB_CLKDIST_BCFG_MSB_PTR     ( (reg8 *) CYREG_CLKDIST_BCFG1)
+
+/* Master clock (clk_sync_d) Divider Value Register */
+#define CY_LIB_CLKDIST_MSTR0_REG        (*(reg8 *) CYREG_CLKDIST_MSTR0)
+#define CY_LIB_CLKDIST_MSTR0_PTR        ( (reg8 *) CYREG_CLKDIST_MSTR0)
+
+/* Master (clk_sync_d) Configuration Register/CPU Divider Value */
+#define CY_LIB_CLKDIST_MSTR1_REG        (*(reg8 *) CYREG_CLKDIST_MSTR1)
+#define CY_LIB_CLKDIST_MSTR1_PTR        ( (reg8 *) CYREG_CLKDIST_MSTR1)
+
+/* Internal Main Oscillator Control Register */
+#define CY_LIB_FASTCLK_IMO_CR_REG       (*(reg8 *) CYREG_FASTCLK_IMO_CR)
+#define CY_LIB_FASTCLK_IMO_CR_PTR       ( (reg8 *) CYREG_FASTCLK_IMO_CR)
+
+/* Configuration Register CR */
+#define CY_LIB_CLKDIST_CR_REG           (*(reg8 *) CYREG_CLKDIST_CR)
+#define CY_LIB_CLKDIST_CR_PTR           ( (reg8 *) CYREG_CLKDIST_CR)
+
+/* Internal Low-speed Oscillator Control Register 0 */
+#define CY_LIB_SLOWCLK_ILO_CR0_REG      (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define CY_LIB_SLOWCLK_ILO_CR0_PTR      ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
+
+
+/*******************************************************************************
+* Interrupt Registers
+*******************************************************************************/
+
+#if(CY_PSOC5)
+
+    /* Interrupt Vector Table Offset */
+    #define CY_INT_VECT_TABLE           ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+
+    /* Interrupt Priority 0-31 */
+    #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_NVIC_PRI_0)
+    #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_NVIC_PRI_0)
+
+    /* Interrupt Enable Set 0-31 */
+    #define CY_INT_ENABLE_REG           (* (reg32 *) CYREG_NVIC_SETENA0)
+    #define CY_INT_ENABLE_PTR           (  (reg32 *) CYREG_NVIC_SETENA0)
+
+    /* Interrupt Enable Clear 0-31 */
+    #define CY_INT_CLEAR_REG            (* (reg32 *) CYREG_NVIC_CLRENA0)
+    #define CY_INT_CLEAR_PTR            (  (reg32 *) CYREG_NVIC_CLRENA0)
+
+    /* Interrupt Pending Set 0-31 */
+    #define CY_INT_SET_PEND_REG         (* (reg32 *) CYREG_NVIC_SETPEND0)
+    #define CY_INT_SET_PEND_PTR         (  (reg32 *) CYREG_NVIC_SETPEND0)
+
+    /* Interrupt Pending Clear 0-31 */
+    #define CY_INT_CLR_PEND_REG         (* (reg32 *) CYREG_NVIC_CLRPEND0)
+    #define CY_INT_CLR_PEND_PTR         (  (reg32 *) CYREG_NVIC_CLRPEND0)
+
+    /* Cache Control Register */
+    #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
+    #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
+
+    /* System tick registers */
+    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
+#elif (CY_PSOC3)
+
+    /* Interrupt Address Vector registers */
+    #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
+
+    /* Interrupt Controller Priority Registers */
+    #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
+    #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
+
+    /* Interrupt Controller Set Enable Registers */
+    #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
+    #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
+
+    #define CY_INT_SET_EN0_REG          (* (reg8 *) CYREG_INTC_SET_EN0)
+    #define CY_INT_SET_EN0_PTR          (  (reg8 *) CYREG_INTC_SET_EN0)
+
+    #define CY_INT_SET_EN1_REG          (* (reg8 *) CYREG_INTC_SET_EN1)
+    #define CY_INT_SET_EN1_PTR          (  (reg8 *) CYREG_INTC_SET_EN1)
+
+    #define CY_INT_SET_EN2_REG          (* (reg8 *) CYREG_INTC_SET_EN2)
+    #define CY_INT_SET_EN2_PTR          (  (reg8 *) CYREG_INTC_SET_EN2)
+
+    #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
+    #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
+
+    /* Interrupt Controller Clear Enable Registers */
+    #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
+    #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
+
+    #define CY_INT_CLR_EN0_REG          (* (reg8 *) CYREG_INTC_CLR_EN0)
+    #define CY_INT_CLR_EN0_PTR          (  (reg8 *) CYREG_INTC_CLR_EN0)
+
+    #define CY_INT_CLR_EN1_REG          (* (reg8 *) CYREG_INTC_CLR_EN1)
+    #define CY_INT_CLR_EN1_PTR          (  (reg8 *) CYREG_INTC_CLR_EN1)
+
+    #define CY_INT_CLR_EN2_REG          (* (reg8 *) CYREG_INTC_CLR_EN2)
+    #define CY_INT_CLR_EN2_PTR          (  (reg8 *) CYREG_INTC_CLR_EN2)
+
+    #define CY_INT_CLR_EN3_REG          (* (reg8 *) CYREG_INTC_CLR_EN3)
+    #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
+
+
+    /* Interrupt Controller Set Pend Registers */
+    #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
+    #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
+
+    /* Interrupt Controller Clear Pend Registers */
+    #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
+    #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
+
+
+    /* Access Interrupt Controller Registers based on interrupt number */
+    #define CY_INT_SET_EN_INDX_PTR(number)    ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
+    #define CY_INT_CLR_EN_INDX_PTR(number)    ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
+    #define CY_INT_CLR_PEND_INDX_PTR(number)  ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
+    #define CY_INT_SET_PEND_INDX_PTR(number)  ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))
+
+#endif  /* (CY_PSOC5) */
+
+
+/*******************************************************************************
+* Macro Name: CyAssert
+********************************************************************************
+* Summary:
+*  The macro that evaluates the expression and if it is false (evaluates to 0)
+*  then the processor is halted.
+*
+*  This macro is evaluated unless NDEBUG is defined.
+*
+*  If NDEBUG is defined, then no code is generated for this macro. NDEBUG is
+*  defined by default for a Release build setting and not defined for a Debug
+*  build setting.
+*
+* Parameters:
+*  expr: Logical expression.  Asserts if false.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+#if !defined(NDEBUG)
+    #define CYASSERT(x)     { \
+                                if(!(x)) \
+                                { \
+                                    CyHalt((uint8) 0u); \
+                                } \
+                            }
+#else
+    #define CYASSERT(x)
+#endif /* !defined(NDEBUG) */
+
+
+/* Reset register fields of RESET_SR0 (CyResetStatus) */
+#define CY_RESET_LVID               (0x01u)
+#define CY_RESET_LVIA               (0x02u)
+#define CY_RESET_HVIA               (0x04u)
+#define CY_RESET_WD                 (0x08u)
+#define CY_RESET_SW                 (0x20u)
+#define CY_RESET_GPIO0              (0x40u)
+#define CY_RESET_GPIO1              (0x80u)
+
+
+/* Interrupt Controller Configuration and Status Register */
+#if(CY_PSOC3)
+    #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
+    #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
+    #define INTERRUPT_DISABLE_IRQ       {*INTERRUPT_CSR |= DISABLE_IRQ_SET;}
+    #define INTERRUPT_ENABLE_IRQ        {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);}
+#endif  /* (CY_PSOC3) */
+
+
+#if defined(__ARMCC_VERSION)
+    #define CyGlobalIntEnable           {__enable_irq();}
+    #define CyGlobalIntDisable          {__disable_irq();}
+#elif defined(__GNUC__) || defined (__ICCARM__)
+    #define CyGlobalIntEnable           {__asm("CPSIE   i");}
+    #define CyGlobalIntDisable          {__asm("CPSID   i");}
+#elif defined(__C51__)
+    #define CyGlobalIntEnable           {\
+                                            EA = 1u; \
+                                            INTERRUPT_ENABLE_IRQ\
+                                        }
+
+    #define CyGlobalIntDisable          {\
+                                            INTERRUPT_DISABLE_IRQ; \
+                                            CY_NOP; \
+                                            EA = 0u;\
+                                        }
+#else
+    #error No compiler toolchain defined
+    #define CyGlobalIntEnable
+    #define CyGlobalIntDisable
+#endif  /* (__ARMCC_VERSION) */
+
+
+#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR
+    #define CYDEV_HALT_CPU      CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u)
+#else
+    #define CYDEV_HALT_CPU      CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u)
+#endif  /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */
+
+
+#ifdef CYREG_MLOGIC_REV_ID_REV_ID
+    #define CYDEV_CHIP_REV_ACTUAL       (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID))
+#else
+    #define CYDEV_CHIP_REV_ACTUAL       (CY_GET_REG8(CYREG_MLOGIC_REV_ID))
+#endif  /* (CYREG_MLOGIC_REV_ID_REV_ID) */
+
+
+/*******************************************************************************
+* System API constants
+*******************************************************************************/
+#define CY_CACHE_CONTROL_FLUSH          (0x0004u)
+#define CY_LIB_RESET_CR2_RESET          (0x01u)
+
+#if(CY_PSOC5)
+    /* System tick API constants */
+    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
+    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
+    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
+    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
+
+/*******************************************************************************
+* Interrupt API constants
+*******************************************************************************/
+#if(CY_PSOC5)
+
+    #define CY_INT_IRQ_BASE             (16u)
+
+#elif (CY_PSOC3)
+
+    #define CY_INT_IRQ_BASE             (0u)
+
+#endif  /* (CY_PSOC5) */
+
+/* Valid range of interrupt 0-31 */
+#define CY_INT_NUMBER_MAX               (31u)
+
+/* Valid range of system interrupt 0-15 */
+#define CY_INT_SYS_NUMBER_MAX           (15u)
+
+/* Valid range of system priority 0-7 */
+#define CY_INT_PRIORITY_MAX             (7u)
+
+/* Mask to get valid range of interrupt 0-31 */
+#define CY_INT_NUMBER_MASK              (0x1Fu)
+
+/* Mask to get valid range of system priority 0-7 */
+#define CY_INT_PRIORITY_MASK            (0x7u)
+
+/* Mask to get valid range of system interrupt 0-15 */
+#define CY_INT_SYS_NUMBER_MASK          (0xFu)
+
+#if(CY_PSOC5)
+
+    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
+    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
+    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
+    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
+    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
+    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
+    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
+    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
+    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
+
+#endif  /* (CY_PSOC5) */
+
+/*******************************************************************************
+* Interrupt Macros
+*******************************************************************************/
+
+#if(CY_PSOC5)
+
+    /*******************************************************************************
+    * Macro Name: CyIntEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntEnable(number)     CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
+
+    /*******************************************************************************
+    * Macro Name: CyIntDisable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntDisable(number)     CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntSetPending
+    ********************************************************************************
+    *
+    * Summary:
+    *   Forces the specified interrupt number to be pending.
+    *
+    * Parameters:
+    *   number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntSetPending(number)     CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntClearPending
+    ********************************************************************************
+    *
+    * Summary:
+    *   Clears any pending interrupt for the specified interrupt number.
+    *
+    * Parameters:
+    *   number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntClearPending(number)   CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))
+
+
+#else   /* PSoC3 */
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntEnable(number)   CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \
+                                          ((uint8)(1u << (0x07u & (number)))))
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntDisable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntDisable(number)   CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \
+                                          ((uint8)(1u << (0x07u & (number)))))
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntSetPending
+    ********************************************************************************
+    *
+    * Summary:
+    *  Forces the specified interrupt number to be pending.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntSetPending(number)   CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \
+                                                  ((uint8)(1u << (0x07u & (number)))))
+
+
+    /*******************************************************************************
+    * Macro Name: CyIntClearPending
+    ********************************************************************************
+    * Summary:
+    *  Clears any pending interrupt for the specified interrupt number.
+    *
+    * Parameters:
+    *  number: Valid range [0-31].  Interrupt number.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    #define CyIntClearPending(number)   CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \
+                                                    ((uint8)(1u << (0x07u & (number)))))
+
+#endif  /* (CY_PSOC5) */
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+
+#define CYGlobalIntEnable       CyGlobalIntEnable
+#define CYGlobalIntDisable      CyGlobalIntDisable
+
+#define cymemset(s,c,n)         memset((s),(c),(n))
+#define cymemcpy(d,s,n)         memcpy((d),(s),(n))
+
+#define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
+#define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
+#define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
+#define SLOWCLK_X32_TST                 (CY_CLK_XTAL32_TST_REG)
+#define SLOWCLK_X32_CR_PTR              (CY_CLK_XTAL32_CR_PTR)
+#define SLOWCLK_X32_CR                  (CY_CLK_XTAL32_CR_REG)
+#define SLOWCLK_X32_CFG_PTR             (CY_CLK_XTAL32_CFG_PTR)
+#define SLOWCLK_X32_CFG                 (CY_CLK_XTAL32_CFG_REG)
+
+#define X32_CONTROL_ANA_STAT            (CY_CLK_XTAL32_CR_ANA_STAT)
+#define X32_CONTROL_DIG_STAT            (0x10u)
+#define X32_CONTROL_LPM                 (CY_CLK_XTAL32_CR_LPM)
+#define X32_CONTROL_LPM_POSITION        (1u)
+#define X32_CONTROL_X32EN               (CY_CLK_XTAL32_CR_EN)
+#define X32_CONTROL_PDBEN           (CY_CLK_XTAL32_CR_PDBEN)
+#define X32_TR_DPMODE                   (CY_CLK_XTAL32_TR_STARTUP)
+#define X32_TR_CLEAR                    (CY_CLK_XTAL32_TR_POWERDOWN)
+#define X32_TR_HPMODE                   (CY_CLK_XTAL32_TR_HIGH_POWER)
+#define X32_TR_LPMODE                   (CY_CLK_XTAL32_TR_LOW_POWER)
+#define X32_TST_SETALL                  (CY_CLK_XTAL32_TST_DEFAULT)
+#define X32_CFG_LP_BITS_MASK            (CY_CLK_XTAL32_CFG_LP_MASK)
+#define X32_CFG_LP_DEFAULT              (CY_CLK_XTAL32_CFG_LP_DEFAULT)
+#define X32_CFG_LOWPOWERMODE            (0x80u)
+#define X32_CFG_LP_LOWPOWER             (0x8u)
+#define CY_X32_HIGHPOWER_MODE           (0u)
+#define CY_X32_LOWPOWER_MODE            (1u)
+#define CY_XTAL32K_DIG_STAT             (0x10u)
+#define CY_XTAL32K_STAT_FIELDS          (0x30u)
+#define CY_XTAL32K_DIG_STAT_UNSTABLE    (0u)
+#define CY_XTAL32K_ANA_STAT_UNSTABLE    (0x0u)
+#define CY_XTAL32K_STATUS               (0x20u)
+
+#define FASTCLK_XMHZ_CSR_PTR            (CY_CLK_XMHZ_CSR_PTR)
+#define FASTCLK_XMHZ_CSR                (CY_CLK_XMHZ_CSR_REG)
+#define FASTCLK_XMHZ_CFG0_PTR           (CY_CLK_XMHZ_CFG0_PTR)
+#define FASTCLK_XMHZ_CFG0               (CY_CLK_XMHZ_CFG0_REG)
+#define FASTCLK_XMHZ_CFG1_PTR           (CY_CLK_XMHZ_CFG1_PTR)
+#define FASTCLK_XMHZ_CFG1               (CY_CLK_XMHZ_CFG1_REG)
+#define FASTCLK_XMHZ_GAINMASK           (CY_CLK_XMHZ_CFG0_XCFG_MASK)
+#define FASTCLK_XMHZ_VREFMASK           (CY_CLK_XMHZ_CFG1_VREF_FB_MASK)
+#define FASTCLK_XMHZ_VREF_WD_MASK       (CY_CLK_XMHZ_CFG1_VREF_WD_MASK)
+#define XMHZ_CONTROL_ENABLE             (CY_CLK_XMHZ_CSR_ENABLE)
+#define X32_CONTROL_XERR_MASK           (CY_CLK_XMHZ_CSR_XERR)
+#define X32_CONTROL_XERR_DIS            (CY_CLK_XMHZ_CSR_XFB)
+#define X32_CONTROL_XERR_POSITION       (7u)
+#define X32_CONTROL_FAULT_RECOVER       (CY_CLK_XMHZ_CSR_XPROT)
+
+#define CYWDT_CFG                       (CY_WDT_CFG_PTR)
+#define CYWDT_CR                        (CY_WDT_CR_PTR)
+
+#define CYWDT_TICKS_MASK                (CY_WDT_CFG_INTERVAL_MASK)
+#define CYWDT_RESET                     (CY_WDT_CFG_CTW_RESET)
+#define CYWDT_LPMODE_SHIFT              (CY_WDT_CFG_LPMODE_SHIFT)
+#define CYWDT_LPMODE_MASK               (CY_WDT_CFG_LPMODE_MASK)
+#define CYWDT_ENABLE_BIT                (CY_WDT_CFG_WDR_EN)
+
+#define FASTCLK_PLL_CFG0_PTR            (CY_CLK_PLL_CFG0_PTR)
+#define FASTCLK_PLL_CFG0                (CY_CLK_PLL_CFG0_REG)
+#define FASTCLK_PLL_SR_PTR              (CY_CLK_PLL_SR_PTR)
+#define FASTCLK_PLL_SR                  (CY_CLK_PLL_SR_REG)
+
+#define MAX_FASTCLK_PLL_Q_VALUE         (CY_CLK_PLL_MAX_Q_VALUE)
+#define MIN_FASTCLK_PLL_Q_VALUE         (CY_CLK_PLL_MIN_Q_VALUE)
+#define MIN_FASTCLK_PLL_P_VALUE         (CY_CLK_PLL_MIN_P_VALUE)
+#define MIN_FASTCLK_PLL_CUR_VALUE       (CY_CLK_PLL_MIN_CUR_VALUE)
+#define MAX_FASTCLK_PLL_CUR_VALUE       (CY_CLK_PLL_MAX_CUR_VALUE)
+
+#define PLL_CONTROL_ENABLE              (CY_CLK_PLL_ENABLE)
+#define PLL_STATUS_LOCK                 (CY_CLK_PLL_LOCK_STATUS)
+#define PLL_STATUS_ENABLED              (CY_CLK_PLL_ENABLE)
+#define PLL_CURRENT_POSITION            (CY_CLK_PLL_CURRENT_POSITION)
+#define PLL_VCO_GAIN_2                  (2u)
+
+#define FASTCLK_PLL_Q_PTR              (CY_CLK_PLL_Q_PTR)
+#define FASTCLK_PLL_Q                  (CY_CLK_PLL_Q_REG)
+#define FASTCLK_PLL_P_PTR              (CY_CLK_PLL_P_PTR)
+#define FASTCLK_PLL_P                  (CY_CLK_PLL_P_REG)
+#define FASTCLK_PLL_CFG1_PTR           (CY_CLK_PLL_CFG1_REG)
+#define FASTCLK_PLL_CFG1               (CY_CLK_PLL_CFG1_REG)
+
+#define CY_VD_PRESISTENT_STATUS_REG    (CY_VD_PERSISTENT_STATUS_REG)
+#define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
+
+
+#if(CY_PSOC5)
+
+    #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
+
+    #define CYINT_VECT_TABLE    (CY_INT_VECT_TABLE)
+    #define CYINT_PRIORITY      (CY_INT_PRIORITY_PTR)
+    #define CYINT_ENABLE        (CY_INT_ENABLE_PTR)
+    #define CYINT_CLEAR         (CY_INT_CLEAR_PTR)
+    #define CYINT_SET_PEND      (CY_INT_SET_PEND_PTR)
+    #define CYINT_CLR_PEND      (CY_INT_CLR_PEND_PTR)
+    #define CACHE_CC_CTL        (CY_CACHE_CONTROL_PTR)
+
+#elif (CY_PSOC3)
+
+    #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
+
+    #define CYINT_VECT_TABLE    (CY_INT_VECT_TABLE)
+    #define CYINT_PRIORITY      (CY_INT_PRIORITY_PTR)
+    #define CYINT_ENABLE        (CY_INT_ENABLE_PTR)
+    #define CYINT_CLEAR         (CY_INT_CLEAR_PTR)
+    #define CYINT_SET_PEND      (CY_INT_SET_PEND_PTR)
+    #define CYINT_CLR_PEND      (CY_INT_CLR_PEND_PTR)
+
+#endif  /* (CY_PSOC5) */
+
+
+
+#define BUS_AMASK_CLEAR                 (0xF0u)
+#define BUS_DMASK_CLEAR                 (0x00u)
+#define CLKDIST_LD_LOAD_SET             (0x01u)
+#define CLKDIST_WRK0_MASK_SET           (0x80u) /* Enable shadow loads */
+#define MASTERCLK_DIVIDER_VALUE         (7u)
+#define CLKDIST_BCFG2_SSS_SET           (0x40u) /* Sync source is same frequency */
+#define MASTER_CLK_SRC_CLEAR            (0xFCu)
+#define IMO_DOUBLER_ENABLE              (0x10u)
+#define CLOCK_IMO_IMO                   (0x20u)
+#define CLOCK_IMO2X_XTAL                (0x40u)
+#define CLOCK_IMO_RANGE_CLEAR           (0xF8u)
+#define CLOCK_CONTROL_DIST_MASK         (0xFCu)
+
+
+#define CLKDIST_AMASK                  (*(reg8 *) CYREG_CLKDIST_AMASK)
+#define CLKDIST_AMASK_PTR              ( (reg8 *) CYREG_CLKDIST_AMASK)
+#define CLKDIST_DMASK_PTR              ( (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLKDIST_DMASK                  (*(reg8 *) CYREG_CLKDIST_DMASK)
+#define CLKDIST_BCFG2_PTR              ( (reg8 *) CYREG_CLKDIST_BCFG2)
+#define CLKDIST_BCFG2                  (*(reg8 *) CYREG_CLKDIST_BCFG2)
+#define CLKDIST_WRK0_PTR               ( (reg8 *) CYREG_CLKDIST_WRK0)
+#define CLKDIST_WRK0                   (*(reg8 *) CYREG_CLKDIST_WRK0)
+#define CLKDIST_LD_PTR                 ( (reg8 *) CYREG_CLKDIST_LD)
+#define CLKDIST_LD                     (*(reg8 *) CYREG_CLKDIST_LD)
+#define CLKDIST_BCFG0_PTR              ( (reg8 *) CYREG_CLKDIST_BCFG0)
+#define CLKDIST_BCFG0                  (*(reg8 *) CYREG_CLKDIST_BCFG0)
+#define CLKDIST_MSTR0_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR0)
+#define CLKDIST_MSTR0                  (*(reg8 *) CYREG_CLKDIST_MSTR0)
+#define FASTCLK_IMO_CR_PTR             ( (reg8 *) CYREG_FASTCLK_IMO_CR)
+#define FASTCLK_IMO_CR                 (*(reg8 *) CYREG_FASTCLK_IMO_CR)
+#define CLKDIST_CR_PTR                 ( (reg8 *) CYREG_CLKDIST_CR)
+#define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
+
+
+#define IMO_PM_ENABLE                   (0x10u)
+#define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
+#define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
+#define SLOWCLK_ILO_CR0_PTR            ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define SLOWCLK_ILO_CR0                (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define ILO_CONTROL_PD_MODE             (0x10u)
+#define ILO_CONTROL_PD_POSITION         (4u)
+#define ILO_CONTROL_1KHZ_ON             (0x02u)
+#define ILO_CONTROL_100KHZ_ON           (0x04u)
+#define ILO_CONTROL_33KHZ_ON            (0x20u)
+#define PM_TW_CFG0_PTR                 ( (reg8 *) CYREG_PM_TW_CFG0)
+#define PM_TW_CFG0                     (*(reg8 *) CYREG_PM_TW_CFG0)
+#define PM_TW_CFG2_PTR                 ( (reg8 *) CYREG_PM_TW_CFG2)
+#define PM_TW_CFG2                     (*(reg8 *) CYREG_PM_TW_CFG2)
+#define RESET_CR2               ((reg8 *) CYREG_RESET_CR2)
+#define FASTCLK_IMO_USBCLK_ON_SET       (0x40u)
+#define CLOCK_IMO_3MHZ_VALUE            (0x03u)
+#define CLOCK_IMO_6MHZ_VALUE            (0x01u)
+#define CLOCK_IMO_12MHZ_VALUE           (0x00u)
+#define CLOCK_IMO_24MHZ_VALUE           (0x02u)
+#define CLOCK_IMO_48MHZ_VALUE           (0x04u)
+#define CLOCK_IMO_62MHZ_VALUE           (0x05u)
+#define CLOCK_IMO_74MHZ_VALUE           (0x06u)
+#define CLKDIST_DIV_POSITION            (4u)
+#define CLKDIST_MSTR1_DIV_CLEAR         (0x0Fu)
+#define SFR_USER_CPUCLK_DIV_MASK        (0x0Fu)
+#define CLOCK_USB_ENABLE                (0x02u)
+#define CLOCK_IMO_OUT_X2                (0x10u)
+#define CLOCK_IMO_OUT_X1                ((uint8)(~CLOCK_IMO_OUT_X2))
+#define CLOCK_IMO2X_ECO                 ((uint8)(~CLOCK_IMO2X_DSI))
+#define USB_CLKDIST_CONFIG_MASK         (0x03u)
+#define USB_CLK_IMO2X                   (0x00u)
+#define USB_CLK_IMO                     (0x01u)
+#define USB_CLK_PLL                     (0x02u)
+#define USB_CLK_DSI                     (0x03u)
+#define USB_CLK_DIV2_ON                 (0x04u)
+#define USB_CLK_STOP_FLAG               (0x00u)
+#define USB_CLK_START_FLAG              (0x01u)
+#define FTW_CLEAR_ALL_BITS              (0x00u)
+#define FTW_CLEAR_FTW_BITS              (0xFCu)
+#define FTW_ENABLE                      (0x01u)
+#define PM_STBY_CFG0_PTR               ( (reg8 *) CYREG_PM_STBY_CFG0)
+#define PM_STBY_CFG0                   (*(reg8 *) CYREG_PM_STBY_CFG0)
+#define PM_AVAIL_CR2_PTR               ( (reg8 *) CYREG_PM_AVAIL_CR2)
+#define PM_AVAIL_CR2                   (*(reg8 *) CYREG_PM_AVAIL_CR2)
+#define CLKDIST_UCFG_PTR               ( (reg8 *) CYREG_CLKDIST_UCFG)
+#define CLKDIST_UCFG                   (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CLKDIST_MSTR1_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR1)
+#define CLKDIST_MSTR1                  (*(reg8 *) CYREG_CLKDIST_MSTR1)
+#define SFR_USER_CPUCLK_DIV_PTR        ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
+#define IMO_TR1_PTR                    ( (reg8 *) CYREG_IMO_TR1)
+#define IMO_TR1                        (*(reg8 *) CYREG_IMO_TR1)
+#define CLOCK_CONTROL                  ( (reg8 *) CYREG_CLKDIST_CR)
+#define CY_USB_CR1_PTR                 ( (reg8 *) CYREG_USB_CR1 )
+#define CY_USB_CR1                     (*(reg8 *) CYREG_USB_CR1 )
+#define USB_CLKDIST_CONFIG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
+#define USB_CLKDIST_CONFIG             (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CY_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
+#define CY_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
+#if(CY_PSOC3)
+    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+ #else
+    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+#endif  /* (CY_PSOC3) */
+
+
+#endif  /* (CY_BOOT_CYLIB_H) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c

@@ -1,736 +1,736 @@
-/*******************************************************************************
-* File Name: CySpc.c
-* Version 4.20
-*
-*  Description:
-*   Provides an API for the System Performance Component.
-*   The SPC functions are not meant to be called directly by the user
-*   application.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "CySpc.h"
-
-#define CY_SPC_KEY_ONE                      (0xB6u)
-#define CY_SPC_KEY_TWO(x)                   ((uint8) (((uint16) 0xD3u) + ((uint16) (x))))
-
-/* Command Codes */
-#define CY_SPC_CMD_LD_BYTE                  (0x00u)
-#define CY_SPC_CMD_LD_MULTI_BYTE            (0x01u)
-#define CY_SPC_CMD_LD_ROW                   (0x02u)
-#define CY_SPC_CMD_RD_BYTE                  (0x03u)
-#define CY_SPC_CMD_RD_MULTI_BYTE            (0x04u)
-#define CY_SPC_CMD_WR_ROW                   (0x05u)
-#define CY_SPC_CMD_WR_USER_NVL              (0x06u)
-#define CY_SPC_CMD_PRG_ROW                  (0x07u)
-#define CY_SPC_CMD_ER_SECTOR                (0x08u)
-#define CY_SPC_CMD_ER_ALL                   (0x09u)
-#define CY_SPC_CMD_RD_HIDDEN                (0x0Au)
-#define CY_SPC_CMD_PRG_PROTECT              (0x0Bu)
-#define CY_SPC_CMD_CHECKSUM                 (0x0Cu)
-#define CY_SPC_CMD_DWNLD_ALGORITHM          (0x0Du)
-#define CY_SPC_CMD_GET_TEMP                 (0x0Eu)
-#define CY_SPC_CMD_GET_ADC                  (0x0Fu)
-#define CY_SPC_CMD_RD_NVL_VOLATILE          (0x10u)
-#define CY_SPC_CMD_SETUP_TS                 (0x11u)
-#define CY_SPC_CMD_DISABLE_TS               (0x12u)
-#define CY_SPC_CMD_ER_ROW                   (0x13u)
-
-/* Enable bit in Active and Alternate Active mode templates */
-#define PM_SPC_PM_EN                        (0x08u)
-
-/* Gate calls to the SPC. */
-uint8 SpcLockState = CY_SPC_UNLOCKED;
-
-
-#if(CY_PSOC5)
-
-    /***************************************************************************
-    * The wait-state pipeline must be enabled prior to accessing the SPC
-    * register interface regardless of CPU frequency. The CySpcLock() saves
-    * current wait-state pipeline state and enables it. The CySpcUnlock()
-    * function, which must be called after SPC transaction, restores original
-    * state.
-    ***************************************************************************/
-    static uint32 spcWaitPipeBypass = 0u;
-
-#endif  /* (CY_PSOC5) */
-
-
-/*******************************************************************************
-* Function Name: CySpcStart
-********************************************************************************
-* Summary:
-*  Starts the SPC.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CySpcStart(void) 
-{
-    /* Save current global interrupt enable and disable it */
-    uint8 interruptState = CyEnterCriticalSection();
-
-    CY_SPC_PM_ACT_REG  |= PM_SPC_PM_EN;
-    CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN;
-
-    /* Restore global interrupt enable state */
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcStop
-********************************************************************************
-* Summary:
-*  Stops the SPC.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CySpcStop(void) 
-{
-    /* Save current global interrupt enable and disable it */
-    uint8 interruptState = CyEnterCriticalSection();
-
-    CY_SPC_PM_ACT_REG  &= ((uint8)(~PM_SPC_PM_EN));
-    CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN));
-
-    /* Restore global interrupt enable state */
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcReadData
-********************************************************************************
-* Summary:
-*  Reads data from the SPC.
-*
-* Parameters:
-*  uint8 buffer:
-*   Address to store data read.
-*
-*  uint8 size:
-*   Number of bytes to read from the SPC.
-*
-* Return:
-*  uint8:
-*   The number of bytes read from the SPC.
-*
-*******************************************************************************/
-uint8 CySpcReadData(uint8 buffer[], uint8 size) 
-{
-    uint8 i;
-
-    for(i = 0u; i < size; i++)
-    {
-        while(!CY_SPC_DATA_READY)
-        {
-            CyDelayUs(1u);
-        }
-        buffer[i] = CY_SPC_CPU_DATA_REG;
-    }
-
-    return(i);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcLoadMultiByte
-********************************************************************************
-* Summary:
-*  Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.
-*
-* Parameters:
-*  uint8 array:
-*   Id of the array.
-*
-*  uint16 address:
-*   Flash/eeprom addrress
-*
-*  uint8* buffer:
-*   Data to load to the row latch
-*
-*  uint16 number:
-*   Number bytes to load.
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*  CYRET_BAD_PARAM
-*
-*******************************************************************************/
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
-
-{
-    cystatus status = CYRET_STARTED;
-    uint8 i;
-
-    /***************************************************************************
-    * Check if number is correct for array. Number must be less than
-    * 32 for Flash or less than 16 for EEPROM.
-    ***************************************************************************/
-    if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) ||
-       ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u)))
-    {
-        if(CY_SPC_IDLE)
-        {
-            CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-            CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE);
-            CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE;
-
-            if(CY_SPC_BUSY)
-            {
-                CY_SPC_CPU_DATA_REG = array;
-                CY_SPC_CPU_DATA_REG = 1u & HI8(address);
-                CY_SPC_CPU_DATA_REG = LO8(address);
-                CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u));
-
-                for(i = 0u; i < size; i++)
-                {
-                    CY_SPC_CPU_DATA_REG = buffer[i];
-                }
-            }
-            else
-            {
-                status = CYRET_CANCELED;
-            }
-        }
-        else
-        {
-            status = CYRET_LOCKED;
-        }
-    }
-    else
-    {
-        status = CYRET_BAD_PARAM;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcLoadRow
-********************************************************************************
-* Summary:
-*  Loads a row of data into the row latch of a Flash/EEPROM array.
-*
-*  The buffer pointer should point to the data that should be written to the
-*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
-*  responsibility to prepare data: the preserved data are copied from flash into
-*  array with the modified data.
-*
-* Parameters:
-*  uint8 array:
-*   Id of the array.
-*
-*  uint8* buffer:
-*   Data to be loaded to the row latch
-*
-*  uint8 size:
-*   The number of data bytes that the SPC expects to be written. Depends on the
-*   type of the array and, if the array is Flash, whether ECC is being enabled
-*   or not. There are following values: flash row latch size with ECC enabled,
-*   flash row latch size with ECC disabled and EEPROM row latch size.
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
-{
-    cystatus status = CYRET_STARTED;
-    uint16 i;
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
-
-        /* Make sure the command was accepted */
-        if(CY_SPC_BUSY)
-        {
-            CY_SPC_CPU_DATA_REG = array;
-
-            for(i = 0u; i < size; i++)
-            {
-                CY_SPC_CPU_DATA_REG = buffer[i];
-            }
-        }
-        else
-        {
-            status = CYRET_CANCELED;
-        }
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcLoadRowFull
-********************************************************************************
-* Summary:
-*  Loads a row of data into the row latch of a Flash/EEPROM array.
-*
-*  The only data that are going to be changed should be passed. The function
-*  will handle unmodified data preservation based on DWR settings and input
-*  parameters.
-*
-* Parameters:
-*  uint8 array:
-*   Id of the array.
-*
-*  uint16 row:
-*   Flash row number to be loaded.
-*
-*  uint8* buffer:
-*   Data to be loaded to the row latch
-*
-*  uint8 size:
-*   The number of data bytes that the SPC expects to be written. Depends on the
-*   type of the array and, if the array is Flash, whether ECC is being enabled
-*   or not. There are following values: flash row latch size with ECC enabled,
-*   flash row latch size with ECC disabled and EEPROM row latch size.
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
-
-{
-    cystatus status = CYRET_STARTED;
-    uint16 i;
-
-    #if (CYDEV_ECC_ENABLE == 0)
-        uint32 offset;
-    #endif /* (CYDEV_ECC_ENABLE == 0) */
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
-
-        /* Make sure the command was accepted */
-        if(CY_SPC_BUSY)
-        {
-            CY_SPC_CPU_DATA_REG = array;
-
-            /*******************************************************************
-            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
-            * Data in ECC" DWR options are disabled, ECC section is available
-            * for user data.
-            *******************************************************************/
-            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
-
-                /*******************************************************************
-                * If size parameter equals size of the ECC row and selected array
-                * identification corresponds to the flash array (but not to EEPROM
-                * array) then data are going to be written to the ECC section.
-                * In this case flash data must be preserved. The flash data copied
-                * from flash data section to the SPC data register.
-                *******************************************************************/
-                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
-                {
-                    offset = CYDEV_FLS_BASE +
-                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
-                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
-
-                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
-                    {
-                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                    }
-                }
-
-            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
-
-
-            for(i = 0u; i < size; i++)
-            {
-                CY_SPC_CPU_DATA_REG = buffer[i];
-            }
-
-
-            /*******************************************************************
-            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
-            * ECC section can be used for storing device configuration data
-            * ("Store Configuration Data in ECC" DWR option is enabled) or for
-            * storing user data in the ECC section ("Store Configuration Data in
-            * ECC" DWR option is enabled). In both cases, the data in the ECC
-            * section must be preserved if flash data is written.
-            *******************************************************************/
-            #if (CYDEV_ECC_ENABLE == 0)
-
-
-                /*******************************************************************
-                * If size parameter equals size of the flash row and selected array
-                * identification corresponds to the flash array (but not to EEPROM
-                * array) then data are going to be written to the flash data
-                * section. In this case, ECC section data must be preserved.
-                * The ECC section data copied from ECC section to the SPC data
-                * register.
-                *******************************************************************/
-                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
-                {
-                    offset = CYDEV_ECC_BASE +
-                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
-                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
-
-                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
-                    {
-                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                    }
-                }
-
-            #else
-
-                if(0u != row)
-                {
-                    /* To remove unreferenced local variable warning */
-                }
-
-            #endif /* (CYDEV_ECC_ENABLE == 0) */
-        }
-        else
-        {
-            status = CYRET_CANCELED;
-        }
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcWriteRow
-********************************************************************************
-* Summary:
-*  Erases then programs a row in Flash/EEPROM with data in row latch.
-*
-* Parameters:
-*  uint8 array:
-*   Id of the array.
-*
-*  uint16 address:
-*   flash/eeprom addrress
-*
-*  uint8 tempPolarity:
-*   temperature polarity.
-*   1: the Temp Magnitude is interpreted as a positive value
-*   0: the Temp Magnitude is interpreted as a negative value
-*
-*  uint8 tempMagnitude:
-*   temperature magnitude.
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
-
-{
-    cystatus status = CYRET_STARTED;
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW;
-
-        /* Make sure the command was accepted */
-        if(CY_SPC_BUSY)
-        {
-            CY_SPC_CPU_DATA_REG = array;
-            CY_SPC_CPU_DATA_REG = HI8(address);
-            CY_SPC_CPU_DATA_REG = LO8(address);
-            CY_SPC_CPU_DATA_REG = tempPolarity;
-            CY_SPC_CPU_DATA_REG = tempMagnitude;
-        }
-        else
-        {
-            status = CYRET_CANCELED;
-        }
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcEraseSector
-********************************************************************************
-* Summary:
-*  Erases all data in the addressed sector (block of 64 rows).
-*
-* Parameters:
-*  uint8 array:
-*   Id of the array.
-*
-*  uint8 sectorNumber:
-*   Zero based sector number within Flash/EEPROM array
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
-{
-    cystatus status = CYRET_STARTED;
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR;
-
-        /* Make sure the command was accepted */
-        if(CY_SPC_BUSY)
-        {
-            CY_SPC_CPU_DATA_REG = array;
-            CY_SPC_CPU_DATA_REG = sectorNumber;
-        }
-        else
-        {
-            status = CYRET_CANCELED;
-        }
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcGetTemp
-********************************************************************************
-* Summary:
-*  Returns the internal die temperature
-*
-* Parameters:
-*  uint8 numSamples:
-*   Number of samples. Valid values are 1-5, resulting in 2 - 32 samples
-*   respectively.
-*
-* uint16 timerPeriod:
-*   Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits
-*   of 16 bit values are ignored.
-*
-* uint8 clkDivSelect:
-*   ADC ACLK clock divide value. Valid values are 2 - 225.
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_CANCELED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcGetTemp(uint8 numSamples)
-{
-    cystatus status = CYRET_STARTED;
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP;
-
-        /* Make sure the command was accepted */
-        if(CY_SPC_BUSY)
-        {
-            CY_SPC_CPU_DATA_REG = numSamples;
-        }
-        else
-        {
-            status = CYRET_CANCELED;
-        }
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcLock
-********************************************************************************
-* Summary:
-*  Locks the SPC so it can not be used by someone else:
-*   - Saves wait-pipeline enable state and enable pipeline (PSoC5)
-*
-* Parameters:
-*  Note
-*
-* Return:
-*  CYRET_SUCCESS - if the resource was free.
-*  CYRET_LOCKED  - if the SPC is in use.
-*
-*******************************************************************************/
-cystatus CySpcLock(void)
-{
-    cystatus status = CYRET_LOCKED;
-    uint8 interruptState;
-
-    /* Enter critical section */
-    interruptState = CyEnterCriticalSection();
-
-    if(CY_SPC_UNLOCKED == SpcLockState)
-    {
-        SpcLockState = CY_SPC_LOCKED;
-        status = CYRET_SUCCESS;
-
-        #if(CY_PSOC5)
-
-            if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
-            {
-                /* Enable pipeline registers */
-                CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS));
-
-                /* At least 2 NOP instructions are recommended */
-                CY_NOP;
-                CY_NOP;
-                CY_NOP;
-
-                spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
-            }
-
-        #endif  /* (CY_PSOC5) */
-    }
-
-    /* Exit critical section */
-    CyExitCriticalSection(interruptState);
-
-    return(status);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcUnlock
-********************************************************************************
-* Summary:
-*  Unlocks the SPC so it can be used by someone else:
-*   - Restores wait-pipeline enable state (PSoC5)
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void CySpcUnlock(void)
-{
-    uint8 interruptState;
-
-    /* Enter critical section */
-    interruptState = CyEnterCriticalSection();
-
-    /* Release the SPC object */
-    SpcLockState = CY_SPC_UNLOCKED;
-
-    #if(CY_PSOC5)
-
-        if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
-        {
-            /* Force to bypass pipeline registers */
-            CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS;
-
-            /* At least 2 NOP instructions are recommended */
-            CY_NOP;
-            CY_NOP;
-            CY_NOP;
-
-            spcWaitPipeBypass = 0u;
-        }
-
-    #endif  /* (CY_PSOC5) */
-
-    /* Exit critical section */
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: CySpcGetAlgorithm
-********************************************************************************
-* Summary:
-*  Downloads SPC algorithm from SPC SROM into SRAM.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  CYRET_STARTED
-*  CYRET_LOCKED
-*
-*******************************************************************************/
-cystatus CySpcGetAlgorithm(void)
-{
-    cystatus status = CYRET_STARTED;
-
-    /* Make sure the SPC is ready to accept command */
-    if(CY_SPC_IDLE)
-    {
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
-        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
-        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
-    }
-    else
-    {
-        status = CYRET_LOCKED;
-    }
-
-    return(status);
-}
-
-/* [] END OF FILE */
-
+/*******************************************************************************
+* File Name: CySpc.c
+* Version 4.20
+*
+*  Description:
+*   Provides an API for the System Performance Component.
+*   The SPC functions are not meant to be called directly by the user
+*   application.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CySpc.h"
+
+#define CY_SPC_KEY_ONE                      (0xB6u)
+#define CY_SPC_KEY_TWO(x)                   ((uint8) (((uint16) 0xD3u) + ((uint16) (x))))
+
+/* Command Codes */
+#define CY_SPC_CMD_LD_BYTE                  (0x00u)
+#define CY_SPC_CMD_LD_MULTI_BYTE            (0x01u)
+#define CY_SPC_CMD_LD_ROW                   (0x02u)
+#define CY_SPC_CMD_RD_BYTE                  (0x03u)
+#define CY_SPC_CMD_RD_MULTI_BYTE            (0x04u)
+#define CY_SPC_CMD_WR_ROW                   (0x05u)
+#define CY_SPC_CMD_WR_USER_NVL              (0x06u)
+#define CY_SPC_CMD_PRG_ROW                  (0x07u)
+#define CY_SPC_CMD_ER_SECTOR                (0x08u)
+#define CY_SPC_CMD_ER_ALL                   (0x09u)
+#define CY_SPC_CMD_RD_HIDDEN                (0x0Au)
+#define CY_SPC_CMD_PRG_PROTECT              (0x0Bu)
+#define CY_SPC_CMD_CHECKSUM                 (0x0Cu)
+#define CY_SPC_CMD_DWNLD_ALGORITHM          (0x0Du)
+#define CY_SPC_CMD_GET_TEMP                 (0x0Eu)
+#define CY_SPC_CMD_GET_ADC                  (0x0Fu)
+#define CY_SPC_CMD_RD_NVL_VOLATILE          (0x10u)
+#define CY_SPC_CMD_SETUP_TS                 (0x11u)
+#define CY_SPC_CMD_DISABLE_TS               (0x12u)
+#define CY_SPC_CMD_ER_ROW                   (0x13u)
+
+/* Enable bit in Active and Alternate Active mode templates */
+#define PM_SPC_PM_EN                        (0x08u)
+
+/* Gate calls to the SPC. */
+uint8 SpcLockState = CY_SPC_UNLOCKED;
+
+
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * The wait-state pipeline must be enabled prior to accessing the SPC
+    * register interface regardless of CPU frequency. The CySpcLock() saves
+    * current wait-state pipeline state and enables it. The CySpcUnlock()
+    * function, which must be called after SPC transaction, restores original
+    * state.
+    ***************************************************************************/
+    static uint32 spcWaitPipeBypass = 0u;
+
+#endif  /* (CY_PSOC5) */
+
+
+/*******************************************************************************
+* Function Name: CySpcStart
+********************************************************************************
+* Summary:
+*  Starts the SPC.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CySpcStart(void) 
+{
+    /* Save current global interrupt enable and disable it */
+    uint8 interruptState = CyEnterCriticalSection();
+
+    CY_SPC_PM_ACT_REG  |= PM_SPC_PM_EN;
+    CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN;
+
+    /* Restore global interrupt enable state */
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcStop
+********************************************************************************
+* Summary:
+*  Stops the SPC.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CySpcStop(void) 
+{
+    /* Save current global interrupt enable and disable it */
+    uint8 interruptState = CyEnterCriticalSection();
+
+    CY_SPC_PM_ACT_REG  &= ((uint8)(~PM_SPC_PM_EN));
+    CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN));
+
+    /* Restore global interrupt enable state */
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcReadData
+********************************************************************************
+* Summary:
+*  Reads data from the SPC.
+*
+* Parameters:
+*  uint8 buffer:
+*   Address to store data read.
+*
+*  uint8 size:
+*   Number of bytes to read from the SPC.
+*
+* Return:
+*  uint8:
+*   The number of bytes read from the SPC.
+*
+*******************************************************************************/
+uint8 CySpcReadData(uint8 buffer[], uint8 size) 
+{
+    uint8 i;
+
+    for(i = 0u; i < size; i++)
+    {
+        while(!CY_SPC_DATA_READY)
+        {
+            CyDelayUs(1u);
+        }
+        buffer[i] = CY_SPC_CPU_DATA_REG;
+    }
+
+    return(i);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcLoadMultiByte
+********************************************************************************
+* Summary:
+*  Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 address:
+*   Flash/eeprom addrress
+*
+*  uint8* buffer:
+*   Data to load to the row latch
+*
+*  uint16 number:
+*   Number bytes to load.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*  CYRET_BAD_PARAM
+*
+*******************************************************************************/
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint8 i;
+
+    /***************************************************************************
+    * Check if number is correct for array. Number must be less than
+    * 32 for Flash or less than 16 for EEPROM.
+    ***************************************************************************/
+    if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) ||
+       ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u)))
+    {
+        if(CY_SPC_IDLE)
+        {
+            CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+            CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE);
+            CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE;
+
+            if(CY_SPC_BUSY)
+            {
+                CY_SPC_CPU_DATA_REG = array;
+                CY_SPC_CPU_DATA_REG = 1u & HI8(address);
+                CY_SPC_CPU_DATA_REG = LO8(address);
+                CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u));
+
+                for(i = 0u; i < size; i++)
+                {
+                    CY_SPC_CPU_DATA_REG = buffer[i];
+                }
+            }
+            else
+            {
+                status = CYRET_CANCELED;
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcLoadRow
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The buffer pointer should point to the data that should be written to the
+*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
+*  responsibility to prepare data: the preserved data are copied from flash into
+*  array with the modified data.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The only data that are going to be changed should be passed. The function
+*  will handle unmodified data preservation based on DWR settings and input
+*  parameters.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 row:
+*   Flash row number to be loaded.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    #if (CYDEV_ECC_ENABLE == 0)
+        uint32 offset;
+    #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+            * Data in ECC" DWR options are disabled, ECC section is available
+            * for user data.
+            *******************************************************************/
+            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+                /*******************************************************************
+                * If size parameter equals size of the ECC row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the ECC section.
+                * In this case flash data must be preserved. The flash data copied
+                * from flash data section to the SPC data register.
+                *******************************************************************/
+                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_FLS_BASE +
+                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+            * ECC section can be used for storing device configuration data
+            * ("Store Configuration Data in ECC" DWR option is enabled) or for
+            * storing user data in the ECC section ("Store Configuration Data in
+            * ECC" DWR option is enabled). In both cases, the data in the ECC
+            * section must be preserved if flash data is written.
+            *******************************************************************/
+            #if (CYDEV_ECC_ENABLE == 0)
+
+
+                /*******************************************************************
+                * If size parameter equals size of the flash row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the flash data
+                * section. In this case, ECC section data must be preserved.
+                * The ECC section data copied from ECC section to the SPC data
+                * register.
+                *******************************************************************/
+                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_ECC_BASE +
+                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #else
+
+                if(0u != row)
+                {
+                    /* To remove unreferenced local variable warning */
+                }
+
+            #endif /* (CYDEV_ECC_ENABLE == 0) */
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcWriteRow
+********************************************************************************
+* Summary:
+*  Erases then programs a row in Flash/EEPROM with data in row latch.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 address:
+*   flash/eeprom addrress
+*
+*  uint8 tempPolarity:
+*   temperature polarity.
+*   1: the Temp Magnitude is interpreted as a positive value
+*   0: the Temp Magnitude is interpreted as a negative value
+*
+*  uint8 tempMagnitude:
+*   temperature magnitude.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
+
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+            CY_SPC_CPU_DATA_REG = HI8(address);
+            CY_SPC_CPU_DATA_REG = LO8(address);
+            CY_SPC_CPU_DATA_REG = tempPolarity;
+            CY_SPC_CPU_DATA_REG = tempMagnitude;
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcEraseSector
+********************************************************************************
+* Summary:
+*  Erases all data in the addressed sector (block of 64 rows).
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint8 sectorNumber:
+*   Zero based sector number within Flash/EEPROM array
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+            CY_SPC_CPU_DATA_REG = sectorNumber;
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcGetTemp
+********************************************************************************
+* Summary:
+*  Returns the internal die temperature
+*
+* Parameters:
+*  uint8 numSamples:
+*   Number of samples. Valid values are 1-5, resulting in 2 - 32 samples
+*   respectively.
+*
+* uint16 timerPeriod:
+*   Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits
+*   of 16 bit values are ignored.
+*
+* uint8 clkDivSelect:
+*   ADC ACLK clock divide value. Valid values are 2 - 225.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetTemp(uint8 numSamples)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = numSamples;
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcLock
+********************************************************************************
+* Summary:
+*  Locks the SPC so it can not be used by someone else:
+*   - Saves wait-pipeline enable state and enable pipeline (PSoC5)
+*
+* Parameters:
+*  Note
+*
+* Return:
+*  CYRET_SUCCESS - if the resource was free.
+*  CYRET_LOCKED  - if the SPC is in use.
+*
+*******************************************************************************/
+cystatus CySpcLock(void)
+{
+    cystatus status = CYRET_LOCKED;
+    uint8 interruptState;
+
+    /* Enter critical section */
+    interruptState = CyEnterCriticalSection();
+
+    if(CY_SPC_UNLOCKED == SpcLockState)
+    {
+        SpcLockState = CY_SPC_LOCKED;
+        status = CYRET_SUCCESS;
+
+        #if(CY_PSOC5)
+
+            if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
+            {
+                /* Enable pipeline registers */
+                CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS));
+
+                /* At least 2 NOP instructions are recommended */
+                CY_NOP;
+                CY_NOP;
+                CY_NOP;
+
+                spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
+            }
+
+        #endif  /* (CY_PSOC5) */
+    }
+
+    /* Exit critical section */
+    CyExitCriticalSection(interruptState);
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcUnlock
+********************************************************************************
+* Summary:
+*  Unlocks the SPC so it can be used by someone else:
+*   - Restores wait-pipeline enable state (PSoC5)
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CySpcUnlock(void)
+{
+    uint8 interruptState;
+
+    /* Enter critical section */
+    interruptState = CyEnterCriticalSection();
+
+    /* Release the SPC object */
+    SpcLockState = CY_SPC_UNLOCKED;
+
+    #if(CY_PSOC5)
+
+        if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
+        {
+            /* Force to bypass pipeline registers */
+            CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS;
+
+            /* At least 2 NOP instructions are recommended */
+            CY_NOP;
+            CY_NOP;
+            CY_NOP;
+
+            spcWaitPipeBypass = 0u;
+        }
+
+    #endif  /* (CY_PSOC5) */
+
+    /* Exit critical section */
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+*  Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+/* [] END OF FILE */
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h

@@ -1,168 +1,168 @@
-/*******************************************************************************
-* File Name: CySpc.c
-* Version 4.20
-*
-* Description:
-*  Provides definitions for the System Performance Component API.
-*  The SPC functions are not meant to be called directly by the user
-*  application.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_BOOT_CYSPC_H)
-#define CY_BOOT_CYSPC_H
-
-#include "cytypes.h"
-#include "CyLib.h"
-#include "cydevice_trm.h"
-
-
-/***************************************
-*    Global Variables
-***************************************/
-extern uint8 SpcLockState;
-
-
-/***************************************
-*    Function Prototypes
-***************************************/
-void     CySpcStart(void);
-void     CySpcStop(void);
-uint8    CySpcReadData(uint8 buffer[], uint8 size);
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
-;
-cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
-cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
-;
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
-;
-cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
-cystatus CySpcGetTemp(uint8 numSamples);
-cystatus CySpcGetAlgorithm(void);
-cystatus CySpcLock(void);
-void     CySpcUnlock(void);
-
-
-/***************************************
-*    API Constants
-***************************************/
-
-#define CY_SPC_LOCKED                       (0x01u)
-#define CY_SPC_UNLOCKED                     (0x00u)
-
-/*******************************************************************************
-* The Array ID indicates the unique ID of the SONOS array being accessed:
-* - 0x00-0x3E : Flash Arrays
-* - 0x3F      : Selects all Flash arrays simultaneously
-* - 0x40-0x7F : Embedded EEPROM Arrays
-*******************************************************************************/
-#define CY_SPC_FIRST_FLASH_ARRAYID          (0x00u)
-#define CY_SPC_LAST_FLASH_ARRAYID           (0x3Fu)
-#define CY_SPC_FIRST_EE_ARRAYID             (0x40u)
-#define CY_SPC_LAST_EE_ARRAYID              (0x7Fu)
-
-
-#define CY_SPC_STATUS_DATA_READY_MASK       (0x01u)
-#define CY_SPC_STATUS_IDLE_MASK             (0x02u)
-#define CY_SPC_STATUS_CODE_MASK             (0xFCu)
-#define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
-
-/* Status codes for SPC. */
-#define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
-#define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
-#define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
-#define CY_SPC_STATUS_ARRAY_ASLEEP          (0x03u)   /* Addressed Array is Asleep */
-#define CY_SPC_STATUS_EXTERN_ACCESS         (0x04u)   /* External Access Failure (SPC is not in external access mode) */
-#define CY_SPC_STATUS_INVALID_NUMBER        (0x05u)   /* Invalid 'N' Value for given command */
-#define CY_SPC_STATUS_TEST_MODE             (0x06u)   /* Test Mode Failure (SPC is not in test mode) */
-#define CY_SPC_STATUS_ALG_CSUM              (0x07u)   /* Smart Write Algorithm Checksum Failure */
-#define CY_SPC_STATUS_PARAM_CSUM            (0x08u)   /* Smart Write Parameter Checksum Failure */
-#define CY_SPC_STATUS_PROTECTION            (0x09u)   /* Protection Check Failure */
-#define CY_SPC_STATUS_ADDRESS_PARAM         (0x0Au)   /* Invalid Address parameter for the given command */
-#define CY_SPC_STATUS_COMMAND_CODE          (0x0Bu)   /* Invalid Command Code */
-#define CY_SPC_STATUS_ROW_ID                (0x0Cu)   /* Invalid Row ID parameter for given command */
-#define CY_SPC_STATUS_TADC_INPUT            (0x0Du)   /* Invalid input value for Get Temp & Get ADC commands */
-#define CY_SPC_STATUS_BUSY                  (0xFFu)   /* SPC is busy */
-
-#if(CY_PSOC5)
-
-    /* Wait-state pipeline */
-    #define CY_SPC_CPU_WAITPIPE_BYPASS      ((uint32)0x01u)
-
-#endif  /* (CY_PSOC5) */
-
-
-/***************************************
-* Registers
-***************************************/
-
-/* SPC CPU Data Register */
-#define CY_SPC_CPU_DATA_REG         (* (reg8 *) CYREG_SPC_CPU_DATA )
-#define CY_SPC_CPU_DATA_PTR         (  (reg8 *) CYREG_SPC_CPU_DATA )
-
-/* SPC Status Register */
-#define CY_SPC_STATUS_REG           (* (reg8 *) CYREG_SPC_SR )
-#define CY_SPC_STATUS_PTR           (  (reg8 *) CYREG_SPC_SR )
-
-/* Active Power Mode Configuration Register 0 */
-#define CY_SPC_PM_ACT_REG           (* (reg8 *) CYREG_PM_ACT_CFG0 )
-#define CY_SPC_PM_ACT_PTR           (  (reg8 *) CYREG_PM_ACT_CFG0 )
-
-/* Standby Power Mode Configuration Register 0 */
-#define CY_SPC_PM_STBY_REG          (* (reg8 *) CYREG_PM_STBY_CFG0 )
-#define CY_SPC_PM_STBY_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0 )
-
-#if(CY_PSOC5)
-
-    /* Wait State Pipeline */
-    #define CY_SPC_CPU_WAITPIPE_REG     (* (reg32 *) CYREG_PANTHER_WAITPIPE )
-    #define CY_SPC_CPU_WAITPIPE_PTR     (  (reg32 *) CYREG_PANTHER_WAITPIPE )
-
-#endif  /* (CY_PSOC5) */
-
-
-/***************************************
-* Macros
-***************************************/
-#define CY_SPC_IDLE                 (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
-#define CY_SPC_BUSY                 (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
-#define CY_SPC_DATA_READY           (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))
-
-/* SPC must be in idle state in order to obtain correct status */
-#define CY_SPC_READ_STATUS          (CY_SPC_IDLE ? \
-                                     ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \
-                                     ((uint8) CY_SPC_STATUS_BUSY))
-
-
-/*******************************************************************************
-* The following code is OBSOLETE and must not be used.
-*
-* If the obsoleted macro definitions intended for use in the application use the
-* following scheme, redefine your own versions of these definitions:
-*    #ifdef <OBSOLETED_DEFINE>
-*        #undef  <OBSOLETED_DEFINE>
-*        #define <OBSOLETED_DEFINE>      (<New Value>)
-*    #endif
-*
-* Note: Redefine obsoleted macro definitions with caution. They might still be
-*       used in the application and their modification might lead to unexpected
-*       consequences.
-*******************************************************************************/
-#define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
-#define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
-#define FIRST_EE_ARRAYID            (CY_SPC_FIRST_EE_ARRAYID)
-#define LAST_EE_ARRAYID             (CY_SPC_LAST_EE_ARRAYID)
-#define SIZEOF_ECC_ROW              (CYDEV_ECC_ROW_SIZE)
-#define SIZEOF_FLASH_ROW            (CYDEV_FLS_ROW_SIZE)
-#define SIZEOF_EEPROM_ROW           (CYDEV_EEPROM_ROW_SIZE)
-
-
-#endif /* (CY_BOOT_CYSPC_H) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: CySpc.c
+* Version 4.20
+*
+* Description:
+*  Provides definitions for the System Performance Component API.
+*  The SPC functions are not meant to be called directly by the user
+*  application.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_BOOT_CYSPC_H)
+#define CY_BOOT_CYSPC_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+#include "cydevice_trm.h"
+
+
+/***************************************
+*    Global Variables
+***************************************/
+extern uint8 SpcLockState;
+
+
+/***************************************
+*    Function Prototypes
+***************************************/
+void     CySpcStart(void);
+void     CySpcStop(void);
+uint8    CySpcReadData(uint8 buffer[], uint8 size);
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
+;
+cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
+;
+cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
+cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
+cystatus CySpcLock(void);
+void     CySpcUnlock(void);
+
+
+/***************************************
+*    API Constants
+***************************************/
+
+#define CY_SPC_LOCKED                       (0x01u)
+#define CY_SPC_UNLOCKED                     (0x00u)
+
+/*******************************************************************************
+* The Array ID indicates the unique ID of the SONOS array being accessed:
+* - 0x00-0x3E : Flash Arrays
+* - 0x3F      : Selects all Flash arrays simultaneously
+* - 0x40-0x7F : Embedded EEPROM Arrays
+*******************************************************************************/
+#define CY_SPC_FIRST_FLASH_ARRAYID          (0x00u)
+#define CY_SPC_LAST_FLASH_ARRAYID           (0x3Fu)
+#define CY_SPC_FIRST_EE_ARRAYID             (0x40u)
+#define CY_SPC_LAST_EE_ARRAYID              (0x7Fu)
+
+
+#define CY_SPC_STATUS_DATA_READY_MASK       (0x01u)
+#define CY_SPC_STATUS_IDLE_MASK             (0x02u)
+#define CY_SPC_STATUS_CODE_MASK             (0xFCu)
+#define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
+
+/* Status codes for SPC. */
+#define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
+#define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
+#define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
+#define CY_SPC_STATUS_ARRAY_ASLEEP          (0x03u)   /* Addressed Array is Asleep */
+#define CY_SPC_STATUS_EXTERN_ACCESS         (0x04u)   /* External Access Failure (SPC is not in external access mode) */
+#define CY_SPC_STATUS_INVALID_NUMBER        (0x05u)   /* Invalid 'N' Value for given command */
+#define CY_SPC_STATUS_TEST_MODE             (0x06u)   /* Test Mode Failure (SPC is not in test mode) */
+#define CY_SPC_STATUS_ALG_CSUM              (0x07u)   /* Smart Write Algorithm Checksum Failure */
+#define CY_SPC_STATUS_PARAM_CSUM            (0x08u)   /* Smart Write Parameter Checksum Failure */
+#define CY_SPC_STATUS_PROTECTION            (0x09u)   /* Protection Check Failure */
+#define CY_SPC_STATUS_ADDRESS_PARAM         (0x0Au)   /* Invalid Address parameter for the given command */
+#define CY_SPC_STATUS_COMMAND_CODE          (0x0Bu)   /* Invalid Command Code */
+#define CY_SPC_STATUS_ROW_ID                (0x0Cu)   /* Invalid Row ID parameter for given command */
+#define CY_SPC_STATUS_TADC_INPUT            (0x0Du)   /* Invalid input value for Get Temp & Get ADC commands */
+#define CY_SPC_STATUS_BUSY                  (0xFFu)   /* SPC is busy */
+
+#if(CY_PSOC5)
+
+    /* Wait-state pipeline */
+    #define CY_SPC_CPU_WAITPIPE_BYPASS      ((uint32)0x01u)
+
+#endif  /* (CY_PSOC5) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* SPC CPU Data Register */
+#define CY_SPC_CPU_DATA_REG         (* (reg8 *) CYREG_SPC_CPU_DATA )
+#define CY_SPC_CPU_DATA_PTR         (  (reg8 *) CYREG_SPC_CPU_DATA )
+
+/* SPC Status Register */
+#define CY_SPC_STATUS_REG           (* (reg8 *) CYREG_SPC_SR )
+#define CY_SPC_STATUS_PTR           (  (reg8 *) CYREG_SPC_SR )
+
+/* Active Power Mode Configuration Register 0 */
+#define CY_SPC_PM_ACT_REG           (* (reg8 *) CYREG_PM_ACT_CFG0 )
+#define CY_SPC_PM_ACT_PTR           (  (reg8 *) CYREG_PM_ACT_CFG0 )
+
+/* Standby Power Mode Configuration Register 0 */
+#define CY_SPC_PM_STBY_REG          (* (reg8 *) CYREG_PM_STBY_CFG0 )
+#define CY_SPC_PM_STBY_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0 )
+
+#if(CY_PSOC5)
+
+    /* Wait State Pipeline */
+    #define CY_SPC_CPU_WAITPIPE_REG     (* (reg32 *) CYREG_PANTHER_WAITPIPE )
+    #define CY_SPC_CPU_WAITPIPE_PTR     (  (reg32 *) CYREG_PANTHER_WAITPIPE )
+
+#endif  /* (CY_PSOC5) */
+
+
+/***************************************
+* Macros
+***************************************/
+#define CY_SPC_IDLE                 (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
+#define CY_SPC_BUSY                 (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
+#define CY_SPC_DATA_READY           (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))
+
+/* SPC must be in idle state in order to obtain correct status */
+#define CY_SPC_READ_STATUS          (CY_SPC_IDLE ? \
+                                     ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \
+                                     ((uint8) CY_SPC_STATUS_BUSY))
+
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
+#define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
+#define FIRST_EE_ARRAYID            (CY_SPC_FIRST_EE_ARRAYID)
+#define LAST_EE_ARRAYID             (CY_SPC_LAST_EE_ARRAYID)
+#define SIZEOF_ECC_ROW              (CYDEV_ECC_ROW_SIZE)
+#define SIZEOF_FLASH_ROW            (CYDEV_FLS_ROW_SIZE)
+#define SIZEOF_EEPROM_ROW           (CYDEV_EEPROM_ROW_SIZE)
+
+
+#endif /* (CY_BOOT_CYSPC_H) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c

@@ -1,774 +1,774 @@
-/*******************************************************************************
-* File Name: Debug_Timer.c
-* Version 2.70
-*
-* Description:
-*  The Timer component consists of a 8, 16, 24 or 32-bit timer with
-*  a selectable period between 2 and 2^Width - 1.  The timer may free run
-*  or be used as a capture timer as well.  The capture can be initiated
-*  by a positive or negative edge signal as well as via software.
-*  A trigger input can be programmed to enable the timer on rising edge
-*  falling edge, either edge or continous run.
-*  Interrupts may be generated due to a terminal count condition
-*  or a capture event.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-********************************************************************************/
-
-#include "Debug_Timer.h"
-
-uint8 Debug_Timer_initVar = 0u;
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Init
-********************************************************************************
-*
-* Summary:
-*  Initialize to the schematic state
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_Init(void) 
-{
-    #if(!Debug_Timer_UsingFixedFunction)
-            /* Interrupt State Backup for Critical Region*/
-            uint8 Debug_Timer_interruptState;
-    #endif /* Interrupt state back up for Fixed Function only */
-
-    #if (Debug_Timer_UsingFixedFunction)
-        /* Clear all bits but the enable bit (if it's already set) for Timer operation */
-        Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE;
-
-        /* Clear the mode bits for continuous run mode */
-        #if (CY_PSOC5A)
-            Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
-        #endif /* Clear bits in CONTROL2 only in PSOC5A */
-
-        #if (CY_PSOC3 || CY_PSOC5LP)
-            Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
-        #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
-
-        /* Check if One Shot mode is enabled i.e. RunMode !=0*/
-        #if (Debug_Timer_RunModeUsed != 0x0u)
-            /* Set 3rd bit of Control register to enable one shot mode */
-            Debug_Timer_CONTROL |= 0x04u;
-        #endif /* One Shot enabled only when RunModeUsed is not Continuous*/
-
-        #if (Debug_Timer_RunModeUsed == 2)
-            #if (CY_PSOC5A)
-                /* Set last 2 bits of control2 register if one shot(halt on
-                interrupt) is enabled*/
-                Debug_Timer_CONTROL2 |= 0x03u;
-            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
-
-            #if (CY_PSOC3 || CY_PSOC5LP)
-                /* Set last 2 bits of control3 register if one shot(halt on
-                interrupt) is enabled*/
-                Debug_Timer_CONTROL3 |= 0x03u;
-            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
-
-        #endif /* Remove section if One Shot Halt on Interrupt is not enabled */
-
-        #if (Debug_Timer_UsingHWEnable != 0)
-            #if (CY_PSOC5A)
-                /* Set the default Run Mode of the Timer to Continuous */
-                Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH;
-            #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
-
-            #if (CY_PSOC3 || CY_PSOC5LP)
-                /* Clear and Set ROD and COD bits of CFG2 register */
-                Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK));
-                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD;
-
-                /* Clear and Enable the HW enable bit in CFG2 register */
-                Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK));
-                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL;
-
-                /* Set the default Run Mode of the Timer to Continuous */
-                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS;
-            #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
-
-        #endif /* Configure Run Mode with hardware enable */
-
-        /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
-        Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK));
-        Debug_Timer_RT1 |= Debug_Timer_SYNC;
-
-        /*Enable DSI Sync all all inputs of the Timer*/
-        Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK));
-        Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN;
-
-        /* Set the IRQ to use the status register interrupts */
-        Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL;
-    #endif /* Configuring registers of fixed function implementation */
-
-    /* Set Initial values from Configuration */
-    Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD);
-    Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD);
-
-    #if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */
-        Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE;
-        Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT);
-    #endif /* Configure capture counter value */
-
-    #if (!Debug_Timer_UsingFixedFunction)
-        #if (Debug_Timer_SoftwareCaptureMode)
-            Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE);
-        #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
-
-        #if (Debug_Timer_SoftwareTriggerMode)
-            #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-                if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
-                {
-                    Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
-                }
-            #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-        #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
-
-        /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
-        /* Enter Critical Region*/
-        Debug_Timer_interruptState = CyEnterCriticalSection();
-
-        /* Use the interrupt output of the status register for IRQ output */
-        Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
-
-        /* Exit Critical Region*/
-        CyExitCriticalSection(Debug_Timer_interruptState);
-
-        #if (Debug_Timer_EnableTriggerMode)
-            Debug_Timer_EnableTrigger();
-        #endif /* Set Trigger enable bit for UDB implementation in the control register*/
-		
-		
-        #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
-            Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
-        #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
-
-        Debug_Timer_ClearFIFO();
-    #endif /* Configure additional features of UDB implementation */
-
-    Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE);
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Enable
-********************************************************************************
-*
-* Summary:
-*  Enable the Timer
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_Enable(void) 
-{
-    /* Globally Enable the Fixed Function Block chosen */
-    #if (Debug_Timer_UsingFixedFunction)
-        Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK;
-        Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK;
-    #endif /* Set Enable bit for enabling Fixed function timer*/
-
-    /* Remove assignment if control register is removed */
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
-        Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
-    #endif /* Remove assignment if control register is removed */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Start
-********************************************************************************
-*
-* Summary:
-*  The start function initializes the timer with the default values, the
-*  enables the timerto begin counting.  It does not enable interrupts,
-*  the EnableInt command should be called if interrupt generation is required.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Global variables:
-*  Debug_Timer_initVar: Is modified when this function is called for the
-*   first time. Is used to ensure that initialization happens only once.
-*
-*******************************************************************************/
-void Debug_Timer_Start(void) 
-{
-    if(Debug_Timer_initVar == 0u)
-    {
-        Debug_Timer_Init();
-
-        Debug_Timer_initVar = 1u;   /* Clear this bit for Initialization */
-    }
-
-    /* Enable the Timer */
-    Debug_Timer_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Stop
-********************************************************************************
-*
-* Summary:
-*  The stop function halts the timer, but does not change any modes or disable
-*  interrupts.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Side Effects: If the Enable mode is set to Hardware only then this function
-*               has no effect on the operation of the timer.
-*
-*******************************************************************************/
-void Debug_Timer_Stop(void) 
-{
-    /* Disable Timer */
-    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
-        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
-    #endif /* Remove assignment if control register is removed */
-
-    /* Globally disable the Fixed Function Block chosen */
-    #if (Debug_Timer_UsingFixedFunction)
-        Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK));
-        Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK));
-    #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SetInterruptMode
-********************************************************************************
-*
-* Summary:
-*  This function selects which of the interrupt inputs may cause an interrupt.
-*  The twosources are caputure and terminal.  One, both or neither may
-*  be selected.
-*
-* Parameters:
-*  interruptMode:   This parameter is used to enable interrups on either/or
-*                   terminal count or capture.
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_SetInterruptMode(uint8 interruptMode) 
-{
-    Debug_Timer_STATUS_MASK = interruptMode;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SoftwareCapture
-********************************************************************************
-*
-* Summary:
-*  This function forces a capture independent of the capture signal.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Side Effects:
-*  An existing hardware capture could be overwritten.
-*
-*******************************************************************************/
-void Debug_Timer_SoftwareCapture(void) 
-{
-    /* Generate a software capture by reading the counter register */
-    #if(Debug_Timer_UsingFixedFunction)
-        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
-    #else
-        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
-    #endif/* (Debug_Timer_UsingFixedFunction) */
-    /* Capture Data is now in the FIFO */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadStatusRegister
-********************************************************************************
-*
-* Summary:
-*  Reads the status register and returns it's state. This function should use
-*  defined types for the bit-field information as the bits in this register may
-*  be permuteable.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  The contents of the status register
-*
-* Side Effects:
-*  Status register bits may be clear on read.
-*
-*******************************************************************************/
-uint8   Debug_Timer_ReadStatusRegister(void) 
-{
-    return (Debug_Timer_STATUS);
-}
-
-
-#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadControlRegister
-********************************************************************************
-*
-* Summary:
-*  Reads the control register and returns it's value.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  The contents of the control register
-*
-*******************************************************************************/
-uint8 Debug_Timer_ReadControlRegister(void) 
-{
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
-        return ((uint8)Debug_Timer_CONTROL);
-    #else
-        return (0);
-    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_WriteControlRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the bit-field of the control register.
-*
-* Parameters:
-*  control: The contents of the control register
-*
-* Return:
-*
-*******************************************************************************/
-void Debug_Timer_WriteControlRegister(uint8 control) 
-{
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
-        Debug_Timer_CONTROL = control;
-    #else
-        control = 0u;
-    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-}
-
-#endif /* Remove API if control register is unused */
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadPeriod
-********************************************************************************
-*
-* Summary:
-*  This function returns the current value of the Period.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  The present value of the counter.
-*
-*******************************************************************************/
-uint16 Debug_Timer_ReadPeriod(void) 
-{
-   #if(Debug_Timer_UsingFixedFunction)
-       return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
-   #else
-       return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
-   #endif /* (Debug_Timer_UsingFixedFunction) */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_WritePeriod
-********************************************************************************
-*
-* Summary:
-*  This function is used to change the period of the counter.  The new period
-*  will be loaded the next time terminal count is detected.
-*
-* Parameters:
-*  period: This value may be between 1 and (2^Resolution)-1.  A value of 0 will
-*          result in the counter remaining at zero.
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_WritePeriod(uint16 period) 
-{
-    #if(Debug_Timer_UsingFixedFunction)
-        uint16 period_temp = (uint16)period;
-        CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp);
-    #else
-        CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period);
-    #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadCapture
-********************************************************************************
-*
-* Summary:
-*  This function returns the last value captured.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  Present Capture value.
-*
-*******************************************************************************/
-uint16 Debug_Timer_ReadCapture(void) 
-{
-   #if(Debug_Timer_UsingFixedFunction)
-       return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
-   #else
-       return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
-   #endif /* (Debug_Timer_UsingFixedFunction) */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_WriteCounter
-********************************************************************************
-*
-* Summary:
-*  This funtion is used to set the counter to a specific value
-*
-* Parameters:
-*  counter:  New counter value.
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_WriteCounter(uint16 counter) 
-{
-   #if(Debug_Timer_UsingFixedFunction)
-        /* This functionality is removed until a FixedFunction HW update to
-         * allow this register to be written
-         */
-        CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter);
-        
-    #else
-        CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter);
-    #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadCounter
-********************************************************************************
-*
-* Summary:
-*  This function returns the current counter value.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  Present compare value.
-*
-*******************************************************************************/
-uint16 Debug_Timer_ReadCounter(void) 
-{
-    /* Force capture by reading Accumulator */
-    /* Must first do a software capture to be able to read the counter */
-    /* It is up to the user code to make sure there isn't already captured data in the FIFO */
-    #if(Debug_Timer_UsingFixedFunction)
-        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
-    #else
-        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
-    #endif/* (Debug_Timer_UsingFixedFunction) */
-
-    /* Read the data from the FIFO (or capture register for Fixed Function)*/
-    #if(Debug_Timer_UsingFixedFunction)
-        return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
-    #else
-        return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
-    #endif /* (Debug_Timer_UsingFixedFunction) */
-}
-
-
-#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
-
-    
-/*******************************************************************************
- * The functions below this point are only available using the UDB
- * implementation.  If a feature is selected, then the API is enabled.
- ******************************************************************************/
-
-
-#if (Debug_Timer_SoftwareCaptureMode)
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SetCaptureMode
-********************************************************************************
-*
-* Summary:
-*  This function sets the capture mode to either rising or falling edge.
-*
-* Parameters:
-*  captureMode: This parameter sets the capture mode of the UDB capture feature
-*  The parameter values are defined using the
-*  #define Debug_Timer__B_TIMER__CM_NONE 0
-#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
-#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
-#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
-#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
- identifiers
-*  The following are the possible values of the parameter
-*  Debug_Timer__B_TIMER__CM_NONE        - Set Capture mode to None
-*  Debug_Timer__B_TIMER__CM_RISINGEDGE  - Rising edge of Capture input
-*  Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
-*  Debug_Timer__B_TIMER__CM_EITHEREDGE  - Either edge of Capture input
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_SetCaptureMode(uint8 captureMode) 
-{
-    /* This must only set to two bits of the control register associated */
-    captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
-    captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
-
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-        /* Clear the Current Setting */
-        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
-
-        /* Write The New Setting */
-        Debug_Timer_CONTROL |= captureMode;
-    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-}
-#endif /* Remove API if Capture Mode is not Software Controlled */
-
-
-#if (Debug_Timer_SoftwareTriggerMode)
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SetTriggerMode
-********************************************************************************
-*
-* Summary:
-*  This function sets the trigger input mode
-*
-* Parameters:
-*  triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
-    #define Debug_Timer__B_TIMER__TM_NONE 0x00u
-    #define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
-    #define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
-    #define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
-    #define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_SetTriggerMode(uint8 triggerMode) 
-{
-    /* This must only set to two bits of the control register associated */
-    triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
-
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
-    
-        /* Clear the Current Setting */
-        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
-
-        /* Write The New Setting */
-        Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
-    #endif /* Remove code section if control register is not used */
-}
-#endif /* Remove API if Trigger Mode is not Software Controlled */
-
-#if (Debug_Timer_EnableTriggerMode)
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_EnableTrigger
-********************************************************************************
-*
-* Summary:
-*  Sets the control bit enabling Hardware Trigger mode
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_EnableTrigger(void) 
-{
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
-        Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
-    #endif /* Remove code section if control register is not used */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_DisableTrigger
-********************************************************************************
-*
-* Summary:
-*  Clears the control bit enabling Hardware Trigger mode
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_DisableTrigger(void) 
-{
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED )   /* Remove assignment if control register is removed */
-        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
-    #endif /* Remove code section if control register is not used */
-}
-#endif /* Remove API is Trigger Mode is set to None */
-
-#if(Debug_Timer_InterruptOnCaptureCount)
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SetInterruptCount
-********************************************************************************
-*
-* Summary:
-*  This function sets the capture count before an interrupt is triggered.
-*
-* Parameters:
-*  interruptCount:  A value between 0 and 3 is valid.  If the value is 0, then
-*                   an interrupt will occur each time a capture occurs.
-*                   A value of 1 to 3 will cause the interrupt
-*                   to delay by the same number of captures.
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_SetInterruptCount(uint8 interruptCount) 
-{
-    /* This must only set to two bits of the control register associated */
-    interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
-
-    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-        /* Clear the Current Setting */
-        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
-        /* Write The New Setting */
-        Debug_Timer_CONTROL |= interruptCount;
-    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-}
-#endif /* Debug_Timer_InterruptOnCaptureCount */
-
-
-#if (Debug_Timer_UsingHWCaptureCounter)
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SetCaptureCount
-********************************************************************************
-*
-* Summary:
-*  This function sets the capture count
-*
-* Parameters:
-*  captureCount: A value between 2 and 127 inclusive is valid.  A value of 1
-*                to 127 will cause the interrupt to delay by the same number of
-*                captures.
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_SetCaptureCount(uint8 captureCount) 
-{
-    Debug_Timer_CAP_COUNT = captureCount;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ReadCaptureCount
-********************************************************************************
-*
-* Summary:
-*  This function reads the capture count setting
-*
-* Parameters:
-*  void
-*
-* Return:
-*  Returns the Capture Count Setting
-*
-*******************************************************************************/
-uint8 Debug_Timer_ReadCaptureCount(void) 
-{
-    return ((uint8)Debug_Timer_CAP_COUNT);
-}
-#endif /* Debug_Timer_UsingHWCaptureCounter */
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_ClearFIFO
-********************************************************************************
-*
-* Summary:
-*  This function clears all capture data from the capture FIFO
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-*******************************************************************************/
-void Debug_Timer_ClearFIFO(void) 
-{
-    while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP))
-    {
-        (void)Debug_Timer_ReadCapture();
-    }
-}
-
-#endif /* UDB Specific Functions */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Debug_Timer.c
+* Version 2.70
+*
+* Description:
+*  The Timer component consists of a 8, 16, 24 or 32-bit timer with
+*  a selectable period between 2 and 2^Width - 1.  The timer may free run
+*  or be used as a capture timer as well.  The capture can be initiated
+*  by a positive or negative edge signal as well as via software.
+*  A trigger input can be programmed to enable the timer on rising edge
+*  falling edge, either edge or continous run.
+*  Interrupts may be generated due to a terminal count condition
+*  or a capture event.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "Debug_Timer.h"
+
+uint8 Debug_Timer_initVar = 0u;
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Init
+********************************************************************************
+*
+* Summary:
+*  Initialize to the schematic state
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_Init(void) 
+{
+    #if(!Debug_Timer_UsingFixedFunction)
+            /* Interrupt State Backup for Critical Region*/
+            uint8 Debug_Timer_interruptState;
+    #endif /* Interrupt state back up for Fixed Function only */
+
+    #if (Debug_Timer_UsingFixedFunction)
+        /* Clear all bits but the enable bit (if it's already set) for Timer operation */
+        Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE;
+
+        /* Clear the mode bits for continuous run mode */
+        #if (CY_PSOC5A)
+            Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
+        #endif /* Clear bits in CONTROL2 only in PSOC5A */
+
+        #if (CY_PSOC3 || CY_PSOC5LP)
+            Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
+        #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
+
+        /* Check if One Shot mode is enabled i.e. RunMode !=0*/
+        #if (Debug_Timer_RunModeUsed != 0x0u)
+            /* Set 3rd bit of Control register to enable one shot mode */
+            Debug_Timer_CONTROL |= 0x04u;
+        #endif /* One Shot enabled only when RunModeUsed is not Continuous*/
+
+        #if (Debug_Timer_RunModeUsed == 2)
+            #if (CY_PSOC5A)
+                /* Set last 2 bits of control2 register if one shot(halt on
+                interrupt) is enabled*/
+                Debug_Timer_CONTROL2 |= 0x03u;
+            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
+
+            #if (CY_PSOC3 || CY_PSOC5LP)
+                /* Set last 2 bits of control3 register if one shot(halt on
+                interrupt) is enabled*/
+                Debug_Timer_CONTROL3 |= 0x03u;
+            #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
+
+        #endif /* Remove section if One Shot Halt on Interrupt is not enabled */
+
+        #if (Debug_Timer_UsingHWEnable != 0)
+            #if (CY_PSOC5A)
+                /* Set the default Run Mode of the Timer to Continuous */
+                Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH;
+            #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
+
+            #if (CY_PSOC3 || CY_PSOC5LP)
+                /* Clear and Set ROD and COD bits of CFG2 register */
+                Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK));
+                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD;
+
+                /* Clear and Enable the HW enable bit in CFG2 register */
+                Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK));
+                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL;
+
+                /* Set the default Run Mode of the Timer to Continuous */
+                Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS;
+            #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
+
+        #endif /* Configure Run Mode with hardware enable */
+
+        /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
+        Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK));
+        Debug_Timer_RT1 |= Debug_Timer_SYNC;
+
+        /*Enable DSI Sync all all inputs of the Timer*/
+        Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK));
+        Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN;
+
+        /* Set the IRQ to use the status register interrupts */
+        Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL;
+    #endif /* Configuring registers of fixed function implementation */
+
+    /* Set Initial values from Configuration */
+    Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD);
+    Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD);
+
+    #if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */
+        Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE;
+        Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT);
+    #endif /* Configure capture counter value */
+
+    #if (!Debug_Timer_UsingFixedFunction)
+        #if (Debug_Timer_SoftwareCaptureMode)
+            Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE);
+        #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
+
+        #if (Debug_Timer_SoftwareTriggerMode)
+            #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+                if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
+                {
+                    Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
+                }
+            #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+        #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
+
+        /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
+        /* Enter Critical Region*/
+        Debug_Timer_interruptState = CyEnterCriticalSection();
+
+        /* Use the interrupt output of the status register for IRQ output */
+        Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
+
+        /* Exit Critical Region*/
+        CyExitCriticalSection(Debug_Timer_interruptState);
+
+        #if (Debug_Timer_EnableTriggerMode)
+            Debug_Timer_EnableTrigger();
+        #endif /* Set Trigger enable bit for UDB implementation in the control register*/
+		
+		
+        #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
+        #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+
+        Debug_Timer_ClearFIFO();
+    #endif /* Configure additional features of UDB implementation */
+
+    Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE);
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Enable
+********************************************************************************
+*
+* Summary:
+*  Enable the Timer
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_Enable(void) 
+{
+    /* Globally Enable the Fixed Function Block chosen */
+    #if (Debug_Timer_UsingFixedFunction)
+        Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK;
+        Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK;
+    #endif /* Set Enable bit for enabling Fixed function timer*/
+
+    /* Remove assignment if control register is removed */
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
+        Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
+    #endif /* Remove assignment if control register is removed */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Start
+********************************************************************************
+*
+* Summary:
+*  The start function initializes the timer with the default values, the
+*  enables the timerto begin counting.  It does not enable interrupts,
+*  the EnableInt command should be called if interrupt generation is required.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  Debug_Timer_initVar: Is modified when this function is called for the
+*   first time. Is used to ensure that initialization happens only once.
+*
+*******************************************************************************/
+void Debug_Timer_Start(void) 
+{
+    if(Debug_Timer_initVar == 0u)
+    {
+        Debug_Timer_Init();
+
+        Debug_Timer_initVar = 1u;   /* Clear this bit for Initialization */
+    }
+
+    /* Enable the Timer */
+    Debug_Timer_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Stop
+********************************************************************************
+*
+* Summary:
+*  The stop function halts the timer, but does not change any modes or disable
+*  interrupts.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Side Effects: If the Enable mode is set to Hardware only then this function
+*               has no effect on the operation of the timer.
+*
+*******************************************************************************/
+void Debug_Timer_Stop(void) 
+{
+    /* Disable Timer */
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
+    #endif /* Remove assignment if control register is removed */
+
+    /* Globally disable the Fixed Function Block chosen */
+    #if (Debug_Timer_UsingFixedFunction)
+        Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK));
+        Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK));
+    #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SetInterruptMode
+********************************************************************************
+*
+* Summary:
+*  This function selects which of the interrupt inputs may cause an interrupt.
+*  The twosources are caputure and terminal.  One, both or neither may
+*  be selected.
+*
+* Parameters:
+*  interruptMode:   This parameter is used to enable interrups on either/or
+*                   terminal count or capture.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_SetInterruptMode(uint8 interruptMode) 
+{
+    Debug_Timer_STATUS_MASK = interruptMode;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SoftwareCapture
+********************************************************************************
+*
+* Summary:
+*  This function forces a capture independent of the capture signal.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Side Effects:
+*  An existing hardware capture could be overwritten.
+*
+*******************************************************************************/
+void Debug_Timer_SoftwareCapture(void) 
+{
+    /* Generate a software capture by reading the counter register */
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
+    /* Capture Data is now in the FIFO */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadStatusRegister
+********************************************************************************
+*
+* Summary:
+*  Reads the status register and returns it's state. This function should use
+*  defined types for the bit-field information as the bits in this register may
+*  be permuteable.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The contents of the status register
+*
+* Side Effects:
+*  Status register bits may be clear on read.
+*
+*******************************************************************************/
+uint8   Debug_Timer_ReadStatusRegister(void) 
+{
+    return (Debug_Timer_STATUS);
+}
+
+
+#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadControlRegister
+********************************************************************************
+*
+* Summary:
+*  Reads the control register and returns it's value.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The contents of the control register
+*
+*******************************************************************************/
+uint8 Debug_Timer_ReadControlRegister(void) 
+{
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        return ((uint8)Debug_Timer_CONTROL);
+    #else
+        return (0);
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_WriteControlRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the bit-field of the control register.
+*
+* Parameters:
+*  control: The contents of the control register
+*
+* Return:
+*
+*******************************************************************************/
+void Debug_Timer_WriteControlRegister(uint8 control) 
+{
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        Debug_Timer_CONTROL = control;
+    #else
+        control = 0u;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+}
+
+#endif /* Remove API if control register is unused */
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadPeriod
+********************************************************************************
+*
+* Summary:
+*  This function returns the current value of the Period.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  The present value of the counter.
+*
+*******************************************************************************/
+uint16 Debug_Timer_ReadPeriod(void) 
+{
+   #if(Debug_Timer_UsingFixedFunction)
+       return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
+   #else
+       return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
+   #endif /* (Debug_Timer_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_WritePeriod
+********************************************************************************
+*
+* Summary:
+*  This function is used to change the period of the counter.  The new period
+*  will be loaded the next time terminal count is detected.
+*
+* Parameters:
+*  period: This value may be between 1 and (2^Resolution)-1.  A value of 0 will
+*          result in the counter remaining at zero.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_WritePeriod(uint16 period) 
+{
+    #if(Debug_Timer_UsingFixedFunction)
+        uint16 period_temp = (uint16)period;
+        CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp);
+    #else
+        CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period);
+    #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadCapture
+********************************************************************************
+*
+* Summary:
+*  This function returns the last value captured.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Present Capture value.
+*
+*******************************************************************************/
+uint16 Debug_Timer_ReadCapture(void) 
+{
+   #if(Debug_Timer_UsingFixedFunction)
+       return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+   #else
+       return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+   #endif /* (Debug_Timer_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_WriteCounter
+********************************************************************************
+*
+* Summary:
+*  This funtion is used to set the counter to a specific value
+*
+* Parameters:
+*  counter:  New counter value.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_WriteCounter(uint16 counter) 
+{
+   #if(Debug_Timer_UsingFixedFunction)
+        /* This functionality is removed until a FixedFunction HW update to
+         * allow this register to be written
+         */
+        CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter);
+        
+    #else
+        CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter);
+    #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadCounter
+********************************************************************************
+*
+* Summary:
+*  This function returns the current counter value.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Present compare value.
+*
+*******************************************************************************/
+uint16 Debug_Timer_ReadCounter(void) 
+{
+    /* Force capture by reading Accumulator */
+    /* Must first do a software capture to be able to read the counter */
+    /* It is up to the user code to make sure there isn't already captured data in the FIFO */
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
+
+    /* Read the data from the FIFO (or capture register for Fixed Function)*/
+    #if(Debug_Timer_UsingFixedFunction)
+        return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+    #else
+        return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+    #endif /* (Debug_Timer_UsingFixedFunction) */
+}
+
+
+#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
+
+    
+/*******************************************************************************
+ * The functions below this point are only available using the UDB
+ * implementation.  If a feature is selected, then the API is enabled.
+ ******************************************************************************/
+
+
+#if (Debug_Timer_SoftwareCaptureMode)
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SetCaptureMode
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture mode to either rising or falling edge.
+*
+* Parameters:
+*  captureMode: This parameter sets the capture mode of the UDB capture feature
+*  The parameter values are defined using the
+*  #define Debug_Timer__B_TIMER__CM_NONE 0
+#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
+#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
+#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
+#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
+ identifiers
+*  The following are the possible values of the parameter
+*  Debug_Timer__B_TIMER__CM_NONE        - Set Capture mode to None
+*  Debug_Timer__B_TIMER__CM_RISINGEDGE  - Rising edge of Capture input
+*  Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
+*  Debug_Timer__B_TIMER__CM_EITHEREDGE  - Either edge of Capture input
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_SetCaptureMode(uint8 captureMode) 
+{
+    /* This must only set to two bits of the control register associated */
+    captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
+    captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
+
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
+
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= captureMode;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+}
+#endif /* Remove API if Capture Mode is not Software Controlled */
+
+
+#if (Debug_Timer_SoftwareTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SetTriggerMode
+********************************************************************************
+*
+* Summary:
+*  This function sets the trigger input mode
+*
+* Parameters:
+*  triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
+    #define Debug_Timer__B_TIMER__TM_NONE 0x00u
+    #define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
+    #define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
+    #define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
+    #define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_SetTriggerMode(uint8 triggerMode) 
+{
+    /* This must only set to two bits of the control register associated */
+    triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
+
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
+    
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
+
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+    #endif /* Remove code section if control register is not used */
+}
+#endif /* Remove API if Trigger Mode is not Software Controlled */
+
+#if (Debug_Timer_EnableTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_EnableTrigger
+********************************************************************************
+*
+* Summary:
+*  Sets the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_EnableTrigger(void) 
+{
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
+        Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
+    #endif /* Remove code section if control register is not used */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_DisableTrigger
+********************************************************************************
+*
+* Summary:
+*  Clears the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_DisableTrigger(void) 
+{
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED )   /* Remove assignment if control register is removed */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
+    #endif /* Remove code section if control register is not used */
+}
+#endif /* Remove API is Trigger Mode is set to None */
+
+#if(Debug_Timer_InterruptOnCaptureCount)
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SetInterruptCount
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture count before an interrupt is triggered.
+*
+* Parameters:
+*  interruptCount:  A value between 0 and 3 is valid.  If the value is 0, then
+*                   an interrupt will occur each time a capture occurs.
+*                   A value of 1 to 3 will cause the interrupt
+*                   to delay by the same number of captures.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_SetInterruptCount(uint8 interruptCount) 
+{
+    /* This must only set to two bits of the control register associated */
+    interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
+
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= interruptCount;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+}
+#endif /* Debug_Timer_InterruptOnCaptureCount */
+
+
+#if (Debug_Timer_UsingHWCaptureCounter)
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SetCaptureCount
+********************************************************************************
+*
+* Summary:
+*  This function sets the capture count
+*
+* Parameters:
+*  captureCount: A value between 2 and 127 inclusive is valid.  A value of 1
+*                to 127 will cause the interrupt to delay by the same number of
+*                captures.
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_SetCaptureCount(uint8 captureCount) 
+{
+    Debug_Timer_CAP_COUNT = captureCount;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ReadCaptureCount
+********************************************************************************
+*
+* Summary:
+*  This function reads the capture count setting
+*
+* Parameters:
+*  void
+*
+* Return:
+*  Returns the Capture Count Setting
+*
+*******************************************************************************/
+uint8 Debug_Timer_ReadCaptureCount(void) 
+{
+    return ((uint8)Debug_Timer_CAP_COUNT);
+}
+#endif /* Debug_Timer_UsingHWCaptureCounter */
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_ClearFIFO
+********************************************************************************
+*
+* Summary:
+*  This function clears all capture data from the capture FIFO
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+*******************************************************************************/
+void Debug_Timer_ClearFIFO(void) 
+{
+    while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP))
+    {
+        (void)Debug_Timer_ReadCapture();
+    }
+}
+
+#endif /* UDB Specific Functions */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h

@@ -1,434 +1,434 @@
-/*******************************************************************************
-* File Name: Debug_Timer.h
-* Version 2.70
-*
-*  Description:
-*     Contains the function prototypes and constants available to the timer
-*     user module.
-*
-*   Note:
-*     None
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-********************************************************************************/
-
-#if !defined(CY_Timer_v2_60_Debug_Timer_H)
-#define CY_Timer_v2_60_Debug_Timer_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
-
-extern uint8 Debug_Timer_initVar;
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component Timer_v2_70 requires cy_boot v3.0 or later
-#endif /* (CY_ PSOC5LP) */
-
-
-/**************************************
-*           Parameter Defaults
-**************************************/
-
-#define Debug_Timer_Resolution                 16u
-#define Debug_Timer_UsingFixedFunction         1u
-#define Debug_Timer_UsingHWCaptureCounter      0u
-#define Debug_Timer_SoftwareCaptureMode        0u
-#define Debug_Timer_SoftwareTriggerMode        0u
-#define Debug_Timer_UsingHWEnable              0u
-#define Debug_Timer_EnableTriggerMode          0u
-#define Debug_Timer_InterruptOnCaptureCount    0u
-#define Debug_Timer_RunModeUsed                0u
-#define Debug_Timer_ControlRegRemoved          0u
-
-#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
-    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
-#elif  (Debug_Timer_UsingFixedFunction)
-    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
-#else 
-    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (1u)
-#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
-
-
-/***************************************
-*       Type defines
-***************************************/
-
-
-/**************************************************************************
- * Sleep Wakeup Backup structure for Timer Component
- *************************************************************************/
-typedef struct
-{
-    uint8 TimerEnableState;
-    #if(!Debug_Timer_UsingFixedFunction)
-
-        uint16 TimerUdb;
-        uint8 InterruptMaskValue;
-        #if (Debug_Timer_UsingHWCaptureCounter)
-            uint8 TimerCaptureCounter;
-        #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
-
-        #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-            uint8 TimerControlRegister;
-        #endif /* variable declaration for backing up enable state of the Timer */
-    #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
-
-}Debug_Timer_backupStruct;
-
-
-/***************************************
-*       Function Prototypes
-***************************************/
-
-void    Debug_Timer_Start(void) ;
-void    Debug_Timer_Stop(void) ;
-
-void    Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
-uint8   Debug_Timer_ReadStatusRegister(void) ;
-/* Deprecated function. Do not use this in future. Retained for backward compatibility */
-#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
-
-#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-    uint8   Debug_Timer_ReadControlRegister(void) ;
-    void    Debug_Timer_WriteControlRegister(uint8 control) ;
-#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
-
-uint16  Debug_Timer_ReadPeriod(void) ;
-void    Debug_Timer_WritePeriod(uint16 period) ;
-uint16  Debug_Timer_ReadCounter(void) ;
-void    Debug_Timer_WriteCounter(uint16 counter) ;
-uint16  Debug_Timer_ReadCapture(void) ;
-void    Debug_Timer_SoftwareCapture(void) ;
-
-#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
-    #if (Debug_Timer_SoftwareCaptureMode)
-        void    Debug_Timer_SetCaptureMode(uint8 captureMode) ;
-    #endif /* (!Debug_Timer_UsingFixedFunction) */
-
-    #if (Debug_Timer_SoftwareTriggerMode)
-        void    Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
-    #endif /* (Debug_Timer_SoftwareTriggerMode) */
-
-    #if (Debug_Timer_EnableTriggerMode)
-        void    Debug_Timer_EnableTrigger(void) ;
-        void    Debug_Timer_DisableTrigger(void) ;
-    #endif /* (Debug_Timer_EnableTriggerMode) */
-
-
-    #if(Debug_Timer_InterruptOnCaptureCount)
-        void    Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
-    #endif /* (Debug_Timer_InterruptOnCaptureCount) */
-
-    #if (Debug_Timer_UsingHWCaptureCounter)
-        void    Debug_Timer_SetCaptureCount(uint8 captureCount) ;
-        uint8   Debug_Timer_ReadCaptureCount(void) ;
-    #endif /* (Debug_Timer_UsingHWCaptureCounter) */
-
-    void Debug_Timer_ClearFIFO(void) ;
-#endif /* UDB Prototypes */
-
-/* Sleep Retention APIs */
-void Debug_Timer_Init(void)          ;
-void Debug_Timer_Enable(void)        ;
-void Debug_Timer_SaveConfig(void)    ;
-void Debug_Timer_RestoreConfig(void) ;
-void Debug_Timer_Sleep(void)         ;
-void Debug_Timer_Wakeup(void)        ;
-
-
-/***************************************
-*   Enumerated Types and Parameters
-***************************************/
-
-/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
-#define Debug_Timer__B_TIMER__CM_NONE 0
-#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
-#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
-#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
-#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
-
-
-
-/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
-#define Debug_Timer__B_TIMER__TM_NONE 0x00u
-#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
-#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
-#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
-#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
-
-
-/***************************************
-*    Initialial Parameter Constants
-***************************************/
-
-#define Debug_Timer_INIT_PERIOD             31999u
-#define Debug_Timer_INIT_CAPTURE_MODE       ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
-#define Debug_Timer_INIT_TRIGGER_MODE       ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
-#if (Debug_Timer_UsingFixedFunction)
-    #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
-                                                  ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
-#else
-    #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
-                                                 ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
-                                                 ((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
-#endif /* (Debug_Timer_UsingFixedFunction) */
-#define Debug_Timer_INIT_CAPTURE_COUNT      (2u)
-#define Debug_Timer_INIT_INT_CAPTURE_COUNT  ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
-
-
-/***************************************
-*           Registers
-***************************************/
-
-#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
-
-
-    /***************************************
-    *    Fixed Function Registers
-    ***************************************/
-
-    #define Debug_Timer_STATUS         (*(reg8 *) Debug_Timer_TimerHW__SR0 )
-    /* In Fixed Function Block Status and Mask are the same register */
-    #define Debug_Timer_STATUS_MASK    (*(reg8 *) Debug_Timer_TimerHW__SR0 )
-    #define Debug_Timer_CONTROL        (*(reg8 *) Debug_Timer_TimerHW__CFG0)
-    #define Debug_Timer_CONTROL2       (*(reg8 *) Debug_Timer_TimerHW__CFG1)
-    #define Debug_Timer_CONTROL2_PTR   ( (reg8 *) Debug_Timer_TimerHW__CFG1)
-    #define Debug_Timer_RT1            (*(reg8 *) Debug_Timer_TimerHW__RT1)
-    #define Debug_Timer_RT1_PTR        ( (reg8 *) Debug_Timer_TimerHW__RT1)
-
-    #if (CY_PSOC3 || CY_PSOC5LP)
-        #define Debug_Timer_CONTROL3       (*(reg8 *) Debug_Timer_TimerHW__CFG2)
-        #define Debug_Timer_CONTROL3_PTR   ( (reg8 *) Debug_Timer_TimerHW__CFG2)
-    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
-    #define Debug_Timer_GLOBAL_ENABLE  (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
-    #define Debug_Timer_GLOBAL_STBY_ENABLE  (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
-
-    #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
-    #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerHW__CAP0 )
-    #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerHW__PER0 )
-    #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerHW__PER0 )
-    #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
-    #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
-
-
-    /***************************************
-    *    Register Constants
-    ***************************************/
-
-    /* Fixed Function Block Chosen */
-    #define Debug_Timer_BLOCK_EN_MASK                     Debug_Timer_TimerHW__PM_ACT_MSK
-    #define Debug_Timer_BLOCK_STBY_EN_MASK                Debug_Timer_TimerHW__PM_STBY_MSK
-
-    /* Control Register Bit Locations */
-    /* Interrupt Count - Not valid for Fixed Function Block */
-    #define Debug_Timer_CTRL_INTCNT_SHIFT                  0x00u
-    /* Trigger Polarity - Not valid for Fixed Function Block */
-    #define Debug_Timer_CTRL_TRIG_MODE_SHIFT               0x00u
-    /* Trigger Enable - Not valid for Fixed Function Block */
-    #define Debug_Timer_CTRL_TRIG_EN_SHIFT                 0x00u
-    /* Capture Polarity - Not valid for Fixed Function Block */
-    #define Debug_Timer_CTRL_CAP_MODE_SHIFT                0x00u
-    /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
-    #define Debug_Timer_CTRL_ENABLE_SHIFT                  0x00u
-
-    /* Control Register Bit Masks */
-    #define Debug_Timer_CTRL_ENABLE                        ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
-
-    /* Control2 Register Bit Masks */
-    /* As defined in Register Map, Part of the TMRX_CFG1 register */
-    #define Debug_Timer_CTRL2_IRQ_SEL_SHIFT                 0x00u
-    #define Debug_Timer_CTRL2_IRQ_SEL                      ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
-
-    #if (CY_PSOC5A)
-        /* Use CFG1 Mode bits to set run mode */
-        /* As defined by Verilog Implementation */
-        #define Debug_Timer_CTRL_MODE_SHIFT                 0x01u
-        #define Debug_Timer_CTRL_MODE_MASK                 ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
-    #endif /* (CY_PSOC5A) */
-    #if (CY_PSOC3 || CY_PSOC5LP)
-        /* Control3 Register Bit Locations */
-        #define Debug_Timer_CTRL_RCOD_SHIFT        0x02u
-        #define Debug_Timer_CTRL_ENBL_SHIFT        0x00u
-        #define Debug_Timer_CTRL_MODE_SHIFT        0x00u
-
-        /* Control3 Register Bit Masks */
-        #define Debug_Timer_CTRL_RCOD_MASK  ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
-        #define Debug_Timer_CTRL_ENBL_MASK  ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
-        #define Debug_Timer_CTRL_MODE_MASK  ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
-
-        #define Debug_Timer_CTRL_RCOD       ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
-        #define Debug_Timer_CTRL_ENBL       ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
-    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-    /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
-    #define Debug_Timer_RT1_SHIFT                       0x04u
-    /* Sync TC and CMP bit masks */
-    #define Debug_Timer_RT1_MASK                        ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
-    #define Debug_Timer_SYNC                            ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
-    #define Debug_Timer_SYNCDSI_SHIFT                   0x00u
-    /* Sync all DSI inputs with Mask  */
-    #define Debug_Timer_SYNCDSI_MASK                    ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
-    /* Sync all DSI inputs */
-    #define Debug_Timer_SYNCDSI_EN                      ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
-
-    #define Debug_Timer_CTRL_MODE_PULSEWIDTH            ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
-    #define Debug_Timer_CTRL_MODE_PERIOD                ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
-    #define Debug_Timer_CTRL_MODE_CONTINUOUS            ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
-
-    /* Status Register Bit Locations */
-    /* As defined in Register Map, part of TMRX_SR0 register */
-    #define Debug_Timer_STATUS_TC_SHIFT                 0x07u
-    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
-    #define Debug_Timer_STATUS_CAPTURE_SHIFT            0x06u
-    /* As defined in Register Map, part of TMRX_SR0 register */
-    #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT        (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
-    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
-    #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT   (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
-
-    /* Status Register Bit Masks */
-    #define Debug_Timer_STATUS_TC                       ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
-    #define Debug_Timer_STATUS_CAPTURE                  ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
-    /* Interrupt Enable Bit-Mask for interrupt on TC */
-    #define Debug_Timer_STATUS_TC_INT_MASK              ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
-    /* Interrupt Enable Bit-Mask for interrupt on Capture */
-    #define Debug_Timer_STATUS_CAPTURE_INT_MASK         ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
-
-#else   /* UDB Registers and Register Constants */
-
-
-    /***************************************
-    *           UDB Registers
-    ***************************************/
-
-    #define Debug_Timer_STATUS              (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
-    #define Debug_Timer_STATUS_MASK         (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
-    #define Debug_Timer_STATUS_AUX_CTRL     (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
-    #define Debug_Timer_CONTROL             (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
-    
-    #if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
-        #define Debug_Timer_CAPTURE_LSB         (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define Debug_Timer_CAPTURE_LSB_PTR       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define Debug_Timer_PERIOD_LSB          (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define Debug_Timer_PERIOD_LSB_PTR        ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define Debug_Timer_COUNTER_LSB         (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #define Debug_Timer_COUNTER_LSB_PTR       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-    #elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
-        #if(CY_PSOC3) /* 8-bit addres space */
-            #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-            #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #else /* 16-bit address space */
-            #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
-            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
-            #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
-            #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
-            #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
-            #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
-        #endif /* CY_PSOC3 */
-    #elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
-        #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-        #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-        #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-    #else /* 32-bit Timer */
-        #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
-            #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
-            #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
-            #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-            #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-        #else /* 32-bit address space */
-            #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
-            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
-            #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
-            #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
-            #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
-            #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
-        #endif /* CY_PSOC3 || CY_PSOC5 */ 
-    #endif
-
-    #define Debug_Timer_COUNTER_LSB_PTR_8BIT       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
-    
-    #if (Debug_Timer_UsingHWCaptureCounter)
-        #define Debug_Timer_CAP_COUNT              (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
-        #define Debug_Timer_CAP_COUNT_PTR          ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
-        #define Debug_Timer_CAPTURE_COUNT_CTRL     (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
-        #define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
-    #endif /* (Debug_Timer_UsingHWCaptureCounter) */
-
-
-    /***************************************
-    *       Register Constants
-    ***************************************/
-
-    /* Control Register Bit Locations */
-    #define Debug_Timer_CTRL_INTCNT_SHIFT              0x00u       /* As defined by Verilog Implementation */
-    #define Debug_Timer_CTRL_TRIG_MODE_SHIFT           0x02u       /* As defined by Verilog Implementation */
-    #define Debug_Timer_CTRL_TRIG_EN_SHIFT             0x04u       /* As defined by Verilog Implementation */
-    #define Debug_Timer_CTRL_CAP_MODE_SHIFT            0x05u       /* As defined by Verilog Implementation */
-    #define Debug_Timer_CTRL_ENABLE_SHIFT              0x07u       /* As defined by Verilog Implementation */
-
-    /* Control Register Bit Masks */
-    #define Debug_Timer_CTRL_INTCNT_MASK               ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
-    #define Debug_Timer_CTRL_TRIG_MODE_MASK            ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
-    #define Debug_Timer_CTRL_TRIG_EN                   ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
-    #define Debug_Timer_CTRL_CAP_MODE_MASK             ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
-    #define Debug_Timer_CTRL_ENABLE                    ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
-
-    /* Bit Counter (7-bit) Control Register Bit Definitions */
-    /* As defined by the Register map for the AUX Control Register */
-    #define Debug_Timer_CNTR_ENABLE                    0x20u
-
-    /* Status Register Bit Locations */
-    #define Debug_Timer_STATUS_TC_SHIFT                0x00u  /* As defined by Verilog Implementation */
-    #define Debug_Timer_STATUS_CAPTURE_SHIFT           0x01u  /* As defined by Verilog Implementation */
-    #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT       Debug_Timer_STATUS_TC_SHIFT
-    #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT  Debug_Timer_STATUS_CAPTURE_SHIFT
-    #define Debug_Timer_STATUS_FIFOFULL_SHIFT          0x02u  /* As defined by Verilog Implementation */
-    #define Debug_Timer_STATUS_FIFONEMP_SHIFT          0x03u  /* As defined by Verilog Implementation */
-    #define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
-
-    /* Status Register Bit Masks */
-    /* Sticky TC Event Bit-Mask */
-    #define Debug_Timer_STATUS_TC                      ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
-    /* Sticky Capture Event Bit-Mask */
-    #define Debug_Timer_STATUS_CAPTURE                 ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define Debug_Timer_STATUS_TC_INT_MASK             ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define Debug_Timer_STATUS_CAPTURE_INT_MASK        ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
-    /* NOT-Sticky FIFO Full Bit-Mask */
-    #define Debug_Timer_STATUS_FIFOFULL                ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
-    /* NOT-Sticky FIFO Not Empty Bit-Mask */
-    #define Debug_Timer_STATUS_FIFONEMP                ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
-    /* Interrupt Enable Bit-Mask */
-    #define Debug_Timer_STATUS_FIFOFULL_INT_MASK       ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
-
-    #define Debug_Timer_STATUS_ACTL_INT_EN             0x10u   /* As defined for the ACTL Register */
-
-    /* Datapath Auxillary Control Register definitions */
-    #define Debug_Timer_AUX_CTRL_FIFO0_CLR             0x01u   /* As defined by Register map */
-    #define Debug_Timer_AUX_CTRL_FIFO1_CLR             0x02u   /* As defined by Register map */
-    #define Debug_Timer_AUX_CTRL_FIFO0_LVL             0x04u   /* As defined by Register map */
-    #define Debug_Timer_AUX_CTRL_FIFO1_LVL             0x08u   /* As defined by Register map */
-    #define Debug_Timer_STATUS_ACTL_INT_EN_MASK        0x10u   /* As defined for the ACTL Register */
-
-#endif /* Implementation Specific Registers and Register Constants */
-
-#endif  /* CY_Timer_v2_30_Debug_Timer_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Debug_Timer.h
+* Version 2.70
+*
+*  Description:
+*     Contains the function prototypes and constants available to the timer
+*     user module.
+*
+*   Note:
+*     None
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#if !defined(CY_Timer_v2_60_Debug_Timer_H)
+#define CY_Timer_v2_60_Debug_Timer_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
+
+extern uint8 Debug_Timer_initVar;
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component Timer_v2_70 requires cy_boot v3.0 or later
+#endif /* (CY_ PSOC5LP) */
+
+
+/**************************************
+*           Parameter Defaults
+**************************************/
+
+#define Debug_Timer_Resolution                 16u
+#define Debug_Timer_UsingFixedFunction         1u
+#define Debug_Timer_UsingHWCaptureCounter      0u
+#define Debug_Timer_SoftwareCaptureMode        0u
+#define Debug_Timer_SoftwareTriggerMode        0u
+#define Debug_Timer_UsingHWEnable              0u
+#define Debug_Timer_EnableTriggerMode          0u
+#define Debug_Timer_InterruptOnCaptureCount    0u
+#define Debug_Timer_RunModeUsed                0u
+#define Debug_Timer_ControlRegRemoved          0u
+
+#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#elif  (Debug_Timer_UsingFixedFunction)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#else 
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (1u)
+#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
+
+
+/***************************************
+*       Type defines
+***************************************/
+
+
+/**************************************************************************
+ * Sleep Wakeup Backup structure for Timer Component
+ *************************************************************************/
+typedef struct
+{
+    uint8 TimerEnableState;
+    #if(!Debug_Timer_UsingFixedFunction)
+
+        uint16 TimerUdb;
+        uint8 InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            uint8 TimerCaptureCounter;
+        #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+
+        #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            uint8 TimerControlRegister;
+        #endif /* variable declaration for backing up enable state of the Timer */
+    #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+
+}Debug_Timer_backupStruct;
+
+
+/***************************************
+*       Function Prototypes
+***************************************/
+
+void    Debug_Timer_Start(void) ;
+void    Debug_Timer_Stop(void) ;
+
+void    Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
+uint8   Debug_Timer_ReadStatusRegister(void) ;
+/* Deprecated function. Do not use this in future. Retained for backward compatibility */
+#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
+
+#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+    uint8   Debug_Timer_ReadControlRegister(void) ;
+    void    Debug_Timer_WriteControlRegister(uint8 control) ;
+#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
+
+uint16  Debug_Timer_ReadPeriod(void) ;
+void    Debug_Timer_WritePeriod(uint16 period) ;
+uint16  Debug_Timer_ReadCounter(void) ;
+void    Debug_Timer_WriteCounter(uint16 counter) ;
+uint16  Debug_Timer_ReadCapture(void) ;
+void    Debug_Timer_SoftwareCapture(void) ;
+
+#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
+    #if (Debug_Timer_SoftwareCaptureMode)
+        void    Debug_Timer_SetCaptureMode(uint8 captureMode) ;
+    #endif /* (!Debug_Timer_UsingFixedFunction) */
+
+    #if (Debug_Timer_SoftwareTriggerMode)
+        void    Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
+    #endif /* (Debug_Timer_SoftwareTriggerMode) */
+
+    #if (Debug_Timer_EnableTriggerMode)
+        void    Debug_Timer_EnableTrigger(void) ;
+        void    Debug_Timer_DisableTrigger(void) ;
+    #endif /* (Debug_Timer_EnableTriggerMode) */
+
+
+    #if(Debug_Timer_InterruptOnCaptureCount)
+        void    Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
+    #endif /* (Debug_Timer_InterruptOnCaptureCount) */
+
+    #if (Debug_Timer_UsingHWCaptureCounter)
+        void    Debug_Timer_SetCaptureCount(uint8 captureCount) ;
+        uint8   Debug_Timer_ReadCaptureCount(void) ;
+    #endif /* (Debug_Timer_UsingHWCaptureCounter) */
+
+    void Debug_Timer_ClearFIFO(void) ;
+#endif /* UDB Prototypes */
+
+/* Sleep Retention APIs */
+void Debug_Timer_Init(void)          ;
+void Debug_Timer_Enable(void)        ;
+void Debug_Timer_SaveConfig(void)    ;
+void Debug_Timer_RestoreConfig(void) ;
+void Debug_Timer_Sleep(void)         ;
+void Debug_Timer_Wakeup(void)        ;
+
+
+/***************************************
+*   Enumerated Types and Parameters
+***************************************/
+
+/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
+#define Debug_Timer__B_TIMER__CM_NONE 0
+#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
+#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
+#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
+#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
+
+
+
+/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
+#define Debug_Timer__B_TIMER__TM_NONE 0x00u
+#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
+#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
+#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
+#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
+
+
+/***************************************
+*    Initialial Parameter Constants
+***************************************/
+
+#define Debug_Timer_INIT_PERIOD             31999u
+#define Debug_Timer_INIT_CAPTURE_MODE       ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
+#define Debug_Timer_INIT_TRIGGER_MODE       ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
+#if (Debug_Timer_UsingFixedFunction)
+    #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
+                                                  ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
+#else
+    #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
+                                                 ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
+                                                 ((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
+#endif /* (Debug_Timer_UsingFixedFunction) */
+#define Debug_Timer_INIT_CAPTURE_COUNT      (2u)
+#define Debug_Timer_INIT_INT_CAPTURE_COUNT  ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
+
+
+/***************************************
+*           Registers
+***************************************/
+
+#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
+
+
+    /***************************************
+    *    Fixed Function Registers
+    ***************************************/
+
+    #define Debug_Timer_STATUS         (*(reg8 *) Debug_Timer_TimerHW__SR0 )
+    /* In Fixed Function Block Status and Mask are the same register */
+    #define Debug_Timer_STATUS_MASK    (*(reg8 *) Debug_Timer_TimerHW__SR0 )
+    #define Debug_Timer_CONTROL        (*(reg8 *) Debug_Timer_TimerHW__CFG0)
+    #define Debug_Timer_CONTROL2       (*(reg8 *) Debug_Timer_TimerHW__CFG1)
+    #define Debug_Timer_CONTROL2_PTR   ( (reg8 *) Debug_Timer_TimerHW__CFG1)
+    #define Debug_Timer_RT1            (*(reg8 *) Debug_Timer_TimerHW__RT1)
+    #define Debug_Timer_RT1_PTR        ( (reg8 *) Debug_Timer_TimerHW__RT1)
+
+    #if (CY_PSOC3 || CY_PSOC5LP)
+        #define Debug_Timer_CONTROL3       (*(reg8 *) Debug_Timer_TimerHW__CFG2)
+        #define Debug_Timer_CONTROL3_PTR   ( (reg8 *) Debug_Timer_TimerHW__CFG2)
+    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+    #define Debug_Timer_GLOBAL_ENABLE  (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
+    #define Debug_Timer_GLOBAL_STBY_ENABLE  (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
+
+    #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
+    #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerHW__CAP0 )
+    #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerHW__PER0 )
+    #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerHW__PER0 )
+    #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
+    #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
+
+
+    /***************************************
+    *    Register Constants
+    ***************************************/
+
+    /* Fixed Function Block Chosen */
+    #define Debug_Timer_BLOCK_EN_MASK                     Debug_Timer_TimerHW__PM_ACT_MSK
+    #define Debug_Timer_BLOCK_STBY_EN_MASK                Debug_Timer_TimerHW__PM_STBY_MSK
+
+    /* Control Register Bit Locations */
+    /* Interrupt Count - Not valid for Fixed Function Block */
+    #define Debug_Timer_CTRL_INTCNT_SHIFT                  0x00u
+    /* Trigger Polarity - Not valid for Fixed Function Block */
+    #define Debug_Timer_CTRL_TRIG_MODE_SHIFT               0x00u
+    /* Trigger Enable - Not valid for Fixed Function Block */
+    #define Debug_Timer_CTRL_TRIG_EN_SHIFT                 0x00u
+    /* Capture Polarity - Not valid for Fixed Function Block */
+    #define Debug_Timer_CTRL_CAP_MODE_SHIFT                0x00u
+    /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
+    #define Debug_Timer_CTRL_ENABLE_SHIFT                  0x00u
+
+    /* Control Register Bit Masks */
+    #define Debug_Timer_CTRL_ENABLE                        ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
+
+    /* Control2 Register Bit Masks */
+    /* As defined in Register Map, Part of the TMRX_CFG1 register */
+    #define Debug_Timer_CTRL2_IRQ_SEL_SHIFT                 0x00u
+    #define Debug_Timer_CTRL2_IRQ_SEL                      ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
+
+    #if (CY_PSOC5A)
+        /* Use CFG1 Mode bits to set run mode */
+        /* As defined by Verilog Implementation */
+        #define Debug_Timer_CTRL_MODE_SHIFT                 0x01u
+        #define Debug_Timer_CTRL_MODE_MASK                 ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+    #endif /* (CY_PSOC5A) */
+    #if (CY_PSOC3 || CY_PSOC5LP)
+        /* Control3 Register Bit Locations */
+        #define Debug_Timer_CTRL_RCOD_SHIFT        0x02u
+        #define Debug_Timer_CTRL_ENBL_SHIFT        0x00u
+        #define Debug_Timer_CTRL_MODE_SHIFT        0x00u
+
+        /* Control3 Register Bit Masks */
+        #define Debug_Timer_CTRL_RCOD_MASK  ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
+        #define Debug_Timer_CTRL_ENBL_MASK  ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
+        #define Debug_Timer_CTRL_MODE_MASK  ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
+
+        #define Debug_Timer_CTRL_RCOD       ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
+        #define Debug_Timer_CTRL_ENBL       ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
+    #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+    /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
+    #define Debug_Timer_RT1_SHIFT                       0x04u
+    /* Sync TC and CMP bit masks */
+    #define Debug_Timer_RT1_MASK                        ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
+    #define Debug_Timer_SYNC                            ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
+    #define Debug_Timer_SYNCDSI_SHIFT                   0x00u
+    /* Sync all DSI inputs with Mask  */
+    #define Debug_Timer_SYNCDSI_MASK                    ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
+    /* Sync all DSI inputs */
+    #define Debug_Timer_SYNCDSI_EN                      ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
+
+    #define Debug_Timer_CTRL_MODE_PULSEWIDTH            ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
+    #define Debug_Timer_CTRL_MODE_PERIOD                ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
+    #define Debug_Timer_CTRL_MODE_CONTINUOUS            ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
+
+    /* Status Register Bit Locations */
+    /* As defined in Register Map, part of TMRX_SR0 register */
+    #define Debug_Timer_STATUS_TC_SHIFT                 0x07u
+    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+    #define Debug_Timer_STATUS_CAPTURE_SHIFT            0x06u
+    /* As defined in Register Map, part of TMRX_SR0 register */
+    #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT        (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
+    /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+    #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT   (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
+
+    /* Status Register Bit Masks */
+    #define Debug_Timer_STATUS_TC                       ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+    #define Debug_Timer_STATUS_CAPTURE                  ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+    /* Interrupt Enable Bit-Mask for interrupt on TC */
+    #define Debug_Timer_STATUS_TC_INT_MASK              ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
+    /* Interrupt Enable Bit-Mask for interrupt on Capture */
+    #define Debug_Timer_STATUS_CAPTURE_INT_MASK         ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
+
+#else   /* UDB Registers and Register Constants */
+
+
+    /***************************************
+    *           UDB Registers
+    ***************************************/
+
+    #define Debug_Timer_STATUS              (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
+    #define Debug_Timer_STATUS_MASK         (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
+    #define Debug_Timer_STATUS_AUX_CTRL     (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
+    #define Debug_Timer_CONTROL             (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
+    
+    #if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
+        #define Debug_Timer_CAPTURE_LSB         (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+        #define Debug_Timer_CAPTURE_LSB_PTR       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+        #define Debug_Timer_PERIOD_LSB          (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+        #define Debug_Timer_PERIOD_LSB_PTR        ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+        #define Debug_Timer_COUNTER_LSB         (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+        #define Debug_Timer_COUNTER_LSB_PTR       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+    #elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
+        #if(CY_PSOC3) /* 8-bit addres space */
+            #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+            #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+            #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+            #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+            #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+        #else /* 16-bit address space */
+            #define Debug_Timer_CAPTURE_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+            #define Debug_Timer_PERIOD_LSB          (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+            #define Debug_Timer_PERIOD_LSB_PTR        ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+            #define Debug_Timer_COUNTER_LSB         (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+            #define Debug_Timer_COUNTER_LSB_PTR       ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+        #endif /* CY_PSOC3 */
+    #elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
+        #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+        #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+        #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+        #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+        #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+        #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+    #else /* 32-bit Timer */
+        #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
+            #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+            #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+            #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+            #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+            #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+        #else /* 32-bit address space */
+            #define Debug_Timer_CAPTURE_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+            #define Debug_Timer_CAPTURE_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+            #define Debug_Timer_PERIOD_LSB          (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+            #define Debug_Timer_PERIOD_LSB_PTR        ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+            #define Debug_Timer_COUNTER_LSB         (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+            #define Debug_Timer_COUNTER_LSB_PTR       ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+        #endif /* CY_PSOC3 || CY_PSOC5 */ 
+    #endif
+
+    #define Debug_Timer_COUNTER_LSB_PTR_8BIT       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+    
+    #if (Debug_Timer_UsingHWCaptureCounter)
+        #define Debug_Timer_CAP_COUNT              (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
+        #define Debug_Timer_CAP_COUNT_PTR          ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
+        #define Debug_Timer_CAPTURE_COUNT_CTRL     (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+        #define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+    #endif /* (Debug_Timer_UsingHWCaptureCounter) */
+
+
+    /***************************************
+    *       Register Constants
+    ***************************************/
+
+    /* Control Register Bit Locations */
+    #define Debug_Timer_CTRL_INTCNT_SHIFT              0x00u       /* As defined by Verilog Implementation */
+    #define Debug_Timer_CTRL_TRIG_MODE_SHIFT           0x02u       /* As defined by Verilog Implementation */
+    #define Debug_Timer_CTRL_TRIG_EN_SHIFT             0x04u       /* As defined by Verilog Implementation */
+    #define Debug_Timer_CTRL_CAP_MODE_SHIFT            0x05u       /* As defined by Verilog Implementation */
+    #define Debug_Timer_CTRL_ENABLE_SHIFT              0x07u       /* As defined by Verilog Implementation */
+
+    /* Control Register Bit Masks */
+    #define Debug_Timer_CTRL_INTCNT_MASK               ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
+    #define Debug_Timer_CTRL_TRIG_MODE_MASK            ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
+    #define Debug_Timer_CTRL_TRIG_EN                   ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
+    #define Debug_Timer_CTRL_CAP_MODE_MASK             ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
+    #define Debug_Timer_CTRL_ENABLE                    ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
+
+    /* Bit Counter (7-bit) Control Register Bit Definitions */
+    /* As defined by the Register map for the AUX Control Register */
+    #define Debug_Timer_CNTR_ENABLE                    0x20u
+
+    /* Status Register Bit Locations */
+    #define Debug_Timer_STATUS_TC_SHIFT                0x00u  /* As defined by Verilog Implementation */
+    #define Debug_Timer_STATUS_CAPTURE_SHIFT           0x01u  /* As defined by Verilog Implementation */
+    #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT       Debug_Timer_STATUS_TC_SHIFT
+    #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT  Debug_Timer_STATUS_CAPTURE_SHIFT
+    #define Debug_Timer_STATUS_FIFOFULL_SHIFT          0x02u  /* As defined by Verilog Implementation */
+    #define Debug_Timer_STATUS_FIFONEMP_SHIFT          0x03u  /* As defined by Verilog Implementation */
+    #define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
+
+    /* Status Register Bit Masks */
+    /* Sticky TC Event Bit-Mask */
+    #define Debug_Timer_STATUS_TC                      ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+    /* Sticky Capture Event Bit-Mask */
+    #define Debug_Timer_STATUS_CAPTURE                 ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+    /* Interrupt Enable Bit-Mask */
+    #define Debug_Timer_STATUS_TC_INT_MASK             ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+    /* Interrupt Enable Bit-Mask */
+    #define Debug_Timer_STATUS_CAPTURE_INT_MASK        ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+    /* NOT-Sticky FIFO Full Bit-Mask */
+    #define Debug_Timer_STATUS_FIFOFULL                ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
+    /* NOT-Sticky FIFO Not Empty Bit-Mask */
+    #define Debug_Timer_STATUS_FIFONEMP                ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
+    /* Interrupt Enable Bit-Mask */
+    #define Debug_Timer_STATUS_FIFOFULL_INT_MASK       ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
+
+    #define Debug_Timer_STATUS_ACTL_INT_EN             0x10u   /* As defined for the ACTL Register */
+
+    /* Datapath Auxillary Control Register definitions */
+    #define Debug_Timer_AUX_CTRL_FIFO0_CLR             0x01u   /* As defined by Register map */
+    #define Debug_Timer_AUX_CTRL_FIFO1_CLR             0x02u   /* As defined by Register map */
+    #define Debug_Timer_AUX_CTRL_FIFO0_LVL             0x04u   /* As defined by Register map */
+    #define Debug_Timer_AUX_CTRL_FIFO1_LVL             0x08u   /* As defined by Register map */
+    #define Debug_Timer_STATUS_ACTL_INT_EN_MASK        0x10u   /* As defined for the ACTL Register */
+
+#endif /* Implementation Specific Registers and Register Constants */
+
+#endif  /* CY_Timer_v2_30_Debug_Timer_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: Debug_Timer_Interrupt.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <Debug_Timer_Interrupt.h>
-
-#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START Debug_Timer_Interrupt_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    Debug_Timer_Interrupt_Disable();
-
-    /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
-    Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt);
-
-    /* Set the priority. */
-    Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    Debug_Timer_Interrupt_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    Debug_Timer_Interrupt_Disable();
-
-    /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
-    Debug_Timer_Interrupt_SetVector(address);
-
-    /* Set the priority. */
-    Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    Debug_Timer_Interrupt_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_Stop(void)
-{
-    /* Disable this interrupt. */
-    Debug_Timer_Interrupt_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    Debug_Timer_Interrupt_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for Debug_Timer_Interrupt.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(Debug_Timer_Interrupt_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START Debug_Timer_Interrupt_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use Debug_Timer_Interrupt_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress Debug_Timer_Interrupt_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_SetPriority(uint8 priority)
-{
-    *Debug_Timer_Interrupt_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 Debug_Timer_Interrupt_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 Debug_Timer_Interrupt_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_SetPending(void)
-{
-    *Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Interrupt_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void Debug_Timer_Interrupt_ClearPending(void)
-{
-    *Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Debug_Timer_Interrupt.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <Debug_Timer_Interrupt.h>
+
+#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START Debug_Timer_Interrupt_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    Debug_Timer_Interrupt_Disable();
+
+    /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
+    Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt);
+
+    /* Set the priority. */
+    Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    Debug_Timer_Interrupt_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    Debug_Timer_Interrupt_Disable();
+
+    /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
+    Debug_Timer_Interrupt_SetVector(address);
+
+    /* Set the priority. */
+    Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    Debug_Timer_Interrupt_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Stop(void)
+{
+    /* Disable this interrupt. */
+    Debug_Timer_Interrupt_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    Debug_Timer_Interrupt_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for Debug_Timer_Interrupt.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(Debug_Timer_Interrupt_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START Debug_Timer_Interrupt_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress Debug_Timer_Interrupt_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetPriority(uint8 priority)
+{
+    *Debug_Timer_Interrupt_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 Debug_Timer_Interrupt_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 Debug_Timer_Interrupt_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetPending(void)
+{
+    *Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_ClearPending(void)
+{
+    *Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: Debug_Timer_Interrupt.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_Debug_Timer_Interrupt_H)
-#define CY_ISR_Debug_Timer_Interrupt_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void Debug_Timer_Interrupt_Start(void);
-void Debug_Timer_Interrupt_StartEx(cyisraddress address);
-void Debug_Timer_Interrupt_Stop(void);
-
-CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt);
-
-void Debug_Timer_Interrupt_SetVector(cyisraddress address);
-cyisraddress Debug_Timer_Interrupt_GetVector(void);
-
-void Debug_Timer_Interrupt_SetPriority(uint8 priority);
-uint8 Debug_Timer_Interrupt_GetPriority(void);
-
-void Debug_Timer_Interrupt_Enable(void);
-uint8 Debug_Timer_Interrupt_GetState(void);
-void Debug_Timer_Interrupt_Disable(void);
-
-void Debug_Timer_Interrupt_SetPending(void);
-void Debug_Timer_Interrupt_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */
-#define Debug_Timer_Interrupt_INTC_VECTOR            ((reg32 *) Debug_Timer_Interrupt__INTC_VECT)
-
-/* Address of the Debug_Timer_Interrupt ISR priority. */
-#define Debug_Timer_Interrupt_INTC_PRIOR             ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG)
-
-/* Priority of the Debug_Timer_Interrupt interrupt. */
-#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER      Debug_Timer_Interrupt__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */
-#define Debug_Timer_Interrupt_INTC_SET_EN            ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */
-#define Debug_Timer_Interrupt_INTC_CLR_EN            ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */
-#define Debug_Timer_Interrupt_INTC_SET_PD            ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */
-#define Debug_Timer_Interrupt_INTC_CLR_PD            ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_Debug_Timer_Interrupt_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Debug_Timer_Interrupt.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_Debug_Timer_Interrupt_H)
+#define CY_ISR_Debug_Timer_Interrupt_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void Debug_Timer_Interrupt_Start(void);
+void Debug_Timer_Interrupt_StartEx(cyisraddress address);
+void Debug_Timer_Interrupt_Stop(void);
+
+CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt);
+
+void Debug_Timer_Interrupt_SetVector(cyisraddress address);
+cyisraddress Debug_Timer_Interrupt_GetVector(void);
+
+void Debug_Timer_Interrupt_SetPriority(uint8 priority);
+uint8 Debug_Timer_Interrupt_GetPriority(void);
+
+void Debug_Timer_Interrupt_Enable(void);
+uint8 Debug_Timer_Interrupt_GetState(void);
+void Debug_Timer_Interrupt_Disable(void);
+
+void Debug_Timer_Interrupt_SetPending(void);
+void Debug_Timer_Interrupt_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */
+#define Debug_Timer_Interrupt_INTC_VECTOR            ((reg32 *) Debug_Timer_Interrupt__INTC_VECT)
+
+/* Address of the Debug_Timer_Interrupt ISR priority. */
+#define Debug_Timer_Interrupt_INTC_PRIOR             ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG)
+
+/* Priority of the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER      Debug_Timer_Interrupt__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_SET_EN            ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_CLR_EN            ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */
+#define Debug_Timer_Interrupt_INTC_SET_PD            ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_CLR_PD            ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_Debug_Timer_Interrupt_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c

@@ -1,162 +1,162 @@
-/*******************************************************************************
-* File Name: Debug_Timer_PM.c
-* Version 2.70
-*
-*  Description:
-*     This file provides the power management source code to API for the
-*     Timer.
-*
-*   Note:
-*     None
-*
-*******************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-********************************************************************************/
-
-#include "Debug_Timer.h"
-
-static Debug_Timer_backupStruct Debug_Timer_backup;
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_SaveConfig
-********************************************************************************
-*
-* Summary:
-*     Save the current user configuration
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Global variables:
-*  Debug_Timer_backup:  Variables of this global structure are modified to
-*  store the values of non retention configuration registers when Sleep() API is
-*  called.
-*
-*******************************************************************************/
-void Debug_Timer_SaveConfig(void) 
-{
-    #if (!Debug_Timer_UsingFixedFunction)
-        Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
-        Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
-        #if (Debug_Timer_UsingHWCaptureCounter)
-            Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
-        #endif /* Back Up capture counter register  */
-
-        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-            Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
-        #endif /* Backup the enable state of the Timer component */
-    #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores the current user configuration.
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Global variables:
-*  Debug_Timer_backup:  Variables of this global structure are used to
-*  restore the values of non retention registers on wakeup from sleep mode.
-*
-*******************************************************************************/
-void Debug_Timer_RestoreConfig(void) 
-{   
-    #if (!Debug_Timer_UsingFixedFunction)
-
-        Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
-        Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
-        #if (Debug_Timer_UsingHWCaptureCounter)
-            Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
-        #endif /* Restore Capture counter register*/
-
-        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-            Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
-        #endif /* Restore the enable state of the Timer component */
-    #endif /* Restore non retention registers in the UDB implementation only */
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Sleep
-********************************************************************************
-*
-* Summary:
-*     Stop and Save the user configuration
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Global variables:
-*  Debug_Timer_backup.TimerEnableState:  Is modified depending on the
-*  enable state of the block before entering sleep mode.
-*
-*******************************************************************************/
-void Debug_Timer_Sleep(void) 
-{
-    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-        /* Save Counter's enable state */
-        if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
-        {
-            /* Timer is enabled */
-            Debug_Timer_backup.TimerEnableState = 1u;
-        }
-        else
-        {
-            /* Timer is disabled */
-            Debug_Timer_backup.TimerEnableState = 0u;
-        }
-    #endif /* Back up enable state from the Timer control register */
-    Debug_Timer_Stop();
-    Debug_Timer_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: Debug_Timer_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Restores and enables the user configuration
-*
-* Parameters:
-*  void
-*
-* Return:
-*  void
-*
-* Global variables:
-*  Debug_Timer_backup.enableState:  Is used to restore the enable state of
-*  block on wakeup from sleep mode.
-*
-*******************************************************************************/
-void Debug_Timer_Wakeup(void) 
-{
-    Debug_Timer_RestoreConfig();
-    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
-        if(Debug_Timer_backup.TimerEnableState == 1u)
-        {     /* Enable Timer's operation */
-                Debug_Timer_Enable();
-        } /* Do nothing if Timer was disabled before */
-    #endif /* Remove this code section if Control register is removed */
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: Debug_Timer_PM.c
+* Version 2.70
+*
+*  Description:
+*     This file provides the power management source code to API for the
+*     Timer.
+*
+*   Note:
+*     None
+*
+*******************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "Debug_Timer.h"
+
+static Debug_Timer_backupStruct Debug_Timer_backup;
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_SaveConfig
+********************************************************************************
+*
+* Summary:
+*     Save the current user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  Debug_Timer_backup:  Variables of this global structure are modified to
+*  store the values of non retention configuration registers when Sleep() API is
+*  called.
+*
+*******************************************************************************/
+void Debug_Timer_SaveConfig(void) 
+{
+    #if (!Debug_Timer_UsingFixedFunction)
+        Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+        Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
+        #endif /* Back Up capture counter register  */
+
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
+        #endif /* Backup the enable state of the Timer component */
+    #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the current user configuration.
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  Debug_Timer_backup:  Variables of this global structure are used to
+*  restore the values of non retention registers on wakeup from sleep mode.
+*
+*******************************************************************************/
+void Debug_Timer_RestoreConfig(void) 
+{   
+    #if (!Debug_Timer_UsingFixedFunction)
+
+        Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+        Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
+        #endif /* Restore Capture counter register*/
+
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
+        #endif /* Restore the enable state of the Timer component */
+    #endif /* Restore non retention registers in the UDB implementation only */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Sleep
+********************************************************************************
+*
+* Summary:
+*     Stop and Save the user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  Debug_Timer_backup.TimerEnableState:  Is modified depending on the
+*  enable state of the block before entering sleep mode.
+*
+*******************************************************************************/
+void Debug_Timer_Sleep(void) 
+{
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Save Counter's enable state */
+        if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
+        {
+            /* Timer is enabled */
+            Debug_Timer_backup.TimerEnableState = 1u;
+        }
+        else
+        {
+            /* Timer is disabled */
+            Debug_Timer_backup.TimerEnableState = 0u;
+        }
+    #endif /* Back up enable state from the Timer control register */
+    Debug_Timer_Stop();
+    Debug_Timer_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores and enables the user configuration
+*
+* Parameters:
+*  void
+*
+* Return:
+*  void
+*
+* Global variables:
+*  Debug_Timer_backup.enableState:  Is used to restore the enable state of
+*  block on wakeup from sleep mode.
+*
+*******************************************************************************/
+void Debug_Timer_Wakeup(void) 
+{
+    Debug_Timer_RestoreConfig();
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        if(Debug_Timer_backup.TimerEnableState == 1u)
+        {     /* Enable Timer's operation */
+                Debug_Timer_Enable();
+        } /* Do nothing if Timer was disabled before */
+    #endif /* Remove this code section if Control register is removed */
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: EXTLED.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "EXTLED.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: EXTLED_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void EXTLED_Write(uint8 value) 
-{
-    uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK));
-    EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: EXTLED_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  EXTLED_DM_STRONG     Strong Drive 
-*  EXTLED_DM_OD_HI      Open Drain, Drives High 
-*  EXTLED_DM_OD_LO      Open Drain, Drives Low 
-*  EXTLED_DM_RES_UP     Resistive Pull Up 
-*  EXTLED_DM_RES_DWN    Resistive Pull Down 
-*  EXTLED_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  EXTLED_DM_DIG_HIZ    High Impedance Digital 
-*  EXTLED_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void EXTLED_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(EXTLED_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: EXTLED_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro EXTLED_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 EXTLED_Read(void) 
-{
-    return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: EXTLED_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 EXTLED_ReadDataReg(void) 
-{
-    return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(EXTLED_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: EXTLED_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 EXTLED_ClearInterrupt(void) 
-    {
-        return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: EXTLED.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "EXTLED.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: EXTLED_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void EXTLED_Write(uint8 value) 
+{
+    uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK));
+    EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  EXTLED_DM_STRONG     Strong Drive 
+*  EXTLED_DM_OD_HI      Open Drain, Drives High 
+*  EXTLED_DM_OD_LO      Open Drain, Drives Low 
+*  EXTLED_DM_RES_UP     Resistive Pull Up 
+*  EXTLED_DM_RES_DWN    Resistive Pull Down 
+*  EXTLED_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  EXTLED_DM_DIG_HIZ    High Impedance Digital 
+*  EXTLED_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void EXTLED_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(EXTLED_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro EXTLED_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 EXTLED_Read(void) 
+{
+    return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: EXTLED_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 EXTLED_ReadDataReg(void) 
+{
+    return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(EXTLED_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: EXTLED_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 EXTLED_ClearInterrupt(void) 
+    {
+        return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: EXTLED.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_EXTLED_H) /* Pins EXTLED_H */
-#define CY_PINS_EXTLED_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "EXTLED_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    EXTLED_Write(uint8 value) ;
-void    EXTLED_SetDriveMode(uint8 mode) ;
-uint8   EXTLED_ReadDataReg(void) ;
-uint8   EXTLED_Read(void) ;
-uint8   EXTLED_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define EXTLED_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define EXTLED_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define EXTLED_DM_RES_UP          PIN_DM_RES_UP
-#define EXTLED_DM_RES_DWN         PIN_DM_RES_DWN
-#define EXTLED_DM_OD_LO           PIN_DM_OD_LO
-#define EXTLED_DM_OD_HI           PIN_DM_OD_HI
-#define EXTLED_DM_STRONG          PIN_DM_STRONG
-#define EXTLED_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define EXTLED_MASK               EXTLED__MASK
-#define EXTLED_SHIFT              EXTLED__SHIFT
-#define EXTLED_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define EXTLED_PS                     (* (reg8 *) EXTLED__PS)
-/* Data Register */
-#define EXTLED_DR                     (* (reg8 *) EXTLED__DR)
-/* Port Number */
-#define EXTLED_PRT_NUM                (* (reg8 *) EXTLED__PRT) 
-/* Connect to Analog Globals */                                                  
-#define EXTLED_AG                     (* (reg8 *) EXTLED__AG)                       
-/* Analog MUX bux enable */
-#define EXTLED_AMUX                   (* (reg8 *) EXTLED__AMUX) 
-/* Bidirectional Enable */                                                        
-#define EXTLED_BIE                    (* (reg8 *) EXTLED__BIE)
-/* Bit-mask for Aliased Register Access */
-#define EXTLED_BIT_MASK               (* (reg8 *) EXTLED__BIT_MASK)
-/* Bypass Enable */
-#define EXTLED_BYP                    (* (reg8 *) EXTLED__BYP)
-/* Port wide control signals */                                                   
-#define EXTLED_CTL                    (* (reg8 *) EXTLED__CTL)
-/* Drive Modes */
-#define EXTLED_DM0                    (* (reg8 *) EXTLED__DM0) 
-#define EXTLED_DM1                    (* (reg8 *) EXTLED__DM1)
-#define EXTLED_DM2                    (* (reg8 *) EXTLED__DM2) 
-/* Input Buffer Disable Override */
-#define EXTLED_INP_DIS                (* (reg8 *) EXTLED__INP_DIS)
-/* LCD Common or Segment Drive */
-#define EXTLED_LCD_COM_SEG            (* (reg8 *) EXTLED__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define EXTLED_LCD_EN                 (* (reg8 *) EXTLED__LCD_EN)
-/* Slew Rate Control */
-#define EXTLED_SLW                    (* (reg8 *) EXTLED__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define EXTLED_PRTDSI__CAPS_SEL       (* (reg8 *) EXTLED__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define EXTLED_PRTDSI__DBL_SYNC_IN    (* (reg8 *) EXTLED__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define EXTLED_PRTDSI__OE_SEL0        (* (reg8 *) EXTLED__PRTDSI__OE_SEL0) 
-#define EXTLED_PRTDSI__OE_SEL1        (* (reg8 *) EXTLED__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define EXTLED_PRTDSI__OUT_SEL0       (* (reg8 *) EXTLED__PRTDSI__OUT_SEL0) 
-#define EXTLED_PRTDSI__OUT_SEL1       (* (reg8 *) EXTLED__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define EXTLED_PRTDSI__SYNC_OUT       (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT) 
-
-
-#if defined(EXTLED__INTSTAT)  /* Interrupt Registers */
-
-    #define EXTLED_INTSTAT                (* (reg8 *) EXTLED__INTSTAT)
-    #define EXTLED_SNAP                   (* (reg8 *) EXTLED__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_EXTLED_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: EXTLED.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_EXTLED_H) /* Pins EXTLED_H */
+#define CY_PINS_EXTLED_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "EXTLED_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    EXTLED_Write(uint8 value) ;
+void    EXTLED_SetDriveMode(uint8 mode) ;
+uint8   EXTLED_ReadDataReg(void) ;
+uint8   EXTLED_Read(void) ;
+uint8   EXTLED_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define EXTLED_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define EXTLED_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define EXTLED_DM_RES_UP          PIN_DM_RES_UP
+#define EXTLED_DM_RES_DWN         PIN_DM_RES_DWN
+#define EXTLED_DM_OD_LO           PIN_DM_OD_LO
+#define EXTLED_DM_OD_HI           PIN_DM_OD_HI
+#define EXTLED_DM_STRONG          PIN_DM_STRONG
+#define EXTLED_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define EXTLED_MASK               EXTLED__MASK
+#define EXTLED_SHIFT              EXTLED__SHIFT
+#define EXTLED_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define EXTLED_PS                     (* (reg8 *) EXTLED__PS)
+/* Data Register */
+#define EXTLED_DR                     (* (reg8 *) EXTLED__DR)
+/* Port Number */
+#define EXTLED_PRT_NUM                (* (reg8 *) EXTLED__PRT) 
+/* Connect to Analog Globals */                                                  
+#define EXTLED_AG                     (* (reg8 *) EXTLED__AG)                       
+/* Analog MUX bux enable */
+#define EXTLED_AMUX                   (* (reg8 *) EXTLED__AMUX) 
+/* Bidirectional Enable */                                                        
+#define EXTLED_BIE                    (* (reg8 *) EXTLED__BIE)
+/* Bit-mask for Aliased Register Access */
+#define EXTLED_BIT_MASK               (* (reg8 *) EXTLED__BIT_MASK)
+/* Bypass Enable */
+#define EXTLED_BYP                    (* (reg8 *) EXTLED__BYP)
+/* Port wide control signals */                                                   
+#define EXTLED_CTL                    (* (reg8 *) EXTLED__CTL)
+/* Drive Modes */
+#define EXTLED_DM0                    (* (reg8 *) EXTLED__DM0) 
+#define EXTLED_DM1                    (* (reg8 *) EXTLED__DM1)
+#define EXTLED_DM2                    (* (reg8 *) EXTLED__DM2) 
+/* Input Buffer Disable Override */
+#define EXTLED_INP_DIS                (* (reg8 *) EXTLED__INP_DIS)
+/* LCD Common or Segment Drive */
+#define EXTLED_LCD_COM_SEG            (* (reg8 *) EXTLED__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define EXTLED_LCD_EN                 (* (reg8 *) EXTLED__LCD_EN)
+/* Slew Rate Control */
+#define EXTLED_SLW                    (* (reg8 *) EXTLED__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define EXTLED_PRTDSI__CAPS_SEL       (* (reg8 *) EXTLED__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define EXTLED_PRTDSI__DBL_SYNC_IN    (* (reg8 *) EXTLED__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define EXTLED_PRTDSI__OE_SEL0        (* (reg8 *) EXTLED__PRTDSI__OE_SEL0) 
+#define EXTLED_PRTDSI__OE_SEL1        (* (reg8 *) EXTLED__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define EXTLED_PRTDSI__OUT_SEL0       (* (reg8 *) EXTLED__PRTDSI__OUT_SEL0) 
+#define EXTLED_PRTDSI__OUT_SEL1       (* (reg8 *) EXTLED__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define EXTLED_PRTDSI__SYNC_OUT       (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT) 
+
+
+#if defined(EXTLED__INTSTAT)  /* Interrupt Registers */
+
+    #define EXTLED_INTSTAT                (* (reg8 *) EXTLED__INTSTAT)
+    #define EXTLED_SNAP                   (* (reg8 *) EXTLED__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_EXTLED_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: EXTLED.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_EXTLED_ALIASES_H) /* Pins EXTLED_ALIASES_H */
-#define CY_PINS_EXTLED_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define EXTLED_0		(EXTLED__0__PC)
-
-#endif /* End Pins EXTLED_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: EXTLED.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_EXTLED_ALIASES_H) /* Pins EXTLED_ALIASES_H */
+#define CY_PINS_EXTLED_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define EXTLED_0		(EXTLED__0__PC)
+
+#endif /* End Pins EXTLED_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: LED1.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "LED1.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: LED1_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void LED1_Write(uint8 value) 
-{
-    uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));
-    LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: LED1_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  LED1_DM_STRONG     Strong Drive 
-*  LED1_DM_OD_HI      Open Drain, Drives High 
-*  LED1_DM_OD_LO      Open Drain, Drives Low 
-*  LED1_DM_RES_UP     Resistive Pull Up 
-*  LED1_DM_RES_DWN    Resistive Pull Down 
-*  LED1_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  LED1_DM_DIG_HIZ    High Impedance Digital 
-*  LED1_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void LED1_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(LED1_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: LED1_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro LED1_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 LED1_Read(void) 
-{
-    return (LED1_PS & LED1_MASK) >> LED1_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: LED1_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 LED1_ReadDataReg(void) 
-{
-    return (LED1_DR & LED1_MASK) >> LED1_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(LED1_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: LED1_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 LED1_ClearInterrupt(void) 
-    {
-        return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: LED1.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "LED1.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: LED1_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void LED1_Write(uint8 value) 
+{
+    uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));
+    LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: LED1_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  LED1_DM_STRONG     Strong Drive 
+*  LED1_DM_OD_HI      Open Drain, Drives High 
+*  LED1_DM_OD_LO      Open Drain, Drives Low 
+*  LED1_DM_RES_UP     Resistive Pull Up 
+*  LED1_DM_RES_DWN    Resistive Pull Down 
+*  LED1_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  LED1_DM_DIG_HIZ    High Impedance Digital 
+*  LED1_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void LED1_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(LED1_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: LED1_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro LED1_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 LED1_Read(void) 
+{
+    return (LED1_PS & LED1_MASK) >> LED1_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: LED1_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 LED1_ReadDataReg(void) 
+{
+    return (LED1_DR & LED1_MASK) >> LED1_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(LED1_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: LED1_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 LED1_ClearInterrupt(void) 
+    {
+        return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: LED1.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */
-#define CY_PINS_LED1_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "LED1_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    LED1_Write(uint8 value) ;
-void    LED1_SetDriveMode(uint8 mode) ;
-uint8   LED1_ReadDataReg(void) ;
-uint8   LED1_Read(void) ;
-uint8   LED1_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define LED1_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define LED1_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define LED1_DM_RES_UP          PIN_DM_RES_UP
-#define LED1_DM_RES_DWN         PIN_DM_RES_DWN
-#define LED1_DM_OD_LO           PIN_DM_OD_LO
-#define LED1_DM_OD_HI           PIN_DM_OD_HI
-#define LED1_DM_STRONG          PIN_DM_STRONG
-#define LED1_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define LED1_MASK               LED1__MASK
-#define LED1_SHIFT              LED1__SHIFT
-#define LED1_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define LED1_PS                     (* (reg8 *) LED1__PS)
-/* Data Register */
-#define LED1_DR                     (* (reg8 *) LED1__DR)
-/* Port Number */
-#define LED1_PRT_NUM                (* (reg8 *) LED1__PRT) 
-/* Connect to Analog Globals */                                                  
-#define LED1_AG                     (* (reg8 *) LED1__AG)                       
-/* Analog MUX bux enable */
-#define LED1_AMUX                   (* (reg8 *) LED1__AMUX) 
-/* Bidirectional Enable */                                                        
-#define LED1_BIE                    (* (reg8 *) LED1__BIE)
-/* Bit-mask for Aliased Register Access */
-#define LED1_BIT_MASK               (* (reg8 *) LED1__BIT_MASK)
-/* Bypass Enable */
-#define LED1_BYP                    (* (reg8 *) LED1__BYP)
-/* Port wide control signals */                                                   
-#define LED1_CTL                    (* (reg8 *) LED1__CTL)
-/* Drive Modes */
-#define LED1_DM0                    (* (reg8 *) LED1__DM0) 
-#define LED1_DM1                    (* (reg8 *) LED1__DM1)
-#define LED1_DM2                    (* (reg8 *) LED1__DM2) 
-/* Input Buffer Disable Override */
-#define LED1_INP_DIS                (* (reg8 *) LED1__INP_DIS)
-/* LCD Common or Segment Drive */
-#define LED1_LCD_COM_SEG            (* (reg8 *) LED1__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define LED1_LCD_EN                 (* (reg8 *) LED1__LCD_EN)
-/* Slew Rate Control */
-#define LED1_SLW                    (* (reg8 *) LED1__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define LED1_PRTDSI__CAPS_SEL       (* (reg8 *) LED1__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define LED1_PRTDSI__DBL_SYNC_IN    (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define LED1_PRTDSI__OE_SEL0        (* (reg8 *) LED1__PRTDSI__OE_SEL0) 
-#define LED1_PRTDSI__OE_SEL1        (* (reg8 *) LED1__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define LED1_PRTDSI__OUT_SEL0       (* (reg8 *) LED1__PRTDSI__OUT_SEL0) 
-#define LED1_PRTDSI__OUT_SEL1       (* (reg8 *) LED1__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define LED1_PRTDSI__SYNC_OUT       (* (reg8 *) LED1__PRTDSI__SYNC_OUT) 
-
-
-#if defined(LED1__INTSTAT)  /* Interrupt Registers */
-
-    #define LED1_INTSTAT                (* (reg8 *) LED1__INTSTAT)
-    #define LED1_SNAP                   (* (reg8 *) LED1__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_LED1_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: LED1.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */
+#define CY_PINS_LED1_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "LED1_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    LED1_Write(uint8 value) ;
+void    LED1_SetDriveMode(uint8 mode) ;
+uint8   LED1_ReadDataReg(void) ;
+uint8   LED1_Read(void) ;
+uint8   LED1_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define LED1_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define LED1_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define LED1_DM_RES_UP          PIN_DM_RES_UP
+#define LED1_DM_RES_DWN         PIN_DM_RES_DWN
+#define LED1_DM_OD_LO           PIN_DM_OD_LO
+#define LED1_DM_OD_HI           PIN_DM_OD_HI
+#define LED1_DM_STRONG          PIN_DM_STRONG
+#define LED1_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define LED1_MASK               LED1__MASK
+#define LED1_SHIFT              LED1__SHIFT
+#define LED1_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define LED1_PS                     (* (reg8 *) LED1__PS)
+/* Data Register */
+#define LED1_DR                     (* (reg8 *) LED1__DR)
+/* Port Number */
+#define LED1_PRT_NUM                (* (reg8 *) LED1__PRT) 
+/* Connect to Analog Globals */                                                  
+#define LED1_AG                     (* (reg8 *) LED1__AG)                       
+/* Analog MUX bux enable */
+#define LED1_AMUX                   (* (reg8 *) LED1__AMUX) 
+/* Bidirectional Enable */                                                        
+#define LED1_BIE                    (* (reg8 *) LED1__BIE)
+/* Bit-mask for Aliased Register Access */
+#define LED1_BIT_MASK               (* (reg8 *) LED1__BIT_MASK)
+/* Bypass Enable */
+#define LED1_BYP                    (* (reg8 *) LED1__BYP)
+/* Port wide control signals */                                                   
+#define LED1_CTL                    (* (reg8 *) LED1__CTL)
+/* Drive Modes */
+#define LED1_DM0                    (* (reg8 *) LED1__DM0) 
+#define LED1_DM1                    (* (reg8 *) LED1__DM1)
+#define LED1_DM2                    (* (reg8 *) LED1__DM2) 
+/* Input Buffer Disable Override */
+#define LED1_INP_DIS                (* (reg8 *) LED1__INP_DIS)
+/* LCD Common or Segment Drive */
+#define LED1_LCD_COM_SEG            (* (reg8 *) LED1__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define LED1_LCD_EN                 (* (reg8 *) LED1__LCD_EN)
+/* Slew Rate Control */
+#define LED1_SLW                    (* (reg8 *) LED1__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define LED1_PRTDSI__CAPS_SEL       (* (reg8 *) LED1__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define LED1_PRTDSI__DBL_SYNC_IN    (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define LED1_PRTDSI__OE_SEL0        (* (reg8 *) LED1__PRTDSI__OE_SEL0) 
+#define LED1_PRTDSI__OE_SEL1        (* (reg8 *) LED1__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define LED1_PRTDSI__OUT_SEL0       (* (reg8 *) LED1__PRTDSI__OUT_SEL0) 
+#define LED1_PRTDSI__OUT_SEL1       (* (reg8 *) LED1__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define LED1_PRTDSI__SYNC_OUT       (* (reg8 *) LED1__PRTDSI__SYNC_OUT) 
+
+
+#if defined(LED1__INTSTAT)  /* Interrupt Registers */
+
+    #define LED1_INTSTAT                (* (reg8 *) LED1__INTSTAT)
+    #define LED1_SNAP                   (* (reg8 *) LED1__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_LED1_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: LED1.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */
-#define CY_PINS_LED1_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define LED1_0		(LED1__0__PC)
-
-#endif /* End Pins LED1_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: LED1.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */
+#define CY_PINS_LED1_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define LED1_0		(LED1__0__PC)
+
+#endif /* End Pins LED1_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c

@@ -1,521 +1,521 @@
-/*******************************************************************************
-* File Name: SCSI_CLK.c
-* Version 2.20
-*
-*  Description:
-*   This file provides the source code to the API for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include <cydevice_trm.h>
-#include "SCSI_CLK.h"
-
-/* Clock Distribution registers. */
-#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
-#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
-#define BCFG2_MASK               (0x80u)
-#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
-#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
-
-#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_Start
-********************************************************************************
-*
-* Summary:
-*  Starts the clock. Note that on startup, clocks may be already running if the
-*  "Start on Reset" option is enabled in the DWR.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_Start(void) 
-{
-    /* Set the bit to enable the clock. */
-    SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
-	SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_Stop
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and returns immediately. This API does not require the
-*  source clock to be running but may return before the hardware is actually
-*  disabled. If the settings of the clock are changed after calling this
-*  function, the clock may glitch when it is started. To avoid the clock
-*  glitch, use the StopBlock function.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_Stop(void) 
-{
-    /* Clear the bit to disable the clock. */
-    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
-	SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
-}
-
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_StopBlock
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and waits for the hardware to actually be disabled before
-*  returning. This ensures that the clock is never truncated (high part of the
-*  cycle will terminate before the clock is disabled and the API returns).
-*  Note that the source clock must be running or this API will never return as
-*  a stopped clock cannot be disabled.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_StopBlock(void) 
-{
-    if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
-    {
-#if HAS_CLKDIST_LD_DISABLE
-        uint16 oldDivider;
-
-        CLK_DIST_LD = 0u;
-
-        /* Clear all the mask bits except ours. */
-#if defined(SCSI_CLK__CFG3)
-        CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
-        CLK_DIST_DMASK = 0x00u;
-#else
-        CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
-        CLK_DIST_AMASK = 0x00u;
-#endif /* SCSI_CLK__CFG3 */
-
-        /* Clear mask of bus clock. */
-        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-        oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
-        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
-
-        /* Wait for clock to be disabled */
-        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-        /* Clear the bit to disable the clock. */
-        SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
-        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-        /* Clear the disable bit */
-        CLK_DIST_LD = 0x00u;
-        CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
-#endif /* HAS_CLKDIST_LD_DISABLE */
-    }
-}
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_StandbyPower
-********************************************************************************
-*
-* Summary:
-*  Sets whether the clock is active in standby mode.
-*
-* Parameters:
-*  state:  0 to disable clock during standby, nonzero to enable.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_StandbyPower(uint8 state) 
-{
-    if(state == 0u)
-    {
-        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
-    }
-    else
-    {
-        SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_SetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Modifies the clock divider and, thus, the frequency. When the clock divider
-*  register is set to zero or changed from zero, the clock will be temporarily
-*  disabled in order to change the SSS mode bit. If the clock is enabled when
-*  SetDividerRegister is called, then the source clock must be running.
-*
-* Parameters:
-*  clkDivider:  Divider register value (0-65,535). This value is NOT the
-*    divider; the clock hardware divides by clkDivider plus one. For example,
-*    to divide the clock by 2, this parameter should be set to 1.
-*  restart:  If nonzero, restarts the clock divider: the current clock cycle
-*   will be truncated and the new divide value will take effect immediately. If
-*   zero, the new divide value will take effect at the end of the current clock
-*   cycle.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
-                                
-{
-    uint8 enabled;
-
-    uint8 currSrc = SCSI_CLK_GetSourceRegister();
-    uint16 oldDivider = SCSI_CLK_GetDividerRegister();
-
-    if (clkDivider != oldDivider)
-    {
-        enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
-
-        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
-        {
-            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
-            if (oldDivider == 0u)
-            {
-                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
-                /* don't halt the clock.  Using the shadow load isn't required as the       */
-                /* divider is ignored while SSS is set.                                     */
-                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
-                SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
-            }
-            else
-            {
-                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
-                /* it without bothering with the shadow load.                               */
-                SCSI_CLK_MOD_SRC |= CYCLK_SSS;
-                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
-            }
-        }
-        else
-        {
-			
-            if (enabled != 0u)
-            {
-                CLK_DIST_LD = 0x00u;
-
-                /* Clear all the mask bits except ours. */
-#if defined(SCSI_CLK__CFG3)
-                CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
-                CLK_DIST_DMASK = 0x00u;
-#else
-                CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
-                CLK_DIST_AMASK = 0x00u;
-#endif /* SCSI_CLK__CFG3 */
-                /* Clear mask of bus clock. */
-                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-                /* If clock is currently enabled, disable it if async or going from N-to-1*/
-                if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
-                {
-#if HAS_CLKDIST_LD_DISABLE
-                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
-
-                    /* Wait for clock to be disabled */
-                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-                    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-                    /* Clear the disable bit */
-                    CLK_DIST_LD = 0x00u;
-#endif /* HAS_CLKDIST_LD_DISABLE */
-                }
-            }
-
-            /* Load divide value. */
-            if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
-            {
-                /* If the clock is still enabled, use the shadow registers */
-                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
-
-                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
-                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-            }
-            else
-            {
-                /* If the clock is disabled, set the divider directly */
-                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
-				SCSI_CLK_CLKEN |= enabled;
-            }
-        }
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_GetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock divider register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Divide value of the clock minus 1. For example, if the clock is set to
-*  divide by 2, the return value will be 1.
-*
-*******************************************************************************/
-uint16 SCSI_CLK_GetDividerRegister(void) 
-{
-    return CY_GET_REG16(SCSI_CLK_DIV_PTR);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_SetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Sets flags that control the operating mode of the clock. This function only
-*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
-*  To clear flags, use the ClearModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_SetModeRegister(uint8 modeBitMask) 
-{
-    SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_ClearModeRegister
-********************************************************************************
-*
-* Summary:
-*  Clears flags that control the operating mode of the clock. This function
-*  only changes flags from 1 to 0; flags that are already 0 will remain
-*  unchanged. To set flags, use the SetModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) 
-{
-    SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_GetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock mode register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Bit mask representing the enabled mode bits. See the SetModeRegister and
-*  ClearModeRegister descriptions for details about the mode bits.
-*
-*******************************************************************************/
-uint8 SCSI_CLK_GetModeRegister(void) 
-{
-    return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_SetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the input source of the clock. The clock must be disabled before
-*  changing the source. The old and new clock sources must be running.
-*
-* Parameters:
-*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
-*   following input sources:
-*   - CYCLK_SRC_SEL_SYNC_DIG
-*   - CYCLK_SRC_SEL_IMO
-*   - CYCLK_SRC_SEL_XTALM
-*   - CYCLK_SRC_SEL_ILO
-*   - CYCLK_SRC_SEL_PLL
-*   - CYCLK_SRC_SEL_XTALK
-*   - CYCLK_SRC_SEL_DSI_G
-*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
-*   See the Technical Reference Manual for details on clock sources.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_SetSourceRegister(uint8 clkSource) 
-{
-    uint16 currDiv = SCSI_CLK_GetDividerRegister();
-    uint8 oldSrc = SCSI_CLK_GetSourceRegister();
-
-    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching to Master and divider is 1, set SSS, which will output master, */
-        /* then set the source so we are consistent.                                */
-        SCSI_CLK_MOD_SRC |= CYCLK_SSS;
-        SCSI_CLK_MOD_SRC =
-            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
-    }
-    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching from Master to not and divider is 1, set source, so we don't   */
-        /* lock when we clear SSS.                                                  */
-        SCSI_CLK_MOD_SRC =
-            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
-        SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
-    }
-    else
-    {
-        SCSI_CLK_MOD_SRC =
-            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_GetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the input source of the clock.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  The input source of the clock. See SetSourceRegister for details.
-*
-*******************************************************************************/
-uint8 SCSI_CLK_GetSourceRegister(void) 
-{
-    return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
-}
-
-
-#if defined(SCSI_CLK__CFG3)
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_SetPhaseRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the phase delay of the analog clock. This function is only available
-*  for analog clocks. The clock must be disabled before changing the phase
-*  delay to avoid glitches.
-*
-* Parameters:
-*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
-*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
-*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
-*   produces a 10ns delay.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) 
-{
-    SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CLK_GetPhase
-********************************************************************************
-*
-* Summary:
-*  Gets the phase delay of the analog clock. This function is only available
-*  for analog clocks.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Phase of the analog clock. See SetPhaseRegister for details.
-*
-*******************************************************************************/
-uint8 SCSI_CLK_GetPhaseRegister(void) 
-{
-    return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
-}
-
-#endif /* SCSI_CLK__CFG3 */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CLK.c
+* Version 2.20
+*
+*  Description:
+*   This file provides the source code to the API for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SCSI_CLK.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK               (0x80u)
+#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Start
+********************************************************************************
+*
+* Summary:
+*  Starts the clock. Note that on startup, clocks may be already running if the
+*  "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Start(void) 
+{
+    /* Set the bit to enable the clock. */
+    SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
+	SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and returns immediately. This API does not require the
+*  source clock to be running but may return before the hardware is actually
+*  disabled. If the settings of the clock are changed after calling this
+*  function, the clock may glitch when it is started. To avoid the clock
+*  glitch, use the StopBlock function.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Stop(void) 
+{
+    /* Clear the bit to disable the clock. */
+    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+	SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StopBlock
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and waits for the hardware to actually be disabled before
+*  returning. This ensures that the clock is never truncated (high part of the
+*  cycle will terminate before the clock is disabled and the API returns).
+*  Note that the source clock must be running or this API will never return as
+*  a stopped clock cannot be disabled.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StopBlock(void) 
+{
+    if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+    {
+#if HAS_CLKDIST_LD_DISABLE
+        uint16 oldDivider;
+
+        CLK_DIST_LD = 0u;
+
+        /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+        CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_DMASK = 0x00u;
+#else
+        CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+
+        /* Clear mask of bus clock. */
+        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+        oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
+        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+        /* Wait for clock to be disabled */
+        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+        /* Clear the bit to disable the clock. */
+        SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+        /* Clear the disable bit */
+        CLK_DIST_LD = 0x00u;
+        CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+    }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StandbyPower
+********************************************************************************
+*
+* Summary:
+*  Sets whether the clock is active in standby mode.
+*
+* Parameters:
+*  state:  0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StandbyPower(uint8 state) 
+{
+    if(state == 0u)
+    {
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+    }
+    else
+    {
+        SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Modifies the clock divider and, thus, the frequency. When the clock divider
+*  register is set to zero or changed from zero, the clock will be temporarily
+*  disabled in order to change the SSS mode bit. If the clock is enabled when
+*  SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+*  clkDivider:  Divider register value (0-65,535). This value is NOT the
+*    divider; the clock hardware divides by clkDivider plus one. For example,
+*    to divide the clock by 2, this parameter should be set to 1.
+*  restart:  If nonzero, restarts the clock divider: the current clock cycle
+*   will be truncated and the new divide value will take effect immediately. If
+*   zero, the new divide value will take effect at the end of the current clock
+*   cycle.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+                                
+{
+    uint8 enabled;
+
+    uint8 currSrc = SCSI_CLK_GetSourceRegister();
+    uint16 oldDivider = SCSI_CLK_GetDividerRegister();
+
+    if (clkDivider != oldDivider)
+    {
+        enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
+
+        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+        {
+            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
+            if (oldDivider == 0u)
+            {
+                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
+                /* don't halt the clock.  Using the shadow load isn't required as the       */
+                /* divider is ignored while SSS is set.                                     */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+                SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+            }
+            else
+            {
+                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
+                /* it without bothering with the shadow load.                               */
+                SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+            }
+        }
+        else
+        {
+			
+            if (enabled != 0u)
+            {
+                CLK_DIST_LD = 0x00u;
+
+                /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+                CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_DMASK = 0x00u;
+#else
+                CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+                /* Clear mask of bus clock. */
+                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+                /* If clock is currently enabled, disable it if async or going from N-to-1*/
+                if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+                {
+#if HAS_CLKDIST_LD_DISABLE
+                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+                    /* Wait for clock to be disabled */
+                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+                    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+                    /* Clear the disable bit */
+                    CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+                }
+            }
+
+            /* Load divide value. */
+            if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+            {
+                /* If the clock is still enabled, use the shadow registers */
+                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+            }
+            else
+            {
+                /* If the clock is disabled, set the divider directly */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+				SCSI_CLK_CLKEN |= enabled;
+            }
+        }
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock divider register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Divide value of the clock minus 1. For example, if the clock is set to
+*  divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SCSI_CLK_GetDividerRegister(void) 
+{
+    return CY_GET_REG16(SCSI_CLK_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Sets flags that control the operating mode of the clock. This function only
+*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+*  To clear flags, use the ClearModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+*  Clears flags that control the operating mode of the clock. This function
+*  only changes flags from 1 to 0; flags that are already 0 will remain
+*  unchanged. To set flags, use the SetModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock mode register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Bit mask representing the enabled mode bits. See the SetModeRegister and
+*  ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetModeRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the input source of the clock. The clock must be disabled before
+*  changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+*   following input sources:
+*   - CYCLK_SRC_SEL_SYNC_DIG
+*   - CYCLK_SRC_SEL_IMO
+*   - CYCLK_SRC_SEL_XTALM
+*   - CYCLK_SRC_SEL_ILO
+*   - CYCLK_SRC_SEL_PLL
+*   - CYCLK_SRC_SEL_XTALK
+*   - CYCLK_SRC_SEL_DSI_G
+*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+*   See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) 
+{
+    uint16 currDiv = SCSI_CLK_GetDividerRegister();
+    uint8 oldSrc = SCSI_CLK_GetSourceRegister();
+
+    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching to Master and divider is 1, set SSS, which will output master, */
+        /* then set the source so we are consistent.                                */
+        SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching from Master to not and divider is 1, set source, so we don't   */
+        /* lock when we clear SSS.                                                  */
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+        SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+    }
+    else
+    {
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the input source of the clock.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetSourceRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
+}
+
+
+#if defined(SCSI_CLK__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the phase delay of the analog clock. This function is only available
+*  for analog clocks. The clock must be disabled before changing the phase
+*  delay to avoid glitches.
+*
+* Parameters:
+*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
+*   produces a 10ns delay.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) 
+{
+    SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetPhase
+********************************************************************************
+*
+* Summary:
+*  Gets the phase delay of the analog clock. This function is only available
+*  for analog clocks.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetPhaseRegister(void) 
+{
+    return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
+}
+
+#endif /* SCSI_CLK__CFG3 */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h

@@ -1,124 +1,124 @@
-/*******************************************************************************
-* File Name: SCSI_CLK.h
-* Version 2.20
-*
-*  Description:
-*   Provides the function and constant definitions for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CLOCK_SCSI_CLK_H)
-#define CY_CLOCK_SCSI_CLK_H
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-
-/***************************************
-* Conditional Compilation Parameters
-***************************************/
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5LP) */
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void SCSI_CLK_Start(void) ;
-void SCSI_CLK_Stop(void) ;
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-void SCSI_CLK_StopBlock(void) ;
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-void SCSI_CLK_StandbyPower(uint8 state) ;
-void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) 
-                                ;
-uint16 SCSI_CLK_GetDividerRegister(void) ;
-void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
-void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
-uint8 SCSI_CLK_GetModeRegister(void) ;
-void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
-uint8 SCSI_CLK_GetSourceRegister(void) ;
-#if defined(SCSI_CLK__CFG3)
-void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
-uint8 SCSI_CLK_GetPhaseRegister(void) ;
-#endif /* defined(SCSI_CLK__CFG3) */
-
-#define SCSI_CLK_Enable()                       SCSI_CLK_Start()
-#define SCSI_CLK_Disable()                      SCSI_CLK_Stop()
-#define SCSI_CLK_SetDivider(clkDivider)         SCSI_CLK_SetDividerRegister(clkDivider, 1u)
-#define SCSI_CLK_SetDividerValue(clkDivider)    SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
-#define SCSI_CLK_SetMode(clkMode)               SCSI_CLK_SetModeRegister(clkMode)
-#define SCSI_CLK_SetSource(clkSource)           SCSI_CLK_SetSourceRegister(clkSource)
-#if defined(SCSI_CLK__CFG3)
-#define SCSI_CLK_SetPhase(clkPhase)             SCSI_CLK_SetPhaseRegister(clkPhase)
-#define SCSI_CLK_SetPhaseValue(clkPhase)        SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
-#endif /* defined(SCSI_CLK__CFG3) */
-
-
-/***************************************
-*             Registers
-***************************************/
-
-/* Register to enable or disable the clock */
-#define SCSI_CLK_CLKEN              (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
-#define SCSI_CLK_CLKEN_PTR          ((reg8 *) SCSI_CLK__PM_ACT_CFG)
-
-/* Register to enable or disable the clock */
-#define SCSI_CLK_CLKSTBY            (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
-#define SCSI_CLK_CLKSTBY_PTR        ((reg8 *) SCSI_CLK__PM_STBY_CFG)
-
-/* Clock LSB divider configuration register. */
-#define SCSI_CLK_DIV_LSB            (* (reg8 *) SCSI_CLK__CFG0)
-#define SCSI_CLK_DIV_LSB_PTR        ((reg8 *) SCSI_CLK__CFG0)
-#define SCSI_CLK_DIV_PTR            ((reg16 *) SCSI_CLK__CFG0)
-
-/* Clock MSB divider configuration register. */
-#define SCSI_CLK_DIV_MSB            (* (reg8 *) SCSI_CLK__CFG1)
-#define SCSI_CLK_DIV_MSB_PTR        ((reg8 *) SCSI_CLK__CFG1)
-
-/* Mode and source configuration register */
-#define SCSI_CLK_MOD_SRC            (* (reg8 *) SCSI_CLK__CFG2)
-#define SCSI_CLK_MOD_SRC_PTR        ((reg8 *) SCSI_CLK__CFG2)
-
-#if defined(SCSI_CLK__CFG3)
-/* Analog clock phase configuration register */
-#define SCSI_CLK_PHASE              (* (reg8 *) SCSI_CLK__CFG3)
-#define SCSI_CLK_PHASE_PTR          ((reg8 *) SCSI_CLK__CFG3)
-#endif /* defined(SCSI_CLK__CFG3) */
-
-
-/**************************************
-*       Register Constants
-**************************************/
-
-/* Power manager register masks */
-#define SCSI_CLK_CLKEN_MASK         SCSI_CLK__PM_ACT_MSK
-#define SCSI_CLK_CLKSTBY_MASK       SCSI_CLK__PM_STBY_MSK
-
-/* CFG2 field masks */
-#define SCSI_CLK_SRC_SEL_MSK        SCSI_CLK__CFG2_SRC_SEL_MASK
-#define SCSI_CLK_MODE_MASK          (~(SCSI_CLK_SRC_SEL_MSK))
-
-#if defined(SCSI_CLK__CFG3)
-/* CFG3 phase mask */
-#define SCSI_CLK_PHASE_MASK         SCSI_CLK__CFG3_PHASE_DLY_MASK
-#endif /* defined(SCSI_CLK__CFG3) */
-
-#endif /* CY_CLOCK_SCSI_CLK_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CLK.h
+* Version 2.20
+*
+*  Description:
+*   Provides the function and constant definitions for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SCSI_CLK_H)
+#define CY_CLOCK_SCSI_CLK_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void SCSI_CLK_Start(void) ;
+void SCSI_CLK_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SCSI_CLK_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SCSI_CLK_StandbyPower(uint8 state) ;
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) 
+                                ;
+uint16 SCSI_CLK_GetDividerRegister(void) ;
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SCSI_CLK_GetModeRegister(void) ;
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
+uint8 SCSI_CLK_GetSourceRegister(void) ;
+#if defined(SCSI_CLK__CFG3)
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SCSI_CLK_GetPhaseRegister(void) ;
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#define SCSI_CLK_Enable()                       SCSI_CLK_Start()
+#define SCSI_CLK_Disable()                      SCSI_CLK_Stop()
+#define SCSI_CLK_SetDivider(clkDivider)         SCSI_CLK_SetDividerRegister(clkDivider, 1u)
+#define SCSI_CLK_SetDividerValue(clkDivider)    SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SCSI_CLK_SetMode(clkMode)               SCSI_CLK_SetModeRegister(clkMode)
+#define SCSI_CLK_SetSource(clkSource)           SCSI_CLK_SetSourceRegister(clkSource)
+#if defined(SCSI_CLK__CFG3)
+#define SCSI_CLK_SetPhase(clkPhase)             SCSI_CLK_SetPhaseRegister(clkPhase)
+#define SCSI_CLK_SetPhaseValue(clkPhase)        SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKEN              (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
+#define SCSI_CLK_CLKEN_PTR          ((reg8 *) SCSI_CLK__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKSTBY            (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
+#define SCSI_CLK_CLKSTBY_PTR        ((reg8 *) SCSI_CLK__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SCSI_CLK_DIV_LSB            (* (reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_LSB_PTR        ((reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_PTR            ((reg16 *) SCSI_CLK__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SCSI_CLK_DIV_MSB            (* (reg8 *) SCSI_CLK__CFG1)
+#define SCSI_CLK_DIV_MSB_PTR        ((reg8 *) SCSI_CLK__CFG1)
+
+/* Mode and source configuration register */
+#define SCSI_CLK_MOD_SRC            (* (reg8 *) SCSI_CLK__CFG2)
+#define SCSI_CLK_MOD_SRC_PTR        ((reg8 *) SCSI_CLK__CFG2)
+
+#if defined(SCSI_CLK__CFG3)
+/* Analog clock phase configuration register */
+#define SCSI_CLK_PHASE              (* (reg8 *) SCSI_CLK__CFG3)
+#define SCSI_CLK_PHASE_PTR          ((reg8 *) SCSI_CLK__CFG3)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/**************************************
+*       Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SCSI_CLK_CLKEN_MASK         SCSI_CLK__PM_ACT_MSK
+#define SCSI_CLK_CLKSTBY_MASK       SCSI_CLK__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SCSI_CLK_SRC_SEL_MSK        SCSI_CLK__CFG2_SRC_SEL_MASK
+#define SCSI_CLK_MODE_MASK          (~(SCSI_CLK_SRC_SEL_MSK))
+
+#if defined(SCSI_CLK__CFG3)
+/* CFG3 phase mask */
+#define SCSI_CLK_PHASE_MASK         SCSI_CLK__CFG3_PHASE_DLY_MASK
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#endif /* CY_CLOCK_SCSI_CLK_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c

@@ -1,65 +1,65 @@
-/*******************************************************************************
-* File Name: SCSI_CTL_PHASE.c  
-* Version 1.80
-*
-* Description:
-*  This file contains API to enable firmware control of a Control Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_CTL_PHASE.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
-
-    
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_Write
-********************************************************************************
-*
-* Summary:
-*  Write a byte to the Control Register.
-*
-* Parameters:
-*  control:  The value to be assigned to the Control Register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_CTL_PHASE_Write(uint8 control) 
-{
-    SCSI_CTL_PHASE_Control = control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Control Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Returns the current value in the Control Register.
-*
-*******************************************************************************/
-uint8 SCSI_CTL_PHASE_Read(void) 
-{
-    return SCSI_CTL_PHASE_Control;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.c  
+* Version 1.80
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
+    
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Write(uint8 control) 
+{
+    SCSI_CTL_PHASE_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_CTL_PHASE_Read(void) 
+{
+    return SCSI_CTL_PHASE_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h

@@ -1,59 +1,59 @@
-/*******************************************************************************
-* File Name: SCSI_CTL_PHASE.h  
-* Version 1.80
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
-#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
-
-#include "cytypes.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 controlState;
-
-} SCSI_CTL_PHASE_BACKUP_STRUCT;
-
-
-/***************************************
-*         Function Prototypes 
-***************************************/
-
-void    SCSI_CTL_PHASE_Write(uint8 control) ;
-uint8   SCSI_CTL_PHASE_Read(void) ;
-
-void SCSI_CTL_PHASE_SaveConfig(void) ;
-void SCSI_CTL_PHASE_RestoreConfig(void) ;
-void SCSI_CTL_PHASE_Sleep(void) ; 
-void SCSI_CTL_PHASE_Wakeup(void) ;
-
-
-/***************************************
-*            Registers        
-***************************************/
-
-/* Control Register */
-#define SCSI_CTL_PHASE_Control        (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
-#define SCSI_CTL_PHASE_Control_PTR    (  (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
-
-#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.h  
+* Version 1.80
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
+
+#include "cytypes.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_CTL_PHASE_BACKUP_STRUCT;
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_CTL_PHASE_Write(uint8 control) ;
+uint8   SCSI_CTL_PHASE_Read(void) ;
+
+void SCSI_CTL_PHASE_SaveConfig(void) ;
+void SCSI_CTL_PHASE_RestoreConfig(void) ;
+void SCSI_CTL_PHASE_Sleep(void) ; 
+void SCSI_CTL_PHASE_Wakeup(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_CTL_PHASE_Control        (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_CTL_PHASE_Control_PTR    (  (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c

@@ -1,109 +1,109 @@
-/*******************************************************************************
-* File Name: SCSI_CTL_PHASE_PM.c
-* Version 1.80
-*
-* Description:
-*  This file contains the setup, control, and status commands to support 
-*  the component operation in the low power mode. 
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_CTL_PHASE.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
-
-static SCSI_CTL_PHASE_BACKUP_STRUCT  SCSI_CTL_PHASE_backup = {0u};
-
-    
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Saves the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_CTL_PHASE_SaveConfig(void) 
-{
-    SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*
-*******************************************************************************/
-void SCSI_CTL_PHASE_RestoreConfig(void) 
-{
-     SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepares the component for entering the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_CTL_PHASE_Sleep(void) 
-{
-    SCSI_CTL_PHASE_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_PHASE_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Restores the component after waking up from the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_CTL_PHASE_Wakeup(void)  
-{
-    SCSI_CTL_PHASE_RestoreConfig();
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
+static SCSI_CTL_PHASE_BACKUP_STRUCT  SCSI_CTL_PHASE_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_SaveConfig(void) 
+{
+    SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_RestoreConfig(void) 
+{
+     SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Sleep(void) 
+{
+    SCSI_CTL_PHASE_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Wakeup(void)  
+{
+    SCSI_CTL_PHASE_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c

@@ -1,134 +1,134 @@
-/*******************************************************************************
-* File Name: SCSI_Filtered.c  
-* Version 1.90
-*
-* Description:
-*  This file contains API to enable firmware to read the value of a Status 
-*  Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Filtered.h"
-
-#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
-
-
-/*******************************************************************************
-* Function Name: SCSI_Filtered_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Status Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The current value in the Status Register.
-*
-*******************************************************************************/
-uint8 SCSI_Filtered_Read(void) 
-{ 
-    return SCSI_Filtered_Status;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Filtered_InterruptEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the Status Register interrupt.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Filtered_InterruptEnable(void) 
-{
-    uint8 interruptState;
-    interruptState = CyEnterCriticalSection();
-    SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Filtered_InterruptDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the Status Register interrupt.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Filtered_InterruptDisable(void) 
-{
-    uint8 interruptState;
-    interruptState = CyEnterCriticalSection();
-    SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Filtered_WriteMask
-********************************************************************************
-*
-* Summary:
-*  Writes the current mask value assigned to the Status Register.
-*
-* Parameters:
-*  mask:  Value to write into the mask register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Filtered_WriteMask(uint8 mask) 
-{
-    #if(SCSI_Filtered_INPUTS < 8u)
-    	mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
-	#endif /* End SCSI_Filtered_INPUTS < 8u */
-    SCSI_Filtered_Status_Mask = mask;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Filtered_ReadMask
-********************************************************************************
-*
-* Summary:
-*  Reads the current interrupt mask assigned to the Status Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The value of the interrupt mask of the Status Register.
-*
-*******************************************************************************/
-uint8 SCSI_Filtered_ReadMask(void) 
-{
-    return SCSI_Filtered_Status_Mask;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Filtered.c  
+* Version 1.90
+*
+* Description:
+*  This file contains API to enable firmware to read the value of a Status 
+*  Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Filtered.h"
+
+#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_Read(void) 
+{ 
+    return SCSI_Filtered_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptEnable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptDisable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_WriteMask
+********************************************************************************
+*
+* Summary:
+*  Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+*  mask:  Value to write into the mask register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Filtered_WriteMask(uint8 mask) 
+{
+    #if(SCSI_Filtered_INPUTS < 8u)
+    	mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
+	#endif /* End SCSI_Filtered_INPUTS < 8u */
+    SCSI_Filtered_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_ReadMask
+********************************************************************************
+*
+* Summary:
+*  Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_ReadMask(void) 
+{
+    return SCSI_Filtered_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h

@@ -1,75 +1,75 @@
-/*******************************************************************************
-* File Name: SCSI_Filtered.h  
-* Version 1.90
-*
-* Description:
-*  This file containts Status Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
-#define CY_STATUS_REG_SCSI_Filtered_H
-
-#include "cytypes.h"
-#include "CyLib.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 statusState;
-
-} SCSI_Filtered_BACKUP_STRUCT;
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-uint8 SCSI_Filtered_Read(void) ;
-void SCSI_Filtered_InterruptEnable(void) ;
-void SCSI_Filtered_InterruptDisable(void) ;
-void SCSI_Filtered_WriteMask(uint8 mask) ;
-uint8 SCSI_Filtered_ReadMask(void) ;
-
-
-/***************************************
-*           API Constants
-***************************************/
-
-#define SCSI_Filtered_STATUS_INTR_ENBL    0x10u
-
-
-/***************************************
-*         Parameter Constants
-***************************************/
-
-/* Status Register Inputs */
-#define SCSI_Filtered_INPUTS              5
-
-
-/***************************************
-*             Registers
-***************************************/
-
-/* Status Register */
-#define SCSI_Filtered_Status             (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
-#define SCSI_Filtered_Status_PTR         (  (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
-#define SCSI_Filtered_Status_Mask        (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
-#define SCSI_Filtered_Status_Aux_Ctrl    (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
-
-#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Filtered.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
+#define CY_STATUS_REG_SCSI_Filtered_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 statusState;
+
+} SCSI_Filtered_BACKUP_STRUCT;
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+uint8 SCSI_Filtered_Read(void) ;
+void SCSI_Filtered_InterruptEnable(void) ;
+void SCSI_Filtered_InterruptDisable(void) ;
+void SCSI_Filtered_WriteMask(uint8 mask) ;
+uint8 SCSI_Filtered_ReadMask(void) ;
+
+
+/***************************************
+*           API Constants
+***************************************/
+
+#define SCSI_Filtered_STATUS_INTR_ENBL    0x10u
+
+
+/***************************************
+*         Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Filtered_INPUTS              5
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Filtered_Status             (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_PTR         (  (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_Mask        (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
+#define SCSI_Filtered_Status_Aux_Ctrl    (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c

@@ -1,65 +1,65 @@
-/*******************************************************************************
-* File Name: SCSI_Glitch_Ctl.c  
-* Version 1.80
-*
-* Description:
-*  This file contains API to enable firmware control of a Control Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Glitch_Ctl.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_Write
-********************************************************************************
-*
-* Summary:
-*  Write a byte to the Control Register.
-*
-* Parameters:
-*  control:  The value to be assigned to the Control Register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Glitch_Ctl_Write(uint8 control) 
-{
-    SCSI_Glitch_Ctl_Control = control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Control Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Returns the current value in the Control Register.
-*
-*******************************************************************************/
-uint8 SCSI_Glitch_Ctl_Read(void) 
-{
-    return SCSI_Glitch_Ctl_Control;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c  
+* Version 1.80
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control) 
+{
+    SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void) 
+{
+    return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h

@@ -1,59 +1,59 @@
-/*******************************************************************************
-* File Name: SCSI_Glitch_Ctl.h  
-* Version 1.80
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
-#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
-
-#include "cytypes.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 controlState;
-
-} SCSI_Glitch_Ctl_BACKUP_STRUCT;
-
-
-/***************************************
-*         Function Prototypes 
-***************************************/
-
-void    SCSI_Glitch_Ctl_Write(uint8 control) ;
-uint8   SCSI_Glitch_Ctl_Read(void) ;
-
-void SCSI_Glitch_Ctl_SaveConfig(void) ;
-void SCSI_Glitch_Ctl_RestoreConfig(void) ;
-void SCSI_Glitch_Ctl_Sleep(void) ; 
-void SCSI_Glitch_Ctl_Wakeup(void) ;
-
-
-/***************************************
-*            Registers        
-***************************************/
-
-/* Control Register */
-#define SCSI_Glitch_Ctl_Control        (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
-#define SCSI_Glitch_Ctl_Control_PTR    (  (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
-
-#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h  
+* Version 1.80
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Glitch_Ctl_BACKUP_STRUCT;
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8   SCSI_Glitch_Ctl_Read(void) ;
+
+void SCSI_Glitch_Ctl_SaveConfig(void) ;
+void SCSI_Glitch_Ctl_RestoreConfig(void) ;
+void SCSI_Glitch_Ctl_Sleep(void) ; 
+void SCSI_Glitch_Ctl_Wakeup(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control        (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR    (  (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c

@@ -1,109 +1,109 @@
-/*******************************************************************************
-* File Name: SCSI_Glitch_Ctl_PM.c
-* Version 1.80
-*
-* Description:
-*  This file contains the setup, control, and status commands to support 
-*  the component operation in the low power mode. 
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Glitch_Ctl.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
-
-static SCSI_Glitch_Ctl_BACKUP_STRUCT  SCSI_Glitch_Ctl_backup = {0u};
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Saves the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Glitch_Ctl_SaveConfig(void) 
-{
-    SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*
-*******************************************************************************/
-void SCSI_Glitch_Ctl_RestoreConfig(void) 
-{
-     SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepares the component for entering the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Glitch_Ctl_Sleep(void) 
-{
-    SCSI_Glitch_Ctl_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Glitch_Ctl_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Restores the component after waking up from the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Glitch_Ctl_Wakeup(void)  
-{
-    SCSI_Glitch_Ctl_RestoreConfig();
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Glitch_Ctl_BACKUP_STRUCT  SCSI_Glitch_Ctl_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_SaveConfig(void) 
+{
+    SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_RestoreConfig(void) 
+{
+     SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Sleep(void) 
+{
+    SCSI_Glitch_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Wakeup(void)  
+{
+    SCSI_Glitch_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h

@@ -1,48 +1,48 @@
-/*******************************************************************************
-* File Name: SCSI_In_DBx.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */
-#define CY_PINS_SCSI_In_DBx_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_In_DBx_0		(SCSI_In_DBx__0__PC)
-#define SCSI_In_DBx_1		(SCSI_In_DBx__1__PC)
-#define SCSI_In_DBx_2		(SCSI_In_DBx__2__PC)
-#define SCSI_In_DBx_3		(SCSI_In_DBx__3__PC)
-#define SCSI_In_DBx_4		(SCSI_In_DBx__4__PC)
-#define SCSI_In_DBx_5		(SCSI_In_DBx__5__PC)
-#define SCSI_In_DBx_6		(SCSI_In_DBx__6__PC)
-#define SCSI_In_DBx_7		(SCSI_In_DBx__7__PC)
-
-#define SCSI_In_DBx_DB0		(SCSI_In_DBx__DB0__PC)
-#define SCSI_In_DBx_DB1		(SCSI_In_DBx__DB1__PC)
-#define SCSI_In_DBx_DB2		(SCSI_In_DBx__DB2__PC)
-#define SCSI_In_DBx_DB3		(SCSI_In_DBx__DB3__PC)
-#define SCSI_In_DBx_DB4		(SCSI_In_DBx__DB4__PC)
-#define SCSI_In_DBx_DB5		(SCSI_In_DBx__DB5__PC)
-#define SCSI_In_DBx_DB6		(SCSI_In_DBx__DB6__PC)
-#define SCSI_In_DBx_DB7		(SCSI_In_DBx__DB7__PC)
-
-#endif /* End Pins SCSI_In_DBx_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_In_DBx.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */
+#define CY_PINS_SCSI_In_DBx_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_In_DBx_0		(SCSI_In_DBx__0__PC)
+#define SCSI_In_DBx_1		(SCSI_In_DBx__1__PC)
+#define SCSI_In_DBx_2		(SCSI_In_DBx__2__PC)
+#define SCSI_In_DBx_3		(SCSI_In_DBx__3__PC)
+#define SCSI_In_DBx_4		(SCSI_In_DBx__4__PC)
+#define SCSI_In_DBx_5		(SCSI_In_DBx__5__PC)
+#define SCSI_In_DBx_6		(SCSI_In_DBx__6__PC)
+#define SCSI_In_DBx_7		(SCSI_In_DBx__7__PC)
+
+#define SCSI_In_DBx_DB0		(SCSI_In_DBx__DB0__PC)
+#define SCSI_In_DBx_DB1		(SCSI_In_DBx__DB1__PC)
+#define SCSI_In_DBx_DB2		(SCSI_In_DBx__DB2__PC)
+#define SCSI_In_DBx_DB3		(SCSI_In_DBx__DB3__PC)
+#define SCSI_In_DBx_DB4		(SCSI_In_DBx__DB4__PC)
+#define SCSI_In_DBx_DB5		(SCSI_In_DBx__DB5__PC)
+#define SCSI_In_DBx_DB6		(SCSI_In_DBx__DB6__PC)
+#define SCSI_In_DBx_DB7		(SCSI_In_DBx__DB7__PC)
+
+#endif /* End Pins SCSI_In_DBx_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h

@@ -1,42 +1,42 @@
-/*******************************************************************************
-* File Name: SCSI_In.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */
-#define CY_PINS_SCSI_In_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_In_0		(SCSI_In__0__PC)
-#define SCSI_In_1		(SCSI_In__1__PC)
-#define SCSI_In_2		(SCSI_In__2__PC)
-#define SCSI_In_3		(SCSI_In__3__PC)
-#define SCSI_In_4		(SCSI_In__4__PC)
-
-#define SCSI_In_DBP		(SCSI_In__DBP__PC)
-#define SCSI_In_MSG		(SCSI_In__MSG__PC)
-#define SCSI_In_CD		(SCSI_In__CD__PC)
-#define SCSI_In_REQ		(SCSI_In__REQ__PC)
-#define SCSI_In_IO		(SCSI_In__IO__PC)
-
-#endif /* End Pins SCSI_In_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_In.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */
+#define CY_PINS_SCSI_In_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_In_0		(SCSI_In__0__PC)
+#define SCSI_In_1		(SCSI_In__1__PC)
+#define SCSI_In_2		(SCSI_In__2__PC)
+#define SCSI_In_3		(SCSI_In__3__PC)
+#define SCSI_In_4		(SCSI_In__4__PC)
+
+#define SCSI_In_DBP		(SCSI_In__DBP__PC)
+#define SCSI_In_MSG		(SCSI_In__MSG__PC)
+#define SCSI_In_CD		(SCSI_In__CD__PC)
+#define SCSI_In_REQ		(SCSI_In__REQ__PC)
+#define SCSI_In_IO		(SCSI_In__IO__PC)
+
+#endif /* End Pins SCSI_In_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h

@@ -1,42 +1,42 @@
-/*******************************************************************************
-* File Name: SCSI_Noise.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
-#define CY_PINS_SCSI_Noise_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_Noise_0		(SCSI_Noise__0__PC)
-#define SCSI_Noise_1		(SCSI_Noise__1__PC)
-#define SCSI_Noise_2		(SCSI_Noise__2__PC)
-#define SCSI_Noise_3		(SCSI_Noise__3__PC)
-#define SCSI_Noise_4		(SCSI_Noise__4__PC)
-
-#define SCSI_Noise_ATN		(SCSI_Noise__ATN__PC)
-#define SCSI_Noise_BSY		(SCSI_Noise__BSY__PC)
-#define SCSI_Noise_SEL		(SCSI_Noise__SEL__PC)
-#define SCSI_Noise_RST		(SCSI_Noise__RST__PC)
-#define SCSI_Noise_ACK		(SCSI_Noise__ACK__PC)
-
-#endif /* End Pins SCSI_Noise_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Noise.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
+#define CY_PINS_SCSI_Noise_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_Noise_0		(SCSI_Noise__0__PC)
+#define SCSI_Noise_1		(SCSI_Noise__1__PC)
+#define SCSI_Noise_2		(SCSI_Noise__2__PC)
+#define SCSI_Noise_3		(SCSI_Noise__3__PC)
+#define SCSI_Noise_4		(SCSI_Noise__4__PC)
+
+#define SCSI_Noise_ATN		(SCSI_Noise__ATN__PC)
+#define SCSI_Noise_BSY		(SCSI_Noise__BSY__PC)
+#define SCSI_Noise_SEL		(SCSI_Noise__SEL__PC)
+#define SCSI_Noise_RST		(SCSI_Noise__RST__PC)
+#define SCSI_Noise_ACK		(SCSI_Noise__ACK__PC)
+
+#endif /* End Pins SCSI_Noise_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c

@@ -1,65 +1,65 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Bits.c  
-* Version 1.80
-*
-* Description:
-*  This file contains API to enable firmware control of a Control Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Out_Bits.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_Write
-********************************************************************************
-*
-* Summary:
-*  Write a byte to the Control Register.
-*
-* Parameters:
-*  control:  The value to be assigned to the Control Register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Out_Bits_Write(uint8 control) 
-{
-    SCSI_Out_Bits_Control = control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Control Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Returns the current value in the Control Register.
-*
-*******************************************************************************/
-uint8 SCSI_Out_Bits_Read(void) 
-{
-    return SCSI_Out_Bits_Control;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Bits.c  
+* Version 1.80
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Write(uint8 control) 
+{
+    SCSI_Out_Bits_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Out_Bits_Read(void) 
+{
+    return SCSI_Out_Bits_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h

@@ -1,59 +1,59 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Bits.h  
-* Version 1.80
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
-#define CY_CONTROL_REG_SCSI_Out_Bits_H
-
-#include "cytypes.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 controlState;
-
-} SCSI_Out_Bits_BACKUP_STRUCT;
-
-
-/***************************************
-*         Function Prototypes 
-***************************************/
-
-void    SCSI_Out_Bits_Write(uint8 control) ;
-uint8   SCSI_Out_Bits_Read(void) ;
-
-void SCSI_Out_Bits_SaveConfig(void) ;
-void SCSI_Out_Bits_RestoreConfig(void) ;
-void SCSI_Out_Bits_Sleep(void) ; 
-void SCSI_Out_Bits_Wakeup(void) ;
-
-
-/***************************************
-*            Registers        
-***************************************/
-
-/* Control Register */
-#define SCSI_Out_Bits_Control        (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
-#define SCSI_Out_Bits_Control_PTR    (  (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
-
-#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Bits.h  
+* Version 1.80
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
+#define CY_CONTROL_REG_SCSI_Out_Bits_H
+
+#include "cytypes.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Out_Bits_BACKUP_STRUCT;
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Out_Bits_Write(uint8 control) ;
+uint8   SCSI_Out_Bits_Read(void) ;
+
+void SCSI_Out_Bits_SaveConfig(void) ;
+void SCSI_Out_Bits_RestoreConfig(void) ;
+void SCSI_Out_Bits_Sleep(void) ; 
+void SCSI_Out_Bits_Wakeup(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Out_Bits_Control        (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Out_Bits_Control_PTR    (  (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c

@@ -1,109 +1,109 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Bits_PM.c
-* Version 1.80
-*
-* Description:
-*  This file contains the setup, control, and status commands to support 
-*  the component operation in the low power mode. 
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Out_Bits.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
-
-static SCSI_Out_Bits_BACKUP_STRUCT  SCSI_Out_Bits_backup = {0u};
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Saves the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Bits_SaveConfig(void) 
-{
-    SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*
-*******************************************************************************/
-void SCSI_Out_Bits_RestoreConfig(void) 
-{
-     SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepares the component for entering the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Bits_Sleep(void) 
-{
-    SCSI_Out_Bits_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Bits_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Restores the component after waking up from the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Bits_Wakeup(void)  
-{
-    SCSI_Out_Bits_RestoreConfig();
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Bits_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Bits_BACKUP_STRUCT  SCSI_Out_Bits_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_SaveConfig(void) 
+{
+    SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Bits_RestoreConfig(void) 
+{
+     SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Sleep(void) 
+{
+    SCSI_Out_Bits_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Wakeup(void)  
+{
+    SCSI_Out_Bits_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c

@@ -1,65 +1,65 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Ctl.c  
-* Version 1.80
-*
-* Description:
-*  This file contains API to enable firmware control of a Control Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Out_Ctl.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_Write
-********************************************************************************
-*
-* Summary:
-*  Write a byte to the Control Register.
-*
-* Parameters:
-*  control:  The value to be assigned to the Control Register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Out_Ctl_Write(uint8 control) 
-{
-    SCSI_Out_Ctl_Control = control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Control Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Returns the current value in the Control Register.
-*
-*******************************************************************************/
-uint8 SCSI_Out_Ctl_Read(void) 
-{
-    return SCSI_Out_Ctl_Control;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl.c  
+* Version 1.80
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Write(uint8 control) 
+{
+    SCSI_Out_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Out_Ctl_Read(void) 
+{
+    return SCSI_Out_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h

@@ -1,59 +1,59 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Ctl.h  
-* Version 1.80
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
-#define CY_CONTROL_REG_SCSI_Out_Ctl_H
-
-#include "cytypes.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 controlState;
-
-} SCSI_Out_Ctl_BACKUP_STRUCT;
-
-
-/***************************************
-*         Function Prototypes 
-***************************************/
-
-void    SCSI_Out_Ctl_Write(uint8 control) ;
-uint8   SCSI_Out_Ctl_Read(void) ;
-
-void SCSI_Out_Ctl_SaveConfig(void) ;
-void SCSI_Out_Ctl_RestoreConfig(void) ;
-void SCSI_Out_Ctl_Sleep(void) ; 
-void SCSI_Out_Ctl_Wakeup(void) ;
-
-
-/***************************************
-*            Registers        
-***************************************/
-
-/* Control Register */
-#define SCSI_Out_Ctl_Control        (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
-#define SCSI_Out_Ctl_Control_PTR    (  (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
-
-#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl.h  
+* Version 1.80
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Out_Ctl_H
+
+#include "cytypes.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 controlState;
+
+} SCSI_Out_Ctl_BACKUP_STRUCT;
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_Out_Ctl_Write(uint8 control) ;
+uint8   SCSI_Out_Ctl_Read(void) ;
+
+void SCSI_Out_Ctl_SaveConfig(void) ;
+void SCSI_Out_Ctl_RestoreConfig(void) ;
+void SCSI_Out_Ctl_Sleep(void) ; 
+void SCSI_Out_Ctl_Wakeup(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_Out_Ctl_Control        (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Out_Ctl_Control_PTR    (  (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c

@@ -1,109 +1,109 @@
-/*******************************************************************************
-* File Name: SCSI_Out_Ctl_PM.c
-* Version 1.80
-*
-* Description:
-*  This file contains the setup, control, and status commands to support 
-*  the component operation in the low power mode. 
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Out_Ctl.h"
-
-/* Check for removal by optimization */
-#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
-
-static SCSI_Out_Ctl_BACKUP_STRUCT  SCSI_Out_Ctl_backup = {0u};
-
-    
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Saves the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Ctl_SaveConfig(void) 
-{
-    SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores the control register value.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*
-*******************************************************************************/
-void SCSI_Out_Ctl_RestoreConfig(void) 
-{
-     SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepares the component for entering the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Ctl_Sleep(void) 
-{
-    SCSI_Out_Ctl_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Out_Ctl_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Restores the component after waking up from the low power mode.
-*
-* Parameters:
-*  None
-*
-* Return:
-*  None
-*
-*******************************************************************************/
-void SCSI_Out_Ctl_Wakeup(void)  
-{
-    SCSI_Out_Ctl_RestoreConfig();
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+*  This file contains the setup, control, and status commands to support 
+*  the component operation in the low power mode. 
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Ctl_BACKUP_STRUCT  SCSI_Out_Ctl_backup = {0u};
+
+    
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Saves the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_SaveConfig(void) 
+{
+    SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Restores the control register value.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_RestoreConfig(void) 
+{
+     SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepares the component for entering the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Sleep(void) 
+{
+    SCSI_Out_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Restores the component after waking up from the low power mode.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Wakeup(void)  
+{
+    SCSI_Out_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h

@@ -1,48 +1,48 @@
-/*******************************************************************************
-* File Name: SCSI_Out_DBx.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */
-#define CY_PINS_SCSI_Out_DBx_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
-#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
-#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
-#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
-#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
-#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
-#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
-#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
-
-#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
-#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
-#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
-#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
-#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
-#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
-#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
-#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
-
-#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out_DBx.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */
+#define CY_PINS_SCSI_Out_DBx_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
+
+#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h

@@ -1,52 +1,52 @@
-/*******************************************************************************
-* File Name: SCSI_Out.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */
-#define CY_PINS_SCSI_Out_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_Out_0		(SCSI_Out__0__PC)
-#define SCSI_Out_1		(SCSI_Out__1__PC)
-#define SCSI_Out_2		(SCSI_Out__2__PC)
-#define SCSI_Out_3		(SCSI_Out__3__PC)
-#define SCSI_Out_4		(SCSI_Out__4__PC)
-#define SCSI_Out_5		(SCSI_Out__5__PC)
-#define SCSI_Out_6		(SCSI_Out__6__PC)
-#define SCSI_Out_7		(SCSI_Out__7__PC)
-#define SCSI_Out_8		(SCSI_Out__8__PC)
-#define SCSI_Out_9		(SCSI_Out__9__PC)
-
-#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
-#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
-#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
-#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
-#define SCSI_Out_RST		(SCSI_Out__RST__PC)
-#define SCSI_Out_MSG_raw		(SCSI_Out__MSG_raw__PC)
-#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
-#define SCSI_Out_CD_raw		(SCSI_Out__CD_raw__PC)
-#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
-#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
-
-#endif /* End Pins SCSI_Out_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Out.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */
+#define CY_PINS_SCSI_Out_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_Out_0		(SCSI_Out__0__PC)
+#define SCSI_Out_1		(SCSI_Out__1__PC)
+#define SCSI_Out_2		(SCSI_Out__2__PC)
+#define SCSI_Out_3		(SCSI_Out__3__PC)
+#define SCSI_Out_4		(SCSI_Out__4__PC)
+#define SCSI_Out_5		(SCSI_Out__5__PC)
+#define SCSI_Out_6		(SCSI_Out__6__PC)
+#define SCSI_Out_7		(SCSI_Out__7__PC)
+#define SCSI_Out_8		(SCSI_Out__8__PC)
+#define SCSI_Out_9		(SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
+#define SCSI_Out_RST		(SCSI_Out__RST__PC)
+#define SCSI_Out_MSG_raw		(SCSI_Out__MSG_raw__PC)
+#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
+#define SCSI_Out_CD_raw		(SCSI_Out__CD_raw__PC)
+#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
+
+#endif /* End Pins SCSI_Out_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c

@@ -1,134 +1,134 @@
-/*******************************************************************************
-* File Name: SCSI_Parity_Error.c  
-* Version 1.90
-*
-* Description:
-*  This file contains API to enable firmware to read the value of a Status 
-*  Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_Parity_Error.h"
-
-#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
-
-
-/*******************************************************************************
-* Function Name: SCSI_Parity_Error_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Status Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The current value in the Status Register.
-*
-*******************************************************************************/
-uint8 SCSI_Parity_Error_Read(void) 
-{ 
-    return SCSI_Parity_Error_Status;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Parity_Error_InterruptEnable
-********************************************************************************
-*
-* Summary:
-*  Enables the Status Register interrupt.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Parity_Error_InterruptEnable(void) 
-{
-    uint8 interruptState;
-    interruptState = CyEnterCriticalSection();
-    SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Parity_Error_InterruptDisable
-********************************************************************************
-*
-* Summary:
-*  Disables the Status Register interrupt.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Parity_Error_InterruptDisable(void) 
-{
-    uint8 interruptState;
-    interruptState = CyEnterCriticalSection();
-    SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
-    CyExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Parity_Error_WriteMask
-********************************************************************************
-*
-* Summary:
-*  Writes the current mask value assigned to the Status Register.
-*
-* Parameters:
-*  mask:  Value to write into the mask register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_Parity_Error_WriteMask(uint8 mask) 
-{
-    #if(SCSI_Parity_Error_INPUTS < 8u)
-    	mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
-	#endif /* End SCSI_Parity_Error_INPUTS < 8u */
-    SCSI_Parity_Error_Status_Mask = mask;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_Parity_Error_ReadMask
-********************************************************************************
-*
-* Summary:
-*  Reads the current interrupt mask assigned to the Status Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The value of the interrupt mask of the Status Register.
-*
-*******************************************************************************/
-uint8 SCSI_Parity_Error_ReadMask(void) 
-{
-    return SCSI_Parity_Error_Status_Mask;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.c  
+* Version 1.90
+*
+* Description:
+*  This file contains API to enable firmware to read the value of a Status 
+*  Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Parity_Error.h"
+
+#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_Read(void) 
+{ 
+    return SCSI_Parity_Error_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptEnable
+********************************************************************************
+*
+* Summary:
+*  Enables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptEnable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptDisable
+********************************************************************************
+*
+* Summary:
+*  Disables the Status Register interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptDisable(void) 
+{
+    uint8 interruptState;
+    interruptState = CyEnterCriticalSection();
+    SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
+    CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_WriteMask
+********************************************************************************
+*
+* Summary:
+*  Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+*  mask:  Value to write into the mask register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_WriteMask(uint8 mask) 
+{
+    #if(SCSI_Parity_Error_INPUTS < 8u)
+    	mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
+	#endif /* End SCSI_Parity_Error_INPUTS < 8u */
+    SCSI_Parity_Error_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_ReadMask
+********************************************************************************
+*
+* Summary:
+*  Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_ReadMask(void) 
+{
+    return SCSI_Parity_Error_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h

@@ -1,75 +1,75 @@
-/*******************************************************************************
-* File Name: SCSI_Parity_Error.h  
-* Version 1.90
-*
-* Description:
-*  This file containts Status Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
-#define CY_STATUS_REG_SCSI_Parity_Error_H
-
-#include "cytypes.h"
-#include "CyLib.h"
-
-    
-/***************************************
-*     Data Struct Definitions
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 statusState;
-
-} SCSI_Parity_Error_BACKUP_STRUCT;
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-uint8 SCSI_Parity_Error_Read(void) ;
-void SCSI_Parity_Error_InterruptEnable(void) ;
-void SCSI_Parity_Error_InterruptDisable(void) ;
-void SCSI_Parity_Error_WriteMask(uint8 mask) ;
-uint8 SCSI_Parity_Error_ReadMask(void) ;
-
-
-/***************************************
-*           API Constants
-***************************************/
-
-#define SCSI_Parity_Error_STATUS_INTR_ENBL    0x10u
-
-
-/***************************************
-*         Parameter Constants
-***************************************/
-
-/* Status Register Inputs */
-#define SCSI_Parity_Error_INPUTS              1
-
-
-/***************************************
-*             Registers
-***************************************/
-
-/* Status Register */
-#define SCSI_Parity_Error_Status             (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
-#define SCSI_Parity_Error_Status_PTR         (  (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
-#define SCSI_Parity_Error_Status_Mask        (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
-#define SCSI_Parity_Error_Status_Aux_Ctrl    (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
-
-#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
+#define CY_STATUS_REG_SCSI_Parity_Error_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+    
+/***************************************
+*     Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 statusState;
+
+} SCSI_Parity_Error_BACKUP_STRUCT;
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+uint8 SCSI_Parity_Error_Read(void) ;
+void SCSI_Parity_Error_InterruptEnable(void) ;
+void SCSI_Parity_Error_InterruptDisable(void) ;
+void SCSI_Parity_Error_WriteMask(uint8 mask) ;
+uint8 SCSI_Parity_Error_ReadMask(void) ;
+
+
+/***************************************
+*           API Constants
+***************************************/
+
+#define SCSI_Parity_Error_STATUS_INTR_ENBL    0x10u
+
+
+/***************************************
+*         Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Parity_Error_INPUTS              1
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Parity_Error_Status             (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_PTR         (  (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_Mask        (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
+#define SCSI_Parity_Error_Status_Aux_Ctrl    (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SCSI_RST_ISR.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SCSI_RST_ISR.h>
-
-#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SCSI_RST_ISR_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_RST_ISR_Disable();
-
-    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
-    SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);
-
-    /* Set the priority. */
-    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_RST_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_RST_ISR_Disable();
-
-    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
-    SCSI_RST_ISR_SetVector(address);
-
-    /* Set the priority. */
-    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_RST_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_Stop(void)
-{
-    /* Disable this interrupt. */
-    SCSI_RST_ISR_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SCSI_RST_ISR_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SCSI_RST_ISR.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SCSI_RST_ISR_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SCSI_RST_ISR_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SCSI_RST_ISR_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SCSI_RST_ISR_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_SetPriority(uint8 priority)
-{
-    *SCSI_RST_ISR_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SCSI_RST_ISR_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SCSI_RST_ISR_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SCSI_RST_ISR_SetPending(void)
-{
-    *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RST_ISR_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RST_ISR_ClearPending(void)
-{
-    *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_RST_ISR.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_RST_ISR.h>
+
+#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_RST_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
+    SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);
+
+    /* Set the priority. */
+    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RST_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
+    SCSI_RST_ISR_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RST_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_RST_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_RST_ISR.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_RST_ISR_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_RST_ISR_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_RST_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_RST_ISR_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetPriority(uint8 priority)
+{
+    *SCSI_RST_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SCSI_RST_ISR_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_RST_ISR_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetPending(void)
+{
+    *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_ClearPending(void)
+{
+    *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SCSI_RST_ISR.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SCSI_RST_ISR_H)
-#define CY_ISR_SCSI_RST_ISR_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SCSI_RST_ISR_Start(void);
-void SCSI_RST_ISR_StartEx(cyisraddress address);
-void SCSI_RST_ISR_Stop(void);
-
-CY_ISR_PROTO(SCSI_RST_ISR_Interrupt);
-
-void SCSI_RST_ISR_SetVector(cyisraddress address);
-cyisraddress SCSI_RST_ISR_GetVector(void);
-
-void SCSI_RST_ISR_SetPriority(uint8 priority);
-uint8 SCSI_RST_ISR_GetPriority(void);
-
-void SCSI_RST_ISR_Enable(void);
-uint8 SCSI_RST_ISR_GetState(void);
-void SCSI_RST_ISR_Disable(void);
-
-void SCSI_RST_ISR_SetPending(void);
-void SCSI_RST_ISR_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */
-#define SCSI_RST_ISR_INTC_VECTOR            ((reg32 *) SCSI_RST_ISR__INTC_VECT)
-
-/* Address of the SCSI_RST_ISR ISR priority. */
-#define SCSI_RST_ISR_INTC_PRIOR             ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG)
-
-/* Priority of the SCSI_RST_ISR interrupt. */
-#define SCSI_RST_ISR_INTC_PRIOR_NUMBER      SCSI_RST_ISR__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */
-#define SCSI_RST_ISR_INTC_SET_EN            ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */
-#define SCSI_RST_ISR_INTC_CLR_EN            ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */
-#define SCSI_RST_ISR_INTC_SET_PD            ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */
-#define SCSI_RST_ISR_INTC_CLR_PD            ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SCSI_RST_ISR_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_RST_ISR.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_RST_ISR_H)
+#define CY_ISR_SCSI_RST_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_RST_ISR_Start(void);
+void SCSI_RST_ISR_StartEx(cyisraddress address);
+void SCSI_RST_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_RST_ISR_Interrupt);
+
+void SCSI_RST_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_RST_ISR_GetVector(void);
+
+void SCSI_RST_ISR_SetPriority(uint8 priority);
+uint8 SCSI_RST_ISR_GetPriority(void);
+
+void SCSI_RST_ISR_Enable(void);
+uint8 SCSI_RST_ISR_GetState(void);
+void SCSI_RST_ISR_Disable(void);
+
+void SCSI_RST_ISR_SetPending(void);
+void SCSI_RST_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */
+#define SCSI_RST_ISR_INTC_VECTOR            ((reg32 *) SCSI_RST_ISR__INTC_VECT)
+
+/* Address of the SCSI_RST_ISR ISR priority. */
+#define SCSI_RST_ISR_INTC_PRIOR             ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_PRIOR_NUMBER      SCSI_RST_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_SET_EN            ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_CLR_EN            ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */
+#define SCSI_RST_ISR_INTC_SET_PD            ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_CLR_PD            ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_RST_ISR_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SCSI_RX_DMA_COMPLETE.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SCSI_RX_DMA_COMPLETE.h>
-
-#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SCSI_RX_DMA_COMPLETE_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
-    SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt);
-
-    /* Set the priority. */
-    SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_RX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
-    SCSI_RX_DMA_COMPLETE_SetVector(address);
-
-    /* Set the priority. */
-    SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_RX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_Stop(void)
-{
-    /* Disable this interrupt. */
-    SCSI_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
-{
-    *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_SetPending(void)
-{
-    *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_RX_DMA_COMPLETE_ClearPending(void)
-{
-    *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_RX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+    SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt);
+
+    /* Set the priority. */
+    SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+    SCSI_RX_DMA_COMPLETE_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+    *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPending(void)
+{
+    *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_ClearPending(void)
+{
+    *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SCSI_RX_DMA_COMPLETE.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H)
-#define CY_ISR_SCSI_RX_DMA_COMPLETE_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SCSI_RX_DMA_COMPLETE_Start(void);
-void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address);
-void SCSI_RX_DMA_COMPLETE_Stop(void);
-
-CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt);
-
-void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address);
-cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void);
-
-void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority);
-uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void);
-
-void SCSI_RX_DMA_COMPLETE_Enable(void);
-uint8 SCSI_RX_DMA_COMPLETE_GetState(void);
-void SCSI_RX_DMA_COMPLETE_Disable(void);
-
-void SCSI_RX_DMA_COMPLETE_SetPending(void);
-void SCSI_RX_DMA_COMPLETE_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */
-#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT)
-
-/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */
-#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG)
-
-/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */
-#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */
-#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */
-#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */
-#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */
-#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_RX_DMA_COMPLETE_Start(void);
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt);
+
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_RX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void);
+void SCSI_RX_DMA_COMPLETE_Disable(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPending(void);
+void SCSI_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */
+#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c

@@ -1,141 +1,141 @@
-/***************************************************************************
-* File Name: SCSI_RX_DMA_dma.c  
-* Version 1.70
-*
-*  Description:
-*   Provides an API for the DMAC component. The API includes functions
-*   for the DMA controller, DMA channels and Transfer Descriptors.
-*
-*
-*   Note:
-*     This module requires the developer to finish or fill in the auto
-*     generated funcions and setup the dma channel and TD's.
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#include <CYLIB.H>
-#include <CYDMAC.H>
-#include <SCSI_RX_DMA_dma.H>
-
-
-
-/****************************************************************************
-* 
-* The following defines are available in Cyfitter.h
-* 
-* 
-* 
-* SCSI_RX_DMA__DRQ_CTL_REG
-* 
-* 
-* SCSI_RX_DMA__DRQ_NUMBER
-* 
-* Number of TD's used by this channel.
-* SCSI_RX_DMA__NUMBEROF_TDS
-* 
-* Priority of this channel.
-* SCSI_RX_DMA__PRIORITY
-* 
-* True if SCSI_RX_DMA_TERMIN_SEL is used.
-* SCSI_RX_DMA__TERMIN_EN
-* 
-* TERMIN interrupt line to signal terminate.
-* SCSI_RX_DMA__TERMIN_SEL
-* 
-* 
-* True if SCSI_RX_DMA_TERMOUT0_SEL is used.
-* SCSI_RX_DMA__TERMOUT0_EN
-* 
-* 
-* TERMOUT0 interrupt line to signal completion.
-* SCSI_RX_DMA__TERMOUT0_SEL
-* 
-* 
-* True if SCSI_RX_DMA_TERMOUT1_SEL is used.
-* SCSI_RX_DMA__TERMOUT1_EN
-* 
-* 
-* TERMOUT1 interrupt line to signal completion.
-* SCSI_RX_DMA__TERMOUT1_SEL
-* 
-****************************************************************************/
-
-
-/* Zero based index of SCSI_RX_DMA dma channel */
-uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
-
-/*********************************************************************
-* Function Name: uint8 SCSI_RX_DMA_DmaInitalize
-**********************************************************************
-* Summary:
-*   Allocates and initialises a channel of the DMAC to be used by the
-*   caller.
-*
-* Parameters:
-*   BurstCount.
-*       
-*       
-*   ReqestPerBurst.
-*       
-*       
-*   UpperSrcAddress.
-*       
-*       
-*   UpperDestAddress.
-*       
-*
-* Return:
-*   The channel that can be used by the caller for DMA activity.
-*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
-*
-*
-*******************************************************************/
-uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
-{
-
-    /* Allocate a DMA channel. */
-    SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER;
-
-    /* Configure the channel. */
-    (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle,
-                                  BurstCount,
-                                  ReqestPerBurst,
-                                  (uint8)SCSI_RX_DMA__TERMOUT0_SEL,
-                                  (uint8)SCSI_RX_DMA__TERMOUT1_SEL,
-                                  (uint8)SCSI_RX_DMA__TERMIN_SEL);
-
-    /* Set the extended address for the transfers */
-    (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
-
-    /* Set the priority for this channel */
-    (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY);
-    
-    return SCSI_RX_DMA_DmaHandle;
-}
-
-/*********************************************************************
-* Function Name: void SCSI_RX_DMA_DmaRelease
-**********************************************************************
-* Summary:
-*   Frees the channel associated with SCSI_RX_DMA.
-*
-*
-* Parameters:
-*   void.
-*
-*
-*
-* Return:
-*   void.
-*
-*******************************************************************/
-void SCSI_RX_DMA_DmaRelease(void) 
-{
-    /* Disable the channel */
-    (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle);
-}
-
+/***************************************************************************
+* File Name: SCSI_RX_DMA_dma.c  
+* Version 1.70
+*
+*  Description:
+*   Provides an API for the DMAC component. The API includes functions
+*   for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+*   Note:
+*     This module requires the developer to finish or fill in the auto
+*     generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+* 
+* The following defines are available in Cyfitter.h
+* 
+* 
+* 
+* SCSI_RX_DMA__DRQ_CTL_REG
+* 
+* 
+* SCSI_RX_DMA__DRQ_NUMBER
+* 
+* Number of TD's used by this channel.
+* SCSI_RX_DMA__NUMBEROF_TDS
+* 
+* Priority of this channel.
+* SCSI_RX_DMA__PRIORITY
+* 
+* True if SCSI_RX_DMA_TERMIN_SEL is used.
+* SCSI_RX_DMA__TERMIN_EN
+* 
+* TERMIN interrupt line to signal terminate.
+* SCSI_RX_DMA__TERMIN_SEL
+* 
+* 
+* True if SCSI_RX_DMA_TERMOUT0_SEL is used.
+* SCSI_RX_DMA__TERMOUT0_EN
+* 
+* 
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT0_SEL
+* 
+* 
+* True if SCSI_RX_DMA_TERMOUT1_SEL is used.
+* SCSI_RX_DMA__TERMOUT1_EN
+* 
+* 
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT1_SEL
+* 
+****************************************************************************/
+
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+*   Allocates and initialises a channel of the DMAC to be used by the
+*   caller.
+*
+* Parameters:
+*   BurstCount.
+*       
+*       
+*   ReqestPerBurst.
+*       
+*       
+*   UpperSrcAddress.
+*       
+*       
+*   UpperDestAddress.
+*       
+*
+* Return:
+*   The channel that can be used by the caller for DMA activity.
+*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
+*
+*
+*******************************************************************/
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
+{
+
+    /* Allocate a DMA channel. */
+    SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER;
+
+    /* Configure the channel. */
+    (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle,
+                                  BurstCount,
+                                  ReqestPerBurst,
+                                  (uint8)SCSI_RX_DMA__TERMOUT0_SEL,
+                                  (uint8)SCSI_RX_DMA__TERMOUT1_SEL,
+                                  (uint8)SCSI_RX_DMA__TERMIN_SEL);
+
+    /* Set the extended address for the transfers */
+    (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+    /* Set the priority for this channel */
+    (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY);
+    
+    return SCSI_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+*   Frees the channel associated with SCSI_RX_DMA.
+*
+*
+* Parameters:
+*   void.
+*
+*
+*
+* Return:
+*   void.
+*
+*******************************************************************/
+void SCSI_RX_DMA_DmaRelease(void) 
+{
+    /* Disable the channel */
+    (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle);
+}
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h

@@ -1,35 +1,35 @@
-/******************************************************************************
-* File Name: SCSI_RX_DMA_dma.h  
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the DMA Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__)
-#define CY_DMA_SCSI_RX_DMA_DMA_H__
-
-
-
-#include <CYDMAC.H>
-#include <CYFITTER.H>
-
-#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
-    (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
-
-/* Zero based index of SCSI_RX_DMA dma channel */
-extern uint8 SCSI_RX_DMA_DmaHandle;
-
-
-uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
-void  SCSI_RX_DMA_DmaRelease(void) ;
-
-
-/* CY_DMA_SCSI_RX_DMA_DMA_H__ */
-#endif
+/******************************************************************************
+* File Name: SCSI_RX_DMA_dma.h  
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__)
+#define CY_DMA_SCSI_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+    (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+extern uint8 SCSI_RX_DMA_DmaHandle;
+
+
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void  SCSI_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_RX_DMA_DMA_H__ */
+#endif

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SCSI_SEL_ISR.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SCSI_SEL_ISR.h>
-
-#if !defined(SCSI_SEL_ISR__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SCSI_SEL_ISR_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_SEL_ISR_Disable();
-
-    /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */
-    SCSI_SEL_ISR_SetVector(&SCSI_SEL_ISR_Interrupt);
-
-    /* Set the priority. */
-    SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_SEL_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_SEL_ISR_Disable();
-
-    /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */
-    SCSI_SEL_ISR_SetVector(address);
-
-    /* Set the priority. */
-    SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_SEL_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_Stop(void)
-{
-    /* Disable this interrupt. */
-    SCSI_SEL_ISR_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SCSI_SEL_ISR_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SCSI_SEL_ISR.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SCSI_SEL_ISR_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SCSI_SEL_ISR_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SCSI_SEL_ISR_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SCSI_SEL_ISR_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_SetPriority(uint8 priority)
-{
-    *SCSI_SEL_ISR_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SCSI_SEL_ISR_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SCSI_SEL_ISR_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SCSI_SEL_ISR_INTC_SET_EN = SCSI_SEL_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SCSI_SEL_ISR_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SCSI_SEL_ISR_INTC_SET_EN & (uint32)SCSI_SEL_ISR__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SCSI_SEL_ISR_INTC_CLR_EN = SCSI_SEL_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_SetPending(void)
-{
-    *SCSI_SEL_ISR_INTC_SET_PD = SCSI_SEL_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_SEL_ISR_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_SEL_ISR_ClearPending(void)
-{
-    *SCSI_SEL_ISR_INTC_CLR_PD = SCSI_SEL_ISR__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_SEL_ISR.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_SEL_ISR.h>
+
+#if !defined(SCSI_SEL_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_SEL_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_SEL_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */
+    SCSI_SEL_ISR_SetVector(&SCSI_SEL_ISR_Interrupt);
+
+    /* Set the priority. */
+    SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_SEL_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_SEL_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */
+    SCSI_SEL_ISR_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_SEL_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_SEL_ISR_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_SEL_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_SEL_ISR.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_SEL_ISR_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_SEL_ISR_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_SEL_ISR_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_SEL_ISR_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_SetPriority(uint8 priority)
+{
+    *SCSI_SEL_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SCSI_SEL_ISR_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_SEL_ISR_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_SEL_ISR_INTC_SET_EN = SCSI_SEL_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_SEL_ISR_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_SEL_ISR_INTC_SET_EN & (uint32)SCSI_SEL_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_SEL_ISR_INTC_CLR_EN = SCSI_SEL_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_SetPending(void)
+{
+    *SCSI_SEL_ISR_INTC_SET_PD = SCSI_SEL_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_SEL_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_SEL_ISR_ClearPending(void)
+{
+    *SCSI_SEL_ISR_INTC_CLR_PD = SCSI_SEL_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SCSI_SEL_ISR.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SCSI_SEL_ISR_H)
-#define CY_ISR_SCSI_SEL_ISR_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SCSI_SEL_ISR_Start(void);
-void SCSI_SEL_ISR_StartEx(cyisraddress address);
-void SCSI_SEL_ISR_Stop(void);
-
-CY_ISR_PROTO(SCSI_SEL_ISR_Interrupt);
-
-void SCSI_SEL_ISR_SetVector(cyisraddress address);
-cyisraddress SCSI_SEL_ISR_GetVector(void);
-
-void SCSI_SEL_ISR_SetPriority(uint8 priority);
-uint8 SCSI_SEL_ISR_GetPriority(void);
-
-void SCSI_SEL_ISR_Enable(void);
-uint8 SCSI_SEL_ISR_GetState(void);
-void SCSI_SEL_ISR_Disable(void);
-
-void SCSI_SEL_ISR_SetPending(void);
-void SCSI_SEL_ISR_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_SEL_ISR ISR. */
-#define SCSI_SEL_ISR_INTC_VECTOR            ((reg32 *) SCSI_SEL_ISR__INTC_VECT)
-
-/* Address of the SCSI_SEL_ISR ISR priority. */
-#define SCSI_SEL_ISR_INTC_PRIOR             ((reg8 *) SCSI_SEL_ISR__INTC_PRIOR_REG)
-
-/* Priority of the SCSI_SEL_ISR interrupt. */
-#define SCSI_SEL_ISR_INTC_PRIOR_NUMBER      SCSI_SEL_ISR__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_SEL_ISR interrupt. */
-#define SCSI_SEL_ISR_INTC_SET_EN            ((reg32 *) SCSI_SEL_ISR__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_SEL_ISR interrupt. */
-#define SCSI_SEL_ISR_INTC_CLR_EN            ((reg32 *) SCSI_SEL_ISR__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SCSI_SEL_ISR interrupt state to pending. */
-#define SCSI_SEL_ISR_INTC_SET_PD            ((reg32 *) SCSI_SEL_ISR__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_SEL_ISR interrupt. */
-#define SCSI_SEL_ISR_INTC_CLR_PD            ((reg32 *) SCSI_SEL_ISR__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SCSI_SEL_ISR_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_SEL_ISR.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_SEL_ISR_H)
+#define CY_ISR_SCSI_SEL_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_SEL_ISR_Start(void);
+void SCSI_SEL_ISR_StartEx(cyisraddress address);
+void SCSI_SEL_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_SEL_ISR_Interrupt);
+
+void SCSI_SEL_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_SEL_ISR_GetVector(void);
+
+void SCSI_SEL_ISR_SetPriority(uint8 priority);
+uint8 SCSI_SEL_ISR_GetPriority(void);
+
+void SCSI_SEL_ISR_Enable(void);
+uint8 SCSI_SEL_ISR_GetState(void);
+void SCSI_SEL_ISR_Disable(void);
+
+void SCSI_SEL_ISR_SetPending(void);
+void SCSI_SEL_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_SEL_ISR ISR. */
+#define SCSI_SEL_ISR_INTC_VECTOR            ((reg32 *) SCSI_SEL_ISR__INTC_VECT)
+
+/* Address of the SCSI_SEL_ISR ISR priority. */
+#define SCSI_SEL_ISR_INTC_PRIOR             ((reg8 *) SCSI_SEL_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_SEL_ISR interrupt. */
+#define SCSI_SEL_ISR_INTC_PRIOR_NUMBER      SCSI_SEL_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_SEL_ISR interrupt. */
+#define SCSI_SEL_ISR_INTC_SET_EN            ((reg32 *) SCSI_SEL_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_SEL_ISR interrupt. */
+#define SCSI_SEL_ISR_INTC_CLR_EN            ((reg32 *) SCSI_SEL_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_SEL_ISR interrupt state to pending. */
+#define SCSI_SEL_ISR_INTC_SET_PD            ((reg32 *) SCSI_SEL_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_SEL_ISR interrupt. */
+#define SCSI_SEL_ISR_INTC_CLR_PD            ((reg32 *) SCSI_SEL_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_SEL_ISR_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SCSI_TX_DMA_COMPLETE.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SCSI_TX_DMA_COMPLETE.h>
-
-#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SCSI_TX_DMA_COMPLETE_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
-    SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt);
-
-    /* Set the priority. */
-    SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_TX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SCSI_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
-    SCSI_TX_DMA_COMPLETE_SetVector(address);
-
-    /* Set the priority. */
-    SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SCSI_TX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_Stop(void)
-{
-    /* Disable this interrupt. */
-    SCSI_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
-{
-    *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_SetPending(void)
-{
-    *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SCSI_TX_DMA_COMPLETE_ClearPending(void)
-{
-    *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_TX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+    SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt);
+
+    /* Set the priority. */
+    SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+    SCSI_TX_DMA_COMPLETE_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+    *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPending(void)
+{
+    *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_ClearPending(void)
+{
+    *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SCSI_TX_DMA_COMPLETE.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
-#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SCSI_TX_DMA_COMPLETE_Start(void);
-void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
-void SCSI_TX_DMA_COMPLETE_Stop(void);
-
-CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
-
-void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
-cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
-
-void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
-uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
-
-void SCSI_TX_DMA_COMPLETE_Enable(void);
-uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
-void SCSI_TX_DMA_COMPLETE_Disable(void);
-
-void SCSI_TX_DMA_COMPLETE_SetPending(void);
-void SCSI_TX_DMA_COMPLETE_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
-#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
-
-/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
-#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
-
-/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
-#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
-#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
-#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
-#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
-#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_TX_DMA_COMPLETE_Start(void);
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
+
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_TX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
+void SCSI_TX_DMA_COMPLETE_Disable(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPending(void);
+void SCSI_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
+#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c

@@ -1,141 +1,141 @@
-/***************************************************************************
-* File Name: SCSI_TX_DMA_dma.c  
-* Version 1.70
-*
-*  Description:
-*   Provides an API for the DMAC component. The API includes functions
-*   for the DMA controller, DMA channels and Transfer Descriptors.
-*
-*
-*   Note:
-*     This module requires the developer to finish or fill in the auto
-*     generated funcions and setup the dma channel and TD's.
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#include <CYLIB.H>
-#include <CYDMAC.H>
-#include <SCSI_TX_DMA_dma.H>
-
-
-
-/****************************************************************************
-* 
-* The following defines are available in Cyfitter.h
-* 
-* 
-* 
-* SCSI_TX_DMA__DRQ_CTL_REG
-* 
-* 
-* SCSI_TX_DMA__DRQ_NUMBER
-* 
-* Number of TD's used by this channel.
-* SCSI_TX_DMA__NUMBEROF_TDS
-* 
-* Priority of this channel.
-* SCSI_TX_DMA__PRIORITY
-* 
-* True if SCSI_TX_DMA_TERMIN_SEL is used.
-* SCSI_TX_DMA__TERMIN_EN
-* 
-* TERMIN interrupt line to signal terminate.
-* SCSI_TX_DMA__TERMIN_SEL
-* 
-* 
-* True if SCSI_TX_DMA_TERMOUT0_SEL is used.
-* SCSI_TX_DMA__TERMOUT0_EN
-* 
-* 
-* TERMOUT0 interrupt line to signal completion.
-* SCSI_TX_DMA__TERMOUT0_SEL
-* 
-* 
-* True if SCSI_TX_DMA_TERMOUT1_SEL is used.
-* SCSI_TX_DMA__TERMOUT1_EN
-* 
-* 
-* TERMOUT1 interrupt line to signal completion.
-* SCSI_TX_DMA__TERMOUT1_SEL
-* 
-****************************************************************************/
-
-
-/* Zero based index of SCSI_TX_DMA dma channel */
-uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
-
-/*********************************************************************
-* Function Name: uint8 SCSI_TX_DMA_DmaInitalize
-**********************************************************************
-* Summary:
-*   Allocates and initialises a channel of the DMAC to be used by the
-*   caller.
-*
-* Parameters:
-*   BurstCount.
-*       
-*       
-*   ReqestPerBurst.
-*       
-*       
-*   UpperSrcAddress.
-*       
-*       
-*   UpperDestAddress.
-*       
-*
-* Return:
-*   The channel that can be used by the caller for DMA activity.
-*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
-*
-*
-*******************************************************************/
-uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
-{
-
-    /* Allocate a DMA channel. */
-    SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER;
-
-    /* Configure the channel. */
-    (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle,
-                                  BurstCount,
-                                  ReqestPerBurst,
-                                  (uint8)SCSI_TX_DMA__TERMOUT0_SEL,
-                                  (uint8)SCSI_TX_DMA__TERMOUT1_SEL,
-                                  (uint8)SCSI_TX_DMA__TERMIN_SEL);
-
-    /* Set the extended address for the transfers */
-    (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
-
-    /* Set the priority for this channel */
-    (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY);
-    
-    return SCSI_TX_DMA_DmaHandle;
-}
-
-/*********************************************************************
-* Function Name: void SCSI_TX_DMA_DmaRelease
-**********************************************************************
-* Summary:
-*   Frees the channel associated with SCSI_TX_DMA.
-*
-*
-* Parameters:
-*   void.
-*
-*
-*
-* Return:
-*   void.
-*
-*******************************************************************/
-void SCSI_TX_DMA_DmaRelease(void) 
-{
-    /* Disable the channel */
-    (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle);
-}
-
+/***************************************************************************
+* File Name: SCSI_TX_DMA_dma.c  
+* Version 1.70
+*
+*  Description:
+*   Provides an API for the DMAC component. The API includes functions
+*   for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+*   Note:
+*     This module requires the developer to finish or fill in the auto
+*     generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+* 
+* The following defines are available in Cyfitter.h
+* 
+* 
+* 
+* SCSI_TX_DMA__DRQ_CTL_REG
+* 
+* 
+* SCSI_TX_DMA__DRQ_NUMBER
+* 
+* Number of TD's used by this channel.
+* SCSI_TX_DMA__NUMBEROF_TDS
+* 
+* Priority of this channel.
+* SCSI_TX_DMA__PRIORITY
+* 
+* True if SCSI_TX_DMA_TERMIN_SEL is used.
+* SCSI_TX_DMA__TERMIN_EN
+* 
+* TERMIN interrupt line to signal terminate.
+* SCSI_TX_DMA__TERMIN_SEL
+* 
+* 
+* True if SCSI_TX_DMA_TERMOUT0_SEL is used.
+* SCSI_TX_DMA__TERMOUT0_EN
+* 
+* 
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT0_SEL
+* 
+* 
+* True if SCSI_TX_DMA_TERMOUT1_SEL is used.
+* SCSI_TX_DMA__TERMOUT1_EN
+* 
+* 
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT1_SEL
+* 
+****************************************************************************/
+
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+*   Allocates and initialises a channel of the DMAC to be used by the
+*   caller.
+*
+* Parameters:
+*   BurstCount.
+*       
+*       
+*   ReqestPerBurst.
+*       
+*       
+*   UpperSrcAddress.
+*       
+*       
+*   UpperDestAddress.
+*       
+*
+* Return:
+*   The channel that can be used by the caller for DMA activity.
+*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
+*
+*
+*******************************************************************/
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
+{
+
+    /* Allocate a DMA channel. */
+    SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER;
+
+    /* Configure the channel. */
+    (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle,
+                                  BurstCount,
+                                  ReqestPerBurst,
+                                  (uint8)SCSI_TX_DMA__TERMOUT0_SEL,
+                                  (uint8)SCSI_TX_DMA__TERMOUT1_SEL,
+                                  (uint8)SCSI_TX_DMA__TERMIN_SEL);
+
+    /* Set the extended address for the transfers */
+    (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+    /* Set the priority for this channel */
+    (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY);
+    
+    return SCSI_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+*   Frees the channel associated with SCSI_TX_DMA.
+*
+*
+* Parameters:
+*   void.
+*
+*
+*
+* Return:
+*   void.
+*
+*******************************************************************/
+void SCSI_TX_DMA_DmaRelease(void) 
+{
+    /* Disable the channel */
+    (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle);
+}
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h

@@ -1,35 +1,35 @@
-/******************************************************************************
-* File Name: SCSI_TX_DMA_dma.h  
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the DMA Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__)
-#define CY_DMA_SCSI_TX_DMA_DMA_H__
-
-
-
-#include <CYDMAC.H>
-#include <CYFITTER.H>
-
-#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
-    (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
-
-/* Zero based index of SCSI_TX_DMA dma channel */
-extern uint8 SCSI_TX_DMA_DmaHandle;
-
-
-uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
-void  SCSI_TX_DMA_DmaRelease(void) ;
-
-
-/* CY_DMA_SCSI_TX_DMA_DMA_H__ */
-#endif
+/******************************************************************************
+* File Name: SCSI_TX_DMA_dma.h  
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__)
+#define CY_DMA_SCSI_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+    (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+extern uint8 SCSI_TX_DMA_DmaHandle;
+
+
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void  SCSI_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_TX_DMA_DMA_H__ */
+#endif

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c

@@ -1,1154 +1,1154 @@
-/*******************************************************************************
-* File Name: SDCard.c
-* Version 2.50
-*
-* Description:
-*  This file provides all API functionality of the SPI Master component.
-*
-* Note:
-*  None.
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SDCard_PVT.h"
-
-#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
-    volatile uint8 SDCard_txBufferFull;
-    volatile uint8 SDCard_txBufferRead;
-    volatile uint8 SDCard_txBufferWrite;
-#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
-    volatile uint8 SDCard_rxBufferFull;
-    volatile uint8 SDCard_rxBufferRead;
-    volatile uint8 SDCard_rxBufferWrite;
-#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-uint8 SDCard_initVar = 0u;
-
-volatile uint8 SDCard_swStatusTx;
-volatile uint8 SDCard_swStatusRx;
-
-
-/*******************************************************************************
-* Function Name: SDCard_Init
-********************************************************************************
-*
-* Summary:
-*  Inits/Restores default SPIM configuration provided with customizer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  When this function is called it initializes all of the necessary parameters
-*  for execution. i.e. setting the initial interrupt mask, configuring the
-*  interrupt service routine, configuring the bit-counter parameters and
-*  clearing the FIFO and Status Register.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_Init(void) 
-{
-    /* Initialize the Bit counter */
-    SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT;
-
-    /* Init TX ISR  */
-    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
-        CyIntDisable         (SDCard_TX_ISR_NUMBER);
-        CyIntSetPriority     (SDCard_TX_ISR_NUMBER,  SDCard_TX_ISR_PRIORITY);
-        (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR);
-    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
-
-    /* Init RX ISR  */
-    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
-        CyIntDisable         (SDCard_RX_ISR_NUMBER);
-        CyIntSetPriority     (SDCard_RX_ISR_NUMBER,  SDCard_RX_ISR_PRIORITY);
-        (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR);
-    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
-
-    /* Clear any stray data from the RX and TX FIFO */
-    SDCard_ClearFIFO();
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-        SDCard_rxBufferFull  = 0u;
-        SDCard_rxBufferRead  = 0u;
-        SDCard_rxBufferWrite = 0u;
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        SDCard_txBufferFull  = 0u;
-        SDCard_txBufferRead  = 0u;
-        SDCard_txBufferWrite = 0u;
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */
-    (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */
-
-    /* Configure TX and RX interrupt mask */
-    SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK;
-    SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_Enable
-********************************************************************************
-*
-* Summary:
-*  Enable SPIM component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SDCard_Enable(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE;
-    SDCard_TX_STATUS_ACTL_REG  |= SDCard_INT_ENABLE;
-    SDCard_RX_STATUS_ACTL_REG  |= SDCard_INT_ENABLE;
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(0u != SDCard_INTERNAL_CLOCK)
-        SDCard_IntClock_Enable();
-    #endif /* (0u != SDCard_INTERNAL_CLOCK) */
-
-    SDCard_EnableTxInt();
-    SDCard_EnableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_Start
-********************************************************************************
-*
-* Summary:
-*  Initialize and Enable the SPI Master component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_initVar - used to check initial configuration, modified on
-*  first function call.
-*
-* Theory:
-*  Enable the clock input to enable operation.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_Start(void) 
-{
-    if(0u == SDCard_initVar)
-    {
-        SDCard_Init();
-        SDCard_initVar = 1u;
-    }
-
-    SDCard_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_Stop
-********************************************************************************
-*
-* Summary:
-*  Disable the SPI Master component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the clock input to enable operation.
-*
-*******************************************************************************/
-void SDCard_Stop(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);
-    SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(0u != SDCard_INTERNAL_CLOCK)
-        SDCard_IntClock_Disable();
-    #endif /* (0u != SDCard_INTERNAL_CLOCK) */
-
-    SDCard_DisableTxInt();
-    SDCard_DisableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_EnableTxInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal Tx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal Tx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_EnableTxInt(void) 
-{
-    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
-        CyIntEnable(SDCard_TX_ISR_NUMBER);
-    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_EnableRxInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal Rx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal Rx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_EnableRxInt(void) 
-{
-    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
-        CyIntEnable(SDCard_RX_ISR_NUMBER);
-    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_DisableTxInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal Tx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal Tx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_DisableTxInt(void) 
-{
-    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
-        CyIntDisable(SDCard_TX_ISR_NUMBER);
-    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_DisableRxInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal Rx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal Rx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_DisableRxInt(void) 
-{
-    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
-        CyIntDisable(SDCard_RX_ISR_NUMBER);
-    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_SetTxInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SDCard_SetTxInterruptMode(uint8 intSrc) 
-{
-    SDCard_TX_STATUS_MASK_REG = intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_SetRxInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SDCard_SetRxInterruptMode(uint8 intSrc) 
-{
-    SDCard_RX_STATUS_MASK_REG  = intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ReadTxStatus
-********************************************************************************
-*
-* Summary:
-*  Read the Tx status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the Tx status register.
-*
-* Global variables:
-*  SDCard_swStatusTx - used to store in software status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the Tx status register for error
-*  detection and flow control.
-*
-* Side Effects:
-*  Clear Tx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SDCard_ReadTxStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SDCard_DisableTxInt();
-
-        tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
-        SDCard_swStatusTx = 0u;
-
-        SDCard_EnableTxInt();
-
-    #else
-
-        tmpStatus = SDCard_TX_STATUS_REG;
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ReadRxStatus
-********************************************************************************
-*
-* Summary:
-*  Read the Rx status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the Rx status register.
-*
-* Global variables:
-*  SDCard_swStatusRx - used to store in software Rx status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the Rx status register for error
-*  detection and flow control.
-*
-* Side Effects:
-*  Clear Rx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SDCard_ReadRxStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-        /* Disable RX interrupt to protect global veriables */
-        SDCard_DisableRxInt();
-
-        tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
-        SDCard_swStatusRx = 0u;
-
-        SDCard_EnableRxInt();
-
-    #else
-
-        tmpStatus = SDCard_RX_STATUS_REG;
-
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_WriteTxData
-********************************************************************************
-*
-* Summary:
-*  Write a byte of data to be sent across the SPI.
-*
-* Parameters:
-*  txDataByte: The data value to send across the SPI.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer, modified every function
-*  call if TX Software Buffer is used.
-*  SDCard_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer.
-*  SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store
-*  data to sending, modified every function call if TX Software Buffer is used.
-*
-* Theory:
-*  Allows the user to transmit any byte of data in a single transfer.
-*
-* Side Effects:
-*  If this function is called again before the previous byte is finished then
-*  the next byte will be appended to the transfer with no time between
-*  the byte transfers. Clear Tx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_WriteTxData(uint8 txData) 
-{
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-
-        uint8 tempStatus;
-        uint8 tmpTxBufferRead;
-
-        /* Block if TX buffer is FULL: don't overwrite */
-        do
-        {
-            tmpTxBufferRead = SDCard_txBufferRead;
-            if(0u == tmpTxBufferRead)
-            {
-                tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u);
-            }
-            else
-            {
-                tmpTxBufferRead--;
-            }
-
-        }while(tmpTxBufferRead == SDCard_txBufferWrite);
-
-        /* Disable TX interrupt to protect global veriables */
-        SDCard_DisableTxInt();
-
-        tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
-        SDCard_swStatusTx = tempStatus;
-
-
-        if((SDCard_txBufferRead == SDCard_txBufferWrite) &&
-           (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))
-        {
-            /* Put data element into the TX FIFO */
-            CY_SET_REG8(SDCard_TXDATA_PTR, txData);
-        }
-        else
-        {
-            /* Add to the TX software buffer */
-            SDCard_txBufferWrite++;
-            if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE)
-            {
-                SDCard_txBufferWrite = 0u;
-            }
-
-            if(SDCard_txBufferWrite == SDCard_txBufferRead)
-            {
-                SDCard_txBufferRead++;
-                if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)
-                {
-                    SDCard_txBufferRead = 0u;
-                }
-                SDCard_txBufferFull = 1u;
-            }
-
-            SDCard_txBuffer[SDCard_txBufferWrite] = txData;
-
-            SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL;
-        }
-
-        SDCard_EnableTxInt();
-
-    #else
-        /* Wait until TX FIFO has a place */
-        while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))
-        {
-        }
-
-        /* Put data element into the TX FIFO */
-        CY_SET_REG8(SDCard_TXDATA_PTR, txData);
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ReadRxData
-********************************************************************************
-*
-* Summary:
-*  Read the next byte of data received across the SPI.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The next byte of data read from the FIFO.
-*
-* Global variables:
-*  SDCard_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer.
-*  SDCard_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified every function
-*  call if RX Software Buffer is used.
-*  SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store
-*  received data.
-*
-* Theory:
-*  Allows the user to read a byte of data received.
-*
-* Side Effects:
-*  Will return invalid data if the FIFO is empty. The user should Call
-*  GetRxBufferSize() and if it returns a non-zero value then it is safe to call
-*  ReadByte() function.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SDCard_ReadRxData(void) 
-{
-    uint8 rxData;
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-
-        /* Disable RX interrupt to protect global veriables */
-        SDCard_DisableRxInt();
-
-        if(SDCard_rxBufferRead != SDCard_rxBufferWrite)
-        {
-            if(0u == SDCard_rxBufferFull)
-            {
-                SDCard_rxBufferRead++;
-                if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)
-                {
-                    SDCard_rxBufferRead = 0u;
-                }
-            }
-            else
-            {
-                SDCard_rxBufferFull = 0u;
-            }
-        }
-
-        rxData = SDCard_rxBuffer[SDCard_rxBufferRead];
-
-        SDCard_EnableRxInt();
-
-    #else
-
-        rxData = CY_GET_REG8(SDCard_RXDATA_PTR);
-
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(rxData);
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_GetRxBufferSize
-********************************************************************************
-*
-* Summary:
-*  Returns the number of bytes/words of data currently held in the RX buffer.
-*  If RX Software Buffer not used then function return 0 if FIFO empty or 1 if
-*  FIFO not empty. In another case function return size of RX Software Buffer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Integer count of the number of bytes/words in the RX buffer.
-*
-* Global variables:
-*  SDCard_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer.
-*  SDCard_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-uint8 SDCard_GetRxBufferSize(void) 
-{
-    uint8 size;
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-
-        /* Disable RX interrupt to protect global veriables */
-        SDCard_DisableRxInt();
-
-        if(SDCard_rxBufferRead == SDCard_rxBufferWrite)
-        {
-            size = 0u;
-        }
-        else if(SDCard_rxBufferRead < SDCard_rxBufferWrite)
-        {
-            size = (SDCard_rxBufferWrite - SDCard_rxBufferRead);
-        }
-        else
-        {
-            size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite;
-        }
-
-        SDCard_EnableRxInt();
-
-    #else
-
-        /* We can only know if there is data in the RX FIFO */
-        size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(size);
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_GetTxBufferSize
-********************************************************************************
-*
-* Summary:
-*  Returns the number of bytes/words of data currently held in the TX buffer.
-*  If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if
-*  FIFO not full, 4 - if FIFO full. In another case function return size of TX
-*  Software Buffer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Integer count of the number of bytes/words in the TX buffer.
-*
-* Global variables:
-*  SDCard_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer.
-*  SDCard_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-uint8  SDCard_GetTxBufferSize(void) 
-{
-    uint8 size;
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SDCard_DisableTxInt();
-
-        if(SDCard_txBufferRead == SDCard_txBufferWrite)
-        {
-            size = 0u;
-        }
-        else if(SDCard_txBufferRead < SDCard_txBufferWrite)
-        {
-            size = (SDCard_txBufferWrite - SDCard_txBufferRead);
-        }
-        else
-        {
-            size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite;
-        }
-
-        SDCard_EnableTxInt();
-
-    #else
-
-        size = SDCard_TX_STATUS_REG;
-
-        if(0u != (size & SDCard_STS_TX_FIFO_EMPTY))
-        {
-            size = 0u;
-        }
-        else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL))
-        {
-            size = 1u;
-        }
-        else
-        {
-            size = SDCard_FIFO_SIZE;
-        }
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(size);
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ClearRxBuffer
-********************************************************************************
-*
-* Summary:
-*  Clear the RX RAM buffer by setting the read and write pointers both to zero.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer, modified every function
-*  call - resets to zero.
-*  SDCard_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified every function call -
-*  resets to zero.
-*
-* Theory:
-*  Setting the pointers to zero makes the system believe there is no data to
-*  read and writing will resume at address 0 overwriting any data that may have
-*  remained in the RAM.
-*
-* Side Effects:
-*  Any received data not read from the RAM buffer will be lost when overwritten.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_ClearRxBuffer(void) 
-{
-    /* Clear Hardware RX FIFO */
-    while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))
-    {
-        (void) CY_GET_REG8(SDCard_RXDATA_PTR);
-    }
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-        /* Disable RX interrupt to protect global veriables */
-        SDCard_DisableRxInt();
-
-        SDCard_rxBufferFull  = 0u;
-        SDCard_rxBufferRead  = 0u;
-        SDCard_rxBufferWrite = 0u;
-
-        SDCard_EnableRxInt();
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ClearTxBuffer
-********************************************************************************
-*
-* Summary:
-*  Clear the TX RAM buffer by setting the read and write pointers both to zero.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer, modified every function
-*  call - resets to zero.
-*  SDCard_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer, modified every function call -
-*  resets to zero.
-*
-* Theory:
-*  Setting the pointers to zero makes the system believe there is no data to
-*  read and writing will resume at address 0 overwriting any data that may have
-*  remained in the RAM.
-*
-* Side Effects:
-*  Any data not yet transmitted from the RAM buffer will be lost when
-*  overwritten.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_ClearTxBuffer(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    /* Clear TX FIFO */
-    SDCard_AUX_CONTROL_DP0_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
-    SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
-
-    #if(SDCard_USE_SECOND_DATAPATH)
-        /* Clear TX FIFO for 2nd Datapath */
-        SDCard_AUX_CONTROL_DP1_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
-        SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
-    #endif /* (SDCard_USE_SECOND_DATAPATH) */
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SDCard_DisableTxInt();
-
-        SDCard_txBufferFull  = 0u;
-        SDCard_txBufferRead  = 0u;
-        SDCard_txBufferWrite = 0u;
-
-        /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */
-        SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);
-
-        SDCard_EnableTxInt();
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-#if(0u != SDCard_BIDIRECTIONAL_MODE)
-    /*******************************************************************************
-    * Function Name: SDCard_TxEnable
-    ********************************************************************************
-    *
-    * Summary:
-    *  If the SPI master is configured to use a single bi-directional pin then this
-    *  will set the bi-directional pin to transmit.
-    *
-    * Parameters:
-    *  None.
-    *
-    * Return:
-    *  None.
-    *
-    *******************************************************************************/
-    void SDCard_TxEnable(void) 
-    {
-        SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: SDCard_TxDisable
-    ********************************************************************************
-    *
-    * Summary:
-    *  If the SPI master is configured to use a single bi-directional pin then this
-    *  will set the bi-directional pin to receive.
-    *
-    * Parameters:
-    *  None.
-    *
-    * Return:
-    *  None.
-    *
-    *******************************************************************************/
-    void SDCard_TxDisable(void) 
-    {
-        SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN);
-    }
-
-#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */
-
-
-/*******************************************************************************
-* Function Name: SDCard_PutArray
-********************************************************************************
-*
-* Summary:
-*  Write available data from ROM/RAM to the TX buffer while space is available
-*  in the TX buffer. Keep trying until all data is passed to the TX buffer.
-*
-* Parameters:
-*  *buffer: Pointer to the location in RAM containing the data to send
-*  byteCount: The number of bytes to move to the transmit buffer.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  Will stay in this routine until all data has been sent.  May get locked in
-*  this loop if data is not being initiated by the master if there is not
-*  enough room in the TX FIFO.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_PutArray(const uint8 buffer[], uint8 byteCount)
-                                                                          
-{
-    uint8 bufIndex;
-
-    bufIndex = 0u;
-
-    while(byteCount > 0u)
-    {
-        SDCard_WriteTxData(buffer[bufIndex]);
-        bufIndex++;
-        byteCount--;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ClearFIFO
-********************************************************************************
-*
-* Summary:
-*  Clear the RX and TX FIFO's of all data for a fresh start.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-void SDCard_ClearFIFO(void) 
-{
-    uint8 enableInterrupts;
-
-    /* Clear Hardware RX FIFO */
-    while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))
-    {
-        (void) CY_GET_REG8(SDCard_RXDATA_PTR);
-    }
-
-    enableInterrupts = CyEnterCriticalSection();
-    /* Clear TX FIFO */
-    SDCard_AUX_CONTROL_DP0_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
-    SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
-
-    #if(SDCard_USE_SECOND_DATAPATH)
-        /* Clear TX FIFO for 2nd Datapath */
-        SDCard_AUX_CONTROL_DP1_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
-        SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
-    #endif /* (SDCard_USE_SECOND_DATAPATH) */
-    CyExitCriticalSection(enableInterrupts);
-}
-
-
-/* Following functions are for version Compatibility, they are obsolete.
-*  Please do not use it in new projects.
-*/
-
-
-/*******************************************************************************
-* Function Name: SDCard_EnableInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_EnableInt(void) 
-{
-    SDCard_EnableRxInt();
-    SDCard_EnableTxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_DisableInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SDCard_DisableInt(void) 
-{
-    SDCard_DisableTxInt();
-    SDCard_DisableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_SetInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SDCard_SetInterruptMode(uint8 intSrc) 
-{
-    SDCard_TX_STATUS_MASK_REG  = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE));
-    SDCard_RX_STATUS_MASK_REG  =  intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_ReadStatus
-********************************************************************************
-*
-* Summary:
-*  Read the status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the status register.
-*
-* Global variables:
-*  SDCard_swStatus - used to store in software status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the status register for error detection
-*  and flow control.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SDCard_ReadStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED)
-
-        SDCard_DisableInt();
-
-        tmpStatus  = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
-        tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx);
-        tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);
-
-        SDCard_swStatusTx = 0u;
-        SDCard_swStatusRx = 0u;
-
-        SDCard_EnableInt();
-
-    #else
-
-        tmpStatus  = SDCard_RX_STATUS_REG;
-        tmpStatus |= SDCard_TX_STATUS_REG;
-        tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SDCard.c
+* Version 2.50
+*
+* Description:
+*  This file provides all API functionality of the SPI Master component.
+*
+* Note:
+*  None.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SDCard_PVT.h"
+
+#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+    volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
+    volatile uint8 SDCard_txBufferFull;
+    volatile uint8 SDCard_txBufferRead;
+    volatile uint8 SDCard_txBufferWrite;
+#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+    volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
+    volatile uint8 SDCard_rxBufferFull;
+    volatile uint8 SDCard_rxBufferRead;
+    volatile uint8 SDCard_rxBufferWrite;
+#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+uint8 SDCard_initVar = 0u;
+
+volatile uint8 SDCard_swStatusTx;
+volatile uint8 SDCard_swStatusRx;
+
+
+/*******************************************************************************
+* Function Name: SDCard_Init
+********************************************************************************
+*
+* Summary:
+*  Inits/Restores default SPIM configuration provided with customizer.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Side Effects:
+*  When this function is called it initializes all of the necessary parameters
+*  for execution. i.e. setting the initial interrupt mask, configuring the
+*  interrupt service routine, configuring the bit-counter parameters and
+*  clearing the FIFO and Status Register.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_Init(void) 
+{
+    /* Initialize the Bit counter */
+    SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT;
+
+    /* Init TX ISR  */
+    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
+        CyIntDisable         (SDCard_TX_ISR_NUMBER);
+        CyIntSetPriority     (SDCard_TX_ISR_NUMBER,  SDCard_TX_ISR_PRIORITY);
+        (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR);
+    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
+
+    /* Init RX ISR  */
+    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
+        CyIntDisable         (SDCard_RX_ISR_NUMBER);
+        CyIntSetPriority     (SDCard_RX_ISR_NUMBER,  SDCard_RX_ISR_PRIORITY);
+        (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR);
+    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
+
+    /* Clear any stray data from the RX and TX FIFO */
+    SDCard_ClearFIFO();
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+        SDCard_rxBufferFull  = 0u;
+        SDCard_rxBufferRead  = 0u;
+        SDCard_rxBufferWrite = 0u;
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        SDCard_txBufferFull  = 0u;
+        SDCard_txBufferRead  = 0u;
+        SDCard_txBufferWrite = 0u;
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */
+    (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */
+
+    /* Configure TX and RX interrupt mask */
+    SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK;
+    SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_Enable
+********************************************************************************
+*
+* Summary:
+*  Enable SPIM component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SDCard_Enable(void) 
+{
+    uint8 enableInterrupts;
+
+    enableInterrupts = CyEnterCriticalSection();
+    SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE;
+    SDCard_TX_STATUS_ACTL_REG  |= SDCard_INT_ENABLE;
+    SDCard_RX_STATUS_ACTL_REG  |= SDCard_INT_ENABLE;
+    CyExitCriticalSection(enableInterrupts);
+
+    #if(0u != SDCard_INTERNAL_CLOCK)
+        SDCard_IntClock_Enable();
+    #endif /* (0u != SDCard_INTERNAL_CLOCK) */
+
+    SDCard_EnableTxInt();
+    SDCard_EnableRxInt();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_Start
+********************************************************************************
+*
+* Summary:
+*  Initialize and Enable the SPI Master component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_initVar - used to check initial configuration, modified on
+*  first function call.
+*
+* Theory:
+*  Enable the clock input to enable operation.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_Start(void) 
+{
+    if(0u == SDCard_initVar)
+    {
+        SDCard_Init();
+        SDCard_initVar = 1u;
+    }
+
+    SDCard_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_Stop
+********************************************************************************
+*
+* Summary:
+*  Disable the SPI Master component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Disable the clock input to enable operation.
+*
+*******************************************************************************/
+void SDCard_Stop(void) 
+{
+    uint8 enableInterrupts;
+
+    enableInterrupts = CyEnterCriticalSection();
+    SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);
+    SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);
+    CyExitCriticalSection(enableInterrupts);
+
+    #if(0u != SDCard_INTERNAL_CLOCK)
+        SDCard_IntClock_Disable();
+    #endif /* (0u != SDCard_INTERNAL_CLOCK) */
+
+    SDCard_DisableTxInt();
+    SDCard_DisableRxInt();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_EnableTxInt
+********************************************************************************
+*
+* Summary:
+*  Enable internal Tx interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enable the internal Tx interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_EnableTxInt(void) 
+{
+    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
+        CyIntEnable(SDCard_TX_ISR_NUMBER);
+    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_EnableRxInt
+********************************************************************************
+*
+* Summary:
+*  Enable internal Rx interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enable the internal Rx interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_EnableRxInt(void) 
+{
+    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
+        CyIntEnable(SDCard_RX_ISR_NUMBER);
+    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_DisableTxInt
+********************************************************************************
+*
+* Summary:
+*  Disable internal Tx interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Disable the internal Tx interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_DisableTxInt(void) 
+{
+    #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)
+        CyIntDisable(SDCard_TX_ISR_NUMBER);
+    #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_DisableRxInt
+********************************************************************************
+*
+* Summary:
+*  Disable internal Rx interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Disable the internal Rx interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_DisableRxInt(void) 
+{
+    #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)
+        CyIntDisable(SDCard_RX_ISR_NUMBER);
+    #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_SetTxInterruptMode
+********************************************************************************
+*
+* Summary:
+*  Configure which status bits trigger an interrupt event.
+*
+* Parameters:
+*  intSrc: An or'd combination of the desired status bit masks (defined in the
+*  header file).
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enables the output of specific status bits to the interrupt controller.
+*
+*******************************************************************************/
+void SDCard_SetTxInterruptMode(uint8 intSrc) 
+{
+    SDCard_TX_STATUS_MASK_REG = intSrc;
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_SetRxInterruptMode
+********************************************************************************
+*
+* Summary:
+*  Configure which status bits trigger an interrupt event.
+*
+* Parameters:
+*  intSrc: An or'd combination of the desired status bit masks (defined in the
+*  header file).
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enables the output of specific status bits to the interrupt controller.
+*
+*******************************************************************************/
+void SDCard_SetRxInterruptMode(uint8 intSrc) 
+{
+    SDCard_RX_STATUS_MASK_REG  = intSrc;
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ReadTxStatus
+********************************************************************************
+*
+* Summary:
+*  Read the Tx status register for the component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Contents of the Tx status register.
+*
+* Global variables:
+*  SDCard_swStatusTx - used to store in software status register,
+*  modified every function call - resets to zero.
+*
+* Theory:
+*  Allows the user and the API to read the Tx status register for error
+*  detection and flow control.
+*
+* Side Effects:
+*  Clear Tx status register of the component.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+uint8 SDCard_ReadTxStatus(void) 
+{
+    uint8 tmpStatus;
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        /* Disable TX interrupt to protect global veriables */
+        SDCard_DisableTxInt();
+
+        tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
+        SDCard_swStatusTx = 0u;
+
+        SDCard_EnableTxInt();
+
+    #else
+
+        tmpStatus = SDCard_TX_STATUS_REG;
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    return(tmpStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ReadRxStatus
+********************************************************************************
+*
+* Summary:
+*  Read the Rx status register for the component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Contents of the Rx status register.
+*
+* Global variables:
+*  SDCard_swStatusRx - used to store in software Rx status register,
+*  modified every function call - resets to zero.
+*
+* Theory:
+*  Allows the user and the API to read the Rx status register for error
+*  detection and flow control.
+*
+* Side Effects:
+*  Clear Rx status register of the component.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+uint8 SDCard_ReadRxStatus(void) 
+{
+    uint8 tmpStatus;
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+        /* Disable RX interrupt to protect global veriables */
+        SDCard_DisableRxInt();
+
+        tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
+        SDCard_swStatusRx = 0u;
+
+        SDCard_EnableRxInt();
+
+    #else
+
+        tmpStatus = SDCard_RX_STATUS_REG;
+
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    return(tmpStatus);
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_WriteTxData
+********************************************************************************
+*
+* Summary:
+*  Write a byte of data to be sent across the SPI.
+*
+* Parameters:
+*  txDataByte: The data value to send across the SPI.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_txBufferWrite - used for the account of the bytes which
+*  have been written down in the TX software buffer, modified every function
+*  call if TX Software Buffer is used.
+*  SDCard_txBufferRead - used for the account of the bytes which
+*  have been read from the TX software buffer.
+*  SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store
+*  data to sending, modified every function call if TX Software Buffer is used.
+*
+* Theory:
+*  Allows the user to transmit any byte of data in a single transfer.
+*
+* Side Effects:
+*  If this function is called again before the previous byte is finished then
+*  the next byte will be appended to the transfer with no time between
+*  the byte transfers. Clear Tx status register of the component.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_WriteTxData(uint8 txData) 
+{
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+
+        uint8 tempStatus;
+        uint8 tmpTxBufferRead;
+
+        /* Block if TX buffer is FULL: don't overwrite */
+        do
+        {
+            tmpTxBufferRead = SDCard_txBufferRead;
+            if(0u == tmpTxBufferRead)
+            {
+                tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u);
+            }
+            else
+            {
+                tmpTxBufferRead--;
+            }
+
+        }while(tmpTxBufferRead == SDCard_txBufferWrite);
+
+        /* Disable TX interrupt to protect global veriables */
+        SDCard_DisableTxInt();
+
+        tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
+        SDCard_swStatusTx = tempStatus;
+
+
+        if((SDCard_txBufferRead == SDCard_txBufferWrite) &&
+           (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))
+        {
+            /* Put data element into the TX FIFO */
+            CY_SET_REG8(SDCard_TXDATA_PTR, txData);
+        }
+        else
+        {
+            /* Add to the TX software buffer */
+            SDCard_txBufferWrite++;
+            if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE)
+            {
+                SDCard_txBufferWrite = 0u;
+            }
+
+            if(SDCard_txBufferWrite == SDCard_txBufferRead)
+            {
+                SDCard_txBufferRead++;
+                if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)
+                {
+                    SDCard_txBufferRead = 0u;
+                }
+                SDCard_txBufferFull = 1u;
+            }
+
+            SDCard_txBuffer[SDCard_txBufferWrite] = txData;
+
+            SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL;
+        }
+
+        SDCard_EnableTxInt();
+
+    #else
+        /* Wait until TX FIFO has a place */
+        while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))
+        {
+        }
+
+        /* Put data element into the TX FIFO */
+        CY_SET_REG8(SDCard_TXDATA_PTR, txData);
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ReadRxData
+********************************************************************************
+*
+* Summary:
+*  Read the next byte of data received across the SPI.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  The next byte of data read from the FIFO.
+*
+* Global variables:
+*  SDCard_rxBufferWrite - used for the account of the bytes which
+*  have been written down in the RX software buffer.
+*  SDCard_rxBufferRead - used for the account of the bytes which
+*  have been read from the RX software buffer, modified every function
+*  call if RX Software Buffer is used.
+*  SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store
+*  received data.
+*
+* Theory:
+*  Allows the user to read a byte of data received.
+*
+* Side Effects:
+*  Will return invalid data if the FIFO is empty. The user should Call
+*  GetRxBufferSize() and if it returns a non-zero value then it is safe to call
+*  ReadByte() function.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+uint8 SDCard_ReadRxData(void) 
+{
+    uint8 rxData;
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+
+        /* Disable RX interrupt to protect global veriables */
+        SDCard_DisableRxInt();
+
+        if(SDCard_rxBufferRead != SDCard_rxBufferWrite)
+        {
+            if(0u == SDCard_rxBufferFull)
+            {
+                SDCard_rxBufferRead++;
+                if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)
+                {
+                    SDCard_rxBufferRead = 0u;
+                }
+            }
+            else
+            {
+                SDCard_rxBufferFull = 0u;
+            }
+        }
+
+        rxData = SDCard_rxBuffer[SDCard_rxBufferRead];
+
+        SDCard_EnableRxInt();
+
+    #else
+
+        rxData = CY_GET_REG8(SDCard_RXDATA_PTR);
+
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    return(rxData);
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_GetRxBufferSize
+********************************************************************************
+*
+* Summary:
+*  Returns the number of bytes/words of data currently held in the RX buffer.
+*  If RX Software Buffer not used then function return 0 if FIFO empty or 1 if
+*  FIFO not empty. In another case function return size of RX Software Buffer.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Integer count of the number of bytes/words in the RX buffer.
+*
+* Global variables:
+*  SDCard_rxBufferWrite - used for the account of the bytes which
+*  have been written down in the RX software buffer.
+*  SDCard_rxBufferRead - used for the account of the bytes which
+*  have been read from the RX software buffer.
+*
+* Side Effects:
+*  Clear status register of the component.
+*
+*******************************************************************************/
+uint8 SDCard_GetRxBufferSize(void) 
+{
+    uint8 size;
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+
+        /* Disable RX interrupt to protect global veriables */
+        SDCard_DisableRxInt();
+
+        if(SDCard_rxBufferRead == SDCard_rxBufferWrite)
+        {
+            size = 0u;
+        }
+        else if(SDCard_rxBufferRead < SDCard_rxBufferWrite)
+        {
+            size = (SDCard_rxBufferWrite - SDCard_rxBufferRead);
+        }
+        else
+        {
+            size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite;
+        }
+
+        SDCard_EnableRxInt();
+
+    #else
+
+        /* We can only know if there is data in the RX FIFO */
+        size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    return(size);
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_GetTxBufferSize
+********************************************************************************
+*
+* Summary:
+*  Returns the number of bytes/words of data currently held in the TX buffer.
+*  If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if
+*  FIFO not full, 4 - if FIFO full. In another case function return size of TX
+*  Software Buffer.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Integer count of the number of bytes/words in the TX buffer.
+*
+* Global variables:
+*  SDCard_txBufferWrite - used for the account of the bytes which
+*  have been written down in the TX software buffer.
+*  SDCard_txBufferRead - used for the account of the bytes which
+*  have been read from the TX software buffer.
+*
+* Side Effects:
+*  Clear status register of the component.
+*
+*******************************************************************************/
+uint8  SDCard_GetTxBufferSize(void) 
+{
+    uint8 size;
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        /* Disable TX interrupt to protect global veriables */
+        SDCard_DisableTxInt();
+
+        if(SDCard_txBufferRead == SDCard_txBufferWrite)
+        {
+            size = 0u;
+        }
+        else if(SDCard_txBufferRead < SDCard_txBufferWrite)
+        {
+            size = (SDCard_txBufferWrite - SDCard_txBufferRead);
+        }
+        else
+        {
+            size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite;
+        }
+
+        SDCard_EnableTxInt();
+
+    #else
+
+        size = SDCard_TX_STATUS_REG;
+
+        if(0u != (size & SDCard_STS_TX_FIFO_EMPTY))
+        {
+            size = 0u;
+        }
+        else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL))
+        {
+            size = 1u;
+        }
+        else
+        {
+            size = SDCard_FIFO_SIZE;
+        }
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    return(size);
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ClearRxBuffer
+********************************************************************************
+*
+* Summary:
+*  Clear the RX RAM buffer by setting the read and write pointers both to zero.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_rxBufferWrite - used for the account of the bytes which
+*  have been written down in the RX software buffer, modified every function
+*  call - resets to zero.
+*  SDCard_rxBufferRead - used for the account of the bytes which
+*  have been read from the RX software buffer, modified every function call -
+*  resets to zero.
+*
+* Theory:
+*  Setting the pointers to zero makes the system believe there is no data to
+*  read and writing will resume at address 0 overwriting any data that may have
+*  remained in the RAM.
+*
+* Side Effects:
+*  Any received data not read from the RAM buffer will be lost when overwritten.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_ClearRxBuffer(void) 
+{
+    /* Clear Hardware RX FIFO */
+    while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))
+    {
+        (void) CY_GET_REG8(SDCard_RXDATA_PTR);
+    }
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+        /* Disable RX interrupt to protect global veriables */
+        SDCard_DisableRxInt();
+
+        SDCard_rxBufferFull  = 0u;
+        SDCard_rxBufferRead  = 0u;
+        SDCard_rxBufferWrite = 0u;
+
+        SDCard_EnableRxInt();
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ClearTxBuffer
+********************************************************************************
+*
+* Summary:
+*  Clear the TX RAM buffer by setting the read and write pointers both to zero.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_txBufferWrite - used for the account of the bytes which
+*  have been written down in the TX software buffer, modified every function
+*  call - resets to zero.
+*  SDCard_txBufferRead - used for the account of the bytes which
+*  have been read from the TX software buffer, modified every function call -
+*  resets to zero.
+*
+* Theory:
+*  Setting the pointers to zero makes the system believe there is no data to
+*  read and writing will resume at address 0 overwriting any data that may have
+*  remained in the RAM.
+*
+* Side Effects:
+*  Any data not yet transmitted from the RAM buffer will be lost when
+*  overwritten.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_ClearTxBuffer(void) 
+{
+    uint8 enableInterrupts;
+
+    enableInterrupts = CyEnterCriticalSection();
+    /* Clear TX FIFO */
+    SDCard_AUX_CONTROL_DP0_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
+    SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
+
+    #if(SDCard_USE_SECOND_DATAPATH)
+        /* Clear TX FIFO for 2nd Datapath */
+        SDCard_AUX_CONTROL_DP1_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
+        SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
+    #endif /* (SDCard_USE_SECOND_DATAPATH) */
+    CyExitCriticalSection(enableInterrupts);
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        /* Disable TX interrupt to protect global veriables */
+        SDCard_DisableTxInt();
+
+        SDCard_txBufferFull  = 0u;
+        SDCard_txBufferRead  = 0u;
+        SDCard_txBufferWrite = 0u;
+
+        /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */
+        SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);
+
+        SDCard_EnableTxInt();
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+}
+
+
+#if(0u != SDCard_BIDIRECTIONAL_MODE)
+    /*******************************************************************************
+    * Function Name: SDCard_TxEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  If the SPI master is configured to use a single bi-directional pin then this
+    *  will set the bi-directional pin to transmit.
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void SDCard_TxEnable(void) 
+    {
+        SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: SDCard_TxDisable
+    ********************************************************************************
+    *
+    * Summary:
+    *  If the SPI master is configured to use a single bi-directional pin then this
+    *  will set the bi-directional pin to receive.
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void SDCard_TxDisable(void) 
+    {
+        SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN);
+    }
+
+#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */
+
+
+/*******************************************************************************
+* Function Name: SDCard_PutArray
+********************************************************************************
+*
+* Summary:
+*  Write available data from ROM/RAM to the TX buffer while space is available
+*  in the TX buffer. Keep trying until all data is passed to the TX buffer.
+*
+* Parameters:
+*  *buffer: Pointer to the location in RAM containing the data to send
+*  byteCount: The number of bytes to move to the transmit buffer.
+*
+* Return:
+*  None.
+*
+* Side Effects:
+*  Will stay in this routine until all data has been sent.  May get locked in
+*  this loop if data is not being initiated by the master if there is not
+*  enough room in the TX FIFO.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_PutArray(const uint8 buffer[], uint8 byteCount)
+                                                                          
+{
+    uint8 bufIndex;
+
+    bufIndex = 0u;
+
+    while(byteCount > 0u)
+    {
+        SDCard_WriteTxData(buffer[bufIndex]);
+        bufIndex++;
+        byteCount--;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ClearFIFO
+********************************************************************************
+*
+* Summary:
+*  Clear the RX and TX FIFO's of all data for a fresh start.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Side Effects:
+*  Clear status register of the component.
+*
+*******************************************************************************/
+void SDCard_ClearFIFO(void) 
+{
+    uint8 enableInterrupts;
+
+    /* Clear Hardware RX FIFO */
+    while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))
+    {
+        (void) CY_GET_REG8(SDCard_RXDATA_PTR);
+    }
+
+    enableInterrupts = CyEnterCriticalSection();
+    /* Clear TX FIFO */
+    SDCard_AUX_CONTROL_DP0_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
+    SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
+
+    #if(SDCard_USE_SECOND_DATAPATH)
+        /* Clear TX FIFO for 2nd Datapath */
+        SDCard_AUX_CONTROL_DP1_REG |= ((uint8)  SDCard_TX_FIFO_CLR);
+        SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);
+    #endif /* (SDCard_USE_SECOND_DATAPATH) */
+    CyExitCriticalSection(enableInterrupts);
+}
+
+
+/* Following functions are for version Compatibility, they are obsolete.
+*  Please do not use it in new projects.
+*/
+
+
+/*******************************************************************************
+* Function Name: SDCard_EnableInt
+********************************************************************************
+*
+* Summary:
+*  Enable internal interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enable the internal interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_EnableInt(void) 
+{
+    SDCard_EnableRxInt();
+    SDCard_EnableTxInt();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_DisableInt
+********************************************************************************
+*
+* Summary:
+*  Disable internal interrupt generation.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Disable the internal interrupt output -or- the interrupt component itself.
+*
+*******************************************************************************/
+void SDCard_DisableInt(void) 
+{
+    SDCard_DisableTxInt();
+    SDCard_DisableRxInt();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_SetInterruptMode
+********************************************************************************
+*
+* Summary:
+*  Configure which status bits trigger an interrupt event.
+*
+* Parameters:
+*  intSrc: An or'd combination of the desired status bit masks (defined in the
+*  header file).
+*
+* Return:
+*  None.
+*
+* Theory:
+*  Enables the output of specific status bits to the interrupt controller.
+*
+*******************************************************************************/
+void SDCard_SetInterruptMode(uint8 intSrc) 
+{
+    SDCard_TX_STATUS_MASK_REG  = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE));
+    SDCard_RX_STATUS_MASK_REG  =  intSrc;
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_ReadStatus
+********************************************************************************
+*
+* Summary:
+*  Read the status register for the component.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Contents of the status register.
+*
+* Global variables:
+*  SDCard_swStatus - used to store in software status register,
+*  modified every function call - resets to zero.
+*
+* Theory:
+*  Allows the user and the API to read the status register for error detection
+*  and flow control.
+*
+* Side Effects:
+*  Clear status register of the component.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+uint8 SDCard_ReadStatus(void) 
+{
+    uint8 tmpStatus;
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED)
+
+        SDCard_DisableInt();
+
+        tmpStatus  = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
+        tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx);
+        tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);
+
+        SDCard_swStatusTx = 0u;
+        SDCard_swStatusRx = 0u;
+
+        SDCard_EnableInt();
+
+    #else
+
+        tmpStatus  = SDCard_RX_STATUS_REG;
+        tmpStatus |= SDCard_TX_STATUS_REG;
+        tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    return(tmpStatus);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h

@@ -1,373 +1,373 @@
-/*******************************************************************************
-* File Name: SDCard.h
-* Version 2.50
-*
-* Description:
-*  Contains the function prototypes, constants and register definition
-*  of the SPI Master Component.
-*
-* Note:
-*  None
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_SPIM_SDCard_H)
-#define CY_SPIM_SDCard_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-
-/***************************************
-*   Conditional Compilation Parameters
-***************************************/
-
-#define SDCard_INTERNAL_CLOCK             (0u)
-
-#if(0u != SDCard_INTERNAL_CLOCK)
-    #include "SDCard_IntClock.h"
-#endif /* (0u != SDCard_INTERNAL_CLOCK) */
-
-#define SDCard_MODE                       (1u)
-#define SDCard_DATA_WIDTH                 (8u)
-#define SDCard_MODE_USE_ZERO              (1u)
-#define SDCard_BIDIRECTIONAL_MODE         (0u)
-
-/* Internal interrupt handling */
-#define SDCard_TX_BUFFER_SIZE             (4u)
-#define SDCard_RX_BUFFER_SIZE             (4u)
-#define SDCard_INTERNAL_TX_INT_ENABLED    (0u)
-#define SDCard_INTERNAL_RX_INT_ENABLED    (0u)
-
-#define SDCard_SINGLE_REG_SIZE            (8u)
-#define SDCard_USE_SECOND_DATAPATH        (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)
-
-#define SDCard_FIFO_SIZE                  (4u)
-#define SDCard_TX_SOFTWARE_BUF_ENABLED    ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \
-                                                     (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE))
-
-#define SDCard_RX_SOFTWARE_BUF_ENABLED    ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \
-                                                     (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE))
-
-
-/***************************************
-*        Data Struct Definition
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 enableState;
-    uint8 cntrPeriod;
-} SDCard_BACKUP_STRUCT;
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void  SDCard_Init(void)                           ;
-void  SDCard_Enable(void)                         ;
-void  SDCard_Start(void)                          ;
-void  SDCard_Stop(void)                           ;
-
-void  SDCard_EnableTxInt(void)                    ;
-void  SDCard_EnableRxInt(void)                    ;
-void  SDCard_DisableTxInt(void)                   ;
-void  SDCard_DisableRxInt(void)                   ;
-
-void  SDCard_Sleep(void)                          ;
-void  SDCard_Wakeup(void)                         ;
-void  SDCard_SaveConfig(void)                     ;
-void  SDCard_RestoreConfig(void)                  ;
-
-void  SDCard_SetTxInterruptMode(uint8 intSrc)     ;
-void  SDCard_SetRxInterruptMode(uint8 intSrc)     ;
-uint8 SDCard_ReadTxStatus(void)                   ;
-uint8 SDCard_ReadRxStatus(void)                   ;
-void  SDCard_WriteTxData(uint8 txData)  \
-                                                            ;
-uint8 SDCard_ReadRxData(void) \
-                                                            ;
-uint8 SDCard_GetRxBufferSize(void)                ;
-uint8 SDCard_GetTxBufferSize(void)                ;
-void  SDCard_ClearRxBuffer(void)                  ;
-void  SDCard_ClearTxBuffer(void)                  ;
-void  SDCard_ClearFIFO(void)                              ;
-void  SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \
-                                                            ;
-
-#if(0u != SDCard_BIDIRECTIONAL_MODE)
-    void  SDCard_TxEnable(void)                   ;
-    void  SDCard_TxDisable(void)                  ;
-#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */
-
-CY_ISR_PROTO(SDCard_TX_ISR);
-CY_ISR_PROTO(SDCard_RX_ISR);
-
-
-/***************************************
-*   Variable with external linkage
-***************************************/
-
-extern uint8 SDCard_initVar;
-
-
-/***************************************
-*           API Constants
-***************************************/
-
-#define SDCard_TX_ISR_NUMBER     ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER))
-#define SDCard_RX_ISR_NUMBER     ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER))
-
-#define SDCard_TX_ISR_PRIORITY   ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM))
-#define SDCard_RX_ISR_PRIORITY   ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM))
-
-
-/***************************************
-*    Initial Parameter Constants
-***************************************/
-
-#define SDCard_INT_ON_SPI_DONE    ((uint8) (0u   << SDCard_STS_SPI_DONE_SHIFT))
-#define SDCard_INT_ON_TX_EMPTY    ((uint8) (1u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
-                                                                           SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
-#define SDCard_INT_ON_BYTE_COMP   ((uint8) (0u  << SDCard_STS_BYTE_COMPLETE_SHIFT))
-#define SDCard_INT_ON_SPI_IDLE    ((uint8) (0u   << SDCard_STS_SPI_IDLE_SHIFT))
-
-/* Disable TX_NOT_FULL if software buffer is used */
-#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \
-                                                                        (0u) : (SDCard_INT_ON_TX_NOT_FULL))
-
-/* TX interrupt mask */
-#define SDCard_TX_INIT_INTERRUPTS_MASK    (SDCard_INT_ON_SPI_DONE  | \
-                                                     SDCard_INT_ON_TX_EMPTY  | \
-                                                     SDCard_INT_ON_TX_NOT_FULL_DEF | \
-                                                     SDCard_INT_ON_BYTE_COMP | \
-                                                     SDCard_INT_ON_SPI_IDLE)
-
-#define SDCard_INT_ON_RX_FULL         ((uint8) (0u << \
-                                                                          SDCard_STS_RX_FIFO_FULL_SHIFT))
-#define SDCard_INT_ON_RX_NOT_EMPTY    ((uint8) (1u << \
-                                                                          SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
-#define SDCard_INT_ON_RX_OVER         ((uint8) (0u << \
-                                                                          SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
-
-/* RX interrupt mask */
-#define SDCard_RX_INIT_INTERRUPTS_MASK    (SDCard_INT_ON_RX_FULL      | \
-                                                     SDCard_INT_ON_RX_NOT_EMPTY | \
-                                                     SDCard_INT_ON_RX_OVER)
-/* Nubmer of bits to receive/transmit */
-#define SDCard_BITCTR_INIT            (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u)
-
-
-/***************************************
-*             Registers
-***************************************/
-#if(CY_PSOC3 || CY_PSOC5)
-    #define SDCard_TXDATA_REG (* (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
-    #define SDCard_TXDATA_PTR (  (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
-    #define SDCard_RXDATA_REG (* (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
-    #define SDCard_RXDATA_PTR (  (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
-#else   /* PSOC4 */
-    #if(SDCard_USE_SECOND_DATAPATH)
-        #define SDCard_TXDATA_REG (* (reg16 *) \
-                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
-        #define SDCard_TXDATA_PTR (  (reg16 *) \
-                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
-        #define SDCard_RXDATA_REG (* (reg16 *) \
-                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
-        #define SDCard_RXDATA_PTR (  (reg16 *) \
-                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
-    #else
-        #define SDCard_TXDATA_REG (* (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
-        #define SDCard_TXDATA_PTR (  (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
-        #define SDCard_RXDATA_REG (* (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
-        #define SDCard_RXDATA_PTR (  (reg8 *) \
-                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
-    #endif /* (SDCard_USE_SECOND_DATAPATH) */
-#endif     /* (CY_PSOC3 || CY_PSOC5) */
-
-#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \
-                                        SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
-#define SDCard_AUX_CONTROL_DP0_PTR (  (reg8 *) \
-                                        SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
-
-#if(SDCard_USE_SECOND_DATAPATH)
-    #define SDCard_AUX_CONTROL_DP1_REG  (* (reg8 *) \
-                                        SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
-    #define SDCard_AUX_CONTROL_DP1_PTR  (  (reg8 *) \
-                                        SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
-#endif /* (SDCard_USE_SECOND_DATAPATH) */
-
-#define SDCard_COUNTER_PERIOD_REG     (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
-#define SDCard_COUNTER_PERIOD_PTR     (  (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
-#define SDCard_COUNTER_CONTROL_REG    (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
-#define SDCard_COUNTER_CONTROL_PTR    (  (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
-
-#define SDCard_TX_STATUS_REG          (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
-#define SDCard_TX_STATUS_PTR          (  (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
-#define SDCard_RX_STATUS_REG          (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
-#define SDCard_RX_STATUS_PTR          (  (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
-
-#define SDCard_CONTROL_REG            (* (reg8 *) \
-                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
-#define SDCard_CONTROL_PTR            (  (reg8 *) \
-                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
-
-#define SDCard_TX_STATUS_MASK_REG     (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
-#define SDCard_TX_STATUS_MASK_PTR     (  (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
-#define SDCard_RX_STATUS_MASK_REG     (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
-#define SDCard_RX_STATUS_MASK_PTR     (  (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
-
-#define SDCard_TX_STATUS_ACTL_REG     (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
-#define SDCard_TX_STATUS_ACTL_PTR     (  (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
-#define SDCard_RX_STATUS_ACTL_REG     (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
-#define SDCard_RX_STATUS_ACTL_PTR     (  (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
-
-#if(SDCard_USE_SECOND_DATAPATH)
-    #define SDCard_AUX_CONTROLDP1     (SDCard_AUX_CONTROL_DP1_REG)
-#endif /* (SDCard_USE_SECOND_DATAPATH) */
-
-
-/***************************************
-*       Register Constants
-***************************************/
-
-/* Status Register Definitions */
-#define SDCard_STS_SPI_DONE_SHIFT             (0x00u)
-#define SDCard_STS_TX_FIFO_EMPTY_SHIFT        (0x01u)
-#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT     (0x02u)
-#define SDCard_STS_BYTE_COMPLETE_SHIFT        (0x03u)
-#define SDCard_STS_SPI_IDLE_SHIFT             (0x04u)
-#define SDCard_STS_RX_FIFO_FULL_SHIFT         (0x04u)
-#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT    (0x05u)
-#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT      (0x06u)
-
-#define SDCard_STS_SPI_DONE           ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT))
-#define SDCard_STS_TX_FIFO_EMPTY      ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
-#define SDCard_STS_TX_FIFO_NOT_FULL   ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
-#define SDCard_STS_BYTE_COMPLETE      ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT))
-#define SDCard_STS_SPI_IDLE           ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT))
-#define SDCard_STS_RX_FIFO_FULL       ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT))
-#define SDCard_STS_RX_FIFO_NOT_EMPTY  ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
-#define SDCard_STS_RX_FIFO_OVERRUN    ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
-
-/* TX and RX masks for clear on read bits */
-#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK    (0x09u)
-#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK    (0x40u)
-
-/* StatusI Register Interrupt Enable Control Bits */
-/* As defined by the Register map for the AUX Control Register */
-#define SDCard_INT_ENABLE     (0x10u) /* Enable interrupt from statusi */
-#define SDCard_TX_FIFO_CLR    (0x01u) /* F0 - TX FIFO */
-#define SDCard_RX_FIFO_CLR    (0x02u) /* F1 - RX FIFO */
-#define SDCard_FIFO_CLR       (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR)
-
-/* Bit Counter (7-bit) Control Register Bit Definitions */
-/* As defined by the Register map for the AUX Control Register */
-#define SDCard_CNTR_ENABLE    (0x20u) /* Enable CNT7 */
-
-/* Bi-Directional mode control bit */
-#define SDCard_CTRL_TX_SIGNAL_EN  (0x01u)
-
-/* Datapath Auxillary Control Register definitions */
-#define SDCard_AUX_CTRL_FIFO0_CLR         (0x01u)
-#define SDCard_AUX_CTRL_FIFO1_CLR         (0x02u)
-#define SDCard_AUX_CTRL_FIFO0_LVL         (0x04u)
-#define SDCard_AUX_CTRL_FIFO1_LVL         (0x08u)
-#define SDCard_STATUS_ACTL_INT_EN_MASK    (0x10u)
-
-/* Component disabled */
-#define SDCard_DISABLED   (0u)
-
-
-/***************************************
-*       Macros
-***************************************/
-
-/* Returns true if componentn enabled */
-#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE))
-
-/* Retuns TX status register */
-#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \
-                                                          ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) )
-/* Retuns RX status register */
-#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \
-                                                          ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) )
-
-
-/***************************************
-* The following code is DEPRECATED and 
-* should not be used in new projects.
-***************************************/
-
-#define SDCard_WriteByte   SDCard_WriteTxData
-#define SDCard_ReadByte    SDCard_ReadRxData
-void  SDCard_SetInterruptMode(uint8 intSrc)       ;
-uint8 SDCard_ReadStatus(void)                     ;
-void  SDCard_EnableInt(void)                      ;
-void  SDCard_DisableInt(void)                     ;
-
-#define SDCard_TXDATA                 (SDCard_TXDATA_REG)
-#define SDCard_RXDATA                 (SDCard_RXDATA_REG)
-#define SDCard_AUX_CONTROLDP0         (SDCard_AUX_CONTROL_DP0_REG)
-#define SDCard_TXBUFFERREAD           (SDCard_txBufferRead)
-#define SDCard_TXBUFFERWRITE          (SDCard_txBufferWrite)
-#define SDCard_RXBUFFERREAD           (SDCard_rxBufferRead)
-#define SDCard_RXBUFFERWRITE          (SDCard_rxBufferWrite)
-
-#define SDCard_COUNTER_PERIOD         (SDCard_COUNTER_PERIOD_REG)
-#define SDCard_COUNTER_CONTROL        (SDCard_COUNTER_CONTROL_REG)
-#define SDCard_STATUS                 (SDCard_TX_STATUS_REG)
-#define SDCard_CONTROL                (SDCard_CONTROL_REG)
-#define SDCard_STATUS_MASK            (SDCard_TX_STATUS_MASK_REG)
-#define SDCard_STATUS_ACTL            (SDCard_TX_STATUS_ACTL_REG)
-
-#define SDCard_INIT_INTERRUPTS_MASK  (SDCard_INT_ON_SPI_DONE     | \
-                                                SDCard_INT_ON_TX_EMPTY     | \
-                                                SDCard_INT_ON_TX_NOT_FULL_DEF  | \
-                                                SDCard_INT_ON_RX_FULL      | \
-                                                SDCard_INT_ON_RX_NOT_EMPTY | \
-                                                SDCard_INT_ON_RX_OVER      | \
-                                                SDCard_INT_ON_BYTE_COMP)
-                                                
-#define SDCard_DataWidth                  (SDCard_DATA_WIDTH)
-#define SDCard_InternalClockUsed          (SDCard_INTERNAL_CLOCK)
-#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)
-#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED)
-#define SDCard_ModeUseZero                (SDCard_MODE_USE_ZERO)
-#define SDCard_BidirectionalMode          (SDCard_BIDIRECTIONAL_MODE)
-#define SDCard_Mode                       (SDCard_MODE)
-#define SDCard_DATAWIDHT                  (SDCard_DATA_WIDTH)
-#define SDCard_InternalInterruptEnabled   (0u)
-
-#define SDCard_TXBUFFERSIZE   (SDCard_TX_BUFFER_SIZE)
-#define SDCard_RXBUFFERSIZE   (SDCard_RX_BUFFER_SIZE)
-
-#define SDCard_TXBUFFER       SDCard_txBuffer
-#define SDCard_RXBUFFER       SDCard_rxBuffer
-
-#endif /* (CY_SPIM_SDCard_H) */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SDCard.h
+* Version 2.50
+*
+* Description:
+*  Contains the function prototypes, constants and register definition
+*  of the SPI Master Component.
+*
+* Note:
+*  None
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_SPIM_SDCard_H)
+#define CY_SPIM_SDCard_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+
+/***************************************
+*   Conditional Compilation Parameters
+***************************************/
+
+#define SDCard_INTERNAL_CLOCK             (0u)
+
+#if(0u != SDCard_INTERNAL_CLOCK)
+    #include "SDCard_IntClock.h"
+#endif /* (0u != SDCard_INTERNAL_CLOCK) */
+
+#define SDCard_MODE                       (1u)
+#define SDCard_DATA_WIDTH                 (8u)
+#define SDCard_MODE_USE_ZERO              (1u)
+#define SDCard_BIDIRECTIONAL_MODE         (0u)
+
+/* Internal interrupt handling */
+#define SDCard_TX_BUFFER_SIZE             (4u)
+#define SDCard_RX_BUFFER_SIZE             (4u)
+#define SDCard_INTERNAL_TX_INT_ENABLED    (0u)
+#define SDCard_INTERNAL_RX_INT_ENABLED    (0u)
+
+#define SDCard_SINGLE_REG_SIZE            (8u)
+#define SDCard_USE_SECOND_DATAPATH        (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)
+
+#define SDCard_FIFO_SIZE                  (4u)
+#define SDCard_TX_SOFTWARE_BUF_ENABLED    ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \
+                                                     (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE))
+
+#define SDCard_RX_SOFTWARE_BUF_ENABLED    ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \
+                                                     (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE))
+
+
+/***************************************
+*        Data Struct Definition
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+    uint8 enableState;
+    uint8 cntrPeriod;
+} SDCard_BACKUP_STRUCT;
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void  SDCard_Init(void)                           ;
+void  SDCard_Enable(void)                         ;
+void  SDCard_Start(void)                          ;
+void  SDCard_Stop(void)                           ;
+
+void  SDCard_EnableTxInt(void)                    ;
+void  SDCard_EnableRxInt(void)                    ;
+void  SDCard_DisableTxInt(void)                   ;
+void  SDCard_DisableRxInt(void)                   ;
+
+void  SDCard_Sleep(void)                          ;
+void  SDCard_Wakeup(void)                         ;
+void  SDCard_SaveConfig(void)                     ;
+void  SDCard_RestoreConfig(void)                  ;
+
+void  SDCard_SetTxInterruptMode(uint8 intSrc)     ;
+void  SDCard_SetRxInterruptMode(uint8 intSrc)     ;
+uint8 SDCard_ReadTxStatus(void)                   ;
+uint8 SDCard_ReadRxStatus(void)                   ;
+void  SDCard_WriteTxData(uint8 txData)  \
+                                                            ;
+uint8 SDCard_ReadRxData(void) \
+                                                            ;
+uint8 SDCard_GetRxBufferSize(void)                ;
+uint8 SDCard_GetTxBufferSize(void)                ;
+void  SDCard_ClearRxBuffer(void)                  ;
+void  SDCard_ClearTxBuffer(void)                  ;
+void  SDCard_ClearFIFO(void)                              ;
+void  SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \
+                                                            ;
+
+#if(0u != SDCard_BIDIRECTIONAL_MODE)
+    void  SDCard_TxEnable(void)                   ;
+    void  SDCard_TxDisable(void)                  ;
+#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */
+
+CY_ISR_PROTO(SDCard_TX_ISR);
+CY_ISR_PROTO(SDCard_RX_ISR);
+
+
+/***************************************
+*   Variable with external linkage
+***************************************/
+
+extern uint8 SDCard_initVar;
+
+
+/***************************************
+*           API Constants
+***************************************/
+
+#define SDCard_TX_ISR_NUMBER     ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER))
+#define SDCard_RX_ISR_NUMBER     ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER))
+
+#define SDCard_TX_ISR_PRIORITY   ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM))
+#define SDCard_RX_ISR_PRIORITY   ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM))
+
+
+/***************************************
+*    Initial Parameter Constants
+***************************************/
+
+#define SDCard_INT_ON_SPI_DONE    ((uint8) (0u   << SDCard_STS_SPI_DONE_SHIFT))
+#define SDCard_INT_ON_TX_EMPTY    ((uint8) (1u   << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
+                                                                           SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
+#define SDCard_INT_ON_BYTE_COMP   ((uint8) (0u  << SDCard_STS_BYTE_COMPLETE_SHIFT))
+#define SDCard_INT_ON_SPI_IDLE    ((uint8) (0u   << SDCard_STS_SPI_IDLE_SHIFT))
+
+/* Disable TX_NOT_FULL if software buffer is used */
+#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \
+                                                                        (0u) : (SDCard_INT_ON_TX_NOT_FULL))
+
+/* TX interrupt mask */
+#define SDCard_TX_INIT_INTERRUPTS_MASK    (SDCard_INT_ON_SPI_DONE  | \
+                                                     SDCard_INT_ON_TX_EMPTY  | \
+                                                     SDCard_INT_ON_TX_NOT_FULL_DEF | \
+                                                     SDCard_INT_ON_BYTE_COMP | \
+                                                     SDCard_INT_ON_SPI_IDLE)
+
+#define SDCard_INT_ON_RX_FULL         ((uint8) (0u << \
+                                                                          SDCard_STS_RX_FIFO_FULL_SHIFT))
+#define SDCard_INT_ON_RX_NOT_EMPTY    ((uint8) (1u << \
+                                                                          SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
+#define SDCard_INT_ON_RX_OVER         ((uint8) (0u << \
+                                                                          SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
+
+/* RX interrupt mask */
+#define SDCard_RX_INIT_INTERRUPTS_MASK    (SDCard_INT_ON_RX_FULL      | \
+                                                     SDCard_INT_ON_RX_NOT_EMPTY | \
+                                                     SDCard_INT_ON_RX_OVER)
+/* Nubmer of bits to receive/transmit */
+#define SDCard_BITCTR_INIT            (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u)
+
+
+/***************************************
+*             Registers
+***************************************/
+#if(CY_PSOC3 || CY_PSOC5)
+    #define SDCard_TXDATA_REG (* (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
+    #define SDCard_TXDATA_PTR (  (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
+    #define SDCard_RXDATA_REG (* (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
+    #define SDCard_RXDATA_PTR (  (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
+#else   /* PSOC4 */
+    #if(SDCard_USE_SECOND_DATAPATH)
+        #define SDCard_TXDATA_REG (* (reg16 *) \
+                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
+        #define SDCard_TXDATA_PTR (  (reg16 *) \
+                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
+        #define SDCard_RXDATA_REG (* (reg16 *) \
+                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
+        #define SDCard_RXDATA_PTR (  (reg16 *) \
+                                          SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
+    #else
+        #define SDCard_TXDATA_REG (* (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
+        #define SDCard_TXDATA_PTR (  (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F0_REG)
+        #define SDCard_RXDATA_REG (* (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
+        #define SDCard_RXDATA_PTR (  (reg8 *) \
+                                                SDCard_BSPIM_sR8_Dp_u0__F1_REG)
+    #endif /* (SDCard_USE_SECOND_DATAPATH) */
+#endif     /* (CY_PSOC3 || CY_PSOC5) */
+
+#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \
+                                        SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
+#define SDCard_AUX_CONTROL_DP0_PTR (  (reg8 *) \
+                                        SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
+
+#if(SDCard_USE_SECOND_DATAPATH)
+    #define SDCard_AUX_CONTROL_DP1_REG  (* (reg8 *) \
+                                        SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
+    #define SDCard_AUX_CONTROL_DP1_PTR  (  (reg8 *) \
+                                        SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
+#endif /* (SDCard_USE_SECOND_DATAPATH) */
+
+#define SDCard_COUNTER_PERIOD_REG     (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
+#define SDCard_COUNTER_PERIOD_PTR     (  (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)
+#define SDCard_COUNTER_CONTROL_REG    (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
+#define SDCard_COUNTER_CONTROL_PTR    (  (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
+
+#define SDCard_TX_STATUS_REG          (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
+#define SDCard_TX_STATUS_PTR          (  (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)
+#define SDCard_RX_STATUS_REG          (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
+#define SDCard_RX_STATUS_PTR          (  (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)
+
+#define SDCard_CONTROL_REG            (* (reg8 *) \
+                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
+#define SDCard_CONTROL_PTR            (  (reg8 *) \
+                                      SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)
+
+#define SDCard_TX_STATUS_MASK_REG     (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
+#define SDCard_TX_STATUS_MASK_PTR     (  (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)
+#define SDCard_RX_STATUS_MASK_REG     (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
+#define SDCard_RX_STATUS_MASK_PTR     (  (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)
+
+#define SDCard_TX_STATUS_ACTL_REG     (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
+#define SDCard_TX_STATUS_ACTL_PTR     (  (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
+#define SDCard_RX_STATUS_ACTL_REG     (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
+#define SDCard_RX_STATUS_ACTL_PTR     (  (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
+
+#if(SDCard_USE_SECOND_DATAPATH)
+    #define SDCard_AUX_CONTROLDP1     (SDCard_AUX_CONTROL_DP1_REG)
+#endif /* (SDCard_USE_SECOND_DATAPATH) */
+
+
+/***************************************
+*       Register Constants
+***************************************/
+
+/* Status Register Definitions */
+#define SDCard_STS_SPI_DONE_SHIFT             (0x00u)
+#define SDCard_STS_TX_FIFO_EMPTY_SHIFT        (0x01u)
+#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT     (0x02u)
+#define SDCard_STS_BYTE_COMPLETE_SHIFT        (0x03u)
+#define SDCard_STS_SPI_IDLE_SHIFT             (0x04u)
+#define SDCard_STS_RX_FIFO_FULL_SHIFT         (0x04u)
+#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT    (0x05u)
+#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT      (0x06u)
+
+#define SDCard_STS_SPI_DONE           ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT))
+#define SDCard_STS_TX_FIFO_EMPTY      ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
+#define SDCard_STS_TX_FIFO_NOT_FULL   ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
+#define SDCard_STS_BYTE_COMPLETE      ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT))
+#define SDCard_STS_SPI_IDLE           ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT))
+#define SDCard_STS_RX_FIFO_FULL       ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT))
+#define SDCard_STS_RX_FIFO_NOT_EMPTY  ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))
+#define SDCard_STS_RX_FIFO_OVERRUN    ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT))
+
+/* TX and RX masks for clear on read bits */
+#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK    (0x09u)
+#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK    (0x40u)
+
+/* StatusI Register Interrupt Enable Control Bits */
+/* As defined by the Register map for the AUX Control Register */
+#define SDCard_INT_ENABLE     (0x10u) /* Enable interrupt from statusi */
+#define SDCard_TX_FIFO_CLR    (0x01u) /* F0 - TX FIFO */
+#define SDCard_RX_FIFO_CLR    (0x02u) /* F1 - RX FIFO */
+#define SDCard_FIFO_CLR       (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR)
+
+/* Bit Counter (7-bit) Control Register Bit Definitions */
+/* As defined by the Register map for the AUX Control Register */
+#define SDCard_CNTR_ENABLE    (0x20u) /* Enable CNT7 */
+
+/* Bi-Directional mode control bit */
+#define SDCard_CTRL_TX_SIGNAL_EN  (0x01u)
+
+/* Datapath Auxillary Control Register definitions */
+#define SDCard_AUX_CTRL_FIFO0_CLR         (0x01u)
+#define SDCard_AUX_CTRL_FIFO1_CLR         (0x02u)
+#define SDCard_AUX_CTRL_FIFO0_LVL         (0x04u)
+#define SDCard_AUX_CTRL_FIFO1_LVL         (0x08u)
+#define SDCard_STATUS_ACTL_INT_EN_MASK    (0x10u)
+
+/* Component disabled */
+#define SDCard_DISABLED   (0u)
+
+
+/***************************************
+*       Macros
+***************************************/
+
+/* Returns true if componentn enabled */
+#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE))
+
+/* Retuns TX status register */
+#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \
+                                                          ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) )
+/* Retuns RX status register */
+#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \
+                                                          ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) )
+
+
+/***************************************
+* The following code is DEPRECATED and 
+* should not be used in new projects.
+***************************************/
+
+#define SDCard_WriteByte   SDCard_WriteTxData
+#define SDCard_ReadByte    SDCard_ReadRxData
+void  SDCard_SetInterruptMode(uint8 intSrc)       ;
+uint8 SDCard_ReadStatus(void)                     ;
+void  SDCard_EnableInt(void)                      ;
+void  SDCard_DisableInt(void)                     ;
+
+#define SDCard_TXDATA                 (SDCard_TXDATA_REG)
+#define SDCard_RXDATA                 (SDCard_RXDATA_REG)
+#define SDCard_AUX_CONTROLDP0         (SDCard_AUX_CONTROL_DP0_REG)
+#define SDCard_TXBUFFERREAD           (SDCard_txBufferRead)
+#define SDCard_TXBUFFERWRITE          (SDCard_txBufferWrite)
+#define SDCard_RXBUFFERREAD           (SDCard_rxBufferRead)
+#define SDCard_RXBUFFERWRITE          (SDCard_rxBufferWrite)
+
+#define SDCard_COUNTER_PERIOD         (SDCard_COUNTER_PERIOD_REG)
+#define SDCard_COUNTER_CONTROL        (SDCard_COUNTER_CONTROL_REG)
+#define SDCard_STATUS                 (SDCard_TX_STATUS_REG)
+#define SDCard_CONTROL                (SDCard_CONTROL_REG)
+#define SDCard_STATUS_MASK            (SDCard_TX_STATUS_MASK_REG)
+#define SDCard_STATUS_ACTL            (SDCard_TX_STATUS_ACTL_REG)
+
+#define SDCard_INIT_INTERRUPTS_MASK  (SDCard_INT_ON_SPI_DONE     | \
+                                                SDCard_INT_ON_TX_EMPTY     | \
+                                                SDCard_INT_ON_TX_NOT_FULL_DEF  | \
+                                                SDCard_INT_ON_RX_FULL      | \
+                                                SDCard_INT_ON_RX_NOT_EMPTY | \
+                                                SDCard_INT_ON_RX_OVER      | \
+                                                SDCard_INT_ON_BYTE_COMP)
+                                                
+#define SDCard_DataWidth                  (SDCard_DATA_WIDTH)
+#define SDCard_InternalClockUsed          (SDCard_INTERNAL_CLOCK)
+#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)
+#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED)
+#define SDCard_ModeUseZero                (SDCard_MODE_USE_ZERO)
+#define SDCard_BidirectionalMode          (SDCard_BIDIRECTIONAL_MODE)
+#define SDCard_Mode                       (SDCard_MODE)
+#define SDCard_DATAWIDHT                  (SDCard_DATA_WIDTH)
+#define SDCard_InternalInterruptEnabled   (0u)
+
+#define SDCard_TXBUFFERSIZE   (SDCard_TX_BUFFER_SIZE)
+#define SDCard_RXBUFFERSIZE   (SDCard_RX_BUFFER_SIZE)
+
+#define SDCard_TXBUFFER       SDCard_txBuffer
+#define SDCard_RXBUFFER       SDCard_rxBuffer
+
+#endif /* (CY_SPIM_SDCard_H) */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c

@@ -1,189 +1,189 @@
-/*******************************************************************************
-* File Name: SDCard_INT.c
-* Version 2.50
-*
-* Description:
-*  This file provides all Interrupt Service Routine (ISR) for the SPI Master
-*  component.
-*
-* Note:
-*  None.
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SDCard_PVT.h"
-
-/* User code required at start of ISR */
-/* `#START SDCard_ISR_START_DEF` */
-
-/* `#END` */
-
-
-/*******************************************************************************
-* Function Name: SDCard_TX_ISR
-********************************************************************************
-*
-* Summary:
-*  Interrupt Service Routine for TX portion of the SPI Master.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer.
-*  SDCard_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer, modified when exist data to
-*  sending and FIFO Not Full.
-*  SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store
-*  data to sending.
-*  All described above Global variables are used when Software Buffer is used.
-*
-*******************************************************************************/
-CY_ISR(SDCard_TX_ISR)
-{
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        uint8 tmpStatus;
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at start of ISR */
-    /* `#START SDCard_TX_ISR_START` */
-
-    /* `#END` */
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        /* Check if TX data buffer is not empty and there is space in TX FIFO */
-        while(SDCard_txBufferRead != SDCard_txBufferWrite)
-        {
-            tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
-            SDCard_swStatusTx = tmpStatus;
-
-            if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))
-            {
-                if(0u == SDCard_txBufferFull)
-                {
-                   SDCard_txBufferRead++;
-
-                    if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)
-                    {
-                        SDCard_txBufferRead = 0u;
-                    }
-                }
-                else
-                {
-                    SDCard_txBufferFull = 0u;
-                }
-
-                /* Put data element into the TX FIFO */
-                CY_SET_REG8(SDCard_TXDATA_PTR, 
-                                             SDCard_txBuffer[SDCard_txBufferRead]);
-            }
-            else
-            {
-                break;
-            }
-        }
-
-        if(SDCard_txBufferRead == SDCard_txBufferWrite)
-        {
-            /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */
-            SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);
-        }
-
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at end of ISR (Optional) */
-    /* `#START SDCard_TX_ISR_END` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_RX_ISR
-********************************************************************************
-*
-* Summary:
-*  Interrupt Service Routine for RX portion of the SPI Master.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SDCard_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer modified when FIFO contains
-*  new data.
-*  SDCard_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified when overflow occurred.
-*  SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store
-*  received data, modified when FIFO contains new data.
-*  All described above Global variables are used when Software Buffer is used.
-*
-*******************************************************************************/
-CY_ISR(SDCard_RX_ISR)
-{
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-        uint8 tmpStatus;
-        uint8 rxData;
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at start of ISR */
-    /* `#START SDCard_RX_ISR_START` */
-
-    /* `#END` */
-
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-
-        tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
-        SDCard_swStatusRx = tmpStatus;
-
-        /* Check if RX data FIFO has some data to be moved into the RX Buffer */
-        while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY))
-        {
-            rxData = CY_GET_REG8(SDCard_RXDATA_PTR);
-
-            /* Set next pointer. */
-            SDCard_rxBufferWrite++;
-            if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE)
-            {
-                SDCard_rxBufferWrite = 0u;
-            }
-
-            if(SDCard_rxBufferWrite == SDCard_rxBufferRead)
-            {
-                SDCard_rxBufferRead++;
-                if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)
-                {
-                    SDCard_rxBufferRead = 0u;
-                }
-
-                SDCard_rxBufferFull = 1u;
-            }
-
-            /* Move data from the FIFO to the Buffer */
-            SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData;
-
-            tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
-            SDCard_swStatusRx = tmpStatus;
-        }
-
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at end of ISR (Optional) */
-    /* `#START SDCard_RX_ISR_END` */
-
-    /* `#END` */
-}
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SDCard_INT.c
+* Version 2.50
+*
+* Description:
+*  This file provides all Interrupt Service Routine (ISR) for the SPI Master
+*  component.
+*
+* Note:
+*  None.
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SDCard_PVT.h"
+
+/* User code required at start of ISR */
+/* `#START SDCard_ISR_START_DEF` */
+
+/* `#END` */
+
+
+/*******************************************************************************
+* Function Name: SDCard_TX_ISR
+********************************************************************************
+*
+* Summary:
+*  Interrupt Service Routine for TX portion of the SPI Master.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_txBufferWrite - used for the account of the bytes which
+*  have been written down in the TX software buffer.
+*  SDCard_txBufferRead - used for the account of the bytes which
+*  have been read from the TX software buffer, modified when exist data to
+*  sending and FIFO Not Full.
+*  SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store
+*  data to sending.
+*  All described above Global variables are used when Software Buffer is used.
+*
+*******************************************************************************/
+CY_ISR(SDCard_TX_ISR)
+{
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        uint8 tmpStatus;
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    /* User code required at start of ISR */
+    /* `#START SDCard_TX_ISR_START` */
+
+    /* `#END` */
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        /* Check if TX data buffer is not empty and there is space in TX FIFO */
+        while(SDCard_txBufferRead != SDCard_txBufferWrite)
+        {
+            tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);
+            SDCard_swStatusTx = tmpStatus;
+
+            if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))
+            {
+                if(0u == SDCard_txBufferFull)
+                {
+                   SDCard_txBufferRead++;
+
+                    if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)
+                    {
+                        SDCard_txBufferRead = 0u;
+                    }
+                }
+                else
+                {
+                    SDCard_txBufferFull = 0u;
+                }
+
+                /* Put data element into the TX FIFO */
+                CY_SET_REG8(SDCard_TXDATA_PTR, 
+                                             SDCard_txBuffer[SDCard_txBufferRead]);
+            }
+            else
+            {
+                break;
+            }
+        }
+
+        if(SDCard_txBufferRead == SDCard_txBufferWrite)
+        {
+            /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */
+            SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);
+        }
+
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    /* User code required at end of ISR (Optional) */
+    /* `#START SDCard_TX_ISR_END` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_RX_ISR
+********************************************************************************
+*
+* Summary:
+*  Interrupt Service Routine for RX portion of the SPI Master.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*  SDCard_rxBufferWrite - used for the account of the bytes which
+*  have been written down in the RX software buffer modified when FIFO contains
+*  new data.
+*  SDCard_rxBufferRead - used for the account of the bytes which
+*  have been read from the RX software buffer, modified when overflow occurred.
+*  SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store
+*  received data, modified when FIFO contains new data.
+*  All described above Global variables are used when Software Buffer is used.
+*
+*******************************************************************************/
+CY_ISR(SDCard_RX_ISR)
+{
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+        uint8 tmpStatus;
+        uint8 rxData;
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    /* User code required at start of ISR */
+    /* `#START SDCard_RX_ISR_START` */
+
+    /* `#END` */
+
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+
+        tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
+        SDCard_swStatusRx = tmpStatus;
+
+        /* Check if RX data FIFO has some data to be moved into the RX Buffer */
+        while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY))
+        {
+            rxData = CY_GET_REG8(SDCard_RXDATA_PTR);
+
+            /* Set next pointer. */
+            SDCard_rxBufferWrite++;
+            if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE)
+            {
+                SDCard_rxBufferWrite = 0u;
+            }
+
+            if(SDCard_rxBufferWrite == SDCard_rxBufferRead)
+            {
+                SDCard_rxBufferRead++;
+                if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)
+                {
+                    SDCard_rxBufferRead = 0u;
+                }
+
+                SDCard_rxBufferFull = 1u;
+            }
+
+            /* Move data from the FIFO to the Buffer */
+            SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData;
+
+            tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);
+            SDCard_swStatusRx = tmpStatus;
+        }
+
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    /* User code required at end of ISR (Optional) */
+    /* `#START SDCard_RX_ISR_END` */
+
+    /* `#END` */
+}
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c

@@ -1,149 +1,149 @@
-/*******************************************************************************
-* File Name: SDCard_PM.c
-* Version 2.50
-*
-* Description:
-*  This file contains the setup, control and status commands to support
-*  component operations in low power mode.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SDCard_PVT.h"
-
-static SDCard_BACKUP_STRUCT SDCard_backup =
-{
-    SDCard_DISABLED,
-    SDCard_BITCTR_INIT,
-};
-
-
-/*******************************************************************************
-* Function Name: SDCard_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Empty function. Included for consistency with other components.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SDCard_SaveConfig(void) 
-{
-
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Empty function. Included for consistency with other components.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SDCard_RestoreConfig(void) 
-{
-
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepare SPIM Component goes to sleep.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SDCard_backup - modified when non-retention registers are saved.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_Sleep(void) 
-{
-    /* Save components enable state */
-    SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);
-
-    SDCard_Stop();
-}
-
-
-/*******************************************************************************
-* Function Name: SDCard_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Prepare SPIM Component to wake up.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SDCard_backup - used when non-retention registers are restored.
-*  SDCard_txBufferWrite - modified every function call - resets to
-*  zero.
-*  SDCard_txBufferRead - modified every function call - resets to
-*  zero.
-*  SDCard_rxBufferWrite - modified every function call - resets to
-*  zero.
-*  SDCard_rxBufferRead - modified every function call - resets to
-*  zero.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SDCard_Wakeup(void) 
-{
-    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-        SDCard_rxBufferFull  = 0u;
-        SDCard_rxBufferRead  = 0u;
-        SDCard_rxBufferWrite = 0u;
-    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-        SDCard_txBufferFull  = 0u;
-        SDCard_txBufferRead  = 0u;
-        SDCard_txBufferWrite = 0u;
-    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* Clear any data from the RX and TX FIFO */
-    SDCard_ClearFIFO();
-
-    /* Restore components block enable state */
-    if(0u != SDCard_backup.enableState)
-    {
-        SDCard_Enable();
-    }
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SDCard_PM.c
+* Version 2.50
+*
+* Description:
+*  This file contains the setup, control and status commands to support
+*  component operations in low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SDCard_PVT.h"
+
+static SDCard_BACKUP_STRUCT SDCard_backup =
+{
+    SDCard_DISABLED,
+    SDCard_BITCTR_INIT,
+};
+
+
+/*******************************************************************************
+* Function Name: SDCard_SaveConfig
+********************************************************************************
+*
+* Summary:
+*  Empty function. Included for consistency with other components.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SDCard_SaveConfig(void) 
+{
+
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_RestoreConfig
+********************************************************************************
+*
+* Summary:
+*  Empty function. Included for consistency with other components.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SDCard_RestoreConfig(void) 
+{
+
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_Sleep
+********************************************************************************
+*
+* Summary:
+*  Prepare SPIM Component goes to sleep.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global Variables:
+*  SDCard_backup - modified when non-retention registers are saved.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_Sleep(void) 
+{
+    /* Save components enable state */
+    SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);
+
+    SDCard_Stop();
+}
+
+
+/*******************************************************************************
+* Function Name: SDCard_Wakeup
+********************************************************************************
+*
+* Summary:
+*  Prepare SPIM Component to wake up.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global Variables:
+*  SDCard_backup - used when non-retention registers are restored.
+*  SDCard_txBufferWrite - modified every function call - resets to
+*  zero.
+*  SDCard_txBufferRead - modified every function call - resets to
+*  zero.
+*  SDCard_rxBufferWrite - modified every function call - resets to
+*  zero.
+*  SDCard_rxBufferRead - modified every function call - resets to
+*  zero.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void SDCard_Wakeup(void) 
+{
+    #if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+        SDCard_rxBufferFull  = 0u;
+        SDCard_rxBufferRead  = 0u;
+        SDCard_rxBufferWrite = 0u;
+    #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+    #if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+        SDCard_txBufferFull  = 0u;
+        SDCard_txBufferRead  = 0u;
+        SDCard_txBufferWrite = 0u;
+    #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+    /* Clear any data from the RX and TX FIFO */
+    SDCard_ClearFIFO();
+
+    /* Restore components block enable state */
+    if(0u != SDCard_backup.enableState)
+    {
+        SDCard_Enable();
+    }
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h

@@ -1,53 +1,53 @@
-/*******************************************************************************
-* File Name: .h
-* Version 2.50
-*
-* Description:
-*  This private header file contains internal definitions for the SPIM
-*  component. Do not use these definitions directly in your application.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_SPIM_PVT_SDCard_H)
-#define CY_SPIM_PVT_SDCard_H
-
-#include "SDCard.h"
-
-
-/**********************************
-*   Functions with external linkage
-**********************************/
-
-
-/**********************************
-*   Variables with external linkage
-**********************************/
-
-extern volatile uint8 SDCard_swStatusTx;
-extern volatile uint8 SDCard_swStatusRx;
-
-#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
-    extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
-    extern volatile uint8 SDCard_txBufferRead;
-    extern volatile uint8 SDCard_txBufferWrite;
-    extern volatile uint8 SDCard_txBufferFull;
-#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
-
-#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
-    extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
-    extern volatile uint8 SDCard_rxBufferRead;
-    extern volatile uint8 SDCard_rxBufferWrite;
-    extern volatile uint8 SDCard_rxBufferFull;
-#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
-
-#endif /* CY_SPIM_PVT_SDCard_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: .h
+* Version 2.50
+*
+* Description:
+*  This private header file contains internal definitions for the SPIM
+*  component. Do not use these definitions directly in your application.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_SPIM_PVT_SDCard_H)
+#define CY_SPIM_PVT_SDCard_H
+
+#include "SDCard.h"
+
+
+/**********************************
+*   Functions with external linkage
+**********************************/
+
+
+/**********************************
+*   Variables with external linkage
+**********************************/
+
+extern volatile uint8 SDCard_swStatusTx;
+extern volatile uint8 SDCard_swStatusRx;
+
+#if(SDCard_TX_SOFTWARE_BUF_ENABLED)
+    extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];
+    extern volatile uint8 SDCard_txBufferRead;
+    extern volatile uint8 SDCard_txBufferWrite;
+    extern volatile uint8 SDCard_txBufferFull;
+#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */
+
+#if(SDCard_RX_SOFTWARE_BUF_ENABLED)
+    extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];
+    extern volatile uint8 SDCard_rxBufferRead;
+    extern volatile uint8 SDCard_rxBufferWrite;
+    extern volatile uint8 SDCard_rxBufferFull;
+#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */
+
+#endif /* CY_SPIM_PVT_SDCard_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: SD_CD.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "SD_CD.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: SD_CD_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void SD_CD_Write(uint8 value) 
-{
-    uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));
-    SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CD_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  SD_CD_DM_STRONG     Strong Drive 
-*  SD_CD_DM_OD_HI      Open Drain, Drives High 
-*  SD_CD_DM_OD_LO      Open Drain, Drives Low 
-*  SD_CD_DM_RES_UP     Resistive Pull Up 
-*  SD_CD_DM_RES_DWN    Resistive Pull Down 
-*  SD_CD_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  SD_CD_DM_DIG_HIZ    High Impedance Digital 
-*  SD_CD_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void SD_CD_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(SD_CD_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CD_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro SD_CD_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 SD_CD_Read(void) 
-{
-    return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CD_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 SD_CD_ReadDataReg(void) 
-{
-    return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(SD_CD_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: SD_CD_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 SD_CD_ClearInterrupt(void) 
-    {
-        return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CD.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SD_CD.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SD_CD_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SD_CD_Write(uint8 value) 
+{
+    uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));
+    SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CD_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CD_DM_STRONG     Strong Drive 
+*  SD_CD_DM_OD_HI      Open Drain, Drives High 
+*  SD_CD_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CD_DM_RES_UP     Resistive Pull Up 
+*  SD_CD_DM_RES_DWN    Resistive Pull Down 
+*  SD_CD_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CD_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CD_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SD_CD_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SD_CD_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CD_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SD_CD_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SD_CD_Read(void) 
+{
+    return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CD_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SD_CD_ReadDataReg(void) 
+{
+    return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SD_CD_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SD_CD_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SD_CD_ClearInterrupt(void) 
+    {
+        return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: SD_CD.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */
-#define CY_PINS_SD_CD_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "SD_CD_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    SD_CD_Write(uint8 value) ;
-void    SD_CD_SetDriveMode(uint8 mode) ;
-uint8   SD_CD_ReadDataReg(void) ;
-uint8   SD_CD_Read(void) ;
-uint8   SD_CD_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define SD_CD_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define SD_CD_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define SD_CD_DM_RES_UP          PIN_DM_RES_UP
-#define SD_CD_DM_RES_DWN         PIN_DM_RES_DWN
-#define SD_CD_DM_OD_LO           PIN_DM_OD_LO
-#define SD_CD_DM_OD_HI           PIN_DM_OD_HI
-#define SD_CD_DM_STRONG          PIN_DM_STRONG
-#define SD_CD_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define SD_CD_MASK               SD_CD__MASK
-#define SD_CD_SHIFT              SD_CD__SHIFT
-#define SD_CD_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define SD_CD_PS                     (* (reg8 *) SD_CD__PS)
-/* Data Register */
-#define SD_CD_DR                     (* (reg8 *) SD_CD__DR)
-/* Port Number */
-#define SD_CD_PRT_NUM                (* (reg8 *) SD_CD__PRT) 
-/* Connect to Analog Globals */                                                  
-#define SD_CD_AG                     (* (reg8 *) SD_CD__AG)                       
-/* Analog MUX bux enable */
-#define SD_CD_AMUX                   (* (reg8 *) SD_CD__AMUX) 
-/* Bidirectional Enable */                                                        
-#define SD_CD_BIE                    (* (reg8 *) SD_CD__BIE)
-/* Bit-mask for Aliased Register Access */
-#define SD_CD_BIT_MASK               (* (reg8 *) SD_CD__BIT_MASK)
-/* Bypass Enable */
-#define SD_CD_BYP                    (* (reg8 *) SD_CD__BYP)
-/* Port wide control signals */                                                   
-#define SD_CD_CTL                    (* (reg8 *) SD_CD__CTL)
-/* Drive Modes */
-#define SD_CD_DM0                    (* (reg8 *) SD_CD__DM0) 
-#define SD_CD_DM1                    (* (reg8 *) SD_CD__DM1)
-#define SD_CD_DM2                    (* (reg8 *) SD_CD__DM2) 
-/* Input Buffer Disable Override */
-#define SD_CD_INP_DIS                (* (reg8 *) SD_CD__INP_DIS)
-/* LCD Common or Segment Drive */
-#define SD_CD_LCD_COM_SEG            (* (reg8 *) SD_CD__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define SD_CD_LCD_EN                 (* (reg8 *) SD_CD__LCD_EN)
-/* Slew Rate Control */
-#define SD_CD_SLW                    (* (reg8 *) SD_CD__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define SD_CD_PRTDSI__CAPS_SEL       (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define SD_CD_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define SD_CD_PRTDSI__OE_SEL0        (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) 
-#define SD_CD_PRTDSI__OE_SEL1        (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define SD_CD_PRTDSI__OUT_SEL0       (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) 
-#define SD_CD_PRTDSI__OUT_SEL1       (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define SD_CD_PRTDSI__SYNC_OUT       (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) 
-
-
-#if defined(SD_CD__INTSTAT)  /* Interrupt Registers */
-
-    #define SD_CD_INTSTAT                (* (reg8 *) SD_CD__INTSTAT)
-    #define SD_CD_SNAP                   (* (reg8 *) SD_CD__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_SD_CD_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CD.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */
+#define CY_PINS_SD_CD_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SD_CD_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SD_CD_Write(uint8 value) ;
+void    SD_CD_SetDriveMode(uint8 mode) ;
+uint8   SD_CD_ReadDataReg(void) ;
+uint8   SD_CD_Read(void) ;
+uint8   SD_CD_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SD_CD_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SD_CD_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SD_CD_DM_RES_UP          PIN_DM_RES_UP
+#define SD_CD_DM_RES_DWN         PIN_DM_RES_DWN
+#define SD_CD_DM_OD_LO           PIN_DM_OD_LO
+#define SD_CD_DM_OD_HI           PIN_DM_OD_HI
+#define SD_CD_DM_STRONG          PIN_DM_STRONG
+#define SD_CD_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SD_CD_MASK               SD_CD__MASK
+#define SD_CD_SHIFT              SD_CD__SHIFT
+#define SD_CD_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SD_CD_PS                     (* (reg8 *) SD_CD__PS)
+/* Data Register */
+#define SD_CD_DR                     (* (reg8 *) SD_CD__DR)
+/* Port Number */
+#define SD_CD_PRT_NUM                (* (reg8 *) SD_CD__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SD_CD_AG                     (* (reg8 *) SD_CD__AG)                       
+/* Analog MUX bux enable */
+#define SD_CD_AMUX                   (* (reg8 *) SD_CD__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SD_CD_BIE                    (* (reg8 *) SD_CD__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SD_CD_BIT_MASK               (* (reg8 *) SD_CD__BIT_MASK)
+/* Bypass Enable */
+#define SD_CD_BYP                    (* (reg8 *) SD_CD__BYP)
+/* Port wide control signals */                                                   
+#define SD_CD_CTL                    (* (reg8 *) SD_CD__CTL)
+/* Drive Modes */
+#define SD_CD_DM0                    (* (reg8 *) SD_CD__DM0) 
+#define SD_CD_DM1                    (* (reg8 *) SD_CD__DM1)
+#define SD_CD_DM2                    (* (reg8 *) SD_CD__DM2) 
+/* Input Buffer Disable Override */
+#define SD_CD_INP_DIS                (* (reg8 *) SD_CD__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SD_CD_LCD_COM_SEG            (* (reg8 *) SD_CD__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SD_CD_LCD_EN                 (* (reg8 *) SD_CD__LCD_EN)
+/* Slew Rate Control */
+#define SD_CD_SLW                    (* (reg8 *) SD_CD__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SD_CD_PRTDSI__CAPS_SEL       (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SD_CD_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SD_CD_PRTDSI__OE_SEL0        (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) 
+#define SD_CD_PRTDSI__OE_SEL1        (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SD_CD_PRTDSI__OUT_SEL0       (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) 
+#define SD_CD_PRTDSI__OUT_SEL1       (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SD_CD_PRTDSI__SYNC_OUT       (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SD_CD__INTSTAT)  /* Interrupt Registers */
+
+    #define SD_CD_INTSTAT                (* (reg8 *) SD_CD__INTSTAT)
+    #define SD_CD_SNAP                   (* (reg8 *) SD_CD__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SD_CD_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: SD_CD.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */
-#define CY_PINS_SD_CD_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SD_CD_0		(SD_CD__0__PC)
-
-#endif /* End Pins SD_CD_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CD.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */
+#define CY_PINS_SD_CD_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SD_CD_0		(SD_CD__0__PC)
+
+#endif /* End Pins SD_CD_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: SD_CS.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "SD_CS.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: SD_CS_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void SD_CS_Write(uint8 value) 
-{
-    uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));
-    SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CS_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  SD_CS_DM_STRONG     Strong Drive 
-*  SD_CS_DM_OD_HI      Open Drain, Drives High 
-*  SD_CS_DM_OD_LO      Open Drain, Drives Low 
-*  SD_CS_DM_RES_UP     Resistive Pull Up 
-*  SD_CS_DM_RES_DWN    Resistive Pull Down 
-*  SD_CS_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  SD_CS_DM_DIG_HIZ    High Impedance Digital 
-*  SD_CS_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void SD_CS_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(SD_CS_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CS_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro SD_CS_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 SD_CS_Read(void) 
-{
-    return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_CS_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 SD_CS_ReadDataReg(void) 
-{
-    return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(SD_CS_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: SD_CS_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 SD_CS_ClearInterrupt(void) 
-    {
-        return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CS.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SD_CS.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SD_CS_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SD_CS_Write(uint8 value) 
+{
+    uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));
+    SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CS_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CS_DM_STRONG     Strong Drive 
+*  SD_CS_DM_OD_HI      Open Drain, Drives High 
+*  SD_CS_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CS_DM_RES_UP     Resistive Pull Up 
+*  SD_CS_DM_RES_DWN    Resistive Pull Down 
+*  SD_CS_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CS_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CS_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SD_CS_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SD_CS_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CS_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SD_CS_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SD_CS_Read(void) 
+{
+    return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_CS_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SD_CS_ReadDataReg(void) 
+{
+    return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SD_CS_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SD_CS_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SD_CS_ClearInterrupt(void) 
+    {
+        return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: SD_CS.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */
-#define CY_PINS_SD_CS_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "SD_CS_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    SD_CS_Write(uint8 value) ;
-void    SD_CS_SetDriveMode(uint8 mode) ;
-uint8   SD_CS_ReadDataReg(void) ;
-uint8   SD_CS_Read(void) ;
-uint8   SD_CS_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define SD_CS_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define SD_CS_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define SD_CS_DM_RES_UP          PIN_DM_RES_UP
-#define SD_CS_DM_RES_DWN         PIN_DM_RES_DWN
-#define SD_CS_DM_OD_LO           PIN_DM_OD_LO
-#define SD_CS_DM_OD_HI           PIN_DM_OD_HI
-#define SD_CS_DM_STRONG          PIN_DM_STRONG
-#define SD_CS_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define SD_CS_MASK               SD_CS__MASK
-#define SD_CS_SHIFT              SD_CS__SHIFT
-#define SD_CS_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define SD_CS_PS                     (* (reg8 *) SD_CS__PS)
-/* Data Register */
-#define SD_CS_DR                     (* (reg8 *) SD_CS__DR)
-/* Port Number */
-#define SD_CS_PRT_NUM                (* (reg8 *) SD_CS__PRT) 
-/* Connect to Analog Globals */                                                  
-#define SD_CS_AG                     (* (reg8 *) SD_CS__AG)                       
-/* Analog MUX bux enable */
-#define SD_CS_AMUX                   (* (reg8 *) SD_CS__AMUX) 
-/* Bidirectional Enable */                                                        
-#define SD_CS_BIE                    (* (reg8 *) SD_CS__BIE)
-/* Bit-mask for Aliased Register Access */
-#define SD_CS_BIT_MASK               (* (reg8 *) SD_CS__BIT_MASK)
-/* Bypass Enable */
-#define SD_CS_BYP                    (* (reg8 *) SD_CS__BYP)
-/* Port wide control signals */                                                   
-#define SD_CS_CTL                    (* (reg8 *) SD_CS__CTL)
-/* Drive Modes */
-#define SD_CS_DM0                    (* (reg8 *) SD_CS__DM0) 
-#define SD_CS_DM1                    (* (reg8 *) SD_CS__DM1)
-#define SD_CS_DM2                    (* (reg8 *) SD_CS__DM2) 
-/* Input Buffer Disable Override */
-#define SD_CS_INP_DIS                (* (reg8 *) SD_CS__INP_DIS)
-/* LCD Common or Segment Drive */
-#define SD_CS_LCD_COM_SEG            (* (reg8 *) SD_CS__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define SD_CS_LCD_EN                 (* (reg8 *) SD_CS__LCD_EN)
-/* Slew Rate Control */
-#define SD_CS_SLW                    (* (reg8 *) SD_CS__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define SD_CS_PRTDSI__CAPS_SEL       (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define SD_CS_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define SD_CS_PRTDSI__OE_SEL0        (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) 
-#define SD_CS_PRTDSI__OE_SEL1        (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define SD_CS_PRTDSI__OUT_SEL0       (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) 
-#define SD_CS_PRTDSI__OUT_SEL1       (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define SD_CS_PRTDSI__SYNC_OUT       (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) 
-
-
-#if defined(SD_CS__INTSTAT)  /* Interrupt Registers */
-
-    #define SD_CS_INTSTAT                (* (reg8 *) SD_CS__INTSTAT)
-    #define SD_CS_SNAP                   (* (reg8 *) SD_CS__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_SD_CS_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CS.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */
+#define CY_PINS_SD_CS_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SD_CS_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SD_CS_Write(uint8 value) ;
+void    SD_CS_SetDriveMode(uint8 mode) ;
+uint8   SD_CS_ReadDataReg(void) ;
+uint8   SD_CS_Read(void) ;
+uint8   SD_CS_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SD_CS_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SD_CS_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SD_CS_DM_RES_UP          PIN_DM_RES_UP
+#define SD_CS_DM_RES_DWN         PIN_DM_RES_DWN
+#define SD_CS_DM_OD_LO           PIN_DM_OD_LO
+#define SD_CS_DM_OD_HI           PIN_DM_OD_HI
+#define SD_CS_DM_STRONG          PIN_DM_STRONG
+#define SD_CS_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SD_CS_MASK               SD_CS__MASK
+#define SD_CS_SHIFT              SD_CS__SHIFT
+#define SD_CS_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SD_CS_PS                     (* (reg8 *) SD_CS__PS)
+/* Data Register */
+#define SD_CS_DR                     (* (reg8 *) SD_CS__DR)
+/* Port Number */
+#define SD_CS_PRT_NUM                (* (reg8 *) SD_CS__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SD_CS_AG                     (* (reg8 *) SD_CS__AG)                       
+/* Analog MUX bux enable */
+#define SD_CS_AMUX                   (* (reg8 *) SD_CS__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SD_CS_BIE                    (* (reg8 *) SD_CS__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SD_CS_BIT_MASK               (* (reg8 *) SD_CS__BIT_MASK)
+/* Bypass Enable */
+#define SD_CS_BYP                    (* (reg8 *) SD_CS__BYP)
+/* Port wide control signals */                                                   
+#define SD_CS_CTL                    (* (reg8 *) SD_CS__CTL)
+/* Drive Modes */
+#define SD_CS_DM0                    (* (reg8 *) SD_CS__DM0) 
+#define SD_CS_DM1                    (* (reg8 *) SD_CS__DM1)
+#define SD_CS_DM2                    (* (reg8 *) SD_CS__DM2) 
+/* Input Buffer Disable Override */
+#define SD_CS_INP_DIS                (* (reg8 *) SD_CS__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SD_CS_LCD_COM_SEG            (* (reg8 *) SD_CS__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SD_CS_LCD_EN                 (* (reg8 *) SD_CS__LCD_EN)
+/* Slew Rate Control */
+#define SD_CS_SLW                    (* (reg8 *) SD_CS__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SD_CS_PRTDSI__CAPS_SEL       (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SD_CS_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SD_CS_PRTDSI__OE_SEL0        (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) 
+#define SD_CS_PRTDSI__OE_SEL1        (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SD_CS_PRTDSI__OUT_SEL0       (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) 
+#define SD_CS_PRTDSI__OUT_SEL1       (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SD_CS_PRTDSI__SYNC_OUT       (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SD_CS__INTSTAT)  /* Interrupt Registers */
+
+    #define SD_CS_INTSTAT                (* (reg8 *) SD_CS__INTSTAT)
+    #define SD_CS_SNAP                   (* (reg8 *) SD_CS__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SD_CS_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: SD_CS.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */
-#define CY_PINS_SD_CS_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SD_CS_0		(SD_CS__0__PC)
-
-#endif /* End Pins SD_CS_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_CS.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */
+#define CY_PINS_SD_CS_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SD_CS_0		(SD_CS__0__PC)
+
+#endif /* End Pins SD_CS_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c

@@ -1,521 +1,521 @@
-/*******************************************************************************
-* File Name: SD_Data_Clk.c
-* Version 2.20
-*
-*  Description:
-*   This file provides the source code to the API for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include <cydevice_trm.h>
-#include "SD_Data_Clk.h"
-
-/* Clock Distribution registers. */
-#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
-#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
-#define BCFG2_MASK               (0x80u)
-#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
-#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
-
-#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_Start
-********************************************************************************
-*
-* Summary:
-*  Starts the clock. Note that on startup, clocks may be already running if the
-*  "Start on Reset" option is enabled in the DWR.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_Start(void) 
-{
-    /* Set the bit to enable the clock. */
-    SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK;
-	SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_Stop
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and returns immediately. This API does not require the
-*  source clock to be running but may return before the hardware is actually
-*  disabled. If the settings of the clock are changed after calling this
-*  function, the clock may glitch when it is started. To avoid the clock
-*  glitch, use the StopBlock function.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_Stop(void) 
-{
-    /* Clear the bit to disable the clock. */
-    SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
-	SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
-}
-
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_StopBlock
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and waits for the hardware to actually be disabled before
-*  returning. This ensures that the clock is never truncated (high part of the
-*  cycle will terminate before the clock is disabled and the API returns).
-*  Note that the source clock must be running or this API will never return as
-*  a stopped clock cannot be disabled.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_StopBlock(void) 
-{
-    if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)
-    {
-#if HAS_CLKDIST_LD_DISABLE
-        uint16 oldDivider;
-
-        CLK_DIST_LD = 0u;
-
-        /* Clear all the mask bits except ours. */
-#if defined(SD_Data_Clk__CFG3)
-        CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;
-        CLK_DIST_DMASK = 0x00u;
-#else
-        CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;
-        CLK_DIST_AMASK = 0x00u;
-#endif /* SD_Data_Clk__CFG3 */
-
-        /* Clear mask of bus clock. */
-        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-        oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR);
-        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
-
-        /* Wait for clock to be disabled */
-        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-        /* Clear the bit to disable the clock. */
-        SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
-        SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-        /* Clear the disable bit */
-        CLK_DIST_LD = 0x00u;
-        CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider);
-#endif /* HAS_CLKDIST_LD_DISABLE */
-    }
-}
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_StandbyPower
-********************************************************************************
-*
-* Summary:
-*  Sets whether the clock is active in standby mode.
-*
-* Parameters:
-*  state:  0 to disable clock during standby, nonzero to enable.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_StandbyPower(uint8 state) 
-{
-    if(state == 0u)
-    {
-        SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
-    }
-    else
-    {
-        SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_SetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Modifies the clock divider and, thus, the frequency. When the clock divider
-*  register is set to zero or changed from zero, the clock will be temporarily
-*  disabled in order to change the SSS mode bit. If the clock is enabled when
-*  SetDividerRegister is called, then the source clock must be running.
-*
-* Parameters:
-*  clkDivider:  Divider register value (0-65,535). This value is NOT the
-*    divider; the clock hardware divides by clkDivider plus one. For example,
-*    to divide the clock by 2, this parameter should be set to 1.
-*  restart:  If nonzero, restarts the clock divider: the current clock cycle
-*   will be truncated and the new divide value will take effect immediately. If
-*   zero, the new divide value will take effect at the end of the current clock
-*   cycle.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)
-                                
-{
-    uint8 enabled;
-
-    uint8 currSrc = SD_Data_Clk_GetSourceRegister();
-    uint16 oldDivider = SD_Data_Clk_GetDividerRegister();
-
-    if (clkDivider != oldDivider)
-    {
-        enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK;
-
-        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
-        {
-            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
-            if (oldDivider == 0u)
-            {
-                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
-                /* don't halt the clock.  Using the shadow load isn't required as the       */
-                /* divider is ignored while SSS is set.                                     */
-                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
-                SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);
-            }
-            else
-            {
-                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
-                /* it without bothering with the shadow load.                               */
-                SD_Data_Clk_MOD_SRC |= CYCLK_SSS;
-                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
-            }
-        }
-        else
-        {
-			
-            if (enabled != 0u)
-            {
-                CLK_DIST_LD = 0x00u;
-
-                /* Clear all the mask bits except ours. */
-#if defined(SD_Data_Clk__CFG3)
-                CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;
-                CLK_DIST_DMASK = 0x00u;
-#else
-                CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;
-                CLK_DIST_AMASK = 0x00u;
-#endif /* SD_Data_Clk__CFG3 */
-                /* Clear mask of bus clock. */
-                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-                /* If clock is currently enabled, disable it if async or going from N-to-1*/
-                if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
-                {
-#if HAS_CLKDIST_LD_DISABLE
-                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
-
-                    /* Wait for clock to be disabled */
-                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-                    SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-                    /* Clear the disable bit */
-                    CLK_DIST_LD = 0x00u;
-#endif /* HAS_CLKDIST_LD_DISABLE */
-                }
-            }
-
-            /* Load divide value. */
-            if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)
-            {
-                /* If the clock is still enabled, use the shadow registers */
-                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
-
-                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
-                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-            }
-            else
-            {
-                /* If the clock is disabled, set the divider directly */
-                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
-				SD_Data_Clk_CLKEN |= enabled;
-            }
-        }
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_GetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock divider register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Divide value of the clock minus 1. For example, if the clock is set to
-*  divide by 2, the return value will be 1.
-*
-*******************************************************************************/
-uint16 SD_Data_Clk_GetDividerRegister(void) 
-{
-    return CY_GET_REG16(SD_Data_Clk_DIV_PTR);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_SetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Sets flags that control the operating mode of the clock. This function only
-*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
-*  To clear flags, use the ClearModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) 
-{
-    SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_ClearModeRegister
-********************************************************************************
-*
-* Summary:
-*  Clears flags that control the operating mode of the clock. This function
-*  only changes flags from 1 to 0; flags that are already 0 will remain
-*  unchanged. To set flags, use the SetModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) 
-{
-    SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK));
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_GetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock mode register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Bit mask representing the enabled mode bits. See the SetModeRegister and
-*  ClearModeRegister descriptions for details about the mode bits.
-*
-*******************************************************************************/
-uint8 SD_Data_Clk_GetModeRegister(void) 
-{
-    return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_SetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the input source of the clock. The clock must be disabled before
-*  changing the source. The old and new clock sources must be running.
-*
-* Parameters:
-*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
-*   following input sources:
-*   - CYCLK_SRC_SEL_SYNC_DIG
-*   - CYCLK_SRC_SEL_IMO
-*   - CYCLK_SRC_SEL_XTALM
-*   - CYCLK_SRC_SEL_ILO
-*   - CYCLK_SRC_SEL_PLL
-*   - CYCLK_SRC_SEL_XTALK
-*   - CYCLK_SRC_SEL_DSI_G
-*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
-*   See the Technical Reference Manual for details on clock sources.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_SetSourceRegister(uint8 clkSource) 
-{
-    uint16 currDiv = SD_Data_Clk_GetDividerRegister();
-    uint8 oldSrc = SD_Data_Clk_GetSourceRegister();
-
-    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching to Master and divider is 1, set SSS, which will output master, */
-        /* then set the source so we are consistent.                                */
-        SD_Data_Clk_MOD_SRC |= CYCLK_SSS;
-        SD_Data_Clk_MOD_SRC =
-            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
-    }
-    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching from Master to not and divider is 1, set source, so we don't   */
-        /* lock when we clear SSS.                                                  */
-        SD_Data_Clk_MOD_SRC =
-            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
-        SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);
-    }
-    else
-    {
-        SD_Data_Clk_MOD_SRC =
-            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_GetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the input source of the clock.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  The input source of the clock. See SetSourceRegister for details.
-*
-*******************************************************************************/
-uint8 SD_Data_Clk_GetSourceRegister(void) 
-{
-    return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK;
-}
-
-
-#if defined(SD_Data_Clk__CFG3)
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_SetPhaseRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the phase delay of the analog clock. This function is only available
-*  for analog clocks. The clock must be disabled before changing the phase
-*  delay to avoid glitches.
-*
-* Parameters:
-*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
-*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
-*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
-*   produces a 10ns delay.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) 
-{
-    SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Data_Clk_GetPhase
-********************************************************************************
-*
-* Summary:
-*  Gets the phase delay of the analog clock. This function is only available
-*  for analog clocks.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Phase of the analog clock. See SetPhaseRegister for details.
-*
-*******************************************************************************/
-uint8 SD_Data_Clk_GetPhaseRegister(void) 
-{
-    return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK;
-}
-
-#endif /* SD_Data_Clk__CFG3 */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_Data_Clk.c
+* Version 2.20
+*
+*  Description:
+*   This file provides the source code to the API for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SD_Data_Clk.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK               (0x80u)
+#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_Start
+********************************************************************************
+*
+* Summary:
+*  Starts the clock. Note that on startup, clocks may be already running if the
+*  "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_Start(void) 
+{
+    /* Set the bit to enable the clock. */
+    SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK;
+	SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and returns immediately. This API does not require the
+*  source clock to be running but may return before the hardware is actually
+*  disabled. If the settings of the clock are changed after calling this
+*  function, the clock may glitch when it is started. To avoid the clock
+*  glitch, use the StopBlock function.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_Stop(void) 
+{
+    /* Clear the bit to disable the clock. */
+    SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
+	SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_StopBlock
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and waits for the hardware to actually be disabled before
+*  returning. This ensures that the clock is never truncated (high part of the
+*  cycle will terminate before the clock is disabled and the API returns).
+*  Note that the source clock must be running or this API will never return as
+*  a stopped clock cannot be disabled.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_StopBlock(void) 
+{
+    if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)
+    {
+#if HAS_CLKDIST_LD_DISABLE
+        uint16 oldDivider;
+
+        CLK_DIST_LD = 0u;
+
+        /* Clear all the mask bits except ours. */
+#if defined(SD_Data_Clk__CFG3)
+        CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;
+        CLK_DIST_DMASK = 0x00u;
+#else
+        CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;
+        CLK_DIST_AMASK = 0x00u;
+#endif /* SD_Data_Clk__CFG3 */
+
+        /* Clear mask of bus clock. */
+        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+        oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR);
+        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+        /* Wait for clock to be disabled */
+        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+        /* Clear the bit to disable the clock. */
+        SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
+        SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+        /* Clear the disable bit */
+        CLK_DIST_LD = 0x00u;
+        CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+    }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_StandbyPower
+********************************************************************************
+*
+* Summary:
+*  Sets whether the clock is active in standby mode.
+*
+* Parameters:
+*  state:  0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_StandbyPower(uint8 state) 
+{
+    if(state == 0u)
+    {
+        SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);
+    }
+    else
+    {
+        SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Modifies the clock divider and, thus, the frequency. When the clock divider
+*  register is set to zero or changed from zero, the clock will be temporarily
+*  disabled in order to change the SSS mode bit. If the clock is enabled when
+*  SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+*  clkDivider:  Divider register value (0-65,535). This value is NOT the
+*    divider; the clock hardware divides by clkDivider plus one. For example,
+*    to divide the clock by 2, this parameter should be set to 1.
+*  restart:  If nonzero, restarts the clock divider: the current clock cycle
+*   will be truncated and the new divide value will take effect immediately. If
+*   zero, the new divide value will take effect at the end of the current clock
+*   cycle.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)
+                                
+{
+    uint8 enabled;
+
+    uint8 currSrc = SD_Data_Clk_GetSourceRegister();
+    uint16 oldDivider = SD_Data_Clk_GetDividerRegister();
+
+    if (clkDivider != oldDivider)
+    {
+        enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK;
+
+        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+        {
+            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
+            if (oldDivider == 0u)
+            {
+                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
+                /* don't halt the clock.  Using the shadow load isn't required as the       */
+                /* divider is ignored while SSS is set.                                     */
+                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
+                SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);
+            }
+            else
+            {
+                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
+                /* it without bothering with the shadow load.                               */
+                SD_Data_Clk_MOD_SRC |= CYCLK_SSS;
+                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
+            }
+        }
+        else
+        {
+			
+            if (enabled != 0u)
+            {
+                CLK_DIST_LD = 0x00u;
+
+                /* Clear all the mask bits except ours. */
+#if defined(SD_Data_Clk__CFG3)
+                CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;
+                CLK_DIST_DMASK = 0x00u;
+#else
+                CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;
+                CLK_DIST_AMASK = 0x00u;
+#endif /* SD_Data_Clk__CFG3 */
+                /* Clear mask of bus clock. */
+                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+                /* If clock is currently enabled, disable it if async or going from N-to-1*/
+                if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+                {
+#if HAS_CLKDIST_LD_DISABLE
+                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+                    /* Wait for clock to be disabled */
+                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+                    SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+                    /* Clear the disable bit */
+                    CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+                }
+            }
+
+            /* Load divide value. */
+            if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)
+            {
+                /* If the clock is still enabled, use the shadow registers */
+                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+            }
+            else
+            {
+                /* If the clock is disabled, set the divider directly */
+                CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);
+				SD_Data_Clk_CLKEN |= enabled;
+            }
+        }
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock divider register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Divide value of the clock minus 1. For example, if the clock is set to
+*  divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SD_Data_Clk_GetDividerRegister(void) 
+{
+    return CY_GET_REG16(SD_Data_Clk_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_SetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Sets flags that control the operating mode of the clock. This function only
+*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+*  To clear flags, use the ClearModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) 
+{
+    SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+*  Clears flags that control the operating mode of the clock. This function
+*  only changes flags from 1 to 0; flags that are already 0 will remain
+*  unchanged. To set flags, use the SetModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) 
+{
+    SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_GetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock mode register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Bit mask representing the enabled mode bits. See the SetModeRegister and
+*  ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SD_Data_Clk_GetModeRegister(void) 
+{
+    return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the input source of the clock. The clock must be disabled before
+*  changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+*   following input sources:
+*   - CYCLK_SRC_SEL_SYNC_DIG
+*   - CYCLK_SRC_SEL_IMO
+*   - CYCLK_SRC_SEL_XTALM
+*   - CYCLK_SRC_SEL_ILO
+*   - CYCLK_SRC_SEL_PLL
+*   - CYCLK_SRC_SEL_XTALK
+*   - CYCLK_SRC_SEL_DSI_G
+*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+*   See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_SetSourceRegister(uint8 clkSource) 
+{
+    uint16 currDiv = SD_Data_Clk_GetDividerRegister();
+    uint8 oldSrc = SD_Data_Clk_GetSourceRegister();
+
+    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching to Master and divider is 1, set SSS, which will output master, */
+        /* then set the source so we are consistent.                                */
+        SD_Data_Clk_MOD_SRC |= CYCLK_SSS;
+        SD_Data_Clk_MOD_SRC =
+            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
+    }
+    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching from Master to not and divider is 1, set source, so we don't   */
+        /* lock when we clear SSS.                                                  */
+        SD_Data_Clk_MOD_SRC =
+            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
+        SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);
+    }
+    else
+    {
+        SD_Data_Clk_MOD_SRC =
+            (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the input source of the clock.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SD_Data_Clk_GetSourceRegister(void) 
+{
+    return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK;
+}
+
+
+#if defined(SD_Data_Clk__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the phase delay of the analog clock. This function is only available
+*  for analog clocks. The clock must be disabled before changing the phase
+*  delay to avoid glitches.
+*
+* Parameters:
+*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
+*   produces a 10ns delay.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) 
+{
+    SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_Data_Clk_GetPhase
+********************************************************************************
+*
+* Summary:
+*  Gets the phase delay of the analog clock. This function is only available
+*  for analog clocks.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SD_Data_Clk_GetPhaseRegister(void) 
+{
+    return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK;
+}
+
+#endif /* SD_Data_Clk__CFG3 */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h

@@ -1,124 +1,124 @@
-/*******************************************************************************
-* File Name: SD_Data_Clk.h
-* Version 2.20
-*
-*  Description:
-*   Provides the function and constant definitions for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CLOCK_SD_Data_Clk_H)
-#define CY_CLOCK_SD_Data_Clk_H
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-
-/***************************************
-* Conditional Compilation Parameters
-***************************************/
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5LP) */
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void SD_Data_Clk_Start(void) ;
-void SD_Data_Clk_Stop(void) ;
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-void SD_Data_Clk_StopBlock(void) ;
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-void SD_Data_Clk_StandbyPower(uint8 state) ;
-void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) 
-                                ;
-uint16 SD_Data_Clk_GetDividerRegister(void) ;
-void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ;
-void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ;
-uint8 SD_Data_Clk_GetModeRegister(void) ;
-void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ;
-uint8 SD_Data_Clk_GetSourceRegister(void) ;
-#if defined(SD_Data_Clk__CFG3)
-void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ;
-uint8 SD_Data_Clk_GetPhaseRegister(void) ;
-#endif /* defined(SD_Data_Clk__CFG3) */
-
-#define SD_Data_Clk_Enable()                       SD_Data_Clk_Start()
-#define SD_Data_Clk_Disable()                      SD_Data_Clk_Stop()
-#define SD_Data_Clk_SetDivider(clkDivider)         SD_Data_Clk_SetDividerRegister(clkDivider, 1u)
-#define SD_Data_Clk_SetDividerValue(clkDivider)    SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
-#define SD_Data_Clk_SetMode(clkMode)               SD_Data_Clk_SetModeRegister(clkMode)
-#define SD_Data_Clk_SetSource(clkSource)           SD_Data_Clk_SetSourceRegister(clkSource)
-#if defined(SD_Data_Clk__CFG3)
-#define SD_Data_Clk_SetPhase(clkPhase)             SD_Data_Clk_SetPhaseRegister(clkPhase)
-#define SD_Data_Clk_SetPhaseValue(clkPhase)        SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)
-#endif /* defined(SD_Data_Clk__CFG3) */
-
-
-/***************************************
-*             Registers
-***************************************/
-
-/* Register to enable or disable the clock */
-#define SD_Data_Clk_CLKEN              (* (reg8 *) SD_Data_Clk__PM_ACT_CFG)
-#define SD_Data_Clk_CLKEN_PTR          ((reg8 *) SD_Data_Clk__PM_ACT_CFG)
-
-/* Register to enable or disable the clock */
-#define SD_Data_Clk_CLKSTBY            (* (reg8 *) SD_Data_Clk__PM_STBY_CFG)
-#define SD_Data_Clk_CLKSTBY_PTR        ((reg8 *) SD_Data_Clk__PM_STBY_CFG)
-
-/* Clock LSB divider configuration register. */
-#define SD_Data_Clk_DIV_LSB            (* (reg8 *) SD_Data_Clk__CFG0)
-#define SD_Data_Clk_DIV_LSB_PTR        ((reg8 *) SD_Data_Clk__CFG0)
-#define SD_Data_Clk_DIV_PTR            ((reg16 *) SD_Data_Clk__CFG0)
-
-/* Clock MSB divider configuration register. */
-#define SD_Data_Clk_DIV_MSB            (* (reg8 *) SD_Data_Clk__CFG1)
-#define SD_Data_Clk_DIV_MSB_PTR        ((reg8 *) SD_Data_Clk__CFG1)
-
-/* Mode and source configuration register */
-#define SD_Data_Clk_MOD_SRC            (* (reg8 *) SD_Data_Clk__CFG2)
-#define SD_Data_Clk_MOD_SRC_PTR        ((reg8 *) SD_Data_Clk__CFG2)
-
-#if defined(SD_Data_Clk__CFG3)
-/* Analog clock phase configuration register */
-#define SD_Data_Clk_PHASE              (* (reg8 *) SD_Data_Clk__CFG3)
-#define SD_Data_Clk_PHASE_PTR          ((reg8 *) SD_Data_Clk__CFG3)
-#endif /* defined(SD_Data_Clk__CFG3) */
-
-
-/**************************************
-*       Register Constants
-**************************************/
-
-/* Power manager register masks */
-#define SD_Data_Clk_CLKEN_MASK         SD_Data_Clk__PM_ACT_MSK
-#define SD_Data_Clk_CLKSTBY_MASK       SD_Data_Clk__PM_STBY_MSK
-
-/* CFG2 field masks */
-#define SD_Data_Clk_SRC_SEL_MSK        SD_Data_Clk__CFG2_SRC_SEL_MASK
-#define SD_Data_Clk_MODE_MASK          (~(SD_Data_Clk_SRC_SEL_MSK))
-
-#if defined(SD_Data_Clk__CFG3)
-/* CFG3 phase mask */
-#define SD_Data_Clk_PHASE_MASK         SD_Data_Clk__CFG3_PHASE_DLY_MASK
-#endif /* defined(SD_Data_Clk__CFG3) */
-
-#endif /* CY_CLOCK_SD_Data_Clk_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_Data_Clk.h
+* Version 2.20
+*
+*  Description:
+*   Provides the function and constant definitions for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SD_Data_Clk_H)
+#define CY_CLOCK_SD_Data_Clk_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void SD_Data_Clk_Start(void) ;
+void SD_Data_Clk_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SD_Data_Clk_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SD_Data_Clk_StandbyPower(uint8 state) ;
+void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) 
+                                ;
+uint16 SD_Data_Clk_GetDividerRegister(void) ;
+void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ;
+void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SD_Data_Clk_GetModeRegister(void) ;
+void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ;
+uint8 SD_Data_Clk_GetSourceRegister(void) ;
+#if defined(SD_Data_Clk__CFG3)
+void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SD_Data_Clk_GetPhaseRegister(void) ;
+#endif /* defined(SD_Data_Clk__CFG3) */
+
+#define SD_Data_Clk_Enable()                       SD_Data_Clk_Start()
+#define SD_Data_Clk_Disable()                      SD_Data_Clk_Stop()
+#define SD_Data_Clk_SetDivider(clkDivider)         SD_Data_Clk_SetDividerRegister(clkDivider, 1u)
+#define SD_Data_Clk_SetDividerValue(clkDivider)    SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SD_Data_Clk_SetMode(clkMode)               SD_Data_Clk_SetModeRegister(clkMode)
+#define SD_Data_Clk_SetSource(clkSource)           SD_Data_Clk_SetSourceRegister(clkSource)
+#if defined(SD_Data_Clk__CFG3)
+#define SD_Data_Clk_SetPhase(clkPhase)             SD_Data_Clk_SetPhaseRegister(clkPhase)
+#define SD_Data_Clk_SetPhaseValue(clkPhase)        SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SD_Data_Clk__CFG3) */
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SD_Data_Clk_CLKEN              (* (reg8 *) SD_Data_Clk__PM_ACT_CFG)
+#define SD_Data_Clk_CLKEN_PTR          ((reg8 *) SD_Data_Clk__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SD_Data_Clk_CLKSTBY            (* (reg8 *) SD_Data_Clk__PM_STBY_CFG)
+#define SD_Data_Clk_CLKSTBY_PTR        ((reg8 *) SD_Data_Clk__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SD_Data_Clk_DIV_LSB            (* (reg8 *) SD_Data_Clk__CFG0)
+#define SD_Data_Clk_DIV_LSB_PTR        ((reg8 *) SD_Data_Clk__CFG0)
+#define SD_Data_Clk_DIV_PTR            ((reg16 *) SD_Data_Clk__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SD_Data_Clk_DIV_MSB            (* (reg8 *) SD_Data_Clk__CFG1)
+#define SD_Data_Clk_DIV_MSB_PTR        ((reg8 *) SD_Data_Clk__CFG1)
+
+/* Mode and source configuration register */
+#define SD_Data_Clk_MOD_SRC            (* (reg8 *) SD_Data_Clk__CFG2)
+#define SD_Data_Clk_MOD_SRC_PTR        ((reg8 *) SD_Data_Clk__CFG2)
+
+#if defined(SD_Data_Clk__CFG3)
+/* Analog clock phase configuration register */
+#define SD_Data_Clk_PHASE              (* (reg8 *) SD_Data_Clk__CFG3)
+#define SD_Data_Clk_PHASE_PTR          ((reg8 *) SD_Data_Clk__CFG3)
+#endif /* defined(SD_Data_Clk__CFG3) */
+
+
+/**************************************
+*       Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SD_Data_Clk_CLKEN_MASK         SD_Data_Clk__PM_ACT_MSK
+#define SD_Data_Clk_CLKSTBY_MASK       SD_Data_Clk__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SD_Data_Clk_SRC_SEL_MSK        SD_Data_Clk__CFG2_SRC_SEL_MASK
+#define SD_Data_Clk_MODE_MASK          (~(SD_Data_Clk_SRC_SEL_MSK))
+
+#if defined(SD_Data_Clk__CFG3)
+/* CFG3 phase mask */
+#define SD_Data_Clk_PHASE_MASK         SD_Data_Clk__CFG3_PHASE_DLY_MASK
+#endif /* defined(SD_Data_Clk__CFG3) */
+
+#endif /* CY_CLOCK_SD_Data_Clk_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: SD_MISO.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "SD_MISO.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: SD_MISO_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void SD_MISO_Write(uint8 value) 
-{
-    uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK));
-    SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MISO_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  SD_MISO_DM_STRONG     Strong Drive 
-*  SD_MISO_DM_OD_HI      Open Drain, Drives High 
-*  SD_MISO_DM_OD_LO      Open Drain, Drives Low 
-*  SD_MISO_DM_RES_UP     Resistive Pull Up 
-*  SD_MISO_DM_RES_DWN    Resistive Pull Down 
-*  SD_MISO_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  SD_MISO_DM_DIG_HIZ    High Impedance Digital 
-*  SD_MISO_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void SD_MISO_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(SD_MISO_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MISO_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro SD_MISO_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 SD_MISO_Read(void) 
-{
-    return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MISO_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 SD_MISO_ReadDataReg(void) 
-{
-    return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(SD_MISO_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: SD_MISO_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 SD_MISO_ClearInterrupt(void) 
-    {
-        return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MISO.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SD_MISO.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SD_MISO_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SD_MISO_Write(uint8 value) 
+{
+    uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK));
+    SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MISO_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MISO_DM_STRONG     Strong Drive 
+*  SD_MISO_DM_OD_HI      Open Drain, Drives High 
+*  SD_MISO_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MISO_DM_RES_UP     Resistive Pull Up 
+*  SD_MISO_DM_RES_DWN    Resistive Pull Down 
+*  SD_MISO_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MISO_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MISO_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SD_MISO_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SD_MISO_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MISO_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SD_MISO_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SD_MISO_Read(void) 
+{
+    return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MISO_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SD_MISO_ReadDataReg(void) 
+{
+    return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SD_MISO_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SD_MISO_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SD_MISO_ClearInterrupt(void) 
+    {
+        return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: SD_MISO.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */
-#define CY_PINS_SD_MISO_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "SD_MISO_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    SD_MISO_Write(uint8 value) ;
-void    SD_MISO_SetDriveMode(uint8 mode) ;
-uint8   SD_MISO_ReadDataReg(void) ;
-uint8   SD_MISO_Read(void) ;
-uint8   SD_MISO_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define SD_MISO_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define SD_MISO_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define SD_MISO_DM_RES_UP          PIN_DM_RES_UP
-#define SD_MISO_DM_RES_DWN         PIN_DM_RES_DWN
-#define SD_MISO_DM_OD_LO           PIN_DM_OD_LO
-#define SD_MISO_DM_OD_HI           PIN_DM_OD_HI
-#define SD_MISO_DM_STRONG          PIN_DM_STRONG
-#define SD_MISO_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define SD_MISO_MASK               SD_MISO__MASK
-#define SD_MISO_SHIFT              SD_MISO__SHIFT
-#define SD_MISO_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define SD_MISO_PS                     (* (reg8 *) SD_MISO__PS)
-/* Data Register */
-#define SD_MISO_DR                     (* (reg8 *) SD_MISO__DR)
-/* Port Number */
-#define SD_MISO_PRT_NUM                (* (reg8 *) SD_MISO__PRT) 
-/* Connect to Analog Globals */                                                  
-#define SD_MISO_AG                     (* (reg8 *) SD_MISO__AG)                       
-/* Analog MUX bux enable */
-#define SD_MISO_AMUX                   (* (reg8 *) SD_MISO__AMUX) 
-/* Bidirectional Enable */                                                        
-#define SD_MISO_BIE                    (* (reg8 *) SD_MISO__BIE)
-/* Bit-mask for Aliased Register Access */
-#define SD_MISO_BIT_MASK               (* (reg8 *) SD_MISO__BIT_MASK)
-/* Bypass Enable */
-#define SD_MISO_BYP                    (* (reg8 *) SD_MISO__BYP)
-/* Port wide control signals */                                                   
-#define SD_MISO_CTL                    (* (reg8 *) SD_MISO__CTL)
-/* Drive Modes */
-#define SD_MISO_DM0                    (* (reg8 *) SD_MISO__DM0) 
-#define SD_MISO_DM1                    (* (reg8 *) SD_MISO__DM1)
-#define SD_MISO_DM2                    (* (reg8 *) SD_MISO__DM2) 
-/* Input Buffer Disable Override */
-#define SD_MISO_INP_DIS                (* (reg8 *) SD_MISO__INP_DIS)
-/* LCD Common or Segment Drive */
-#define SD_MISO_LCD_COM_SEG            (* (reg8 *) SD_MISO__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define SD_MISO_LCD_EN                 (* (reg8 *) SD_MISO__LCD_EN)
-/* Slew Rate Control */
-#define SD_MISO_SLW                    (* (reg8 *) SD_MISO__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define SD_MISO_PRTDSI__CAPS_SEL       (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define SD_MISO_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define SD_MISO_PRTDSI__OE_SEL0        (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) 
-#define SD_MISO_PRTDSI__OE_SEL1        (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define SD_MISO_PRTDSI__OUT_SEL0       (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) 
-#define SD_MISO_PRTDSI__OUT_SEL1       (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define SD_MISO_PRTDSI__SYNC_OUT       (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) 
-
-
-#if defined(SD_MISO__INTSTAT)  /* Interrupt Registers */
-
-    #define SD_MISO_INTSTAT                (* (reg8 *) SD_MISO__INTSTAT)
-    #define SD_MISO_SNAP                   (* (reg8 *) SD_MISO__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_SD_MISO_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MISO.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */
+#define CY_PINS_SD_MISO_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SD_MISO_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SD_MISO_Write(uint8 value) ;
+void    SD_MISO_SetDriveMode(uint8 mode) ;
+uint8   SD_MISO_ReadDataReg(void) ;
+uint8   SD_MISO_Read(void) ;
+uint8   SD_MISO_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SD_MISO_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SD_MISO_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SD_MISO_DM_RES_UP          PIN_DM_RES_UP
+#define SD_MISO_DM_RES_DWN         PIN_DM_RES_DWN
+#define SD_MISO_DM_OD_LO           PIN_DM_OD_LO
+#define SD_MISO_DM_OD_HI           PIN_DM_OD_HI
+#define SD_MISO_DM_STRONG          PIN_DM_STRONG
+#define SD_MISO_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SD_MISO_MASK               SD_MISO__MASK
+#define SD_MISO_SHIFT              SD_MISO__SHIFT
+#define SD_MISO_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SD_MISO_PS                     (* (reg8 *) SD_MISO__PS)
+/* Data Register */
+#define SD_MISO_DR                     (* (reg8 *) SD_MISO__DR)
+/* Port Number */
+#define SD_MISO_PRT_NUM                (* (reg8 *) SD_MISO__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SD_MISO_AG                     (* (reg8 *) SD_MISO__AG)                       
+/* Analog MUX bux enable */
+#define SD_MISO_AMUX                   (* (reg8 *) SD_MISO__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SD_MISO_BIE                    (* (reg8 *) SD_MISO__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SD_MISO_BIT_MASK               (* (reg8 *) SD_MISO__BIT_MASK)
+/* Bypass Enable */
+#define SD_MISO_BYP                    (* (reg8 *) SD_MISO__BYP)
+/* Port wide control signals */                                                   
+#define SD_MISO_CTL                    (* (reg8 *) SD_MISO__CTL)
+/* Drive Modes */
+#define SD_MISO_DM0                    (* (reg8 *) SD_MISO__DM0) 
+#define SD_MISO_DM1                    (* (reg8 *) SD_MISO__DM1)
+#define SD_MISO_DM2                    (* (reg8 *) SD_MISO__DM2) 
+/* Input Buffer Disable Override */
+#define SD_MISO_INP_DIS                (* (reg8 *) SD_MISO__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SD_MISO_LCD_COM_SEG            (* (reg8 *) SD_MISO__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SD_MISO_LCD_EN                 (* (reg8 *) SD_MISO__LCD_EN)
+/* Slew Rate Control */
+#define SD_MISO_SLW                    (* (reg8 *) SD_MISO__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SD_MISO_PRTDSI__CAPS_SEL       (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SD_MISO_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SD_MISO_PRTDSI__OE_SEL0        (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) 
+#define SD_MISO_PRTDSI__OE_SEL1        (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SD_MISO_PRTDSI__OUT_SEL0       (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) 
+#define SD_MISO_PRTDSI__OUT_SEL1       (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SD_MISO_PRTDSI__SYNC_OUT       (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SD_MISO__INTSTAT)  /* Interrupt Registers */
+
+    #define SD_MISO_INTSTAT                (* (reg8 *) SD_MISO__INTSTAT)
+    #define SD_MISO_SNAP                   (* (reg8 *) SD_MISO__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SD_MISO_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: SD_MISO.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */
-#define CY_PINS_SD_MISO_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SD_MISO_0		(SD_MISO__0__PC)
-
-#endif /* End Pins SD_MISO_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MISO.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */
+#define CY_PINS_SD_MISO_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SD_MISO_0		(SD_MISO__0__PC)
+
+#endif /* End Pins SD_MISO_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: SD_MOSI.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "SD_MOSI.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: SD_MOSI_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void SD_MOSI_Write(uint8 value) 
-{
-    uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK));
-    SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MOSI_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  SD_MOSI_DM_STRONG     Strong Drive 
-*  SD_MOSI_DM_OD_HI      Open Drain, Drives High 
-*  SD_MOSI_DM_OD_LO      Open Drain, Drives Low 
-*  SD_MOSI_DM_RES_UP     Resistive Pull Up 
-*  SD_MOSI_DM_RES_DWN    Resistive Pull Down 
-*  SD_MOSI_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  SD_MOSI_DM_DIG_HIZ    High Impedance Digital 
-*  SD_MOSI_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void SD_MOSI_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(SD_MOSI_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MOSI_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro SD_MOSI_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 SD_MOSI_Read(void) 
-{
-    return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_MOSI_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 SD_MOSI_ReadDataReg(void) 
-{
-    return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(SD_MOSI_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: SD_MOSI_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 SD_MOSI_ClearInterrupt(void) 
-    {
-        return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MOSI.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SD_MOSI.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SD_MOSI_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SD_MOSI_Write(uint8 value) 
+{
+    uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK));
+    SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MOSI_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MOSI_DM_STRONG     Strong Drive 
+*  SD_MOSI_DM_OD_HI      Open Drain, Drives High 
+*  SD_MOSI_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MOSI_DM_RES_UP     Resistive Pull Up 
+*  SD_MOSI_DM_RES_DWN    Resistive Pull Down 
+*  SD_MOSI_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MOSI_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MOSI_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SD_MOSI_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SD_MOSI_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MOSI_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SD_MOSI_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SD_MOSI_Read(void) 
+{
+    return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_MOSI_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SD_MOSI_ReadDataReg(void) 
+{
+    return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SD_MOSI_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SD_MOSI_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SD_MOSI_ClearInterrupt(void) 
+    {
+        return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: SD_MOSI.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */
-#define CY_PINS_SD_MOSI_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "SD_MOSI_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    SD_MOSI_Write(uint8 value) ;
-void    SD_MOSI_SetDriveMode(uint8 mode) ;
-uint8   SD_MOSI_ReadDataReg(void) ;
-uint8   SD_MOSI_Read(void) ;
-uint8   SD_MOSI_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define SD_MOSI_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define SD_MOSI_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define SD_MOSI_DM_RES_UP          PIN_DM_RES_UP
-#define SD_MOSI_DM_RES_DWN         PIN_DM_RES_DWN
-#define SD_MOSI_DM_OD_LO           PIN_DM_OD_LO
-#define SD_MOSI_DM_OD_HI           PIN_DM_OD_HI
-#define SD_MOSI_DM_STRONG          PIN_DM_STRONG
-#define SD_MOSI_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define SD_MOSI_MASK               SD_MOSI__MASK
-#define SD_MOSI_SHIFT              SD_MOSI__SHIFT
-#define SD_MOSI_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define SD_MOSI_PS                     (* (reg8 *) SD_MOSI__PS)
-/* Data Register */
-#define SD_MOSI_DR                     (* (reg8 *) SD_MOSI__DR)
-/* Port Number */
-#define SD_MOSI_PRT_NUM                (* (reg8 *) SD_MOSI__PRT) 
-/* Connect to Analog Globals */                                                  
-#define SD_MOSI_AG                     (* (reg8 *) SD_MOSI__AG)                       
-/* Analog MUX bux enable */
-#define SD_MOSI_AMUX                   (* (reg8 *) SD_MOSI__AMUX) 
-/* Bidirectional Enable */                                                        
-#define SD_MOSI_BIE                    (* (reg8 *) SD_MOSI__BIE)
-/* Bit-mask for Aliased Register Access */
-#define SD_MOSI_BIT_MASK               (* (reg8 *) SD_MOSI__BIT_MASK)
-/* Bypass Enable */
-#define SD_MOSI_BYP                    (* (reg8 *) SD_MOSI__BYP)
-/* Port wide control signals */                                                   
-#define SD_MOSI_CTL                    (* (reg8 *) SD_MOSI__CTL)
-/* Drive Modes */
-#define SD_MOSI_DM0                    (* (reg8 *) SD_MOSI__DM0) 
-#define SD_MOSI_DM1                    (* (reg8 *) SD_MOSI__DM1)
-#define SD_MOSI_DM2                    (* (reg8 *) SD_MOSI__DM2) 
-/* Input Buffer Disable Override */
-#define SD_MOSI_INP_DIS                (* (reg8 *) SD_MOSI__INP_DIS)
-/* LCD Common or Segment Drive */
-#define SD_MOSI_LCD_COM_SEG            (* (reg8 *) SD_MOSI__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define SD_MOSI_LCD_EN                 (* (reg8 *) SD_MOSI__LCD_EN)
-/* Slew Rate Control */
-#define SD_MOSI_SLW                    (* (reg8 *) SD_MOSI__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define SD_MOSI_PRTDSI__CAPS_SEL       (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define SD_MOSI_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define SD_MOSI_PRTDSI__OE_SEL0        (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) 
-#define SD_MOSI_PRTDSI__OE_SEL1        (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define SD_MOSI_PRTDSI__OUT_SEL0       (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) 
-#define SD_MOSI_PRTDSI__OUT_SEL1       (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define SD_MOSI_PRTDSI__SYNC_OUT       (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) 
-
-
-#if defined(SD_MOSI__INTSTAT)  /* Interrupt Registers */
-
-    #define SD_MOSI_INTSTAT                (* (reg8 *) SD_MOSI__INTSTAT)
-    #define SD_MOSI_SNAP                   (* (reg8 *) SD_MOSI__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_SD_MOSI_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MOSI.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */
+#define CY_PINS_SD_MOSI_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SD_MOSI_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SD_MOSI_Write(uint8 value) ;
+void    SD_MOSI_SetDriveMode(uint8 mode) ;
+uint8   SD_MOSI_ReadDataReg(void) ;
+uint8   SD_MOSI_Read(void) ;
+uint8   SD_MOSI_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SD_MOSI_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SD_MOSI_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SD_MOSI_DM_RES_UP          PIN_DM_RES_UP
+#define SD_MOSI_DM_RES_DWN         PIN_DM_RES_DWN
+#define SD_MOSI_DM_OD_LO           PIN_DM_OD_LO
+#define SD_MOSI_DM_OD_HI           PIN_DM_OD_HI
+#define SD_MOSI_DM_STRONG          PIN_DM_STRONG
+#define SD_MOSI_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SD_MOSI_MASK               SD_MOSI__MASK
+#define SD_MOSI_SHIFT              SD_MOSI__SHIFT
+#define SD_MOSI_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SD_MOSI_PS                     (* (reg8 *) SD_MOSI__PS)
+/* Data Register */
+#define SD_MOSI_DR                     (* (reg8 *) SD_MOSI__DR)
+/* Port Number */
+#define SD_MOSI_PRT_NUM                (* (reg8 *) SD_MOSI__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SD_MOSI_AG                     (* (reg8 *) SD_MOSI__AG)                       
+/* Analog MUX bux enable */
+#define SD_MOSI_AMUX                   (* (reg8 *) SD_MOSI__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SD_MOSI_BIE                    (* (reg8 *) SD_MOSI__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SD_MOSI_BIT_MASK               (* (reg8 *) SD_MOSI__BIT_MASK)
+/* Bypass Enable */
+#define SD_MOSI_BYP                    (* (reg8 *) SD_MOSI__BYP)
+/* Port wide control signals */                                                   
+#define SD_MOSI_CTL                    (* (reg8 *) SD_MOSI__CTL)
+/* Drive Modes */
+#define SD_MOSI_DM0                    (* (reg8 *) SD_MOSI__DM0) 
+#define SD_MOSI_DM1                    (* (reg8 *) SD_MOSI__DM1)
+#define SD_MOSI_DM2                    (* (reg8 *) SD_MOSI__DM2) 
+/* Input Buffer Disable Override */
+#define SD_MOSI_INP_DIS                (* (reg8 *) SD_MOSI__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SD_MOSI_LCD_COM_SEG            (* (reg8 *) SD_MOSI__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SD_MOSI_LCD_EN                 (* (reg8 *) SD_MOSI__LCD_EN)
+/* Slew Rate Control */
+#define SD_MOSI_SLW                    (* (reg8 *) SD_MOSI__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SD_MOSI_PRTDSI__CAPS_SEL       (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SD_MOSI_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SD_MOSI_PRTDSI__OE_SEL0        (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) 
+#define SD_MOSI_PRTDSI__OE_SEL1        (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SD_MOSI_PRTDSI__OUT_SEL0       (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) 
+#define SD_MOSI_PRTDSI__OUT_SEL1       (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SD_MOSI_PRTDSI__SYNC_OUT       (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SD_MOSI__INTSTAT)  /* Interrupt Registers */
+
+    #define SD_MOSI_INTSTAT                (* (reg8 *) SD_MOSI__INTSTAT)
+    #define SD_MOSI_SNAP                   (* (reg8 *) SD_MOSI__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SD_MOSI_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: SD_MOSI.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */
-#define CY_PINS_SD_MOSI_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SD_MOSI_0		(SD_MOSI__0__PC)
-
-#endif /* End Pins SD_MOSI_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_MOSI.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */
+#define CY_PINS_SD_MOSI_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SD_MOSI_0		(SD_MOSI__0__PC)
+
+#endif /* End Pins SD_MOSI_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SD_RX_DMA_COMPLETE.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SD_RX_DMA_COMPLETE.h>
-
-#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SD_RX_DMA_COMPLETE_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SD_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
-    SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt);
-
-    /* Set the priority. */
-    SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SD_RX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SD_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
-    SD_RX_DMA_COMPLETE_SetVector(address);
-
-    /* Set the priority. */
-    SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SD_RX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_Stop(void)
-{
-    /* Disable this interrupt. */
-    SD_RX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SD_RX_DMA_COMPLETE.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SD_RX_DMA_COMPLETE_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
-{
-    *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SD_RX_DMA_COMPLETE_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_SetPending(void)
-{
-    *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_DMA_COMPLETE_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_RX_DMA_COMPLETE_ClearPending(void)
-{
-    *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_RX_DMA_COMPLETE.h>
+
+#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SD_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SD_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+    SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt);
+
+    /* Set the priority. */
+    SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SD_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+    SD_RX_DMA_COMPLETE_SetVector(address);
+
+    /* Set the priority. */
+    SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Stop(void)
+{
+    /* Disable this interrupt. */
+    SD_RX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SD_RX_DMA_COMPLETE.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SD_RX_DMA_COMPLETE_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+    *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPending(void)
+{
+    *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_ClearPending(void)
+{
+    *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SD_RX_DMA_COMPLETE.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H)
-#define CY_ISR_SD_RX_DMA_COMPLETE_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SD_RX_DMA_COMPLETE_Start(void);
-void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address);
-void SD_RX_DMA_COMPLETE_Stop(void);
-
-CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt);
-
-void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address);
-cyisraddress SD_RX_DMA_COMPLETE_GetVector(void);
-
-void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority);
-uint8 SD_RX_DMA_COMPLETE_GetPriority(void);
-
-void SD_RX_DMA_COMPLETE_Enable(void);
-uint8 SD_RX_DMA_COMPLETE_GetState(void);
-void SD_RX_DMA_COMPLETE_Disable(void);
-
-void SD_RX_DMA_COMPLETE_SetPending(void);
-void SD_RX_DMA_COMPLETE_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */
-#define SD_RX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT)
-
-/* Address of the SD_RX_DMA_COMPLETE ISR priority. */
-#define SD_RX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG)
-
-/* Priority of the SD_RX_DMA_COMPLETE interrupt. */
-#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */
-#define SD_RX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */
-#define SD_RX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */
-#define SD_RX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */
-#define SD_RX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H)
+#define CY_ISR_SD_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_RX_DMA_COMPLETE_Start(void);
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt);
+
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void);
+
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void);
+
+void SD_RX_DMA_COMPLETE_Enable(void);
+uint8 SD_RX_DMA_COMPLETE_GetState(void);
+void SD_RX_DMA_COMPLETE_Disable(void);
+
+void SD_RX_DMA_COMPLETE_SetPending(void);
+void SD_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */
+#define SD_RX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_RX_DMA_COMPLETE ISR priority. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c

@@ -1,141 +1,141 @@
-/***************************************************************************
-* File Name: SD_RX_DMA_dma.c  
-* Version 1.70
-*
-*  Description:
-*   Provides an API for the DMAC component. The API includes functions
-*   for the DMA controller, DMA channels and Transfer Descriptors.
-*
-*
-*   Note:
-*     This module requires the developer to finish or fill in the auto
-*     generated funcions and setup the dma channel and TD's.
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#include <CYLIB.H>
-#include <CYDMAC.H>
-#include <SD_RX_DMA_dma.H>
-
-
-
-/****************************************************************************
-* 
-* The following defines are available in Cyfitter.h
-* 
-* 
-* 
-* SD_RX_DMA__DRQ_CTL_REG
-* 
-* 
-* SD_RX_DMA__DRQ_NUMBER
-* 
-* Number of TD's used by this channel.
-* SD_RX_DMA__NUMBEROF_TDS
-* 
-* Priority of this channel.
-* SD_RX_DMA__PRIORITY
-* 
-* True if SD_RX_DMA_TERMIN_SEL is used.
-* SD_RX_DMA__TERMIN_EN
-* 
-* TERMIN interrupt line to signal terminate.
-* SD_RX_DMA__TERMIN_SEL
-* 
-* 
-* True if SD_RX_DMA_TERMOUT0_SEL is used.
-* SD_RX_DMA__TERMOUT0_EN
-* 
-* 
-* TERMOUT0 interrupt line to signal completion.
-* SD_RX_DMA__TERMOUT0_SEL
-* 
-* 
-* True if SD_RX_DMA_TERMOUT1_SEL is used.
-* SD_RX_DMA__TERMOUT1_EN
-* 
-* 
-* TERMOUT1 interrupt line to signal completion.
-* SD_RX_DMA__TERMOUT1_SEL
-* 
-****************************************************************************/
-
-
-/* Zero based index of SD_RX_DMA dma channel */
-uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
-
-/*********************************************************************
-* Function Name: uint8 SD_RX_DMA_DmaInitalize
-**********************************************************************
-* Summary:
-*   Allocates and initialises a channel of the DMAC to be used by the
-*   caller.
-*
-* Parameters:
-*   BurstCount.
-*       
-*       
-*   ReqestPerBurst.
-*       
-*       
-*   UpperSrcAddress.
-*       
-*       
-*   UpperDestAddress.
-*       
-*
-* Return:
-*   The channel that can be used by the caller for DMA activity.
-*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
-*
-*
-*******************************************************************/
-uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
-{
-
-    /* Allocate a DMA channel. */
-    SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER;
-
-    /* Configure the channel. */
-    (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle,
-                                  BurstCount,
-                                  ReqestPerBurst,
-                                  (uint8)SD_RX_DMA__TERMOUT0_SEL,
-                                  (uint8)SD_RX_DMA__TERMOUT1_SEL,
-                                  (uint8)SD_RX_DMA__TERMIN_SEL);
-
-    /* Set the extended address for the transfers */
-    (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
-
-    /* Set the priority for this channel */
-    (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY);
-    
-    return SD_RX_DMA_DmaHandle;
-}
-
-/*********************************************************************
-* Function Name: void SD_RX_DMA_DmaRelease
-**********************************************************************
-* Summary:
-*   Frees the channel associated with SD_RX_DMA.
-*
-*
-* Parameters:
-*   void.
-*
-*
-*
-* Return:
-*   void.
-*
-*******************************************************************/
-void SD_RX_DMA_DmaRelease(void) 
-{
-    /* Disable the channel */
-    (void)CyDmaChDisable(SD_RX_DMA_DmaHandle);
-}
-
+/***************************************************************************
+* File Name: SD_RX_DMA_dma.c  
+* Version 1.70
+*
+*  Description:
+*   Provides an API for the DMAC component. The API includes functions
+*   for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+*   Note:
+*     This module requires the developer to finish or fill in the auto
+*     generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+* 
+* The following defines are available in Cyfitter.h
+* 
+* 
+* 
+* SD_RX_DMA__DRQ_CTL_REG
+* 
+* 
+* SD_RX_DMA__DRQ_NUMBER
+* 
+* Number of TD's used by this channel.
+* SD_RX_DMA__NUMBEROF_TDS
+* 
+* Priority of this channel.
+* SD_RX_DMA__PRIORITY
+* 
+* True if SD_RX_DMA_TERMIN_SEL is used.
+* SD_RX_DMA__TERMIN_EN
+* 
+* TERMIN interrupt line to signal terminate.
+* SD_RX_DMA__TERMIN_SEL
+* 
+* 
+* True if SD_RX_DMA_TERMOUT0_SEL is used.
+* SD_RX_DMA__TERMOUT0_EN
+* 
+* 
+* TERMOUT0 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT0_SEL
+* 
+* 
+* True if SD_RX_DMA_TERMOUT1_SEL is used.
+* SD_RX_DMA__TERMOUT1_EN
+* 
+* 
+* TERMOUT1 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT1_SEL
+* 
+****************************************************************************/
+
+
+/* Zero based index of SD_RX_DMA dma channel */
+uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+*   Allocates and initialises a channel of the DMAC to be used by the
+*   caller.
+*
+* Parameters:
+*   BurstCount.
+*       
+*       
+*   ReqestPerBurst.
+*       
+*       
+*   UpperSrcAddress.
+*       
+*       
+*   UpperDestAddress.
+*       
+*
+* Return:
+*   The channel that can be used by the caller for DMA activity.
+*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
+*
+*
+*******************************************************************/
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
+{
+
+    /* Allocate a DMA channel. */
+    SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER;
+
+    /* Configure the channel. */
+    (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle,
+                                  BurstCount,
+                                  ReqestPerBurst,
+                                  (uint8)SD_RX_DMA__TERMOUT0_SEL,
+                                  (uint8)SD_RX_DMA__TERMOUT1_SEL,
+                                  (uint8)SD_RX_DMA__TERMIN_SEL);
+
+    /* Set the extended address for the transfers */
+    (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+    /* Set the priority for this channel */
+    (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY);
+    
+    return SD_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+*   Frees the channel associated with SD_RX_DMA.
+*
+*
+* Parameters:
+*   void.
+*
+*
+*
+* Return:
+*   void.
+*
+*******************************************************************/
+void SD_RX_DMA_DmaRelease(void) 
+{
+    /* Disable the channel */
+    (void)CyDmaChDisable(SD_RX_DMA_DmaHandle);
+}
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h

@@ -1,35 +1,35 @@
-/******************************************************************************
-* File Name: SD_RX_DMA_dma.h  
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the DMA Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#if !defined(CY_DMA_SD_RX_DMA_DMA_H__)
-#define CY_DMA_SD_RX_DMA_DMA_H__
-
-
-
-#include <CYDMAC.H>
-#include <CYFITTER.H>
-
-#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
-    (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
-
-/* Zero based index of SD_RX_DMA dma channel */
-extern uint8 SD_RX_DMA_DmaHandle;
-
-
-uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
-void  SD_RX_DMA_DmaRelease(void) ;
-
-
-/* CY_DMA_SD_RX_DMA_DMA_H__ */
-#endif
+/******************************************************************************
+* File Name: SD_RX_DMA_dma.h  
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_RX_DMA_DMA_H__)
+#define CY_DMA_SD_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+    (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_RX_DMA dma channel */
+extern uint8 SD_RX_DMA_DmaHandle;
+
+
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void  SD_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_RX_DMA_DMA_H__ */
+#endif

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: SD_SCK.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "SD_SCK.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: SD_SCK_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void SD_SCK_Write(uint8 value) 
-{
-    uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK));
-    SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SCK_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  SD_SCK_DM_STRONG     Strong Drive 
-*  SD_SCK_DM_OD_HI      Open Drain, Drives High 
-*  SD_SCK_DM_OD_LO      Open Drain, Drives Low 
-*  SD_SCK_DM_RES_UP     Resistive Pull Up 
-*  SD_SCK_DM_RES_DWN    Resistive Pull Down 
-*  SD_SCK_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  SD_SCK_DM_DIG_HIZ    High Impedance Digital 
-*  SD_SCK_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void SD_SCK_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(SD_SCK_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SCK_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro SD_SCK_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 SD_SCK_Read(void) 
-{
-    return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SCK_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 SD_SCK_ReadDataReg(void) 
-{
-    return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(SD_SCK_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: SD_SCK_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 SD_SCK_ClearInterrupt(void) 
-    {
-        return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_SCK.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SD_SCK.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SD_SCK_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SD_SCK_Write(uint8 value) 
+{
+    uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK));
+    SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_SCK_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_SCK_DM_STRONG     Strong Drive 
+*  SD_SCK_DM_OD_HI      Open Drain, Drives High 
+*  SD_SCK_DM_OD_LO      Open Drain, Drives Low 
+*  SD_SCK_DM_RES_UP     Resistive Pull Up 
+*  SD_SCK_DM_RES_DWN    Resistive Pull Down 
+*  SD_SCK_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_SCK_DM_DIG_HIZ    High Impedance Digital 
+*  SD_SCK_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SD_SCK_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SD_SCK_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_SCK_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SD_SCK_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SD_SCK_Read(void) 
+{
+    return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_SCK_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SD_SCK_ReadDataReg(void) 
+{
+    return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SD_SCK_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SD_SCK_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SD_SCK_ClearInterrupt(void) 
+    {
+        return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: SD_SCK.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */
-#define CY_PINS_SD_SCK_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "SD_SCK_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    SD_SCK_Write(uint8 value) ;
-void    SD_SCK_SetDriveMode(uint8 mode) ;
-uint8   SD_SCK_ReadDataReg(void) ;
-uint8   SD_SCK_Read(void) ;
-uint8   SD_SCK_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define SD_SCK_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define SD_SCK_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define SD_SCK_DM_RES_UP          PIN_DM_RES_UP
-#define SD_SCK_DM_RES_DWN         PIN_DM_RES_DWN
-#define SD_SCK_DM_OD_LO           PIN_DM_OD_LO
-#define SD_SCK_DM_OD_HI           PIN_DM_OD_HI
-#define SD_SCK_DM_STRONG          PIN_DM_STRONG
-#define SD_SCK_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define SD_SCK_MASK               SD_SCK__MASK
-#define SD_SCK_SHIFT              SD_SCK__SHIFT
-#define SD_SCK_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define SD_SCK_PS                     (* (reg8 *) SD_SCK__PS)
-/* Data Register */
-#define SD_SCK_DR                     (* (reg8 *) SD_SCK__DR)
-/* Port Number */
-#define SD_SCK_PRT_NUM                (* (reg8 *) SD_SCK__PRT) 
-/* Connect to Analog Globals */                                                  
-#define SD_SCK_AG                     (* (reg8 *) SD_SCK__AG)                       
-/* Analog MUX bux enable */
-#define SD_SCK_AMUX                   (* (reg8 *) SD_SCK__AMUX) 
-/* Bidirectional Enable */                                                        
-#define SD_SCK_BIE                    (* (reg8 *) SD_SCK__BIE)
-/* Bit-mask for Aliased Register Access */
-#define SD_SCK_BIT_MASK               (* (reg8 *) SD_SCK__BIT_MASK)
-/* Bypass Enable */
-#define SD_SCK_BYP                    (* (reg8 *) SD_SCK__BYP)
-/* Port wide control signals */                                                   
-#define SD_SCK_CTL                    (* (reg8 *) SD_SCK__CTL)
-/* Drive Modes */
-#define SD_SCK_DM0                    (* (reg8 *) SD_SCK__DM0) 
-#define SD_SCK_DM1                    (* (reg8 *) SD_SCK__DM1)
-#define SD_SCK_DM2                    (* (reg8 *) SD_SCK__DM2) 
-/* Input Buffer Disable Override */
-#define SD_SCK_INP_DIS                (* (reg8 *) SD_SCK__INP_DIS)
-/* LCD Common or Segment Drive */
-#define SD_SCK_LCD_COM_SEG            (* (reg8 *) SD_SCK__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define SD_SCK_LCD_EN                 (* (reg8 *) SD_SCK__LCD_EN)
-/* Slew Rate Control */
-#define SD_SCK_SLW                    (* (reg8 *) SD_SCK__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define SD_SCK_PRTDSI__CAPS_SEL       (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define SD_SCK_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define SD_SCK_PRTDSI__OE_SEL0        (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) 
-#define SD_SCK_PRTDSI__OE_SEL1        (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define SD_SCK_PRTDSI__OUT_SEL0       (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) 
-#define SD_SCK_PRTDSI__OUT_SEL1       (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define SD_SCK_PRTDSI__SYNC_OUT       (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) 
-
-
-#if defined(SD_SCK__INTSTAT)  /* Interrupt Registers */
-
-    #define SD_SCK_INTSTAT                (* (reg8 *) SD_SCK__INTSTAT)
-    #define SD_SCK_SNAP                   (* (reg8 *) SD_SCK__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_SD_SCK_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_SCK.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */
+#define CY_PINS_SD_SCK_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SD_SCK_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SD_SCK_Write(uint8 value) ;
+void    SD_SCK_SetDriveMode(uint8 mode) ;
+uint8   SD_SCK_ReadDataReg(void) ;
+uint8   SD_SCK_Read(void) ;
+uint8   SD_SCK_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SD_SCK_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SD_SCK_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SD_SCK_DM_RES_UP          PIN_DM_RES_UP
+#define SD_SCK_DM_RES_DWN         PIN_DM_RES_DWN
+#define SD_SCK_DM_OD_LO           PIN_DM_OD_LO
+#define SD_SCK_DM_OD_HI           PIN_DM_OD_HI
+#define SD_SCK_DM_STRONG          PIN_DM_STRONG
+#define SD_SCK_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SD_SCK_MASK               SD_SCK__MASK
+#define SD_SCK_SHIFT              SD_SCK__SHIFT
+#define SD_SCK_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SD_SCK_PS                     (* (reg8 *) SD_SCK__PS)
+/* Data Register */
+#define SD_SCK_DR                     (* (reg8 *) SD_SCK__DR)
+/* Port Number */
+#define SD_SCK_PRT_NUM                (* (reg8 *) SD_SCK__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SD_SCK_AG                     (* (reg8 *) SD_SCK__AG)                       
+/* Analog MUX bux enable */
+#define SD_SCK_AMUX                   (* (reg8 *) SD_SCK__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SD_SCK_BIE                    (* (reg8 *) SD_SCK__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SD_SCK_BIT_MASK               (* (reg8 *) SD_SCK__BIT_MASK)
+/* Bypass Enable */
+#define SD_SCK_BYP                    (* (reg8 *) SD_SCK__BYP)
+/* Port wide control signals */                                                   
+#define SD_SCK_CTL                    (* (reg8 *) SD_SCK__CTL)
+/* Drive Modes */
+#define SD_SCK_DM0                    (* (reg8 *) SD_SCK__DM0) 
+#define SD_SCK_DM1                    (* (reg8 *) SD_SCK__DM1)
+#define SD_SCK_DM2                    (* (reg8 *) SD_SCK__DM2) 
+/* Input Buffer Disable Override */
+#define SD_SCK_INP_DIS                (* (reg8 *) SD_SCK__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SD_SCK_LCD_COM_SEG            (* (reg8 *) SD_SCK__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SD_SCK_LCD_EN                 (* (reg8 *) SD_SCK__LCD_EN)
+/* Slew Rate Control */
+#define SD_SCK_SLW                    (* (reg8 *) SD_SCK__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SD_SCK_PRTDSI__CAPS_SEL       (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SD_SCK_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SD_SCK_PRTDSI__OE_SEL0        (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) 
+#define SD_SCK_PRTDSI__OE_SEL1        (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SD_SCK_PRTDSI__OUT_SEL0       (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) 
+#define SD_SCK_PRTDSI__OUT_SEL1       (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SD_SCK_PRTDSI__SYNC_OUT       (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SD_SCK__INTSTAT)  /* Interrupt Registers */
+
+    #define SD_SCK_INTSTAT                (* (reg8 *) SD_SCK__INTSTAT)
+    #define SD_SCK_SNAP                   (* (reg8 *) SD_SCK__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SD_SCK_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h

@@ -1,32 +1,32 @@
-/*******************************************************************************
-* File Name: SD_SCK.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */
-#define CY_PINS_SD_SCK_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SD_SCK_0		(SD_SCK__0__PC)
-
-#endif /* End Pins SD_SCK_ALIASES_H */
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_SCK.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */
+#define CY_PINS_SD_SCK_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SD_SCK_0		(SD_SCK__0__PC)
+
+#endif /* End Pins SD_SCK_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c

@@ -1,404 +1,404 @@
-/*******************************************************************************
-* File Name: SD_TX_DMA_COMPLETE.c  
-* Version 1.70
-*
-*  Description:
-*   API for controlling the state of an interrupt.
-*
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SD_TX_DMA_COMPLETE.h>
-
-#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-*  Place your includes, defines and code here 
-********************************************************************************/
-/* `#START SD_TX_DMA_COMPLETE_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE      16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_Start
-********************************************************************************
-*
-* Summary:
-*  Set up the interrupt and enable it. This function disables the interrupt, 
-*  sets the default interrupt vector, sets the priority from the value in the
-*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
-*  interrupt controller.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_Start(void)
-{
-    /* For all we know the interrupt is active. */
-    SD_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
-    SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt);
-
-    /* Set the priority. */
-    SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SD_TX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_StartEx
-********************************************************************************
-*
-* Summary:
-*  Sets up the interrupt and enables it. This function disables the interrupt,
-*  sets the interrupt vector based on the address passed in, sets the priority 
-*  from the value in the Design Wide Resources Interrupt Editor, then enables 
-*  the interrupt to the interrupt controller.
-*  
-*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*  used to provide consistent definition across compilers:
-*  
-*  Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*   Function prototype example:
-*   CY_ISR_PROTO(MyISR);
-*
-* Parameters:  
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
-{
-    /* For all we know the interrupt is active. */
-    SD_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
-    SD_TX_DMA_COMPLETE_SetVector(address);
-
-    /* Set the priority. */
-    SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
-
-    /* Enable it. */
-    SD_TX_DMA_COMPLETE_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_Stop
-********************************************************************************
-*
-* Summary:
-*   Disables and removes the interrupt.
-*
-* Parameters:  
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_Stop(void)
-{
-    /* Disable this interrupt. */
-    SD_TX_DMA_COMPLETE_Disable();
-
-    /* Set the ISR to point to the passive one. */
-    SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_Interrupt
-********************************************************************************
-*
-* Summary:
-*   The default Interrupt Service Routine for SD_TX_DMA_COMPLETE.
-*
-*   Add custom code between the coments to keep the next version of this file
-*   from over writting your code.
-*
-* Parameters:  
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
-{
-    /*  Place your Interrupt code here. */
-    /* `#START SD_TX_DMA_COMPLETE_Interrupt` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_SetVector
-********************************************************************************
-*
-* Summary:
-*   Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
-*   will override any effect this method would have had. To set the vector 
-*   before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
-* 
-*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
-*   used to provide consistent definition across compilers:
-*
-*   Function definition example:
-*   CY_ISR(MyISR)
-*   {
-*   }
-*
-*   Function prototype example:
-*     CY_ISR_PROTO(MyISR);
-*
-* Parameters:
-*   address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_GetVector
-********************************************************************************
-*
-* Summary:
-*   Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
-{
-    cyisraddress * ramVectorTable;
-
-    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
-    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_SetPriority
-********************************************************************************
-*
-* Summary:
-*   Sets the Priority of the Interrupt. 
-*
-*   Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will 
-*   override any effect this API would have had. This API should only be called
-*   after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. 
-*   To set the initial priority for the component, use the Design-Wide Resources
-*   Interrupt Editor.
-*
-*   Note This API has no effect on Non-maskable interrupt NMI).
-*
-* Parameters:
-*   priority: Priority of the interrupt, 0 being the highest priority
-*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*             PSoC 4: Priority is from 0 to 3.
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
-{
-    *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_GetPriority
-********************************************************************************
-*
-* Summary:
-*   Gets the Priority of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   Priority of the interrupt, 0 being the highest priority
-*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
-*    PSoC 4: Priority is from 0 to 3.
-*
-*******************************************************************************/
-uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
-{
-    uint8 priority;
-
-
-    priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
-
-    return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_Enable
-********************************************************************************
-*
-* Summary:
-*   Enables the interrupt to the interrupt controller. Do not call this function
-*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
-*   function, which sets the vector and the priority, has been called.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_Enable(void)
-{
-    /* Enable the general interrupt. */
-    *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_GetState
-********************************************************************************
-*
-* Summary:
-*   Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SD_TX_DMA_COMPLETE_GetState(void)
-{
-    /* Get the state of the general interrupt. */
-    return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_Disable
-********************************************************************************
-*
-* Summary:
-*   Disables the Interrupt in the interrupt controller.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_Disable(void)
-{
-    /* Disable the general interrupt. */
-    *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_SetPending
-********************************************************************************
-*
-* Summary:
-*   Causes the Interrupt to enter the pending state, a software method of
-*   generating the interrupt.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-* Side Effects:
-*   If interrupts are enabled and the interrupt is set up properly, the ISR is
-*   entered (depending on the priority of this interrupt and other pending 
-*   interrupts).
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_SetPending(void)
-{
-    *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_TX_DMA_COMPLETE_ClearPending
-********************************************************************************
-*
-* Summary:
-*   Clears a pending interrupt in the interrupt controller.
-*
-*   Note Some interrupt sources are clear-on-read and require the block 
-*   interrupt/status register to be read/cleared with the appropriate block API 
-*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
-*   pending state even though the interrupt itself is cleared using this API.
-*
-* Parameters:
-*   None
-*
-* Return:
-*   None
-*
-*******************************************************************************/
-void SD_TX_DMA_COMPLETE_ClearPending(void)
-{
-    *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_TX_DMA_COMPLETE.h>
+
+#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SD_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it. This function disables the interrupt, 
+*  sets the default interrupt vector, sets the priority from the value in the
+*  Design Wide Resources Interrupt Editor, then enables the interrupt to the 
+*  interrupt controller.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SD_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+    SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt);
+
+    /* Set the priority. */
+    SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+*  Sets up the interrupt and enables it. This function disables the interrupt,
+*  sets the interrupt vector based on the address passed in, sets the priority 
+*  from the value in the Design Wide Resources Interrupt Editor, then enables 
+*  the interrupt to the interrupt controller.
+*  
+*  When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*  used to provide consistent definition across compilers:
+*  
+*  Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*   Function prototype example:
+*   CY_ISR_PROTO(MyISR);
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SD_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+    SD_TX_DMA_COMPLETE_SetVector(address);
+
+    /* Set the priority. */
+    SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Stop(void)
+{
+    /* Disable this interrupt. */
+    SD_TX_DMA_COMPLETE_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SD_TX_DMA_COMPLETE.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SD_TX_DMA_COMPLETE_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+* 
+*   When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be 
+*   used to provide consistent definition across compilers:
+*
+*   Function definition example:
+*   CY_ISR(MyISR)
+*   {
+*   }
+*
+*   Function prototype example:
+*     CY_ISR_PROTO(MyISR);
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. 
+*
+*   Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will 
+*   override any effect this API would have had. This API should only be called
+*   after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. 
+*   To set the initial priority for the component, use the Design-Wide Resources
+*   Interrupt Editor.
+*
+*   Note This API has no effect on Non-maskable interrupt NMI).
+*
+* Parameters:
+*   priority: Priority of the interrupt, 0 being the highest priority
+*             PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*             PSoC 4: Priority is from 0 to 3.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+    *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt, 0 being the highest priority
+*    PSoC 3 and PSoC 5LP: Priority is from 0 to 7.
+*    PSoC 4: Priority is from 0 to 3.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt to the interrupt controller. Do not call this function
+*   unless ISR_Start() has been called or the functionality of the ISR_Start() 
+*   function, which sets the vector and the priority, has been called.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt in the interrupt controller.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+* Side Effects:
+*   If interrupts are enabled and the interrupt is set up properly, the ISR is
+*   entered (depending on the priority of this interrupt and other pending 
+*   interrupts).
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPending(void)
+{
+    *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt in the interrupt controller.
+*
+*   Note Some interrupt sources are clear-on-read and require the block 
+*   interrupt/status register to be read/cleared with the appropriate block API 
+*   (GPIO, UART, and so on). Otherwise the ISR will continue to remain in 
+*   pending state even though the interrupt itself is cleared using this API.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_ClearPending(void)
+{
+    *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h

@@ -1,70 +1,70 @@
-/*******************************************************************************
-* File Name: SD_TX_DMA_COMPLETE.h
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H)
-#define CY_ISR_SD_TX_DMA_COMPLETE_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SD_TX_DMA_COMPLETE_Start(void);
-void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address);
-void SD_TX_DMA_COMPLETE_Stop(void);
-
-CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt);
-
-void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address);
-cyisraddress SD_TX_DMA_COMPLETE_GetVector(void);
-
-void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority);
-uint8 SD_TX_DMA_COMPLETE_GetPriority(void);
-
-void SD_TX_DMA_COMPLETE_Enable(void);
-uint8 SD_TX_DMA_COMPLETE_GetState(void);
-void SD_TX_DMA_COMPLETE_Disable(void);
-
-void SD_TX_DMA_COMPLETE_SetPending(void);
-void SD_TX_DMA_COMPLETE_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */
-#define SD_TX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT)
-
-/* Address of the SD_TX_DMA_COMPLETE ISR priority. */
-#define SD_TX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG)
-
-/* Priority of the SD_TX_DMA_COMPLETE interrupt. */
-#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */
-#define SD_TX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */
-#define SD_TX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */
-#define SD_TX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */
-#define SD_TX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2015, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H)
+#define CY_ISR_SD_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_TX_DMA_COMPLETE_Start(void);
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt);
+
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void);
+
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void);
+
+void SD_TX_DMA_COMPLETE_Enable(void);
+uint8 SD_TX_DMA_COMPLETE_GetState(void);
+void SD_TX_DMA_COMPLETE_Disable(void);
+
+void SD_TX_DMA_COMPLETE_SetPending(void);
+void SD_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */
+#define SD_TX_DMA_COMPLETE_INTC_VECTOR            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_TX_DMA_COMPLETE ISR priority. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR             ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER      SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_EN            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_EN            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_PD            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_PD            ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c

@@ -1,141 +1,141 @@
-/***************************************************************************
-* File Name: SD_TX_DMA_dma.c  
-* Version 1.70
-*
-*  Description:
-*   Provides an API for the DMAC component. The API includes functions
-*   for the DMA controller, DMA channels and Transfer Descriptors.
-*
-*
-*   Note:
-*     This module requires the developer to finish or fill in the auto
-*     generated funcions and setup the dma channel and TD's.
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#include <CYLIB.H>
-#include <CYDMAC.H>
-#include <SD_TX_DMA_dma.H>
-
-
-
-/****************************************************************************
-* 
-* The following defines are available in Cyfitter.h
-* 
-* 
-* 
-* SD_TX_DMA__DRQ_CTL_REG
-* 
-* 
-* SD_TX_DMA__DRQ_NUMBER
-* 
-* Number of TD's used by this channel.
-* SD_TX_DMA__NUMBEROF_TDS
-* 
-* Priority of this channel.
-* SD_TX_DMA__PRIORITY
-* 
-* True if SD_TX_DMA_TERMIN_SEL is used.
-* SD_TX_DMA__TERMIN_EN
-* 
-* TERMIN interrupt line to signal terminate.
-* SD_TX_DMA__TERMIN_SEL
-* 
-* 
-* True if SD_TX_DMA_TERMOUT0_SEL is used.
-* SD_TX_DMA__TERMOUT0_EN
-* 
-* 
-* TERMOUT0 interrupt line to signal completion.
-* SD_TX_DMA__TERMOUT0_SEL
-* 
-* 
-* True if SD_TX_DMA_TERMOUT1_SEL is used.
-* SD_TX_DMA__TERMOUT1_EN
-* 
-* 
-* TERMOUT1 interrupt line to signal completion.
-* SD_TX_DMA__TERMOUT1_SEL
-* 
-****************************************************************************/
-
-
-/* Zero based index of SD_TX_DMA dma channel */
-uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
-
-/*********************************************************************
-* Function Name: uint8 SD_TX_DMA_DmaInitalize
-**********************************************************************
-* Summary:
-*   Allocates and initialises a channel of the DMAC to be used by the
-*   caller.
-*
-* Parameters:
-*   BurstCount.
-*       
-*       
-*   ReqestPerBurst.
-*       
-*       
-*   UpperSrcAddress.
-*       
-*       
-*   UpperDestAddress.
-*       
-*
-* Return:
-*   The channel that can be used by the caller for DMA activity.
-*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
-*
-*
-*******************************************************************/
-uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
-{
-
-    /* Allocate a DMA channel. */
-    SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER;
-
-    /* Configure the channel. */
-    (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle,
-                                  BurstCount,
-                                  ReqestPerBurst,
-                                  (uint8)SD_TX_DMA__TERMOUT0_SEL,
-                                  (uint8)SD_TX_DMA__TERMOUT1_SEL,
-                                  (uint8)SD_TX_DMA__TERMIN_SEL);
-
-    /* Set the extended address for the transfers */
-    (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
-
-    /* Set the priority for this channel */
-    (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY);
-    
-    return SD_TX_DMA_DmaHandle;
-}
-
-/*********************************************************************
-* Function Name: void SD_TX_DMA_DmaRelease
-**********************************************************************
-* Summary:
-*   Frees the channel associated with SD_TX_DMA.
-*
-*
-* Parameters:
-*   void.
-*
-*
-*
-* Return:
-*   void.
-*
-*******************************************************************/
-void SD_TX_DMA_DmaRelease(void) 
-{
-    /* Disable the channel */
-    (void)CyDmaChDisable(SD_TX_DMA_DmaHandle);
-}
-
+/***************************************************************************
+* File Name: SD_TX_DMA_dma.c  
+* Version 1.70
+*
+*  Description:
+*   Provides an API for the DMAC component. The API includes functions
+*   for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+*   Note:
+*     This module requires the developer to finish or fill in the auto
+*     generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+* 
+* The following defines are available in Cyfitter.h
+* 
+* 
+* 
+* SD_TX_DMA__DRQ_CTL_REG
+* 
+* 
+* SD_TX_DMA__DRQ_NUMBER
+* 
+* Number of TD's used by this channel.
+* SD_TX_DMA__NUMBEROF_TDS
+* 
+* Priority of this channel.
+* SD_TX_DMA__PRIORITY
+* 
+* True if SD_TX_DMA_TERMIN_SEL is used.
+* SD_TX_DMA__TERMIN_EN
+* 
+* TERMIN interrupt line to signal terminate.
+* SD_TX_DMA__TERMIN_SEL
+* 
+* 
+* True if SD_TX_DMA_TERMOUT0_SEL is used.
+* SD_TX_DMA__TERMOUT0_EN
+* 
+* 
+* TERMOUT0 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT0_SEL
+* 
+* 
+* True if SD_TX_DMA_TERMOUT1_SEL is used.
+* SD_TX_DMA__TERMOUT1_EN
+* 
+* 
+* TERMOUT1 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT1_SEL
+* 
+****************************************************************************/
+
+
+/* Zero based index of SD_TX_DMA dma channel */
+uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+*   Allocates and initialises a channel of the DMAC to be used by the
+*   caller.
+*
+* Parameters:
+*   BurstCount.
+*       
+*       
+*   ReqestPerBurst.
+*       
+*       
+*   UpperSrcAddress.
+*       
+*       
+*   UpperDestAddress.
+*       
+*
+* Return:
+*   The channel that can be used by the caller for DMA activity.
+*   DMA_INVALID_CHANNEL (0xFF) if there are no channels left. 
+*
+*
+*******************************************************************/
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) 
+{
+
+    /* Allocate a DMA channel. */
+    SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER;
+
+    /* Configure the channel. */
+    (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle,
+                                  BurstCount,
+                                  ReqestPerBurst,
+                                  (uint8)SD_TX_DMA__TERMOUT0_SEL,
+                                  (uint8)SD_TX_DMA__TERMOUT1_SEL,
+                                  (uint8)SD_TX_DMA__TERMIN_SEL);
+
+    /* Set the extended address for the transfers */
+    (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+    /* Set the priority for this channel */
+    (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY);
+    
+    return SD_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+*   Frees the channel associated with SD_TX_DMA.
+*
+*
+* Parameters:
+*   void.
+*
+*
+*
+* Return:
+*   void.
+*
+*******************************************************************/
+void SD_TX_DMA_DmaRelease(void) 
+{
+    /* Disable the channel */
+    (void)CyDmaChDisable(SD_TX_DMA_DmaHandle);
+}
+

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h

@@ -1,35 +1,35 @@
-/******************************************************************************
-* File Name: SD_TX_DMA_dma.h  
-* Version 1.70
-*
-*  Description:
-*   Provides the function definitions for the DMA Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-********************************************************************************/
-#if !defined(CY_DMA_SD_TX_DMA_DMA_H__)
-#define CY_DMA_SD_TX_DMA_DMA_H__
-
-
-
-#include <CYDMAC.H>
-#include <CYFITTER.H>
-
-#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
-    (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
-
-/* Zero based index of SD_TX_DMA dma channel */
-extern uint8 SD_TX_DMA_DmaHandle;
-
-
-uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
-void  SD_TX_DMA_DmaRelease(void) ;
-
-
-/* CY_DMA_SD_TX_DMA_DMA_H__ */
-#endif
+/******************************************************************************
+* File Name: SD_TX_DMA_dma.h  
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_TX_DMA_DMA_H__)
+#define CY_DMA_SD_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+    (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_TX_DMA dma channel */
+extern uint8 SD_TX_DMA_DmaHandle;
+
+
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void  SD_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_TX_DMA_DMA_H__ */
+#endif

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c

@@ -1,1473 +1,1473 @@
-/*******************************************************************************
-* File Name: USBFS.c
-* Version 2.80
-*
-* Description:
-*  API for USBFS Component.
-*
-* Note:
-*  Many of the functions use endpoint number.  RAM arrays are sized with 9
-*  elements so they are indexed directly by epNumber.  The SIE and ARB
-*  registers are indexed by variations of epNumber - 1.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include <CyDmac.h>
-#include "USBFS.h"
-#include "USBFS_pvt.h"
-#include "USBFS_hid.h"
-#if(USBFS_DMA1_REMOVE == 0u)
-    #include "USBFS_ep1_dma.h"
-#endif   /*  USBFS_DMA1_REMOVE */
-#if(USBFS_DMA2_REMOVE == 0u)
-    #include "USBFS_ep2_dma.h"
-#endif   /*  USBFS_DMA2_REMOVE */
-#if(USBFS_DMA3_REMOVE == 0u)
-    #include "USBFS_ep3_dma.h"
-#endif   /*  USBFS_DMA3_REMOVE */
-#if(USBFS_DMA4_REMOVE == 0u)
-    #include "USBFS_ep4_dma.h"
-#endif   /*  USBFS_DMA4_REMOVE */
-#if(USBFS_DMA5_REMOVE == 0u)
-    #include "USBFS_ep5_dma.h"
-#endif   /*  USBFS_DMA5_REMOVE */
-#if(USBFS_DMA6_REMOVE == 0u)
-    #include "USBFS_ep6_dma.h"
-#endif   /*  USBFS_DMA6_REMOVE */
-#if(USBFS_DMA7_REMOVE == 0u)
-    #include "USBFS_ep7_dma.h"
-#endif   /*  USBFS_DMA7_REMOVE */
-#if(USBFS_DMA8_REMOVE == 0u)
-    #include "USBFS_ep8_dma.h"
-#endif   /*  USBFS_DMA8_REMOVE */
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-    #include "USBFS_EP_DMA_Done_isr.h"
-    #include "USBFS_EP8_DMA_Done_SR.h"
-    #include "USBFS_EP17_DMA_Done_SR.h"
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-
-
-/***************************************
-* Global data allocation
-***************************************/
-
-uint8 USBFS_initVar = 0u;
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    uint8 USBFS_DmaChan[USBFS_MAX_EP];
-    uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /*  USBFS_EP_MM */
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
-    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
-    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
-    {   0u,
-        USBFS_ep1_TD_TERMOUT_EN,
-        USBFS_ep2_TD_TERMOUT_EN,
-        USBFS_ep3_TD_TERMOUT_EN,
-        USBFS_ep4_TD_TERMOUT_EN,
-        USBFS_ep5_TD_TERMOUT_EN,
-        USBFS_ep6_TD_TERMOUT_EN,
-        USBFS_ep7_TD_TERMOUT_EN,
-        USBFS_ep8_TD_TERMOUT_EN
-    };
-    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
-    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
-    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-
-
-/*******************************************************************************
-* Function Name: USBFS_Start
-********************************************************************************
-*
-* Summary:
-*  This function initialize the USB SIE, arbiter and the
-*  endpoint APIs, including setting the D+ Pullup
-*
-* Parameters:
-*  device: Contains the device number of the desired device descriptor.
-*          The device number can be found in the Device Descriptor Tab of
-*          "Configure" dialog, under the settings of desired Device Descriptor,
-*          in the "Device Number" field.
-*  mode: The operating voltage. This determines whether the voltage regulator
-*        is enabled for 5V operation or if pass through mode is used for 3.3V
-*        operation. Symbolic names and their associated values are given in the
-*        following table.
-*       USBFS_3V_OPERATION - Disable voltage regulator and pass-thru
-*                                       Vcc for pull-up
-*       USBFS_5V_OPERATION - Enable voltage regulator and use
-*                                       regulator for pull-up
-*       USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage
-*                         regulator depend on Vddd Voltage configuration in DWR.
-*
-* Return:
-*   None.
-*
-* Global variables:
-*  The USBFS_intiVar variable is used to indicate initial
-*  configuration of this component. The variable is initialized to zero (0u)
-*  and set to one (1u) the first time USBFS_Start() is called.
-*  This allows for component Re-Start without unnecessary re-initialization
-*  in all subsequent calls to the USBFS_Start() routine.
-*  If re-initialization of the component is required the variable should be set
-*  to zero before call of UART_Start() routine, or the user may call
-*  USBFS_Init() and USBFS_InitComponent() as done
-*  in the USBFS_Start() routine.
-*
-* Side Effects:
-*   This function will reset all communication states to default.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_Start(uint8 device, uint8 mode) 
-{
-    /* If not Initialized then initialize all required hardware and software */
-    if(USBFS_initVar == 0u)
-    {
-        USBFS_Init();
-        USBFS_initVar = 1u;
-    }
-    USBFS_InitComponent(device, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Init
-********************************************************************************
-*
-* Summary:
-*  Initialize component's hardware. Usually called in USBFS_Start().
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_Init(void) 
-{
-    uint8 enableInterrupts;
-    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-        uint16 i;
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-    enableInterrupts = CyEnterCriticalSection();
-
-    /* Enable USB block  */
-    USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
-    /* Enable USB block for Standby Power Mode */
-    USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;
-
-    /* Enable core clock */
-    USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE;
-
-    USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
-
-    /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */
-    /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
-    USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN));
-    CyDelayUs(0u);  /*~50ns delay */
-    /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted)
-    *  high. This will have been set low by the power manger out of reset.
-    *  Also confirm USBIO pull-up disabled
-    */
-    USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N |
-                                                  USBFS_PM_USB_CR0_PD_PULLUP_N)));
-
-    /* Select iomode to USB mode*/
-    USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE));
-
-    /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
-    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;
-    /* The reference will be available 1 us after the regulator is enabled */
-    CyDelayUs(1u);
-    /* OR 40us after power restored */
-    CyDelayUs(40u);
-    /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */
-    USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK));
-    USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK));
-
-    /* Enable USBIO */
-    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;
-    CyDelayUs(2u);
-    /* Set the USBIO pull-up enable */
-    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
-
-    /* Write WAx */
-    CY_SET_REG8(USBFS_ARB_RW1_WA_PTR,     0u);
-    CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u);
-
-    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-        /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */
-        for (i = 0u; i < USBFS_MAX_EP; i++)
-        {
-            USBFS_DmaTd[i] = DMA_INVALID_TD;
-            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
-            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-        }
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-    CyExitCriticalSection(enableInterrupts);
-
-
-    /* Set the bus reset Interrupt. */
-    (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM,   &USBFS_BUS_RESET_ISR);
-    CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);
-
-    /* Set the SOF Interrupt. */
-    #if(USBFS_SOF_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
-        CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
-    #endif   /*  USBFS_SOF_ISR_REMOVE */
-
-    /* Set the Control Endpoint Interrupt. */
-    (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
-    CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);
-
-    /* Set the Data Endpoint 1 Interrupt. */
-    #if(USBFS_EP1_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
-        CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
-    #endif   /*  USBFS_EP1_ISR_REMOVE */
-
-    /* Set the Data Endpoint 2 Interrupt. */
-    #if(USBFS_EP2_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
-        CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
-    #endif   /*  USBFS_EP2_ISR_REMOVE */
-
-    /* Set the Data Endpoint 3 Interrupt. */
-    #if(USBFS_EP3_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
-        CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
-    #endif   /*  USBFS_EP3_ISR_REMOVE */
-
-    /* Set the Data Endpoint 4 Interrupt. */
-    #if(USBFS_EP4_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
-        CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
-    #endif   /*  USBFS_EP4_ISR_REMOVE */
-
-    /* Set the Data Endpoint 5 Interrupt. */
-    #if(USBFS_EP5_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
-        CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
-    #endif   /*  USBFS_EP5_ISR_REMOVE */
-
-    /* Set the Data Endpoint 6 Interrupt. */
-    #if(USBFS_EP6_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
-        CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
-    #endif   /*  USBFS_EP6_ISR_REMOVE */
-
-     /* Set the Data Endpoint 7 Interrupt. */
-    #if(USBFS_EP7_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
-        CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
-    #endif   /*  USBFS_EP7_ISR_REMOVE */
-
-    /* Set the Data Endpoint 8 Interrupt. */
-    #if(USBFS_EP8_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
-        CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
-    #endif   /*  USBFS_EP8_ISR_REMOVE */
-
-    #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
-        /* Set the ARB Interrupt. */
-        (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
-        CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_InitComponent
-********************************************************************************
-*
-* Summary:
-*  Initialize the component, except for the HW which is done one time in
-*  the Start function.  This function pulls up D+.
-*
-* Parameters:
-*  device: Contains the device number of the desired device descriptor.
-*          The device number can be found in the Device Descriptor Tab of
-*          "Configure" dialog, under the settings of desired Device Descriptor,
-*          in the "Device Number" field.
-*  mode: The operating voltage. This determines whether the voltage regulator
-*        is enabled for 5V operation or if pass through mode is used for 3.3V
-*        operation. Symbolic names and their associated values are given in the
-*        following table.
-*       USBFS_3V_OPERATION - Disable voltage regulator and pass-thru
-*                                       Vcc for pull-up
-*       USBFS_5V_OPERATION - Enable voltage regulator and use
-*                                       regulator for pull-up
-*       USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage
-*                         regulator depend on Vddd Voltage configuration in DWR.
-*
-* Return:
-*   None.
-*
-* Global variables:
-*   USBFS_device: Contains the device number of the desired device
-*       descriptor. The device number can be found in the Device Descriptor Tab
-*       of "Configure" dialog, under the settings of desired Device Descriptor,
-*       in the "Device Number" field.
-*   USBFS_transferState: This variable used by the communication
-*       functions to handle current transfer state. Initialized to
-*       TRANS_STATE_IDLE in this API.
-*   USBFS_configuration: Contains current configuration number
-*       which is set by the Host using SET_CONFIGURATION request.
-*       Initialized to zero in this API.
-*   USBFS_deviceAddress: Contains current device address. This
-*       variable is initialized to zero in this API. Host starts to communicate
-*      to device with address 0 and then set it to whatever value using
-*      SET_ADDRESS request.
-*   USBFS_deviceStatus: initialized to 0.
-*       This is two bit variable which contain power status in first bit
-*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
-*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
-*   USBFS_lastPacketSize initialized to 0;
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_InitComponent(uint8 device, uint8 mode) 
-{
-    /* Initialize _hidProtocol variable to comply with
-    *  HID 7.2.6 Set_Protocol Request:
-    *  "When initialized, all devices default to report protocol."
-    */
-    #if defined(USBFS_ENABLE_HID_CLASS)
-        uint8 i;
-
-        for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)
-        {
-            USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;
-        }
-    #endif /* USBFS_ENABLE_HID_CLASS */
-
-    /* Enable Interrupts. */
-    CyIntEnable(USBFS_BUS_RESET_VECT_NUM);
-    CyIntEnable(USBFS_EP_0_VECT_NUM);
-    #if(USBFS_EP1_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_1_VECT_NUM);
-    #endif   /*  USBFS_EP1_ISR_REMOVE */
-    #if(USBFS_EP2_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_2_VECT_NUM);
-    #endif   /*  USBFS_EP2_ISR_REMOVE */
-    #if(USBFS_EP3_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_3_VECT_NUM);
-    #endif   /*  USBFS_EP3_ISR_REMOVE */
-    #if(USBFS_EP4_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_4_VECT_NUM);
-    #endif   /*  USBFS_EP4_ISR_REMOVE */
-    #if(USBFS_EP5_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_5_VECT_NUM);
-    #endif   /*  USBFS_EP5_ISR_REMOVE */
-    #if(USBFS_EP6_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_6_VECT_NUM);
-    #endif   /*  USBFS_EP6_ISR_REMOVE */
-    #if(USBFS_EP7_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_7_VECT_NUM);
-    #endif   /*  USBFS_EP7_ISR_REMOVE */
-    #if(USBFS_EP8_ISR_REMOVE == 0u)
-        CyIntEnable(USBFS_EP_8_VECT_NUM);
-    #endif   /*  USBFS_EP8_ISR_REMOVE */
-    #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
-        /* usb arb interrupt enable */
-        USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
-        CyIntEnable(USBFS_ARB_VECT_NUM);
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-    /* Arbiter configuration for DMA transfers */
-    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
-            USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            /*Set cfg cmplt this rises DMA request when the full configuration is done */
-            USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
-                /* Init interrupt which handles verification of the successful DMA transaction */
-                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
-                USBFS_EP17_DMA_Done_SR_InterruptEnable();
-                USBFS_EP8_DMA_Done_SR_InterruptEnable();
-            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
-        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-    USBFS_transferState = USBFS_TRANS_STATE_IDLE;
-
-    /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/
-    switch(mode)
-    {
-        case USBFS_3V_OPERATION:
-            USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
-            break;
-        case USBFS_5V_OPERATION:
-            USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            break;
-        default:   /*USBFS_DWR_VDDD_OPERATION */
-            #if(USBFS_VDDD_MV < USBFS_3500MV)
-                USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
-            #else
-                USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
-            break;
-    }
-
-    /* Record the descriptor selection */
-    USBFS_device = device;
-
-    /* Clear all of the component data */
-    USBFS_configuration = 0u;
-    USBFS_interfaceNumber = 0u;
-    USBFS_configurationChanged = 0u;
-    USBFS_deviceAddress  = 0u;
-    USBFS_deviceStatus = 0u;
-
-    USBFS_lastPacketSize = 0u;
-
-    /*  ACK Setup, Stall IN/OUT */
-    CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
-
-    /* Enable the SIE with an address 0 */
-    CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);
-
-    /* Workaround for PSOC5LP */
-    CyDelayCycles(1u);
-
-    /* Finally, Enable d+ pullup and select iomode to USB mode*/
-    CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_ReInitComponent
-********************************************************************************
-*
-* Summary:
-*  This function reinitialize the component configuration and is
-*  intend to be called from the Reset interrupt.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*   None.
-*
-* Global variables:
-*   USBFS_device: Contains the device number of the desired device
-*        descriptor. The device number can be found in the Device Descriptor Tab
-*       of "Configure" dialog, under the settings of desired Device Descriptor,
-*       in the "Device Number" field.
-*   USBFS_transferState: This variable used by the communication
-*       functions to handle current transfer state. Initialized to
-*       TRANS_STATE_IDLE in this API.
-*   USBFS_configuration: Contains current configuration number
-*       which is set by the Host using SET_CONFIGURATION request.
-*       Initialized to zero in this API.
-*   USBFS_deviceAddress: Contains current device address. This
-*       variable is initialized to zero in this API. Host starts to communicate
-*      to device with address 0 and then set it to whatever value using
-*      SET_ADDRESS request.
-*   USBFS_deviceStatus: initialized to 0.
-*       This is two bit variable which contain power status in first bit
-*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
-*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
-*   USBFS_lastPacketSize initialized to 0;
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_ReInitComponent(void) 
-{
-    /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol
-    *  Request: "When initialized, all devices default to report protocol."
-    */
-    #if defined(USBFS_ENABLE_HID_CLASS)
-        uint8 i;
-
-        for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)
-        {
-            USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;
-        }
-    #endif /* USBFS_ENABLE_HID_CLASS */
-
-    USBFS_transferState = USBFS_TRANS_STATE_IDLE;
-
-    /* Clear all of the component data */
-    USBFS_configuration = 0u;
-    USBFS_interfaceNumber = 0u;
-    USBFS_configurationChanged = 0u;
-    USBFS_deviceAddress  = 0u;
-    USBFS_deviceStatus = 0u;
-
-    USBFS_lastPacketSize = 0u;
-
-
-    /*  ACK Setup, Stall IN/OUT */
-    CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
-
-    /* Enable the SIE with an address 0 */
-    CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);
-
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Stop
-********************************************************************************
-*
-* Summary:
-*  This function shuts down the USB function including to release
-*  the D+ Pullup and disabling the SIE.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*   USBFS_configuration: Contains current configuration number
-*       which is set by the Host using SET_CONFIGURATION request.
-*       Initialized to zero in this API.
-*   USBFS_deviceAddress: Contains current device address. This
-*       variable is initialized to zero in this API. Host starts to communicate
-*      to device with address 0 and then set it to whatever value using
-*      SET_ADDRESS request.
-*   USBFS_deviceStatus: initialized to 0.
-*       This is two bit variable which contain power status in first bit
-*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
-*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
-*   USBFS_configurationChanged: This variable is set to one after
-*       SET_CONFIGURATION request and cleared in this function.
-*   USBFS_intiVar variable is set to zero
-*
-*******************************************************************************/
-void USBFS_Stop(void) 
-{
-
-    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-        USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-    /* Disable the SIE */
-    USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
-    /* Disable the d+ pullup */
-    USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN);
-    /* Disable USB in ACT PM */
-    USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB);
-    /* Disable USB block for Standby Power Mode */
-    USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB);
-
-    /* Disable the reset and EP interrupts */
-    CyIntDisable(USBFS_BUS_RESET_VECT_NUM);
-    CyIntDisable(USBFS_EP_0_VECT_NUM);
-    #if(USBFS_EP1_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_1_VECT_NUM);
-    #endif   /*  USBFS_EP1_ISR_REMOVE */
-    #if(USBFS_EP2_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_2_VECT_NUM);
-    #endif   /*  USBFS_EP2_ISR_REMOVE */
-    #if(USBFS_EP3_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_3_VECT_NUM);
-    #endif   /*  USBFS_EP3_ISR_REMOVE */
-    #if(USBFS_EP4_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_4_VECT_NUM);
-    #endif   /*  USBFS_EP4_ISR_REMOVE */
-    #if(USBFS_EP5_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_5_VECT_NUM);
-    #endif   /*  USBFS_EP5_ISR_REMOVE */
-    #if(USBFS_EP6_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_6_VECT_NUM);
-    #endif   /*  USBFS_EP6_ISR_REMOVE */
-    #if(USBFS_EP7_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_7_VECT_NUM);
-    #endif   /*  USBFS_EP7_ISR_REMOVE */
-    #if(USBFS_EP8_ISR_REMOVE == 0u)
-        CyIntDisable(USBFS_EP_8_VECT_NUM);
-    #endif   /*  USBFS_EP8_ISR_REMOVE */
-
-    /* Clear all of the component data */
-    USBFS_configuration = 0u;
-    USBFS_interfaceNumber = 0u;
-    USBFS_configurationChanged = 0u;
-    USBFS_deviceAddress  = 0u;
-    USBFS_deviceStatus = 0u;
-    USBFS_initVar = 0u;
-
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_CheckActivity
-********************************************************************************
-*
-* Summary:
-*  Returns the activity status of the bus.  Clears the status hardware to
-*  provide fresh activity status on the next call of this routine.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  1 - If bus activity was detected since the last call to this function
-*  0 - If bus activity not was detected since the last call to this function
-*
-*******************************************************************************/
-uint8 USBFS_CheckActivity(void) 
-{
-    uint8 r;
-
-    r = CY_GET_REG8(USBFS_CR1_PTR);
-    CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY))));
-
-    return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_GetConfiguration
-********************************************************************************
-*
-* Summary:
-*  Returns the current configuration setting
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  configuration.
-*
-*******************************************************************************/
-uint8 USBFS_GetConfiguration(void) 
-{
-    return(USBFS_configuration);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_IsConfigurationChanged
-********************************************************************************
-*
-* Summary:
-*  Returns the clear on read configuration state. It is usefull when PC send
-*  double SET_CONFIGURATION request with same configuration number.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Not zero value when new configuration has been changed, otherwise zero is
-*  returned.
-*
-* Global variables:
-*   USBFS_configurationChanged: This variable is set to one after
-*       SET_CONFIGURATION request and cleared in this function.
-*
-*******************************************************************************/
-uint8 USBFS_IsConfigurationChanged(void) 
-{
-    uint8 res = 0u;
-
-    if(USBFS_configurationChanged != 0u)
-    {
-        res = USBFS_configurationChanged;
-        USBFS_configurationChanged = 0u;
-    }
-
-    return(res);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_GetInterfaceSetting
-********************************************************************************
-*
-* Summary:
-*  Returns the alternate setting from current interface
-*
-* Parameters:
-*  uint8 interfaceNumber, interface number
-*
-* Return:
-*  Alternate setting.
-*
-*******************************************************************************/
-uint8  USBFS_GetInterfaceSetting(uint8 interfaceNumber)
-                                                    
-{
-    return(USBFS_interfaceSetting[interfaceNumber]);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_GetEPState
-********************************************************************************
-*
-* Summary:
-*  Returned the state of the requested endpoint.
-*
-* Parameters:
-*  epNumber: Endpoint Number
-*
-* Return:
-*  State of the requested endpoint.
-*
-*******************************************************************************/
-uint8 USBFS_GetEPState(uint8 epNumber) 
-{
-    return(USBFS_EP[epNumber].apiEpState);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_GetEPCount
-********************************************************************************
-*
-* Summary:
-*  This function supports Data Endpoints only(EP1-EP8).
-*  Returns the transfer count for the requested endpoint.  The value from
-*  the count registers includes 2 counts for the two byte checksum of the
-*  packet.  This function subtracts the two counts.
-*
-* Parameters:
-*  epNumber: Data Endpoint Number.
-*            Valid values are between 1 and 8.
-*
-* Return:
-*  Returns the current byte count from the specified endpoint or 0 for an
-*  invalid endpoint.
-*
-*******************************************************************************/
-uint16 USBFS_GetEPCount(uint8 epNumber) 
-{
-    uint8 ri;
-    uint16 result = 0u;
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-
-        result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) &
-                          USBFS_EPX_CNT0_MASK);
-        result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri));
-        result -= USBFS_EPX_CNTX_CRC_COUNT;
-    }
-    return(result);
-}
-
-
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
-
-    /*******************************************************************************
-    * Function Name: USBFS_InitEP_DMA
-    ********************************************************************************
-    *
-    * Summary:
-    *  This function allocates and initializes a DMA channel to be used by the
-    *  USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data
-    *  transfer.
-    *
-    * Parameters:
-    *  epNumber: Contains the data endpoint number.
-    *            Valid values are between 1 and 8.
-    *  *pData: Pointer to a data array that is related to the EP transfers.
-    *
-    * Return:
-    *  None.
-    *
-    * Reentrant:
-    *  No.
-    *
-    *******************************************************************************/
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
-                                                                    
-    {
-        uint16 src;
-        uint16 dst;
-        #if (CY_PSOC3)                  /* PSoC 3 */
-            src = HI16(CYDEV_SRAM_BASE);
-            dst = HI16(CYDEV_PERIPH_BASE);
-            pData = pData;
-        #else                           /* PSoC 5 */
-            if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u )
-            {   /* for the IN EP source is the SRAM memory buffer */
-                src = HI16(pData);
-                dst = HI16(CYDEV_PERIPH_BASE);
-            }
-            else
-            {   /* for the OUT EP source is the SIE register */
-                src = HI16(CYDEV_PERIPH_BASE);
-                dst = HI16(pData);
-            }
-        #endif  /*  C51 */
-        switch(epNumber)
-        {
-            case USBFS_EP1:
-                #if(USBFS_DMA1_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA1_REMOVE */
-                break;
-            case USBFS_EP2:
-                #if(USBFS_DMA2_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA2_REMOVE */
-                break;
-            case USBFS_EP3:
-                #if(USBFS_DMA3_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA3_REMOVE */
-                break;
-            case USBFS_EP4:
-                #if(USBFS_DMA4_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA4_REMOVE */
-                break;
-            case USBFS_EP5:
-                #if(USBFS_DMA5_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA5_REMOVE */
-                break;
-            case USBFS_EP6:
-                #if(USBFS_DMA6_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA6_REMOVE */
-                break;
-            case USBFS_EP7:
-                #if(USBFS_DMA7_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA7_REMOVE */
-                break;
-            case USBFS_EP8:
-                #if(USBFS_DMA8_REMOVE == 0u)
-                    USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
-                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /*  USBFS_DMA8_REMOVE */
-                break;
-            default:
-                /* Do not support EP0 DMA transfers */
-                break;
-        }
-        if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-        {
-            USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
-            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
-            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-
-        }
-    }
-
-
-    /*******************************************************************************
-    * Function Name: USBFS_Stop_DMA
-    ********************************************************************************
-    *
-    * Summary: Stops and free DMA
-    *
-    * Parameters:
-    *  epNumber: Contains the data endpoint number or
-    *           USBFS_MAX_EP to stop all DMAs
-    *
-    * Return:
-    *  None.
-    *
-    * Reentrant:
-    *  No.
-    *
-    *******************************************************************************/
-    void USBFS_Stop_DMA(uint8 epNumber) 
-    {
-        uint8 i;
-        i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1;
-        do
-        {
-            if(USBFS_DmaTd[i] != DMA_INVALID_TD)
-            {
-                (void) CyDmaChDisable(USBFS_DmaChan[i]);
-                CyDmaTdFree(USBFS_DmaTd[i]);
-                USBFS_DmaTd[i] = DMA_INVALID_TD;
-            }
-            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
-                {
-                    CyDmaTdFree(USBFS_DmaNextTd[i]);
-                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
-                }
-            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-            i++;
-        }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
-    }
-
-#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
-
-
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
-
-
-    /*******************************************************************************
-    * Function Name: USBFS_LoadNextInEP
-    ********************************************************************************
-    *
-    * Summary:
-    *  This internal function is used for IN endpoint DMA reconfiguration in
-    *  Auto DMA mode.
-    *
-    * Parameters:
-    *  epNumber: Contains the data endpoint number.
-    *  mode:   0 - Configure DMA to send the the rest of data.
-    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
-    *
-    * Return:
-    *  None.
-    *
-    *******************************************************************************/
-    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
-    {
-        reg16 *convert;
-
-        if(mode == 0u)
-        {
-            /* Configure DMA to send the the rest of data */
-            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
-            /* Set transfer length */
-            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
-            /* CyDmaTdSetAddress API is optimized to change only source address */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
-            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
-                                            USBFS_DMA_BYTES_PER_BURST));
-            USBFS_inBufFull[epNumber] = 1u;
-        }
-        else
-        {
-            /* Configure DMA to repeat 2 last bytes of the first burst. */
-            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
-            /* Set transfer length */
-            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
-            /* CyDmaTdSetAddress API is optimized to change only source address */
-            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
-            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
-                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
-        }
-
-        /* CyDmaChSetInitialTd API is optimised to init TD */
-        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
-    }
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
-
-
-/*******************************************************************************
-* Function Name: USBFS_LoadInEP
-********************************************************************************
-*
-* Summary:
-*  Loads and enables the specified USB data endpoint for an IN transfer.
-*
-* Parameters:
-*  epNumber: Contains the data endpoint number.
-*            Valid values are between 1 and 8.
-*  *pData: A pointer to a data array from which the data for the endpoint space
-*          is loaded.
-*  length: The number of bytes to transfer from the array and then send as a
-*          result of an IN request. Valid values are between 0 and 512.
-*
-* Return:
-*  None.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
-                                                                        
-{
-    uint8 ri;
-    reg8 *p;
-    #if(USBFS_EP_MM == USBFS__EP_MANUAL)
-        uint16 i;
-    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-        p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);
-
-        #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-            /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */
-            if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))
-            {
-                length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
-            }
-        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
-
-        /* Set the count and data toggle */
-        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
-                            (length >> 8u) | (USBFS_EP[epNumber].epToggle));
-        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri),  length & 0xFFu);
-
-        #if(USBFS_EP_MM == USBFS__EP_MANUAL)
-            if(pData != NULL)
-            {
-                /* Copy the data using the arbiter data register */
-                for (i = 0u; i < length; i++)
-                {
-                    CY_SET_REG8(p, pData[i]);
-                }
-            }
-            USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            /* Write the Mode register */
-            CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
-        #else
-            /* Init DMA if it was not initialized */
-            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
-            {
-                USBFS_InitEP_DMA(epNumber, pData);
-            }
-        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
-
-        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
-            USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            if ((pData != NULL) && (length > 0u))
-            {
-                /* Enable DMA in mode2 for transferring data */
-                (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
-                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
-                                                                                 TD_TERMIN_EN | TD_INC_SRC_ADR);
-                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
-                /* Enable the DMA */
-                (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
-                (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
-                /* Generate DMA request */
-                * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
-                * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
-                /* Mode register will be written in arb ISR after DMA transfer complete */
-            }
-            else
-            {
-                /* When zero-length packet - write the Mode register directly */
-                CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
-            }
-        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-
-        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            if (pData != NULL)
-            {
-                /* Enable DMA in mode3 for transferring data */
-                (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
-            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
-                USBFS_inLength[epNumber] = length;
-                USBFS_inDataPointer[epNumber] = pData;
-                /* Configure DMA to send the data only for the first burst */
-                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
-                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
-                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
-                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
-                /* The second TD will be executed only when the first one fails.
-                *  The intention of this TD is to generate NRQ interrupt
-                *  and repeat 2 last bytes of the first burst.
-                */
-                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
-                                               USBFS_DmaNextTd[epNumber],
-                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
-                /* Configure DmaNextTd to clear Data ready status */
-                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
-                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
-            #else /* Configure DMA to send all data*/
-                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
-                                               USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
-                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
-            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
-
-                /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
-                (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
-                /* Enable the DMA */
-                (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
-                (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
-            }
-            else
-            {
-                USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-                if(length > 0u)
-                {
-                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
-                    USBFS_inLength[epNumber] = length;
-                    USBFS_inBufFull[epNumber] = 0u;
-                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
-                    /* Configure DMA to send the data only for the first burst */
-                    (void) CyDmaTdSetConfiguration(
-                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
-                        USBFS_DMA_BYTES_PER_BURST : length,
-                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
-                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
-                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
-                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
-                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
-                    /* Enable the DMA */
-                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
-                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
-                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
-
-                    /* Set Data ready status, This will generate DMA request */
-                    #ifndef USBFS_MANUAL_IN_EP_ARM
-                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
-                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
-                    /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
-                }
-                else
-                {
-                    /* When zero-length packet - write the Mode register directly */
-                    CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
-                }
-            }
-        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_ReadOutEP
-********************************************************************************
-*
-* Summary:
-*  Read data from an endpoint.  The application must call
-*  USBFS_GetEPState to see if an event is pending.
-*
-* Parameters:
-*  epNumber: Contains the data endpoint number.
-*            Valid values are between 1 and 8.
-*  pData: A pointer to a data array from which the data for the endpoint space
-*         is loaded.
-*  length: The number of bytes to transfer from the USB Out endpoint and loads
-*          it into data array. Valid values are between 0 and 1023. The function
-*          moves fewer than the requested number of bytes if the host sends
-*          fewer bytes than requested.
-*
-* Returns:
-*  Number of bytes received, 0 for an invalid endpoint.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
-                                                                        
-{
-    uint8 ri;
-    reg8 *p;
-    #if(USBFS_EP_MM == USBFS__EP_MANUAL)
-        uint16 i;
-    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
-    #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-        uint16 xferCount;
-    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-        p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);
-
-        #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-            /* Determine which is smaller the requested data or the available data */
-            xferCount = USBFS_GetEPCount(epNumber);
-            if (length > xferCount)
-            {
-                length = xferCount;
-            }
-        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
-
-        #if(USBFS_EP_MM == USBFS__EP_MANUAL)
-            /* Copy the data using the arbiter data register */
-            for (i = 0u; i < length; i++)
-            {
-                pData[i] = CY_GET_REG8(p);
-            }
-
-            /* (re)arming of OUT endpoint */
-            USBFS_EnableOutEP(epNumber);
-        #else
-            /*Init DMA if it was not initialized */
-            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
-            {
-                USBFS_InitEP_DMA(epNumber, pData);
-            }
-
-        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
-
-        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
-            /* Enable DMA in mode2 for transferring data */
-            (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
-            (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
-                                                                                TD_TERMIN_EN | TD_INC_DST_ADR);
-            (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)p), LO16((uint32)pData));
-            /* Enable the DMA */
-            (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
-            (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
-
-            /* Generate DMA request */
-            * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
-            * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
-            /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-
-        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            /* Enable DMA in mode3 for transferring data */
-            (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
-            (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber],
-                                                                                TD_TERMIN_EN | TD_INC_DST_ADR);
-            (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)p), LO16((uint32)pData));
-
-            /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
-            (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
-            /* Enable the DMA */
-            (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
-            (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
-            /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
-    }
-    else
-    {
-        length = 0u;
-    }
-
-    return(length);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_EnableOutEP
-********************************************************************************
-*
-* Summary:
-*  This function enables an OUT endpoint.  It should not be
-*  called for an IN endpoint.
-*
-* Parameters:
-*  epNumber: Endpoint Number
-*            Valid values are between 1 and 8.
-*
-* Return:
-*   None.
-*
-* Global variables:
-*  USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_EnableOutEP(uint8 epNumber) 
-{
-    uint8 ri;
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-        USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-        /* Write the Mode register */
-        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_DisableOutEP
-********************************************************************************
-*
-* Summary:
-*  This function disables an OUT endpoint.  It should not be
-*  called for an IN endpoint.
-*
-* Parameters:
-*  epNumber: Endpoint Number
-*            Valid values are between 1 and 8.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void USBFS_DisableOutEP(uint8 epNumber) 
-{
-    uint8 ri ;
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-        /* Write the Mode register */
-        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Force
-********************************************************************************
-*
-* Summary:
-*  Forces the bus state
-*
-* Parameters:
-*  bState
-*    USBFS_FORCE_J
-*    USBFS_FORCE_K
-*    USBFS_FORCE_SE0
-*    USBFS_FORCE_NONE
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void USBFS_Force(uint8 bState) 
-{
-    CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_GetEPAckState
-********************************************************************************
-*
-* Summary:
-*  Returns the ACK of the CR0 Register (ACKD)
-*
-* Parameters:
-*  epNumber: Endpoint Number
-*            Valid values are between 1 and 8.
-*
-* Returns
-*  0 if nothing has been ACKD, non-=zero something has been ACKD
-*
-*******************************************************************************/
-uint8 USBFS_GetEPAckState(uint8 epNumber) 
-{
-    uint8 ri;
-    uint8 cr = 0u;
-
-    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
-    {
-        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-        cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD;
-    }
-
-    return(cr);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_SetPowerStatus
-********************************************************************************
-*
-* Summary:
-*  Sets the device power status for reporting in the Get Device Status
-*  request
-*
-* Parameters:
-*  powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered,
-*               USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered
-*
-* Return:
-*   None.
-*
-* Global variables:
-*  USBFS_deviceStatus - set power status
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void USBFS_SetPowerStatus(uint8 powerStatus) 
-{
-    if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED)
-    {
-        USBFS_deviceStatus |=  USBFS_DEVICE_STATUS_SELF_POWERED;
-    }
-    else
-    {
-        USBFS_deviceStatus &=  ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED));
-    }
-}
-
-
-#if (USBFS_MON_VBUS == 1u)
-
-    /*******************************************************************************
-    * Function Name: USBFS_VBusPresent
-    ********************************************************************************
-    *
-    * Summary:
-    *  Determines VBUS presence for Self Powered Devices.
-    *
-    * Parameters:
-    *  None.
-    *
-    * Return:
-    *  1 if VBUS is present, otherwise 0.
-    *
-    *******************************************************************************/
-    uint8 USBFS_VBusPresent(void) 
-    {
-        return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u);
-    }
-
-#endif /* USBFS_MON_VBUS */
-
-
-/*******************************************************************************
-* Function Name: USBFS_RWUEnabled
-********************************************************************************
-*
-* Summary:
-*  Returns TRUE if Remote Wake Up is enabled, otherwise FALSE
-*
-* Parameters:
-*   None.
-*
-* Return:
-*  TRUE -  Remote Wake Up Enabled
-*  FALSE - Remote Wake Up Disabled
-*
-* Global variables:
-*  USBFS_deviceStatus - checked to determine remote status
-*
-*******************************************************************************/
-uint8 USBFS_RWUEnabled(void) 
-{
-    uint8 result = USBFS_FALSE;
-    if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u)
-    {
-        result = USBFS_TRUE;
-    }
-
-    return(result);
-}
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: USBFS.c
+* Version 2.80
+*
+* Description:
+*  API for USBFS Component.
+*
+* Note:
+*  Many of the functions use endpoint number.  RAM arrays are sized with 9
+*  elements so they are indexed directly by epNumber.  The SIE and ARB
+*  registers are indexed by variations of epNumber - 1.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <CyDmac.h>
+#include "USBFS.h"
+#include "USBFS_pvt.h"
+#include "USBFS_hid.h"
+#if(USBFS_DMA1_REMOVE == 0u)
+    #include "USBFS_ep1_dma.h"
+#endif   /*  USBFS_DMA1_REMOVE */
+#if(USBFS_DMA2_REMOVE == 0u)
+    #include "USBFS_ep2_dma.h"
+#endif   /*  USBFS_DMA2_REMOVE */
+#if(USBFS_DMA3_REMOVE == 0u)
+    #include "USBFS_ep3_dma.h"
+#endif   /*  USBFS_DMA3_REMOVE */
+#if(USBFS_DMA4_REMOVE == 0u)
+    #include "USBFS_ep4_dma.h"
+#endif   /*  USBFS_DMA4_REMOVE */
+#if(USBFS_DMA5_REMOVE == 0u)
+    #include "USBFS_ep5_dma.h"
+#endif   /*  USBFS_DMA5_REMOVE */
+#if(USBFS_DMA6_REMOVE == 0u)
+    #include "USBFS_ep6_dma.h"
+#endif   /*  USBFS_DMA6_REMOVE */
+#if(USBFS_DMA7_REMOVE == 0u)
+    #include "USBFS_ep7_dma.h"
+#endif   /*  USBFS_DMA7_REMOVE */
+#if(USBFS_DMA8_REMOVE == 0u)
+    #include "USBFS_ep8_dma.h"
+#endif   /*  USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP_DMA_Done_isr.h"
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
+
+/***************************************
+* Global data allocation
+***************************************/
+
+uint8 USBFS_initVar = 0u;
+#if(USBFS_EP_MM != USBFS__EP_MANUAL)
+    uint8 USBFS_DmaChan[USBFS_MAX_EP];
+    uint8 USBFS_DmaTd[USBFS_MAX_EP];
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+    {   0u,
+        USBFS_ep1_TD_TERMOUT_EN,
+        USBFS_ep2_TD_TERMOUT_EN,
+        USBFS_ep3_TD_TERMOUT_EN,
+        USBFS_ep4_TD_TERMOUT_EN,
+        USBFS_ep5_TD_TERMOUT_EN,
+        USBFS_ep6_TD_TERMOUT_EN,
+        USBFS_ep7_TD_TERMOUT_EN,
+        USBFS_ep8_TD_TERMOUT_EN
+    };
+    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
+
+/*******************************************************************************
+* Function Name: USBFS_Start
+********************************************************************************
+*
+* Summary:
+*  This function initialize the USB SIE, arbiter and the
+*  endpoint APIs, including setting the D+ Pullup
+*
+* Parameters:
+*  device: Contains the device number of the desired device descriptor.
+*          The device number can be found in the Device Descriptor Tab of
+*          "Configure" dialog, under the settings of desired Device Descriptor,
+*          in the "Device Number" field.
+*  mode: The operating voltage. This determines whether the voltage regulator
+*        is enabled for 5V operation or if pass through mode is used for 3.3V
+*        operation. Symbolic names and their associated values are given in the
+*        following table.
+*       USBFS_3V_OPERATION - Disable voltage regulator and pass-thru
+*                                       Vcc for pull-up
+*       USBFS_5V_OPERATION - Enable voltage regulator and use
+*                                       regulator for pull-up
+*       USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage
+*                         regulator depend on Vddd Voltage configuration in DWR.
+*
+* Return:
+*   None.
+*
+* Global variables:
+*  The USBFS_intiVar variable is used to indicate initial
+*  configuration of this component. The variable is initialized to zero (0u)
+*  and set to one (1u) the first time USBFS_Start() is called.
+*  This allows for component Re-Start without unnecessary re-initialization
+*  in all subsequent calls to the USBFS_Start() routine.
+*  If re-initialization of the component is required the variable should be set
+*  to zero before call of UART_Start() routine, or the user may call
+*  USBFS_Init() and USBFS_InitComponent() as done
+*  in the USBFS_Start() routine.
+*
+* Side Effects:
+*   This function will reset all communication states to default.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_Start(uint8 device, uint8 mode) 
+{
+    /* If not Initialized then initialize all required hardware and software */
+    if(USBFS_initVar == 0u)
+    {
+        USBFS_Init();
+        USBFS_initVar = 1u;
+    }
+    USBFS_InitComponent(device, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Init
+********************************************************************************
+*
+* Summary:
+*  Initialize component's hardware. Usually called in USBFS_Start().
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_Init(void) 
+{
+    uint8 enableInterrupts;
+    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
+        uint16 i;
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+    enableInterrupts = CyEnterCriticalSection();
+
+    /* Enable USB block  */
+    USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
+    /* Enable USB block for Standby Power Mode */
+    USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;
+
+    /* Enable core clock */
+    USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE;
+
+    USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
+
+    /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */
+    /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
+    USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN));
+    CyDelayUs(0u);  /*~50ns delay */
+    /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted)
+    *  high. This will have been set low by the power manger out of reset.
+    *  Also confirm USBIO pull-up disabled
+    */
+    USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N |
+                                                  USBFS_PM_USB_CR0_PD_PULLUP_N)));
+
+    /* Select iomode to USB mode*/
+    USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE));
+
+    /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
+    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;
+    /* The reference will be available 1 us after the regulator is enabled */
+    CyDelayUs(1u);
+    /* OR 40us after power restored */
+    CyDelayUs(40u);
+    /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */
+    USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK));
+    USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK));
+
+    /* Enable USBIO */
+    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;
+    CyDelayUs(2u);
+    /* Set the USBIO pull-up enable */
+    USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
+
+    /* Write WAx */
+    CY_SET_REG8(USBFS_ARB_RW1_WA_PTR,     0u);
+    CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u);
+
+    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
+        /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */
+        for (i = 0u; i < USBFS_MAX_EP; i++)
+        {
+            USBFS_DmaTd[i] = DMA_INVALID_TD;
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+        }
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+    CyExitCriticalSection(enableInterrupts);
+
+
+    /* Set the bus reset Interrupt. */
+    (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM,   &USBFS_BUS_RESET_ISR);
+    CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);
+
+    /* Set the SOF Interrupt. */
+    #if(USBFS_SOF_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
+        CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
+    #endif   /*  USBFS_SOF_ISR_REMOVE */
+
+    /* Set the Control Endpoint Interrupt. */
+    (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
+    CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);
+
+    /* Set the Data Endpoint 1 Interrupt. */
+    #if(USBFS_EP1_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
+        CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
+
+    /* Set the Data Endpoint 2 Interrupt. */
+    #if(USBFS_EP2_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
+        CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
+
+    /* Set the Data Endpoint 3 Interrupt. */
+    #if(USBFS_EP3_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
+        CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
+
+    /* Set the Data Endpoint 4 Interrupt. */
+    #if(USBFS_EP4_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
+        CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
+
+    /* Set the Data Endpoint 5 Interrupt. */
+    #if(USBFS_EP5_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
+        CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
+
+    /* Set the Data Endpoint 6 Interrupt. */
+    #if(USBFS_EP6_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
+        CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
+
+     /* Set the Data Endpoint 7 Interrupt. */
+    #if(USBFS_EP7_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
+        CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
+
+    /* Set the Data Endpoint 8 Interrupt. */
+    #if(USBFS_EP8_ISR_REMOVE == 0u)
+        (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
+        CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
+
+    #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
+        /* Set the ARB Interrupt. */
+        (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
+        CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_InitComponent
+********************************************************************************
+*
+* Summary:
+*  Initialize the component, except for the HW which is done one time in
+*  the Start function.  This function pulls up D+.
+*
+* Parameters:
+*  device: Contains the device number of the desired device descriptor.
+*          The device number can be found in the Device Descriptor Tab of
+*          "Configure" dialog, under the settings of desired Device Descriptor,
+*          in the "Device Number" field.
+*  mode: The operating voltage. This determines whether the voltage regulator
+*        is enabled for 5V operation or if pass through mode is used for 3.3V
+*        operation. Symbolic names and their associated values are given in the
+*        following table.
+*       USBFS_3V_OPERATION - Disable voltage regulator and pass-thru
+*                                       Vcc for pull-up
+*       USBFS_5V_OPERATION - Enable voltage regulator and use
+*                                       regulator for pull-up
+*       USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage
+*                         regulator depend on Vddd Voltage configuration in DWR.
+*
+* Return:
+*   None.
+*
+* Global variables:
+*   USBFS_device: Contains the device number of the desired device
+*       descriptor. The device number can be found in the Device Descriptor Tab
+*       of "Configure" dialog, under the settings of desired Device Descriptor,
+*       in the "Device Number" field.
+*   USBFS_transferState: This variable used by the communication
+*       functions to handle current transfer state. Initialized to
+*       TRANS_STATE_IDLE in this API.
+*   USBFS_configuration: Contains current configuration number
+*       which is set by the Host using SET_CONFIGURATION request.
+*       Initialized to zero in this API.
+*   USBFS_deviceAddress: Contains current device address. This
+*       variable is initialized to zero in this API. Host starts to communicate
+*      to device with address 0 and then set it to whatever value using
+*      SET_ADDRESS request.
+*   USBFS_deviceStatus: initialized to 0.
+*       This is two bit variable which contain power status in first bit
+*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
+*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
+*   USBFS_lastPacketSize initialized to 0;
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_InitComponent(uint8 device, uint8 mode) 
+{
+    /* Initialize _hidProtocol variable to comply with
+    *  HID 7.2.6 Set_Protocol Request:
+    *  "When initialized, all devices default to report protocol."
+    */
+    #if defined(USBFS_ENABLE_HID_CLASS)
+        uint8 i;
+
+        for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)
+        {
+            USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;
+        }
+    #endif /* USBFS_ENABLE_HID_CLASS */
+
+    /* Enable Interrupts. */
+    CyIntEnable(USBFS_BUS_RESET_VECT_NUM);
+    CyIntEnable(USBFS_EP_0_VECT_NUM);
+    #if(USBFS_EP1_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_1_VECT_NUM);
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
+    #if(USBFS_EP2_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_2_VECT_NUM);
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
+    #if(USBFS_EP3_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_3_VECT_NUM);
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
+    #if(USBFS_EP4_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_4_VECT_NUM);
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
+    #if(USBFS_EP5_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_5_VECT_NUM);
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
+    #if(USBFS_EP6_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_6_VECT_NUM);
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
+    #if(USBFS_EP7_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_7_VECT_NUM);
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
+    #if(USBFS_EP8_ISR_REMOVE == 0u)
+        CyIntEnable(USBFS_EP_8_VECT_NUM);
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
+    #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
+        /* usb arb interrupt enable */
+        USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
+        CyIntEnable(USBFS_ARB_VECT_NUM);
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+    /* Arbiter configuration for DMA transfers */
+    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
+        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
+            USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
+            /*Set cfg cmplt this rises DMA request when the full configuration is done */
+            USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
+            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+                /* Init interrupt which handles verification of the successful DMA transaction */
+                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+                USBFS_EP17_DMA_Done_SR_InterruptEnable();
+                USBFS_EP8_DMA_Done_SR_InterruptEnable();
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+    USBFS_transferState = USBFS_TRANS_STATE_IDLE;
+
+    /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/
+    switch(mode)
+    {
+        case USBFS_3V_OPERATION:
+            USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
+            break;
+        case USBFS_5V_OPERATION:
+            USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
+            break;
+        default:   /*USBFS_DWR_VDDD_OPERATION */
+            #if(USBFS_VDDD_MV < USBFS_3500MV)
+                USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
+            #else
+                USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
+            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
+            break;
+    }
+
+    /* Record the descriptor selection */
+    USBFS_device = device;
+
+    /* Clear all of the component data */
+    USBFS_configuration = 0u;
+    USBFS_interfaceNumber = 0u;
+    USBFS_configurationChanged = 0u;
+    USBFS_deviceAddress  = 0u;
+    USBFS_deviceStatus = 0u;
+
+    USBFS_lastPacketSize = 0u;
+
+    /*  ACK Setup, Stall IN/OUT */
+    CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
+
+    /* Enable the SIE with an address 0 */
+    CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);
+
+    /* Workaround for PSOC5LP */
+    CyDelayCycles(1u);
+
+    /* Finally, Enable d+ pullup and select iomode to USB mode*/
+    CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_ReInitComponent
+********************************************************************************
+*
+* Summary:
+*  This function reinitialize the component configuration and is
+*  intend to be called from the Reset interrupt.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*   None.
+*
+* Global variables:
+*   USBFS_device: Contains the device number of the desired device
+*        descriptor. The device number can be found in the Device Descriptor Tab
+*       of "Configure" dialog, under the settings of desired Device Descriptor,
+*       in the "Device Number" field.
+*   USBFS_transferState: This variable used by the communication
+*       functions to handle current transfer state. Initialized to
+*       TRANS_STATE_IDLE in this API.
+*   USBFS_configuration: Contains current configuration number
+*       which is set by the Host using SET_CONFIGURATION request.
+*       Initialized to zero in this API.
+*   USBFS_deviceAddress: Contains current device address. This
+*       variable is initialized to zero in this API. Host starts to communicate
+*      to device with address 0 and then set it to whatever value using
+*      SET_ADDRESS request.
+*   USBFS_deviceStatus: initialized to 0.
+*       This is two bit variable which contain power status in first bit
+*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
+*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
+*   USBFS_lastPacketSize initialized to 0;
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_ReInitComponent(void) 
+{
+    /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol
+    *  Request: "When initialized, all devices default to report protocol."
+    */
+    #if defined(USBFS_ENABLE_HID_CLASS)
+        uint8 i;
+
+        for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)
+        {
+            USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;
+        }
+    #endif /* USBFS_ENABLE_HID_CLASS */
+
+    USBFS_transferState = USBFS_TRANS_STATE_IDLE;
+
+    /* Clear all of the component data */
+    USBFS_configuration = 0u;
+    USBFS_interfaceNumber = 0u;
+    USBFS_configurationChanged = 0u;
+    USBFS_deviceAddress  = 0u;
+    USBFS_deviceStatus = 0u;
+
+    USBFS_lastPacketSize = 0u;
+
+
+    /*  ACK Setup, Stall IN/OUT */
+    CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
+
+    /* Enable the SIE with an address 0 */
+    CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);
+
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Stop
+********************************************************************************
+*
+* Summary:
+*  This function shuts down the USB function including to release
+*  the D+ Pullup and disabling the SIE.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  None.
+*
+* Global variables:
+*   USBFS_configuration: Contains current configuration number
+*       which is set by the Host using SET_CONFIGURATION request.
+*       Initialized to zero in this API.
+*   USBFS_deviceAddress: Contains current device address. This
+*       variable is initialized to zero in this API. Host starts to communicate
+*      to device with address 0 and then set it to whatever value using
+*      SET_ADDRESS request.
+*   USBFS_deviceStatus: initialized to 0.
+*       This is two bit variable which contain power status in first bit
+*       (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
+*       wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
+*   USBFS_configurationChanged: This variable is set to one after
+*       SET_CONFIGURATION request and cleared in this function.
+*   USBFS_intiVar variable is set to zero
+*
+*******************************************************************************/
+void USBFS_Stop(void) 
+{
+
+    #if(USBFS_EP_MM != USBFS__EP_MANUAL)
+        USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+    /* Disable the SIE */
+    USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
+    /* Disable the d+ pullup */
+    USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN);
+    /* Disable USB in ACT PM */
+    USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB);
+    /* Disable USB block for Standby Power Mode */
+    USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB);
+
+    /* Disable the reset and EP interrupts */
+    CyIntDisable(USBFS_BUS_RESET_VECT_NUM);
+    CyIntDisable(USBFS_EP_0_VECT_NUM);
+    #if(USBFS_EP1_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_1_VECT_NUM);
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
+    #if(USBFS_EP2_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_2_VECT_NUM);
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
+    #if(USBFS_EP3_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_3_VECT_NUM);
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
+    #if(USBFS_EP4_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_4_VECT_NUM);
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
+    #if(USBFS_EP5_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_5_VECT_NUM);
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
+    #if(USBFS_EP6_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_6_VECT_NUM);
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
+    #if(USBFS_EP7_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_7_VECT_NUM);
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
+    #if(USBFS_EP8_ISR_REMOVE == 0u)
+        CyIntDisable(USBFS_EP_8_VECT_NUM);
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
+
+    /* Clear all of the component data */
+    USBFS_configuration = 0u;
+    USBFS_interfaceNumber = 0u;
+    USBFS_configurationChanged = 0u;
+    USBFS_deviceAddress  = 0u;
+    USBFS_deviceStatus = 0u;
+    USBFS_initVar = 0u;
+
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_CheckActivity
+********************************************************************************
+*
+* Summary:
+*  Returns the activity status of the bus.  Clears the status hardware to
+*  provide fresh activity status on the next call of this routine.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  1 - If bus activity was detected since the last call to this function
+*  0 - If bus activity not was detected since the last call to this function
+*
+*******************************************************************************/
+uint8 USBFS_CheckActivity(void) 
+{
+    uint8 r;
+
+    r = CY_GET_REG8(USBFS_CR1_PTR);
+    CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY))));
+
+    return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_GetConfiguration
+********************************************************************************
+*
+* Summary:
+*  Returns the current configuration setting
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  configuration.
+*
+*******************************************************************************/
+uint8 USBFS_GetConfiguration(void) 
+{
+    return(USBFS_configuration);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_IsConfigurationChanged
+********************************************************************************
+*
+* Summary:
+*  Returns the clear on read configuration state. It is usefull when PC send
+*  double SET_CONFIGURATION request with same configuration number.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Not zero value when new configuration has been changed, otherwise zero is
+*  returned.
+*
+* Global variables:
+*   USBFS_configurationChanged: This variable is set to one after
+*       SET_CONFIGURATION request and cleared in this function.
+*
+*******************************************************************************/
+uint8 USBFS_IsConfigurationChanged(void) 
+{
+    uint8 res = 0u;
+
+    if(USBFS_configurationChanged != 0u)
+    {
+        res = USBFS_configurationChanged;
+        USBFS_configurationChanged = 0u;
+    }
+
+    return(res);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_GetInterfaceSetting
+********************************************************************************
+*
+* Summary:
+*  Returns the alternate setting from current interface
+*
+* Parameters:
+*  uint8 interfaceNumber, interface number
+*
+* Return:
+*  Alternate setting.
+*
+*******************************************************************************/
+uint8  USBFS_GetInterfaceSetting(uint8 interfaceNumber)
+                                                    
+{
+    return(USBFS_interfaceSetting[interfaceNumber]);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_GetEPState
+********************************************************************************
+*
+* Summary:
+*  Returned the state of the requested endpoint.
+*
+* Parameters:
+*  epNumber: Endpoint Number
+*
+* Return:
+*  State of the requested endpoint.
+*
+*******************************************************************************/
+uint8 USBFS_GetEPState(uint8 epNumber) 
+{
+    return(USBFS_EP[epNumber].apiEpState);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_GetEPCount
+********************************************************************************
+*
+* Summary:
+*  This function supports Data Endpoints only(EP1-EP8).
+*  Returns the transfer count for the requested endpoint.  The value from
+*  the count registers includes 2 counts for the two byte checksum of the
+*  packet.  This function subtracts the two counts.
+*
+* Parameters:
+*  epNumber: Data Endpoint Number.
+*            Valid values are between 1 and 8.
+*
+* Return:
+*  Returns the current byte count from the specified endpoint or 0 for an
+*  invalid endpoint.
+*
+*******************************************************************************/
+uint16 USBFS_GetEPCount(uint8 epNumber) 
+{
+    uint8 ri;
+    uint16 result = 0u;
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+
+        result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) &
+                          USBFS_EPX_CNT0_MASK);
+        result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri));
+        result -= USBFS_EPX_CNTX_CRC_COUNT;
+    }
+    return(result);
+}
+
+
+#if(USBFS_EP_MM != USBFS__EP_MANUAL)
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_InitEP_DMA
+    ********************************************************************************
+    *
+    * Summary:
+    *  This function allocates and initializes a DMA channel to be used by the
+    *  USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data
+    *  transfer.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *            Valid values are between 1 and 8.
+    *  *pData: Pointer to a data array that is related to the EP transfers.
+    *
+    * Return:
+    *  None.
+    *
+    * Reentrant:
+    *  No.
+    *
+    *******************************************************************************/
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
+                                                                    
+    {
+        uint16 src;
+        uint16 dst;
+        #if (CY_PSOC3)                  /* PSoC 3 */
+            src = HI16(CYDEV_SRAM_BASE);
+            dst = HI16(CYDEV_PERIPH_BASE);
+            pData = pData;
+        #else                           /* PSoC 5 */
+            if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u )
+            {   /* for the IN EP source is the SRAM memory buffer */
+                src = HI16(pData);
+                dst = HI16(CYDEV_PERIPH_BASE);
+            }
+            else
+            {   /* for the OUT EP source is the SIE register */
+                src = HI16(CYDEV_PERIPH_BASE);
+                dst = HI16(pData);
+            }
+        #endif  /*  C51 */
+        switch(epNumber)
+        {
+            case USBFS_EP1:
+                #if(USBFS_DMA1_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA1_REMOVE */
+                break;
+            case USBFS_EP2:
+                #if(USBFS_DMA2_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA2_REMOVE */
+                break;
+            case USBFS_EP3:
+                #if(USBFS_DMA3_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA3_REMOVE */
+                break;
+            case USBFS_EP4:
+                #if(USBFS_DMA4_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA4_REMOVE */
+                break;
+            case USBFS_EP5:
+                #if(USBFS_DMA5_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA5_REMOVE */
+                break;
+            case USBFS_EP6:
+                #if(USBFS_DMA6_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA6_REMOVE */
+                break;
+            case USBFS_EP7:
+                #if(USBFS_DMA7_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA7_REMOVE */
+                break;
+            case USBFS_EP8:
+                #if(USBFS_DMA8_REMOVE == 0u)
+                    USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
+                        USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
+                #endif   /*  USBFS_DMA8_REMOVE */
+                break;
+            default:
+                /* Do not support EP0 DMA transfers */
+                break;
+        }
+        if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+        {
+            USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_Stop_DMA
+    ********************************************************************************
+    *
+    * Summary: Stops and free DMA
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number or
+    *           USBFS_MAX_EP to stop all DMAs
+    *
+    * Return:
+    *  None.
+    *
+    * Reentrant:
+    *  No.
+    *
+    *******************************************************************************/
+    void USBFS_Stop_DMA(uint8 epNumber) 
+    {
+        uint8 i;
+        i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1;
+        do
+        {
+            if(USBFS_DmaTd[i] != DMA_INVALID_TD)
+            {
+                (void) CyDmaChDisable(USBFS_DmaChan[i]);
+                CyDmaTdFree(USBFS_DmaTd[i]);
+                USBFS_DmaTd[i] = DMA_INVALID_TD;
+            }
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+                {
+                    CyDmaTdFree(USBFS_DmaNextTd[i]);
+                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+                }
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+            i++;
+        }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
+    }
+
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_LoadNextInEP
+    ********************************************************************************
+    *
+    * Summary:
+    *  This internal function is used for IN endpoint DMA reconfiguration in
+    *  Auto DMA mode.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *  mode:   0 - Configure DMA to send the the rest of data.
+    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
+    {
+        reg16 *convert;
+
+        if(mode == 0u)
+        {
+            /* Configure DMA to send the the rest of data */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                            USBFS_DMA_BYTES_PER_BURST));
+            USBFS_inBufFull[epNumber] = 1u;
+        }
+        else
+        {
+            /* Configure DMA to repeat 2 last bytes of the first burst. */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+        }
+
+        /* CyDmaChSetInitialTd API is optimised to init TD */
+        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
+
+/*******************************************************************************
+* Function Name: USBFS_LoadInEP
+********************************************************************************
+*
+* Summary:
+*  Loads and enables the specified USB data endpoint for an IN transfer.
+*
+* Parameters:
+*  epNumber: Contains the data endpoint number.
+*            Valid values are between 1 and 8.
+*  *pData: A pointer to a data array from which the data for the endpoint space
+*          is loaded.
+*  length: The number of bytes to transfer from the array and then send as a
+*          result of an IN request. Valid values are between 0 and 512.
+*
+* Return:
+*  None.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
+                                                                        
+{
+    uint8 ri;
+    reg8 *p;
+    #if(USBFS_EP_MM == USBFS__EP_MANUAL)
+        uint16 i;
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+        p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);
+
+        #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
+            /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */
+            if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))
+            {
+                length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
+            }
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
+
+        /* Set the count and data toggle */
+        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
+                            (length >> 8u) | (USBFS_EP[epNumber].epToggle));
+        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri),  length & 0xFFu);
+
+        #if(USBFS_EP_MM == USBFS__EP_MANUAL)
+            if(pData != NULL)
+            {
+                /* Copy the data using the arbiter data register */
+                for (i = 0u; i < length; i++)
+                {
+                    CY_SET_REG8(p, pData[i]);
+                }
+            }
+            USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
+            /* Write the Mode register */
+            CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
+        #else
+            /* Init DMA if it was not initialized */
+            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            {
+                USBFS_InitEP_DMA(epNumber, pData);
+            }
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
+            USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
+            if ((pData != NULL) && (length > 0u))
+            {
+                /* Enable DMA in mode2 for transferring data */
+                (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
+                                                                                 TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* Enable the DMA */
+                (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                /* Generate DMA request */
+                * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
+                * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
+                /* Mode register will be written in arb ISR after DMA transfer complete */
+            }
+            else
+            {
+                /* When zero-length packet - write the Mode register directly */
+                CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
+            }
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+
+        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
+            if (pData != NULL)
+            {
+                /* Enable DMA in mode3 for transferring data */
+                (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                USBFS_inLength[epNumber] = length;
+                USBFS_inDataPointer[epNumber] = pData;
+                /* Configure DMA to send the data only for the first burst */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* The second TD will be executed only when the first one fails.
+                *  The intention of this TD is to generate NRQ interrupt
+                *  and repeat 2 last bytes of the first burst.
+                */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+                                               USBFS_DmaNextTd[epNumber],
+                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
+                /* Configure DmaNextTd to clear Data ready status */
+                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
+                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+            #else /* Configure DMA to send all data*/
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
+                                               USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
+                /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                /* Enable the DMA */
+                (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+            }
+            else
+            {
+                USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
+                if(length > 0u)
+                {
+                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                    USBFS_inLength[epNumber] = length;
+                    USBFS_inBufFull[epNumber] = 0u;
+                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                    /* Configure DMA to send the data only for the first burst */
+                    (void) CyDmaTdSetConfiguration(
+                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+                        USBFS_DMA_BYTES_PER_BURST : length,
+                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                    /* Enable the DMA */
+                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
+                    /* Set Data ready status, This will generate DMA request */
+                    #ifndef USBFS_MANUAL_IN_EP_ARM
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
+                    /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
+                }
+                else
+                {
+                    /* When zero-length packet - write the Mode register directly */
+                    CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
+                }
+            }
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_ReadOutEP
+********************************************************************************
+*
+* Summary:
+*  Read data from an endpoint.  The application must call
+*  USBFS_GetEPState to see if an event is pending.
+*
+* Parameters:
+*  epNumber: Contains the data endpoint number.
+*            Valid values are between 1 and 8.
+*  pData: A pointer to a data array from which the data for the endpoint space
+*         is loaded.
+*  length: The number of bytes to transfer from the USB Out endpoint and loads
+*          it into data array. Valid values are between 0 and 1023. The function
+*          moves fewer than the requested number of bytes if the host sends
+*          fewer bytes than requested.
+*
+* Returns:
+*  Number of bytes received, 0 for an invalid endpoint.
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
+                                                                        
+{
+    uint8 ri;
+    reg8 *p;
+    #if(USBFS_EP_MM == USBFS__EP_MANUAL)
+        uint16 i;
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
+    #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
+        uint16 xferCount;
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+        p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);
+
+        #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
+            /* Determine which is smaller the requested data or the available data */
+            xferCount = USBFS_GetEPCount(epNumber);
+            if (length > xferCount)
+            {
+                length = xferCount;
+            }
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
+
+        #if(USBFS_EP_MM == USBFS__EP_MANUAL)
+            /* Copy the data using the arbiter data register */
+            for (i = 0u; i < length; i++)
+            {
+                pData[i] = CY_GET_REG8(p);
+            }
+
+            /* (re)arming of OUT endpoint */
+            USBFS_EnableOutEP(epNumber);
+        #else
+            /*Init DMA if it was not initialized */
+            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            {
+                USBFS_InitEP_DMA(epNumber, pData);
+            }
+
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
+            /* Enable DMA in mode2 for transferring data */
+            (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
+                                                                                TD_TERMIN_EN | TD_INC_DST_ADR);
+            (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)p), LO16((uint32)pData));
+            /* Enable the DMA */
+            (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+            (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+
+            /* Generate DMA request */
+            * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
+            * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
+            /* Out EP will be (re)armed in arb ISR after transfer complete */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+
+        #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
+            /* Enable DMA in mode3 for transferring data */
+            (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber],
+                                                                                TD_TERMIN_EN | TD_INC_DST_ADR);
+            (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)p), LO16((uint32)pData));
+
+            /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+            (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+            /* Enable the DMA */
+            (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+            (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+            /* Out EP will be (re)armed in arb ISR after transfer complete */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+    }
+    else
+    {
+        length = 0u;
+    }
+
+    return(length);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_EnableOutEP
+********************************************************************************
+*
+* Summary:
+*  This function enables an OUT endpoint.  It should not be
+*  called for an IN endpoint.
+*
+* Parameters:
+*  epNumber: Endpoint Number
+*            Valid values are between 1 and 8.
+*
+* Return:
+*   None.
+*
+* Global variables:
+*  USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_EnableOutEP(uint8 epNumber) 
+{
+    uint8 ri;
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+        USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
+        /* Write the Mode register */
+        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_DisableOutEP
+********************************************************************************
+*
+* Summary:
+*  This function disables an OUT endpoint.  It should not be
+*  called for an IN endpoint.
+*
+* Parameters:
+*  epNumber: Endpoint Number
+*            Valid values are between 1 and 8.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void USBFS_DisableOutEP(uint8 epNumber) 
+{
+    uint8 ri ;
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+        /* Write the Mode register */
+        CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Force
+********************************************************************************
+*
+* Summary:
+*  Forces the bus state
+*
+* Parameters:
+*  bState
+*    USBFS_FORCE_J
+*    USBFS_FORCE_K
+*    USBFS_FORCE_SE0
+*    USBFS_FORCE_NONE
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void USBFS_Force(uint8 bState) 
+{
+    CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_GetEPAckState
+********************************************************************************
+*
+* Summary:
+*  Returns the ACK of the CR0 Register (ACKD)
+*
+* Parameters:
+*  epNumber: Endpoint Number
+*            Valid values are between 1 and 8.
+*
+* Returns
+*  0 if nothing has been ACKD, non-=zero something has been ACKD
+*
+*******************************************************************************/
+uint8 USBFS_GetEPAckState(uint8 epNumber) 
+{
+    uint8 ri;
+    uint8 cr = 0u;
+
+    if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
+    {
+        ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+        cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD;
+    }
+
+    return(cr);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_SetPowerStatus
+********************************************************************************
+*
+* Summary:
+*  Sets the device power status for reporting in the Get Device Status
+*  request
+*
+* Parameters:
+*  powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered,
+*               USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered
+*
+* Return:
+*   None.
+*
+* Global variables:
+*  USBFS_deviceStatus - set power status
+*
+* Reentrant:
+*  No.
+*
+*******************************************************************************/
+void USBFS_SetPowerStatus(uint8 powerStatus) 
+{
+    if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED)
+    {
+        USBFS_deviceStatus |=  USBFS_DEVICE_STATUS_SELF_POWERED;
+    }
+    else
+    {
+        USBFS_deviceStatus &=  ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED));
+    }
+}
+
+
+#if (USBFS_MON_VBUS == 1u)
+
+    /*******************************************************************************
+    * Function Name: USBFS_VBusPresent
+    ********************************************************************************
+    *
+    * Summary:
+    *  Determines VBUS presence for Self Powered Devices.
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  1 if VBUS is present, otherwise 0.
+    *
+    *******************************************************************************/
+    uint8 USBFS_VBusPresent(void) 
+    {
+        return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u);
+    }
+
+#endif /* USBFS_MON_VBUS */
+
+
+/*******************************************************************************
+* Function Name: USBFS_RWUEnabled
+********************************************************************************
+*
+* Summary:
+*  Returns TRUE if Remote Wake Up is enabled, otherwise FALSE
+*
+* Parameters:
+*   None.
+*
+* Return:
+*  TRUE -  Remote Wake Up Enabled
+*  FALSE - Remote Wake Up Disabled
+*
+* Global variables:
+*  USBFS_deviceStatus - checked to determine remote status
+*
+*******************************************************************************/
+uint8 USBFS_RWUEnabled(void) 
+{
+    uint8 result = USBFS_FALSE;
+    if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u)
+    {
+        result = USBFS_TRUE;
+    }
+
+    return(result);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h

@@ -1,1255 +1,1255 @@
-/*******************************************************************************
-* File Name: USBFS.h
-* Version 2.80
-*
-* Description:
-*  Header File for the USBFS component. Contains prototypes and constant values.
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_USBFS_USBFS_H)
-#define CY_USBFS_USBFS_H
-
-#include "cytypes.h"
-#include "cydevice_trm.h"
-#include "cyfitter.h"
-#include "CyLib.h"
-
-/*  User supplied definitions. */
-/* `#START USER_DEFINITIONS` Place your declaration here */
-
-/* `#END` */
-
-
-/***************************************
-* Conditional Compilation Parameters
-***************************************/
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5LP) */
-
-
-/***************************************
-*  Memory Type Definitions
-***************************************/
-
-/* Renamed Type Definitions for backward compatibility.
-*  Should not be used in new designs.
-*/
-#define USBFS_CODE CYCODE
-#define USBFS_FAR CYFAR
-#if defined(__C51__) || defined(__CX51__)
-    #define USBFS_DATA data
-    #define USBFS_XDATA xdata
-#else
-    #define USBFS_DATA
-    #define USBFS_XDATA
-#endif /*  __C51__ */
-#define USBFS_NULL       NULL
-
-
-/***************************************
-* Enumerated Types and Parameters
-***************************************/
-
-#define USBFS__EP_MANUAL 0
-#define USBFS__EP_DMAMANUAL 1
-#define USBFS__EP_DMAAUTO 2
-
-#define USBFS__MA_STATIC 0
-#define USBFS__MA_DYNAMIC 1
-
-
-
-/***************************************
-*    Initial Parameter Constants
-***************************************/
-
-#define USBFS_NUM_DEVICES   (1u)
-#define USBFS_ENABLE_DESCRIPTOR_STRINGS   
-#define USBFS_ENABLE_SN_STRING   
-#define USBFS_ENABLE_STRINGS   
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE   (65u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS   (1u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE   (65u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS   (1u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT   (1u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE   (65u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS   (1u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE   (65u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS   (1u)
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT   (1u)
-#define USBFS_ENABLE_HID_CLASS   
-#define USBFS_HID_RPT_1_SIZE_LSB   (0x25u)
-#define USBFS_HID_RPT_1_SIZE_MSB   (0x00u)
-#define USBFS_HID_RPT_2_SIZE_LSB   (0x25u)
-#define USBFS_HID_RPT_2_SIZE_MSB   (0x00u)
-#define USBFS_MAX_REPORTID_NUMBER   (0u)
-
-#define USBFS_MON_VBUS                       (0u)
-#define USBFS_EXTERN_VBUS                    (0u)
-#define USBFS_EXTERN_VND                     (0u)
-#define USBFS_EXTERN_CLS                     (0u)
-#define USBFS_MAX_INTERFACES_NUMBER          (2u)
-#define USBFS_EP0_ISR_REMOVE                 (0u)
-#define USBFS_EP1_ISR_REMOVE                 (0u)
-#define USBFS_EP2_ISR_REMOVE                 (0u)
-#define USBFS_EP3_ISR_REMOVE                 (0u)
-#define USBFS_EP4_ISR_REMOVE                 (0u)
-#define USBFS_EP5_ISR_REMOVE                 (1u)
-#define USBFS_EP6_ISR_REMOVE                 (1u)
-#define USBFS_EP7_ISR_REMOVE                 (1u)
-#define USBFS_EP8_ISR_REMOVE                 (1u)
-#define USBFS_EP_MM                          (0u)
-#define USBFS_EP_MA                          (0u)
-#define USBFS_EP_DMA_AUTO_OPT                (0u)
-#define USBFS_DMA1_REMOVE                    (1u)
-#define USBFS_DMA2_REMOVE                    (1u)
-#define USBFS_DMA3_REMOVE                    (1u)
-#define USBFS_DMA4_REMOVE                    (1u)
-#define USBFS_DMA5_REMOVE                    (1u)
-#define USBFS_DMA6_REMOVE                    (1u)
-#define USBFS_DMA7_REMOVE                    (1u)
-#define USBFS_DMA8_REMOVE                    (1u)
-#define USBFS_SOF_ISR_REMOVE                 (0u)
-#define USBFS_ARB_ISR_REMOVE                 (0u)
-#define USBFS_DP_ISR_REMOVE                  (0u)
-#define USBFS_ENABLE_CDC_CLASS_API           (1u)
-#define USBFS_ENABLE_MIDI_API                (1u)
-#define USBFS_MIDI_EXT_MODE                  (0u)
-
-
-/***************************************
-*    Data Struct Definition
-***************************************/
-
-typedef struct
-{
-    uint8  attrib;
-    uint8  apiEpState;
-    uint8  hwEpState;
-    uint8  epToggle;
-    uint8  addr;
-    uint8  epMode;
-    uint16 buffOffset;
-    uint16 bufferSize;
-    uint8  interface;
-} T_USBFS_EP_CTL_BLOCK;
-
-typedef struct
-{
-    uint8  interface;
-    uint8  altSetting;
-    uint8  addr;
-    uint8  attributes;
-    uint16 bufferSize;
-    uint8  bMisc;
-} T_USBFS_EP_SETTINGS_BLOCK;
-
-typedef struct
-{
-    uint8  status;
-    uint16 length;
-} T_USBFS_XFER_STATUS_BLOCK;
-
-typedef struct
-{
-    uint16  count;
-    volatile uint8 *pData;
-    T_USBFS_XFER_STATUS_BLOCK *pStatusBlock;
-} T_USBFS_TD;
-
-
-typedef struct
-{
-    uint8   c;
-    const void *p_list;
-} T_USBFS_LUT;
-
-/* Resume/Suspend API Support */
-typedef struct
-{
-    uint8 enableState;
-    uint8 mode;
-} USBFS_BACKUP_STRUCT;
-
-
-/* Renamed structure fields for backward compatibility.
-*  Should not be used in new designs.
-*/
-#define wBuffOffset         buffOffset
-#define wBufferSize         bufferSize
-#define bStatus             status
-#define wLength             length
-#define wCount              count
-
-/* Renamed global variable for backward compatibility.
-*  Should not be used in new designs.
-*/
-#define CurrentTD           USBFS_currentTD
-
-
-/***************************************
-*       Function Prototypes
-***************************************/
-
-void   USBFS_Start(uint8 device, uint8 mode) ;
-void   USBFS_Init(void) ;
-void   USBFS_InitComponent(uint8 device, uint8 mode) ;
-void   USBFS_Stop(void) ;
-uint8  USBFS_CheckActivity(void) ;
-uint8  USBFS_GetConfiguration(void) ;
-uint8  USBFS_IsConfigurationChanged(void) ;
-uint8  USBFS_GetInterfaceSetting(uint8 interfaceNumber)
-                                                        ;
-uint8  USBFS_GetEPState(uint8 epNumber) ;
-uint16 USBFS_GetEPCount(uint8 epNumber) ;
-void   USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
-                                                                    ;
-uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
-                                                                    ;
-void   USBFS_EnableOutEP(uint8 epNumber) ;
-void   USBFS_DisableOutEP(uint8 epNumber) ;
-void   USBFS_Force(uint8 bState) ;
-uint8  USBFS_GetEPAckState(uint8 epNumber) ;
-void   USBFS_SetPowerStatus(uint8 powerStatus) ;
-uint8  USBFS_RWUEnabled(void) ;
-void   USBFS_TerminateEP(uint8 ep) ;
-
-void   USBFS_Suspend(void) ;
-void   USBFS_Resume(void) ;
-
-#if defined(USBFS_ENABLE_FWSN_STRING)
-    void   USBFS_SerialNumString(uint8 snString[]) ;
-#endif  /* USBFS_ENABLE_FWSN_STRING */
-#if (USBFS_MON_VBUS == 1u)
-    uint8  USBFS_VBusPresent(void) ;
-#endif /*  USBFS_MON_VBUS */
-
-#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
-                                          (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
-
-    void USBFS_CyBtldrCommStart(void) ;
-    void USBFS_CyBtldrCommStop(void) ;
-    void USBFS_CyBtldrCommReset(void) ;
-    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
-                                                        ;
-    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
-                                                        ;
-
-    #define USBFS_BTLDR_OUT_EP      (0x01u)
-    #define USBFS_BTLDR_IN_EP       (0x02u)
-
-    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
-    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
-    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
-
-    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
-
-    /* These defines active if used USBFS interface as an
-    *  IO Component for bootloading. When Custom_Interface selected
-    *  in Bootloder configuration as the IO Component, user must
-    *  provide these functions.
-    */
-    #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
-        #define CyBtldrCommStart        USBFS_CyBtldrCommStart
-        #define CyBtldrCommStop         USBFS_CyBtldrCommStop
-        #define CyBtldrCommReset        USBFS_CyBtldrCommReset
-        #define CyBtldrCommWrite        USBFS_CyBtldrCommWrite
-        #define CyBtldrCommRead         USBFS_CyBtldrCommRead
-    #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
-
-#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
-
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
-                                                    ;
-    void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
-
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
-    void USBFS_MIDI_EP_Init(void) ;
-
-    #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
-        void USBFS_MIDI_IN_Service(void) ;
-        uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)
-                                                                ;
-    #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
-
-    #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
-        void USBFS_MIDI_OUT_EP_Service(void) ;
-    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-
-#endif /*  USBFS_ENABLE_MIDI_API != 0u */
-
-/* Renamed Functions for backward compatibility.
-*  Should not be used in new designs.
-*/
-
-#define USBFS_bCheckActivity             USBFS_CheckActivity
-#define USBFS_bGetConfiguration          USBFS_GetConfiguration
-#define USBFS_bGetInterfaceSetting       USBFS_GetInterfaceSetting
-#define USBFS_bGetEPState                USBFS_GetEPState
-#define USBFS_wGetEPCount                USBFS_GetEPCount
-#define USBFS_bGetEPAckState             USBFS_GetEPAckState
-#define USBFS_bRWUEnabled                USBFS_RWUEnabled
-#define USBFS_bVBusPresent               USBFS_VBusPresent
-
-#define USBFS_bConfiguration             USBFS_configuration
-#define USBFS_bInterfaceSetting          USBFS_interfaceSetting
-#define USBFS_bDeviceAddress             USBFS_deviceAddress
-#define USBFS_bDeviceStatus              USBFS_deviceStatus
-#define USBFS_bDevice                    USBFS_device
-#define USBFS_bTransferState             USBFS_transferState
-#define USBFS_bLastPacketSize            USBFS_lastPacketSize
-
-#define USBFS_LoadEP                     USBFS_LoadInEP
-#define USBFS_LoadInISOCEP               USBFS_LoadInEP
-#define USBFS_EnableOutISOCEP            USBFS_EnableOutEP
-
-#define USBFS_SetVector                  CyIntSetVector
-#define USBFS_SetPriority                CyIntSetPriority
-#define USBFS_EnableInt                  CyIntEnable
-
-
-/***************************************
-*          API Constants
-***************************************/
-
-#define USBFS_EP0                        (0u)
-#define USBFS_EP1                        (1u)
-#define USBFS_EP2                        (2u)
-#define USBFS_EP3                        (3u)
-#define USBFS_EP4                        (4u)
-#define USBFS_EP5                        (5u)
-#define USBFS_EP6                        (6u)
-#define USBFS_EP7                        (7u)
-#define USBFS_EP8                        (8u)
-#define USBFS_MAX_EP                     (9u)
-
-#define USBFS_TRUE                       (1u)
-#define USBFS_FALSE                      (0u)
-
-#define USBFS_NO_EVENT_ALLOWED           (2u)
-#define USBFS_EVENT_PENDING              (1u)
-#define USBFS_NO_EVENT_PENDING           (0u)
-
-#define USBFS_IN_BUFFER_FULL             USBFS_NO_EVENT_PENDING
-#define USBFS_IN_BUFFER_EMPTY            USBFS_EVENT_PENDING
-#define USBFS_OUT_BUFFER_FULL            USBFS_EVENT_PENDING
-#define USBFS_OUT_BUFFER_EMPTY           USBFS_NO_EVENT_PENDING
-
-#define USBFS_FORCE_J                    (0xA0u)
-#define USBFS_FORCE_K                    (0x80u)
-#define USBFS_FORCE_SE0                  (0xC0u)
-#define USBFS_FORCE_NONE                 (0x00u)
-
-#define USBFS_IDLE_TIMER_RUNNING         (0x02u)
-#define USBFS_IDLE_TIMER_EXPIRED         (0x01u)
-#define USBFS_IDLE_TIMER_INDEFINITE      (0x00u)
-
-#define USBFS_DEVICE_STATUS_BUS_POWERED  (0x00u)
-#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u)
-
-#define USBFS_3V_OPERATION               (0x00u)
-#define USBFS_5V_OPERATION               (0x01u)
-#define USBFS_DWR_VDDD_OPERATION         (0x02u)
-
-#define USBFS_MODE_DISABLE               (0x00u)
-#define USBFS_MODE_NAK_IN_OUT            (0x01u)
-#define USBFS_MODE_STATUS_OUT_ONLY       (0x02u)
-#define USBFS_MODE_STALL_IN_OUT          (0x03u)
-#define USBFS_MODE_RESERVED_0100         (0x04u)
-#define USBFS_MODE_ISO_OUT               (0x05u)
-#define USBFS_MODE_STATUS_IN_ONLY        (0x06u)
-#define USBFS_MODE_ISO_IN                (0x07u)
-#define USBFS_MODE_NAK_OUT               (0x08u)
-#define USBFS_MODE_ACK_OUT               (0x09u)
-#define USBFS_MODE_RESERVED_1010         (0x0Au)
-#define USBFS_MODE_ACK_OUT_STATUS_IN     (0x0Bu)
-#define USBFS_MODE_NAK_IN                (0x0Cu)
-#define USBFS_MODE_ACK_IN                (0x0Du)
-#define USBFS_MODE_RESERVED_1110         (0x0Eu)
-#define USBFS_MODE_ACK_IN_STATUS_OUT     (0x0Fu)
-#define USBFS_MODE_MASK                  (0x0Fu)
-#define USBFS_MODE_STALL_DATA_EP         (0x80u)
-
-#define USBFS_MODE_ACKD                  (0x10u)
-#define USBFS_MODE_OUT_RCVD              (0x20u)
-#define USBFS_MODE_IN_RCVD               (0x40u)
-#define USBFS_MODE_SETUP_RCVD            (0x80u)
-
-#define USBFS_RQST_TYPE_MASK             (0x60u)
-#define USBFS_RQST_TYPE_STD              (0x00u)
-#define USBFS_RQST_TYPE_CLS              (0x20u)
-#define USBFS_RQST_TYPE_VND              (0x40u)
-#define USBFS_RQST_DIR_MASK              (0x80u)
-#define USBFS_RQST_DIR_D2H               (0x80u)
-#define USBFS_RQST_DIR_H2D               (0x00u)
-#define USBFS_RQST_RCPT_MASK             (0x03u)
-#define USBFS_RQST_RCPT_DEV              (0x00u)
-#define USBFS_RQST_RCPT_IFC              (0x01u)
-#define USBFS_RQST_RCPT_EP               (0x02u)
-#define USBFS_RQST_RCPT_OTHER            (0x03u)
-
-/* USB Class Codes */
-#define USBFS_CLASS_DEVICE               (0x00u)     /* Use class code info from Interface Descriptors */
-#define USBFS_CLASS_AUDIO                (0x01u)     /* Audio device */
-#define USBFS_CLASS_CDC                  (0x02u)     /* Communication device class */
-#define USBFS_CLASS_HID                  (0x03u)     /* Human Interface Device */
-#define USBFS_CLASS_PDC                  (0x05u)     /* Physical device class */
-#define USBFS_CLASS_IMAGE                (0x06u)     /* Still Imaging device */
-#define USBFS_CLASS_PRINTER              (0x07u)     /* Printer device  */
-#define USBFS_CLASS_MSD                  (0x08u)     /* Mass Storage device  */
-#define USBFS_CLASS_HUB                  (0x09u)     /* Full/Hi speed Hub */
-#define USBFS_CLASS_CDC_DATA             (0x0Au)     /* CDC data device */
-#define USBFS_CLASS_SMART_CARD           (0x0Bu)     /* Smart Card device */
-#define USBFS_CLASS_CSD                  (0x0Du)     /* Content Security device */
-#define USBFS_CLASS_VIDEO                (0x0Eu)     /* Video device */
-#define USBFS_CLASS_PHD                  (0x0Fu)     /* Personal Healthcare device */
-#define USBFS_CLASS_WIRELESSD            (0xDCu)     /* Wireless Controller */
-#define USBFS_CLASS_MIS                  (0xE0u)     /* Miscellaneous */
-#define USBFS_CLASS_APP                  (0xEFu)     /* Application Specific */
-#define USBFS_CLASS_VENDOR               (0xFFu)     /* Vendor specific */
-
-
-/* Standard Request Types (Table 9-4) */
-#define USBFS_GET_STATUS                 (0x00u)
-#define USBFS_CLEAR_FEATURE              (0x01u)
-#define USBFS_SET_FEATURE                (0x03u)
-#define USBFS_SET_ADDRESS                (0x05u)
-#define USBFS_GET_DESCRIPTOR             (0x06u)
-#define USBFS_SET_DESCRIPTOR             (0x07u)
-#define USBFS_GET_CONFIGURATION          (0x08u)
-#define USBFS_SET_CONFIGURATION          (0x09u)
-#define USBFS_GET_INTERFACE              (0x0Au)
-#define USBFS_SET_INTERFACE              (0x0Bu)
-#define USBFS_SYNCH_FRAME                (0x0Cu)
-
-/* Vendor Specific Request Types */
-/* Request for Microsoft OS String Descriptor */
-#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u)
-
-/* Descriptor Types (Table 9-5) */
-#define USBFS_DESCR_DEVICE                   (1u)
-#define USBFS_DESCR_CONFIG                   (2u)
-#define USBFS_DESCR_STRING                   (3u)
-#define USBFS_DESCR_INTERFACE                (4u)
-#define USBFS_DESCR_ENDPOINT                 (5u)
-#define USBFS_DESCR_DEVICE_QUALIFIER         (6u)
-#define USBFS_DESCR_OTHER_SPEED              (7u)
-#define USBFS_DESCR_INTERFACE_POWER          (8u)
-
-/* Device Descriptor Defines */
-#define USBFS_DEVICE_DESCR_LENGTH            (18u)
-#define USBFS_DEVICE_DESCR_SN_SHIFT          (16u)
-
-/* Config Descriptor Shifts and Masks */
-#define USBFS_CONFIG_DESCR_LENGTH                (0u)
-#define USBFS_CONFIG_DESCR_TYPE                  (1u)
-#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW      (2u)
-#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI       (3u)
-#define USBFS_CONFIG_DESCR_NUM_INTERFACES        (4u)
-#define USBFS_CONFIG_DESCR_CONFIG_VALUE          (5u)
-#define USBFS_CONFIG_DESCR_CONFIGURATION         (6u)
-#define USBFS_CONFIG_DESCR_ATTRIB                (7u)
-#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED   (0x40u)
-#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN         (0x20u)
-
-/* Feature Selectors (Table 9-6) */
-#define USBFS_DEVICE_REMOTE_WAKEUP           (0x01u)
-#define USBFS_ENDPOINT_HALT                  (0x00u)
-#define USBFS_TEST_MODE                      (0x02u)
-
-/* USB Device Status (Figure 9-4) */
-#define USBFS_DEVICE_STATUS_BUS_POWERED      (0x00u)
-#define USBFS_DEVICE_STATUS_SELF_POWERED     (0x01u)
-#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP    (0x02u)
-
-/* USB Endpoint Status (Figure 9-4) */
-#define USBFS_ENDPOINT_STATUS_HALT           (0x01u)
-
-/* USB Endpoint Directions */
-#define USBFS_DIR_IN                         (0x80u)
-#define USBFS_DIR_OUT                        (0x00u)
-#define USBFS_DIR_UNUSED                     (0x7Fu)
-
-/* USB Endpoint Attributes */
-#define USBFS_EP_TYPE_CTRL                   (0x00u)
-#define USBFS_EP_TYPE_ISOC                   (0x01u)
-#define USBFS_EP_TYPE_BULK                   (0x02u)
-#define USBFS_EP_TYPE_INT                    (0x03u)
-#define USBFS_EP_TYPE_MASK                   (0x03u)
-
-#define USBFS_EP_SYNC_TYPE_NO_SYNC           (0x00u)
-#define USBFS_EP_SYNC_TYPE_ASYNC             (0x04u)
-#define USBFS_EP_SYNC_TYPE_ADAPTIVE          (0x08u)
-#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS       (0x0Cu)
-#define USBFS_EP_SYNC_TYPE_MASK              (0x0Cu)
-
-#define USBFS_EP_USAGE_TYPE_DATA             (0x00u)
-#define USBFS_EP_USAGE_TYPE_FEEDBACK         (0x10u)
-#define USBFS_EP_USAGE_TYPE_IMPLICIT         (0x20u)
-#define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
-#define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
-
-/* point Status defines */
-#define USBFS_EP_STATUS_LENGTH               (0x02u)
-
-/* point Device defines */
-#define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
-
-#define USBFS_STATUS_LENGTH_MAX \
-                 ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \
-                    USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH )
-/* Transfer Completion Notification */
-#define USBFS_XFER_IDLE                      (0x00u)
-#define USBFS_XFER_STATUS_ACK                (0x01u)
-#define USBFS_XFER_PREMATURE                 (0x02u)
-#define USBFS_XFER_ERROR                     (0x03u)
-
-/* Driver State defines */
-#define USBFS_TRANS_STATE_IDLE               (0x00u)
-#define USBFS_TRANS_STATE_CONTROL_READ       (0x02u)
-#define USBFS_TRANS_STATE_CONTROL_WRITE      (0x04u)
-#define USBFS_TRANS_STATE_NO_DATA_CONTROL    (0x06u)
-
-/* String Descriptor defines */
-#define USBFS_STRING_MSOS                    (0xEEu)
-#define USBFS_MSOS_DESCRIPTOR_LENGTH         (18u)
-#define USBFS_MSOS_CONF_DESCR_LENGTH         (40u)
-
-#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
-    /* DMA manual mode defines */
-    #define USBFS_DMA_BYTES_PER_BURST        (0u)
-    #define USBFS_DMA_REQUEST_PER_BURST      (0u)
-#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-    /* DMA automatic mode defines */
-    #define USBFS_DMA_BYTES_PER_BURST        (32u)
-    #define USBFS_DMA_BYTES_REPEAT           (2u)
-    /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
-    #define USBFS_DMA_BUF_SIZE               (0x55u)
-    #define USBFS_DMA_REQUEST_PER_BURST      (1u)
-
-    #if(USBFS_DMA1_REMOVE == 0u)
-        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA1_REMOVE == 0u */
-    #if(USBFS_DMA2_REMOVE == 0u)
-        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA2_REMOVE == 0u */
-    #if(USBFS_DMA3_REMOVE == 0u)
-        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA3_REMOVE == 0u */
-    #if(USBFS_DMA4_REMOVE == 0u)
-        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA4_REMOVE == 0u */
-    #if(USBFS_DMA5_REMOVE == 0u)
-        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA5_REMOVE == 0u */
-    #if(USBFS_DMA6_REMOVE == 0u)
-        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA6_REMOVE == 0u */
-    #if(USBFS_DMA7_REMOVE == 0u)
-        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA7_REMOVE == 0u */
-    #if(USBFS_DMA8_REMOVE == 0u)
-        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
-    #else
-        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
-    #endif /* USBFS_DMA8_REMOVE == 0u */
-
-    #define     USBFS_EP17_SR_MASK           (0x7fu)
-    #define     USBFS_EP8_SR_MASK            (0x03u)
-
-#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
-/* DIE ID string descriptor defines */
-#if defined(USBFS_ENABLE_IDSN_STRING)
-    #define USBFS_IDSN_DESCR_LENGTH          (0x22u)
-#endif /* USBFS_ENABLE_IDSN_STRING */
-
-
-/***************************************
-* External data references
-***************************************/
-
-extern uint8 USBFS_initVar;
-extern volatile uint8 USBFS_device;
-extern volatile uint8 USBFS_transferState;
-extern volatile uint8 USBFS_configuration;
-extern volatile uint8 USBFS_configurationChanged;
-extern volatile uint8 USBFS_deviceStatus;
-
-/* HID Variables */
-#if defined(USBFS_ENABLE_HID_CLASS)
-    extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];
-    extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];
-    extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER];
-#endif /* USBFS_ENABLE_HID_CLASS */
-
-
-/***************************************
-*              Registers
-***************************************/
-
-#define USBFS_ARB_CFG_PTR        (  (reg8 *) USBFS_USB__ARB_CFG)
-#define USBFS_ARB_CFG_REG        (* (reg8 *) USBFS_USB__ARB_CFG)
-
-#define USBFS_ARB_EP1_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP1_CFG)
-#define USBFS_ARB_EP1_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP1_CFG)
-#define USBFS_ARB_EP1_CFG_IND    USBFS_USB__ARB_EP1_CFG
-#define USBFS_ARB_EP1_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP1_INT_EN)
-#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN)
-#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN
-#define USBFS_ARB_EP1_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP1_SR)
-#define USBFS_ARB_EP1_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP1_SR)
-#define USBFS_ARB_EP1_SR_IND     USBFS_USB__ARB_EP1_SR
-
-#define USBFS_ARB_EP2_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP2_CFG)
-#define USBFS_ARB_EP2_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP2_CFG)
-#define USBFS_ARB_EP2_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP2_INT_EN)
-#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN)
-#define USBFS_ARB_EP2_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP2_SR)
-#define USBFS_ARB_EP2_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP2_SR)
-
-#define USBFS_ARB_EP3_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP3_CFG)
-#define USBFS_ARB_EP3_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP3_CFG)
-#define USBFS_ARB_EP3_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP3_INT_EN)
-#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN)
-#define USBFS_ARB_EP3_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP3_SR)
-#define USBFS_ARB_EP3_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP3_SR)
-
-#define USBFS_ARB_EP4_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP4_CFG)
-#define USBFS_ARB_EP4_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP4_CFG)
-#define USBFS_ARB_EP4_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP4_INT_EN)
-#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN)
-#define USBFS_ARB_EP4_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP4_SR)
-#define USBFS_ARB_EP4_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP4_SR)
-
-#define USBFS_ARB_EP5_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP5_CFG)
-#define USBFS_ARB_EP5_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP5_CFG)
-#define USBFS_ARB_EP5_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP5_INT_EN)
-#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN)
-#define USBFS_ARB_EP5_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP5_SR)
-#define USBFS_ARB_EP5_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP5_SR)
-
-#define USBFS_ARB_EP6_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP6_CFG)
-#define USBFS_ARB_EP6_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP6_CFG)
-#define USBFS_ARB_EP6_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP6_INT_EN)
-#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN)
-#define USBFS_ARB_EP6_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP6_SR)
-#define USBFS_ARB_EP6_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP6_SR)
-
-#define USBFS_ARB_EP7_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP7_CFG)
-#define USBFS_ARB_EP7_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP7_CFG)
-#define USBFS_ARB_EP7_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP7_INT_EN)
-#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN)
-#define USBFS_ARB_EP7_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP7_SR)
-#define USBFS_ARB_EP7_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP7_SR)
-
-#define USBFS_ARB_EP8_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP8_CFG)
-#define USBFS_ARB_EP8_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP8_CFG)
-#define USBFS_ARB_EP8_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP8_INT_EN)
-#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN)
-#define USBFS_ARB_EP8_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP8_SR)
-#define USBFS_ARB_EP8_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP8_SR)
-
-#define USBFS_ARB_INT_EN_PTR     (  (reg8 *) USBFS_USB__ARB_INT_EN)
-#define USBFS_ARB_INT_EN_REG     (* (reg8 *) USBFS_USB__ARB_INT_EN)
-#define USBFS_ARB_INT_SR_PTR     (  (reg8 *) USBFS_USB__ARB_INT_SR)
-#define USBFS_ARB_INT_SR_REG     (* (reg8 *) USBFS_USB__ARB_INT_SR)
-
-#define USBFS_ARB_RW1_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW1_DR)
-#define USBFS_ARB_RW1_DR_IND     USBFS_USB__ARB_RW1_DR
-#define USBFS_ARB_RW1_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW1_RA)
-#define USBFS_ARB_RW1_RA_IND     USBFS_USB__ARB_RW1_RA
-#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB)
-#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB
-#define USBFS_ARB_RW1_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW1_WA)
-#define USBFS_ARB_RW1_WA_IND     USBFS_USB__ARB_RW1_WA
-#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB)
-#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB
-
-#define USBFS_ARB_RW2_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW2_DR)
-#define USBFS_ARB_RW2_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW2_RA)
-#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB)
-#define USBFS_ARB_RW2_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW2_WA)
-#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB)
-
-#define USBFS_ARB_RW3_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW3_DR)
-#define USBFS_ARB_RW3_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW3_RA)
-#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB)
-#define USBFS_ARB_RW3_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW3_WA)
-#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB)
-
-#define USBFS_ARB_RW4_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW4_DR)
-#define USBFS_ARB_RW4_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW4_RA)
-#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB)
-#define USBFS_ARB_RW4_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW4_WA)
-#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB)
-
-#define USBFS_ARB_RW5_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW5_DR)
-#define USBFS_ARB_RW5_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW5_RA)
-#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB)
-#define USBFS_ARB_RW5_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW5_WA)
-#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB)
-
-#define USBFS_ARB_RW6_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW6_DR)
-#define USBFS_ARB_RW6_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW6_RA)
-#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB)
-#define USBFS_ARB_RW6_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW6_WA)
-#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB)
-
-#define USBFS_ARB_RW7_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW7_DR)
-#define USBFS_ARB_RW7_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW7_RA)
-#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB)
-#define USBFS_ARB_RW7_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW7_WA)
-#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB)
-
-#define USBFS_ARB_RW8_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW8_DR)
-#define USBFS_ARB_RW8_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW8_RA)
-#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB)
-#define USBFS_ARB_RW8_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW8_WA)
-#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB)
-
-#define USBFS_BUF_SIZE_PTR       (  (reg8 *) USBFS_USB__BUF_SIZE)
-#define USBFS_BUF_SIZE_REG       (* (reg8 *) USBFS_USB__BUF_SIZE)
-#define USBFS_BUS_RST_CNT_PTR    (  (reg8 *) USBFS_USB__BUS_RST_CNT)
-#define USBFS_BUS_RST_CNT_REG    (* (reg8 *) USBFS_USB__BUS_RST_CNT)
-#define USBFS_CWA_PTR            (  (reg8 *) USBFS_USB__CWA)
-#define USBFS_CWA_REG            (* (reg8 *) USBFS_USB__CWA)
-#define USBFS_CWA_MSB_PTR        (  (reg8 *) USBFS_USB__CWA_MSB)
-#define USBFS_CWA_MSB_REG        (* (reg8 *) USBFS_USB__CWA_MSB)
-#define USBFS_CR0_PTR            (  (reg8 *) USBFS_USB__CR0)
-#define USBFS_CR0_REG            (* (reg8 *) USBFS_USB__CR0)
-#define USBFS_CR1_PTR            (  (reg8 *) USBFS_USB__CR1)
-#define USBFS_CR1_REG            (* (reg8 *) USBFS_USB__CR1)
-
-#define USBFS_DMA_THRES_PTR      (  (reg8 *) USBFS_USB__DMA_THRES)
-#define USBFS_DMA_THRES_REG      (* (reg8 *) USBFS_USB__DMA_THRES)
-#define USBFS_DMA_THRES_MSB_PTR  (  (reg8 *) USBFS_USB__DMA_THRES_MSB)
-#define USBFS_DMA_THRES_MSB_REG  (* (reg8 *) USBFS_USB__DMA_THRES_MSB)
-
-#define USBFS_EP_ACTIVE_PTR      (  (reg8 *) USBFS_USB__EP_ACTIVE)
-#define USBFS_EP_ACTIVE_REG      (* (reg8 *) USBFS_USB__EP_ACTIVE)
-#define USBFS_EP_TYPE_PTR        (  (reg8 *) USBFS_USB__EP_TYPE)
-#define USBFS_EP_TYPE_REG        (* (reg8 *) USBFS_USB__EP_TYPE)
-
-#define USBFS_EP0_CNT_PTR        (  (reg8 *) USBFS_USB__EP0_CNT)
-#define USBFS_EP0_CNT_REG        (* (reg8 *) USBFS_USB__EP0_CNT)
-#define USBFS_EP0_CR_PTR         (  (reg8 *) USBFS_USB__EP0_CR)
-#define USBFS_EP0_CR_REG         (* (reg8 *) USBFS_USB__EP0_CR)
-#define USBFS_EP0_DR0_PTR        (  (reg8 *) USBFS_USB__EP0_DR0)
-#define USBFS_EP0_DR0_REG        (* (reg8 *) USBFS_USB__EP0_DR0)
-#define USBFS_EP0_DR0_IND        USBFS_USB__EP0_DR0
-#define USBFS_EP0_DR1_PTR        (  (reg8 *) USBFS_USB__EP0_DR1)
-#define USBFS_EP0_DR1_REG        (* (reg8 *) USBFS_USB__EP0_DR1)
-#define USBFS_EP0_DR2_PTR        (  (reg8 *) USBFS_USB__EP0_DR2)
-#define USBFS_EP0_DR2_REG        (* (reg8 *) USBFS_USB__EP0_DR2)
-#define USBFS_EP0_DR3_PTR        (  (reg8 *) USBFS_USB__EP0_DR3)
-#define USBFS_EP0_DR3_REG        (* (reg8 *) USBFS_USB__EP0_DR3)
-#define USBFS_EP0_DR4_PTR        (  (reg8 *) USBFS_USB__EP0_DR4)
-#define USBFS_EP0_DR4_REG        (* (reg8 *) USBFS_USB__EP0_DR4)
-#define USBFS_EP0_DR5_PTR        (  (reg8 *) USBFS_USB__EP0_DR5)
-#define USBFS_EP0_DR5_REG        (* (reg8 *) USBFS_USB__EP0_DR5)
-#define USBFS_EP0_DR6_PTR        (  (reg8 *) USBFS_USB__EP0_DR6)
-#define USBFS_EP0_DR6_REG        (* (reg8 *) USBFS_USB__EP0_DR6)
-#define USBFS_EP0_DR7_PTR        (  (reg8 *) USBFS_USB__EP0_DR7)
-#define USBFS_EP0_DR7_REG        (* (reg8 *) USBFS_USB__EP0_DR7)
-
-#define USBFS_OSCLK_DR0_PTR      (  (reg8 *) USBFS_USB__OSCLK_DR0)
-#define USBFS_OSCLK_DR0_REG      (* (reg8 *) USBFS_USB__OSCLK_DR0)
-#define USBFS_OSCLK_DR1_PTR      (  (reg8 *) USBFS_USB__OSCLK_DR1)
-#define USBFS_OSCLK_DR1_REG      (* (reg8 *) USBFS_USB__OSCLK_DR1)
-
-#define USBFS_PM_ACT_CFG_PTR     (  (reg8 *) USBFS_USB__PM_ACT_CFG)
-#define USBFS_PM_ACT_CFG_REG     (* (reg8 *) USBFS_USB__PM_ACT_CFG)
-#define USBFS_PM_STBY_CFG_PTR    (  (reg8 *) USBFS_USB__PM_STBY_CFG)
-#define USBFS_PM_STBY_CFG_REG    (* (reg8 *) USBFS_USB__PM_STBY_CFG)
-
-#define USBFS_SIE_EP_INT_EN_PTR  (  (reg8 *) USBFS_USB__SIE_EP_INT_EN)
-#define USBFS_SIE_EP_INT_EN_REG  (* (reg8 *) USBFS_USB__SIE_EP_INT_EN)
-#define USBFS_SIE_EP_INT_SR_PTR  (  (reg8 *) USBFS_USB__SIE_EP_INT_SR)
-#define USBFS_SIE_EP_INT_SR_REG  (* (reg8 *) USBFS_USB__SIE_EP_INT_SR)
-
-#define USBFS_SIE_EP1_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP1_CNT0)
-#define USBFS_SIE_EP1_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP1_CNT0)
-#define USBFS_SIE_EP1_CNT0_IND   USBFS_USB__SIE_EP1_CNT0
-#define USBFS_SIE_EP1_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP1_CNT1)
-#define USBFS_SIE_EP1_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP1_CNT1)
-#define USBFS_SIE_EP1_CNT1_IND   USBFS_USB__SIE_EP1_CNT1
-#define USBFS_SIE_EP1_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP1_CR0)
-#define USBFS_SIE_EP1_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP1_CR0)
-#define USBFS_SIE_EP1_CR0_IND    USBFS_USB__SIE_EP1_CR0
-
-#define USBFS_SIE_EP2_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP2_CNT0)
-#define USBFS_SIE_EP2_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP2_CNT0)
-#define USBFS_SIE_EP2_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP2_CNT1)
-#define USBFS_SIE_EP2_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP2_CNT1)
-#define USBFS_SIE_EP2_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP2_CR0)
-#define USBFS_SIE_EP2_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP2_CR0)
-
-#define USBFS_SIE_EP3_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP3_CNT0)
-#define USBFS_SIE_EP3_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP3_CNT0)
-#define USBFS_SIE_EP3_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP3_CNT1)
-#define USBFS_SIE_EP3_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP3_CNT1)
-#define USBFS_SIE_EP3_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP3_CR0)
-#define USBFS_SIE_EP3_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP3_CR0)
-
-#define USBFS_SIE_EP4_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP4_CNT0)
-#define USBFS_SIE_EP4_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP4_CNT0)
-#define USBFS_SIE_EP4_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP4_CNT1)
-#define USBFS_SIE_EP4_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP4_CNT1)
-#define USBFS_SIE_EP4_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP4_CR0)
-#define USBFS_SIE_EP4_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP4_CR0)
-
-#define USBFS_SIE_EP5_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP5_CNT0)
-#define USBFS_SIE_EP5_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP5_CNT0)
-#define USBFS_SIE_EP5_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP5_CNT1)
-#define USBFS_SIE_EP5_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP5_CNT1)
-#define USBFS_SIE_EP5_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP5_CR0)
-#define USBFS_SIE_EP5_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP5_CR0)
-
-#define USBFS_SIE_EP6_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP6_CNT0)
-#define USBFS_SIE_EP6_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP6_CNT0)
-#define USBFS_SIE_EP6_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP6_CNT1)
-#define USBFS_SIE_EP6_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP6_CNT1)
-#define USBFS_SIE_EP6_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP6_CR0)
-#define USBFS_SIE_EP6_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP6_CR0)
-
-#define USBFS_SIE_EP7_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP7_CNT0)
-#define USBFS_SIE_EP7_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP7_CNT0)
-#define USBFS_SIE_EP7_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP7_CNT1)
-#define USBFS_SIE_EP7_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP7_CNT1)
-#define USBFS_SIE_EP7_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP7_CR0)
-#define USBFS_SIE_EP7_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP7_CR0)
-
-#define USBFS_SIE_EP8_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP8_CNT0)
-#define USBFS_SIE_EP8_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP8_CNT0)
-#define USBFS_SIE_EP8_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP8_CNT1)
-#define USBFS_SIE_EP8_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP8_CNT1)
-#define USBFS_SIE_EP8_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP8_CR0)
-#define USBFS_SIE_EP8_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP8_CR0)
-
-#define USBFS_SOF0_PTR           (  (reg8 *) USBFS_USB__SOF0)
-#define USBFS_SOF0_REG           (* (reg8 *) USBFS_USB__SOF0)
-#define USBFS_SOF1_PTR           (  (reg8 *) USBFS_USB__SOF1)
-#define USBFS_SOF1_REG           (* (reg8 *) USBFS_USB__SOF1)
-
-#define USBFS_USB_CLK_EN_PTR     (  (reg8 *) USBFS_USB__USB_CLK_EN)
-#define USBFS_USB_CLK_EN_REG     (* (reg8 *) USBFS_USB__USB_CLK_EN)
-
-#define USBFS_USBIO_CR0_PTR      (  (reg8 *) USBFS_USB__USBIO_CR0)
-#define USBFS_USBIO_CR0_REG      (* (reg8 *) USBFS_USB__USBIO_CR0)
-#define USBFS_USBIO_CR1_PTR      (  (reg8 *) USBFS_USB__USBIO_CR1)
-#define USBFS_USBIO_CR1_REG      (* (reg8 *) USBFS_USB__USBIO_CR1)
-#if(!CY_PSOC5LP)
-    #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
-    #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /*  CY_PSOC5LP */
-
-#define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
-
-#define USBFS_PM_USB_CR0_PTR     (  (reg8 *) CYREG_PM_USB_CR0)
-#define USBFS_PM_USB_CR0_REG     (* (reg8 *) CYREG_PM_USB_CR0)
-#define USBFS_DYN_RECONFIG_PTR   (  (reg8 *) USBFS_USB__DYN_RECONFIG)
-#define USBFS_DYN_RECONFIG_REG   (* (reg8 *) USBFS_USB__DYN_RECONFIG)
-
-#define USBFS_DM_INP_DIS_PTR     (  (reg8 *) USBFS_Dm__INP_DIS)
-#define USBFS_DM_INP_DIS_REG     (* (reg8 *) USBFS_Dm__INP_DIS)
-#define USBFS_DP_INP_DIS_PTR     (  (reg8 *) USBFS_Dp__INP_DIS)
-#define USBFS_DP_INP_DIS_REG     (* (reg8 *) USBFS_Dp__INP_DIS)
-#define USBFS_DP_INTSTAT_PTR     (  (reg8 *) USBFS_Dp__INTSTAT)
-#define USBFS_DP_INTSTAT_REG     (* (reg8 *) USBFS_Dp__INTSTAT)
-
-#if (USBFS_MON_VBUS == 1u)
-    #if (USBFS_EXTERN_VBUS == 0u)
-        #define USBFS_VBUS_DR_PTR        (  (reg8 *) USBFS_VBUS__DR)
-        #define USBFS_VBUS_DR_REG        (* (reg8 *) USBFS_VBUS__DR)
-        #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_VBUS__PS)
-        #define USBFS_VBUS_PS_REG        (* (reg8 *) USBFS_VBUS__PS)
-        #define USBFS_VBUS_MASK          USBFS_VBUS__MASK
-    #else
-        #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
-        #define USBFS_VBUS_MASK          (0x01u)
-    #endif /*  USBFS_EXTERN_VBUS == 0u */
-#endif /*  USBFS_MON_VBUS */
-
-/* Renamed Registers for backward compatibility.
-*  Should not be used in new designs.
-*/
-#define USBFS_ARB_CFG        USBFS_ARB_CFG_PTR
-
-#define USBFS_ARB_EP1_CFG    USBFS_ARB_EP1_CFG_PTR
-#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR
-#define USBFS_ARB_EP1_SR     USBFS_ARB_EP1_SR_PTR
-
-#define USBFS_ARB_EP2_CFG    USBFS_ARB_EP2_CFG_PTR
-#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR
-#define USBFS_ARB_EP2_SR     USBFS_ARB_EP2_SR_PTR
-
-#define USBFS_ARB_EP3_CFG    USBFS_ARB_EP3_CFG_PTR
-#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR
-#define USBFS_ARB_EP3_SR     USBFS_ARB_EP3_SR_PTR
-
-#define USBFS_ARB_EP4_CFG    USBFS_ARB_EP4_CFG_PTR
-#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR
-#define USBFS_ARB_EP4_SR     USBFS_ARB_EP4_SR_PTR
-
-#define USBFS_ARB_EP5_CFG    USBFS_ARB_EP5_CFG_PTR
-#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR
-#define USBFS_ARB_EP5_SR     USBFS_ARB_EP5_SR_PTR
-
-#define USBFS_ARB_EP6_CFG    USBFS_ARB_EP6_CFG_PTR
-#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR
-#define USBFS_ARB_EP6_SR     USBFS_ARB_EP6_SR_PTR
-
-#define USBFS_ARB_EP7_CFG    USBFS_ARB_EP7_CFG_PTR
-#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR
-#define USBFS_ARB_EP7_SR     USBFS_ARB_EP7_SR_PTR
-
-#define USBFS_ARB_EP8_CFG    USBFS_ARB_EP8_CFG_PTR
-#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR
-#define USBFS_ARB_EP8_SR     USBFS_ARB_EP8_SR_PTR
-
-#define USBFS_ARB_INT_EN     USBFS_ARB_INT_EN_PTR
-#define USBFS_ARB_INT_SR     USBFS_ARB_INT_SR_PTR
-
-#define USBFS_ARB_RW1_DR     USBFS_ARB_RW1_DR_PTR
-#define USBFS_ARB_RW1_RA     USBFS_ARB_RW1_RA_PTR
-#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR
-#define USBFS_ARB_RW1_WA     USBFS_ARB_RW1_WA_PTR
-#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR
-
-#define USBFS_ARB_RW2_DR     USBFS_ARB_RW2_DR_PTR
-#define USBFS_ARB_RW2_RA     USBFS_ARB_RW2_RA_PTR
-#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR
-#define USBFS_ARB_RW2_WA     USBFS_ARB_RW2_WA_PTR
-#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR
-
-#define USBFS_ARB_RW3_DR     USBFS_ARB_RW3_DR_PTR
-#define USBFS_ARB_RW3_RA     USBFS_ARB_RW3_RA_PTR
-#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR
-#define USBFS_ARB_RW3_WA     USBFS_ARB_RW3_WA_PTR
-#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR
-
-#define USBFS_ARB_RW4_DR     USBFS_ARB_RW4_DR_PTR
-#define USBFS_ARB_RW4_RA     USBFS_ARB_RW4_RA_PTR
-#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR
-#define USBFS_ARB_RW4_WA     USBFS_ARB_RW4_WA_PTR
-#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR
-
-#define USBFS_ARB_RW5_DR     USBFS_ARB_RW5_DR_PTR
-#define USBFS_ARB_RW5_RA     USBFS_ARB_RW5_RA_PTR
-#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR
-#define USBFS_ARB_RW5_WA     USBFS_ARB_RW5_WA_PTR
-#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR
-
-#define USBFS_ARB_RW6_DR     USBFS_ARB_RW6_DR_PTR
-#define USBFS_ARB_RW6_RA     USBFS_ARB_RW6_RA_PTR
-#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR
-#define USBFS_ARB_RW6_WA     USBFS_ARB_RW6_WA_PTR
-#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR
-
-#define USBFS_ARB_RW7_DR     USBFS_ARB_RW7_DR_PTR
-#define USBFS_ARB_RW7_RA     USBFS_ARB_RW7_RA_PTR
-#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR
-#define USBFS_ARB_RW7_WA     USBFS_ARB_RW7_WA_PTR
-#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR
-
-#define USBFS_ARB_RW8_DR     USBFS_ARB_RW8_DR_PTR
-#define USBFS_ARB_RW8_RA     USBFS_ARB_RW8_RA_PTR
-#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR
-#define USBFS_ARB_RW8_WA     USBFS_ARB_RW8_WA_PTR
-#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR
-
-#define USBFS_BUF_SIZE       USBFS_BUF_SIZE_PTR
-#define USBFS_BUS_RST_CNT    USBFS_BUS_RST_CNT_PTR
-#define USBFS_CR0            USBFS_CR0_PTR
-#define USBFS_CR1            USBFS_CR1_PTR
-#define USBFS_CWA            USBFS_CWA_PTR
-#define USBFS_CWA_MSB        USBFS_CWA_MSB_PTR
-
-#define USBFS_DMA_THRES      USBFS_DMA_THRES_PTR
-#define USBFS_DMA_THRES_MSB  USBFS_DMA_THRES_MSB_PTR
-
-#define USBFS_EP_ACTIVE      USBFS_EP_ACTIVE_PTR
-#define USBFS_EP_TYPE        USBFS_EP_TYPE_PTR
-
-#define USBFS_EP0_CNT        USBFS_EP0_CNT_PTR
-#define USBFS_EP0_CR         USBFS_EP0_CR_PTR
-#define USBFS_EP0_DR0        USBFS_EP0_DR0_PTR
-#define USBFS_EP0_DR1        USBFS_EP0_DR1_PTR
-#define USBFS_EP0_DR2        USBFS_EP0_DR2_PTR
-#define USBFS_EP0_DR3        USBFS_EP0_DR3_PTR
-#define USBFS_EP0_DR4        USBFS_EP0_DR4_PTR
-#define USBFS_EP0_DR5        USBFS_EP0_DR5_PTR
-#define USBFS_EP0_DR6        USBFS_EP0_DR6_PTR
-#define USBFS_EP0_DR7        USBFS_EP0_DR7_PTR
-
-#define USBFS_OSCLK_DR0      USBFS_OSCLK_DR0_PTR
-#define USBFS_OSCLK_DR1      USBFS_OSCLK_DR1_PTR
-
-#define USBFS_PM_ACT_CFG     USBFS_PM_ACT_CFG_PTR
-#define USBFS_PM_STBY_CFG    USBFS_PM_STBY_CFG_PTR
-
-#define USBFS_SIE_EP_INT_EN  USBFS_SIE_EP_INT_EN_PTR
-#define USBFS_SIE_EP_INT_SR  USBFS_SIE_EP_INT_SR_PTR
-
-#define USBFS_SIE_EP1_CNT0   USBFS_SIE_EP1_CNT0_PTR
-#define USBFS_SIE_EP1_CNT1   USBFS_SIE_EP1_CNT1_PTR
-#define USBFS_SIE_EP1_CR0    USBFS_SIE_EP1_CR0_PTR
-
-#define USBFS_SIE_EP2_CNT0   USBFS_SIE_EP2_CNT0_PTR
-#define USBFS_SIE_EP2_CNT1   USBFS_SIE_EP2_CNT1_PTR
-#define USBFS_SIE_EP2_CR0    USBFS_SIE_EP2_CR0_PTR
-
-#define USBFS_SIE_EP3_CNT0   USBFS_SIE_EP3_CNT0_PTR
-#define USBFS_SIE_EP3_CNT1   USBFS_SIE_EP3_CNT1_PTR
-#define USBFS_SIE_EP3_CR0    USBFS_SIE_EP3_CR0_PTR
-
-#define USBFS_SIE_EP4_CNT0   USBFS_SIE_EP4_CNT0_PTR
-#define USBFS_SIE_EP4_CNT1   USBFS_SIE_EP4_CNT1_PTR
-#define USBFS_SIE_EP4_CR0    USBFS_SIE_EP4_CR0_PTR
-
-#define USBFS_SIE_EP5_CNT0   USBFS_SIE_EP5_CNT0_PTR
-#define USBFS_SIE_EP5_CNT1   USBFS_SIE_EP5_CNT1_PTR
-#define USBFS_SIE_EP5_CR0    USBFS_SIE_EP5_CR0_PTR
-
-#define USBFS_SIE_EP6_CNT0   USBFS_SIE_EP6_CNT0_PTR
-#define USBFS_SIE_EP6_CNT1   USBFS_SIE_EP6_CNT1_PTR
-#define USBFS_SIE_EP6_CR0    USBFS_SIE_EP6_CR0_PTR
-
-#define USBFS_SIE_EP7_CNT0   USBFS_SIE_EP7_CNT0_PTR
-#define USBFS_SIE_EP7_CNT1   USBFS_SIE_EP7_CNT1_PTR
-#define USBFS_SIE_EP7_CR0    USBFS_SIE_EP7_CR0_PTR
-
-#define USBFS_SIE_EP8_CNT0   USBFS_SIE_EP8_CNT0_PTR
-#define USBFS_SIE_EP8_CNT1   USBFS_SIE_EP8_CNT1_PTR
-#define USBFS_SIE_EP8_CR0    USBFS_SIE_EP8_CR0_PTR
-
-#define USBFS_SOF0           USBFS_SOF0_PTR
-#define USBFS_SOF1           USBFS_SOF1_PTR
-
-#define USBFS_USB_CLK_EN     USBFS_USB_CLK_EN_PTR
-
-#define USBFS_USBIO_CR0      USBFS_USBIO_CR0_PTR
-#define USBFS_USBIO_CR1      USBFS_USBIO_CR1_PTR
-#define USBFS_USBIO_CR2      USBFS_USBIO_CR2_PTR
-
-#define USBFS_USB_MEM        ((reg8 *) CYDEV_USB_MEM_BASE)
-
-#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)
-    /* PSoC3 interrupt registers*/
-    #define USBFS_USB_ISR_PRIOR  ((reg8 *) CYDEV_INTC_PRIOR0)
-    #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)
-    #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)
-    #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_INTC_VECT_MBASE)
-#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)
-    /* PSoC5 interrupt registers*/
-    #define USBFS_USB_ISR_PRIOR  ((reg8 *) CYDEV_NVIC_PRI_0)
-    #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
-    #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
-    #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /*  CYDEV_CHIP_DIE_EXPECT */
-
-
-/***************************************
-* Interrupt vectors, masks and priorities
-***************************************/
-
-#define USBFS_BUS_RESET_PRIOR    USBFS_bus_reset__INTC_PRIOR_NUM
-#define USBFS_BUS_RESET_MASK     USBFS_bus_reset__INTC_MASK
-#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER
-
-#define USBFS_SOF_PRIOR          USBFS_sof_int__INTC_PRIOR_NUM
-#define USBFS_SOF_MASK           USBFS_sof_int__INTC_MASK
-#define USBFS_SOF_VECT_NUM       USBFS_sof_int__INTC_NUMBER
-
-#define USBFS_EP_0_PRIOR         USBFS_ep_0__INTC_PRIOR_NUM
-#define USBFS_EP_0_MASK          USBFS_ep_0__INTC_MASK
-#define USBFS_EP_0_VECT_NUM      USBFS_ep_0__INTC_NUMBER
-
-#define USBFS_EP_1_PRIOR         USBFS_ep_1__INTC_PRIOR_NUM
-#define USBFS_EP_1_MASK          USBFS_ep_1__INTC_MASK
-#define USBFS_EP_1_VECT_NUM      USBFS_ep_1__INTC_NUMBER
-
-#define USBFS_EP_2_PRIOR         USBFS_ep_2__INTC_PRIOR_NUM
-#define USBFS_EP_2_MASK          USBFS_ep_2__INTC_MASK
-#define USBFS_EP_2_VECT_NUM      USBFS_ep_2__INTC_NUMBER
-
-#define USBFS_EP_3_PRIOR         USBFS_ep_3__INTC_PRIOR_NUM
-#define USBFS_EP_3_MASK          USBFS_ep_3__INTC_MASK
-#define USBFS_EP_3_VECT_NUM      USBFS_ep_3__INTC_NUMBER
-
-#define USBFS_EP_4_PRIOR         USBFS_ep_4__INTC_PRIOR_NUM
-#define USBFS_EP_4_MASK          USBFS_ep_4__INTC_MASK
-#define USBFS_EP_4_VECT_NUM      USBFS_ep_4__INTC_NUMBER
-
-#define USBFS_EP_5_PRIOR         USBFS_ep_5__INTC_PRIOR_NUM
-#define USBFS_EP_5_MASK          USBFS_ep_5__INTC_MASK
-#define USBFS_EP_5_VECT_NUM      USBFS_ep_5__INTC_NUMBER
-
-#define USBFS_EP_6_PRIOR         USBFS_ep_6__INTC_PRIOR_NUM
-#define USBFS_EP_6_MASK          USBFS_ep_6__INTC_MASK
-#define USBFS_EP_6_VECT_NUM      USBFS_ep_6__INTC_NUMBER
-
-#define USBFS_EP_7_PRIOR         USBFS_ep_7__INTC_PRIOR_NUM
-#define USBFS_EP_7_MASK          USBFS_ep_7__INTC_MASK
-#define USBFS_EP_7_VECT_NUM      USBFS_ep_7__INTC_NUMBER
-
-#define USBFS_EP_8_PRIOR         USBFS_ep_8__INTC_PRIOR_NUM
-#define USBFS_EP_8_MASK          USBFS_ep_8__INTC_MASK
-#define USBFS_EP_8_VECT_NUM      USBFS_ep_8__INTC_NUMBER
-
-#define USBFS_DP_INTC_PRIOR      USBFS_dp_int__INTC_PRIOR_NUM
-#define USBFS_DP_INTC_MASK       USBFS_dp_int__INTC_MASK
-#define USBFS_DP_INTC_VECT_NUM   USBFS_dp_int__INTC_NUMBER
-
-/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */
-#define USBFS_ARB_PRIOR          (0u)
-#define USBFS_ARB_MASK           USBFS_arb_int__INTC_MASK
-#define USBFS_ARB_VECT_NUM       USBFS_arb_int__INTC_NUMBER
-
-/***************************************
- *  Endpoint 0 offsets (Table 9-2)
- **************************************/
-
-#define USBFS_bmRequestType      USBFS_EP0_DR0_PTR
-#define USBFS_bRequest           USBFS_EP0_DR1_PTR
-#define USBFS_wValue             USBFS_EP0_DR2_PTR
-#define USBFS_wValueHi           USBFS_EP0_DR3_PTR
-#define USBFS_wValueLo           USBFS_EP0_DR2_PTR
-#define USBFS_wIndex             USBFS_EP0_DR4_PTR
-#define USBFS_wIndexHi           USBFS_EP0_DR5_PTR
-#define USBFS_wIndexLo           USBFS_EP0_DR4_PTR
-#define USBFS_length             USBFS_EP0_DR6_PTR
-#define USBFS_lengthHi           USBFS_EP0_DR7_PTR
-#define USBFS_lengthLo           USBFS_EP0_DR6_PTR
-
-
-/***************************************
-*       Register Constants
-***************************************/
-#define USBFS_VDDD_MV                    CYDEV_VDDD_MV
-#define USBFS_3500MV                     (3500u)
-
-#define USBFS_CR1_REG_ENABLE             (0x01u)
-#define USBFS_CR1_ENABLE_LOCK            (0x02u)
-#define USBFS_CR1_BUS_ACTIVITY_SHIFT     (0x02u)
-#define USBFS_CR1_BUS_ACTIVITY           ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT))
-#define USBFS_CR1_TRIM_MSB_EN            (0x08u)
-
-#define USBFS_EP0_CNT_DATA_TOGGLE        (0x80u)
-#define USBFS_EPX_CNT_DATA_TOGGLE        (0x80u)
-#define USBFS_EPX_CNT0_MASK              (0x0Fu)
-#define USBFS_EPX_CNTX_MSB_MASK          (0x07u)
-#define USBFS_EPX_CNTX_ADDR_SHIFT        (0x04u)
-#define USBFS_EPX_CNTX_ADDR_OFFSET       (0x10u)
-#define USBFS_EPX_CNTX_CRC_COUNT         (0x02u)
-#define USBFS_EPX_DATA_BUF_MAX           (512u)
-
-#define USBFS_CR0_ENABLE                 (0x80u)
-
-/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */
-#define USBFS_BUS_RST_COUNT              (0x0au)
-
-#define USBFS_USBIO_CR1_IOMODE           (0x20u)
-#define USBFS_USBIO_CR1_USBPUEN          (0x04u)
-#define USBFS_USBIO_CR1_DP0              (0x02u)
-#define USBFS_USBIO_CR1_DM0              (0x01u)
-
-#define USBFS_USBIO_CR0_TEN              (0x80u)
-#define USBFS_USBIO_CR0_TSE0             (0x40u)
-#define USBFS_USBIO_CR0_TD               (0x20u)
-#define USBFS_USBIO_CR0_RD               (0x01u)
-
-#define USBFS_FASTCLK_IMO_CR_USBCLK_ON   (0x40u)
-#define USBFS_FASTCLK_IMO_CR_XCLKEN      (0x20u)
-#define USBFS_FASTCLK_IMO_CR_FX2ON       (0x10u)
-
-#define USBFS_ARB_EPX_CFG_RESET          (0x08u)
-#define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
-#define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
-#define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
-#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
-                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
-
-#define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
-#define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
-#define USBFS_ARB_EPX_SR_BUF_OVER        (0x04u)
-#define USBFS_ARB_EPX_SR_BUF_UNDER       (0x08u)
-
-#define USBFS_ARB_CFG_AUTO_MEM           (0x10u)
-#define USBFS_ARB_CFG_MANUAL_DMA         (0x20u)
-#define USBFS_ARB_CFG_AUTO_DMA           (0x40u)
-#define USBFS_ARB_CFG_CFG_CPM            (0x80u)
-
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-    #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
-#else
-    #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
-#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
-#define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
-                                            (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
-                                            (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
-                                            (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \
-                                            (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \
-                                            (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \
-                                            (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \
-                                            (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) )
-
-#define USBFS_SIE_EP_INT_EP1_MASK        (0x01u)
-#define USBFS_SIE_EP_INT_EP2_MASK        (0x02u)
-#define USBFS_SIE_EP_INT_EP3_MASK        (0x04u)
-#define USBFS_SIE_EP_INT_EP4_MASK        (0x08u)
-#define USBFS_SIE_EP_INT_EP5_MASK        (0x10u)
-#define USBFS_SIE_EP_INT_EP6_MASK        (0x20u)
-#define USBFS_SIE_EP_INT_EP7_MASK        (0x40u)
-#define USBFS_SIE_EP_INT_EP8_MASK        (0x80u)
-
-#define USBFS_PM_ACT_EN_FSUSB            USBFS_USB__PM_ACT_MSK
-#define USBFS_PM_STBY_EN_FSUSB           USBFS_USB__PM_STBY_MSK
-#define USBFS_PM_AVAIL_EN_FSUSBIO        (0x10u)
-
-#define USBFS_PM_USB_CR0_REF_EN          (0x01u)
-#define USBFS_PM_USB_CR0_PD_N            (0x02u)
-#define USBFS_PM_USB_CR0_PD_PULLUP_N     (0x04u)
-
-#define USBFS_USB_CLK_ENABLE             (0x01u)
-
-#define USBFS_DM_MASK                    USBFS_Dm__0__MASK
-#define USBFS_DP_MASK                    USBFS_Dp__0__MASK
-
-#define USBFS_DYN_RECONFIG_ENABLE        (0x01u)
-#define USBFS_DYN_RECONFIG_EP_SHIFT      (0x01u)
-#define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
-
-
-#endif /*  CY_USBFS_USBFS_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: USBFS.h
+* Version 2.80
+*
+* Description:
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_USBFS_USBFS_H)
+#define CY_USBFS_USBFS_H
+
+#include "cytypes.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "CyLib.h"
+
+/*  User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*  Memory Type Definitions
+***************************************/
+
+/* Renamed Type Definitions for backward compatibility.
+*  Should not be used in new designs.
+*/
+#define USBFS_CODE CYCODE
+#define USBFS_FAR CYFAR
+#if defined(__C51__) || defined(__CX51__)
+    #define USBFS_DATA data
+    #define USBFS_XDATA xdata
+#else
+    #define USBFS_DATA
+    #define USBFS_XDATA
+#endif /*  __C51__ */
+#define USBFS_NULL       NULL
+
+
+/***************************************
+* Enumerated Types and Parameters
+***************************************/
+
+#define USBFS__EP_MANUAL 0
+#define USBFS__EP_DMAMANUAL 1
+#define USBFS__EP_DMAAUTO 2
+
+#define USBFS__MA_STATIC 0
+#define USBFS__MA_DYNAMIC 1
+
+
+
+/***************************************
+*    Initial Parameter Constants
+***************************************/
+
+#define USBFS_NUM_DEVICES   (1u)
+#define USBFS_ENABLE_DESCRIPTOR_STRINGS   
+#define USBFS_ENABLE_SN_STRING   
+#define USBFS_ENABLE_STRINGS   
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE   (65u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS   (1u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE   (65u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS   (1u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT   (1u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE   (65u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS   (1u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE   (65u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS   (1u)
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT   (1u)
+#define USBFS_ENABLE_HID_CLASS   
+#define USBFS_HID_RPT_1_SIZE_LSB   (0x25u)
+#define USBFS_HID_RPT_1_SIZE_MSB   (0x00u)
+#define USBFS_HID_RPT_2_SIZE_LSB   (0x25u)
+#define USBFS_HID_RPT_2_SIZE_MSB   (0x00u)
+#define USBFS_MAX_REPORTID_NUMBER   (0u)
+
+#define USBFS_MON_VBUS                       (0u)
+#define USBFS_EXTERN_VBUS                    (0u)
+#define USBFS_EXTERN_VND                     (0u)
+#define USBFS_EXTERN_CLS                     (0u)
+#define USBFS_MAX_INTERFACES_NUMBER          (2u)
+#define USBFS_EP0_ISR_REMOVE                 (0u)
+#define USBFS_EP1_ISR_REMOVE                 (0u)
+#define USBFS_EP2_ISR_REMOVE                 (0u)
+#define USBFS_EP3_ISR_REMOVE                 (0u)
+#define USBFS_EP4_ISR_REMOVE                 (0u)
+#define USBFS_EP5_ISR_REMOVE                 (1u)
+#define USBFS_EP6_ISR_REMOVE                 (1u)
+#define USBFS_EP7_ISR_REMOVE                 (1u)
+#define USBFS_EP8_ISR_REMOVE                 (1u)
+#define USBFS_EP_MM                          (0u)
+#define USBFS_EP_MA                          (0u)
+#define USBFS_EP_DMA_AUTO_OPT                (0u)
+#define USBFS_DMA1_REMOVE                    (1u)
+#define USBFS_DMA2_REMOVE                    (1u)
+#define USBFS_DMA3_REMOVE                    (1u)
+#define USBFS_DMA4_REMOVE                    (1u)
+#define USBFS_DMA5_REMOVE                    (1u)
+#define USBFS_DMA6_REMOVE                    (1u)
+#define USBFS_DMA7_REMOVE                    (1u)
+#define USBFS_DMA8_REMOVE                    (1u)
+#define USBFS_SOF_ISR_REMOVE                 (0u)
+#define USBFS_ARB_ISR_REMOVE                 (0u)
+#define USBFS_DP_ISR_REMOVE                  (0u)
+#define USBFS_ENABLE_CDC_CLASS_API           (1u)
+#define USBFS_ENABLE_MIDI_API                (1u)
+#define USBFS_MIDI_EXT_MODE                  (0u)
+
+
+/***************************************
+*    Data Struct Definition
+***************************************/
+
+typedef struct
+{
+    uint8  attrib;
+    uint8  apiEpState;
+    uint8  hwEpState;
+    uint8  epToggle;
+    uint8  addr;
+    uint8  epMode;
+    uint16 buffOffset;
+    uint16 bufferSize;
+    uint8  interface;
+} T_USBFS_EP_CTL_BLOCK;
+
+typedef struct
+{
+    uint8  interface;
+    uint8  altSetting;
+    uint8  addr;
+    uint8  attributes;
+    uint16 bufferSize;
+    uint8  bMisc;
+} T_USBFS_EP_SETTINGS_BLOCK;
+
+typedef struct
+{
+    uint8  status;
+    uint16 length;
+} T_USBFS_XFER_STATUS_BLOCK;
+
+typedef struct
+{
+    uint16  count;
+    volatile uint8 *pData;
+    T_USBFS_XFER_STATUS_BLOCK *pStatusBlock;
+} T_USBFS_TD;
+
+
+typedef struct
+{
+    uint8   c;
+    const void *p_list;
+} T_USBFS_LUT;
+
+/* Resume/Suspend API Support */
+typedef struct
+{
+    uint8 enableState;
+    uint8 mode;
+} USBFS_BACKUP_STRUCT;
+
+
+/* Renamed structure fields for backward compatibility.
+*  Should not be used in new designs.
+*/
+#define wBuffOffset         buffOffset
+#define wBufferSize         bufferSize
+#define bStatus             status
+#define wLength             length
+#define wCount              count
+
+/* Renamed global variable for backward compatibility.
+*  Should not be used in new designs.
+*/
+#define CurrentTD           USBFS_currentTD
+
+
+/***************************************
+*       Function Prototypes
+***************************************/
+
+void   USBFS_Start(uint8 device, uint8 mode) ;
+void   USBFS_Init(void) ;
+void   USBFS_InitComponent(uint8 device, uint8 mode) ;
+void   USBFS_Stop(void) ;
+uint8  USBFS_CheckActivity(void) ;
+uint8  USBFS_GetConfiguration(void) ;
+uint8  USBFS_IsConfigurationChanged(void) ;
+uint8  USBFS_GetInterfaceSetting(uint8 interfaceNumber)
+                                                        ;
+uint8  USBFS_GetEPState(uint8 epNumber) ;
+uint16 USBFS_GetEPCount(uint8 epNumber) ;
+void   USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
+                                                                    ;
+uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
+                                                                    ;
+void   USBFS_EnableOutEP(uint8 epNumber) ;
+void   USBFS_DisableOutEP(uint8 epNumber) ;
+void   USBFS_Force(uint8 bState) ;
+uint8  USBFS_GetEPAckState(uint8 epNumber) ;
+void   USBFS_SetPowerStatus(uint8 powerStatus) ;
+uint8  USBFS_RWUEnabled(void) ;
+void   USBFS_TerminateEP(uint8 ep) ;
+
+void   USBFS_Suspend(void) ;
+void   USBFS_Resume(void) ;
+
+#if defined(USBFS_ENABLE_FWSN_STRING)
+    void   USBFS_SerialNumString(uint8 snString[]) ;
+#endif  /* USBFS_ENABLE_FWSN_STRING */
+#if (USBFS_MON_VBUS == 1u)
+    uint8  USBFS_VBusPresent(void) ;
+#endif /*  USBFS_MON_VBUS */
+
+#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
+                                          (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
+
+    void USBFS_CyBtldrCommStart(void) ;
+    void USBFS_CyBtldrCommStop(void) ;
+    void USBFS_CyBtldrCommReset(void) ;
+    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+                                                        ;
+    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+                                                        ;
+
+    #define USBFS_BTLDR_OUT_EP      (0x01u)
+    #define USBFS_BTLDR_IN_EP       (0x02u)
+
+    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
+    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
+    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
+
+    /* These defines active if used USBFS interface as an
+    *  IO Component for bootloading. When Custom_Interface selected
+    *  in Bootloder configuration as the IO Component, user must
+    *  provide these functions.
+    */
+    #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
+        #define CyBtldrCommStart        USBFS_CyBtldrCommStart
+        #define CyBtldrCommStop         USBFS_CyBtldrCommStop
+        #define CyBtldrCommReset        USBFS_CyBtldrCommReset
+        #define CyBtldrCommWrite        USBFS_CyBtldrCommWrite
+        #define CyBtldrCommRead         USBFS_CyBtldrCommRead
+    #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+
+#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
+
+#if(USBFS_EP_MM != USBFS__EP_MANUAL)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
+                                                    ;
+    void USBFS_Stop_DMA(uint8 epNumber) ;
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
+
+#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+    void USBFS_MIDI_EP_Init(void) ;
+
+    #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
+        void USBFS_MIDI_IN_Service(void) ;
+        uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)
+                                                                ;
+    #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+    #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
+        void USBFS_MIDI_OUT_EP_Service(void) ;
+    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+
+#endif /*  USBFS_ENABLE_MIDI_API != 0u */
+
+/* Renamed Functions for backward compatibility.
+*  Should not be used in new designs.
+*/
+
+#define USBFS_bCheckActivity             USBFS_CheckActivity
+#define USBFS_bGetConfiguration          USBFS_GetConfiguration
+#define USBFS_bGetInterfaceSetting       USBFS_GetInterfaceSetting
+#define USBFS_bGetEPState                USBFS_GetEPState
+#define USBFS_wGetEPCount                USBFS_GetEPCount
+#define USBFS_bGetEPAckState             USBFS_GetEPAckState
+#define USBFS_bRWUEnabled                USBFS_RWUEnabled
+#define USBFS_bVBusPresent               USBFS_VBusPresent
+
+#define USBFS_bConfiguration             USBFS_configuration
+#define USBFS_bInterfaceSetting          USBFS_interfaceSetting
+#define USBFS_bDeviceAddress             USBFS_deviceAddress
+#define USBFS_bDeviceStatus              USBFS_deviceStatus
+#define USBFS_bDevice                    USBFS_device
+#define USBFS_bTransferState             USBFS_transferState
+#define USBFS_bLastPacketSize            USBFS_lastPacketSize
+
+#define USBFS_LoadEP                     USBFS_LoadInEP
+#define USBFS_LoadInISOCEP               USBFS_LoadInEP
+#define USBFS_EnableOutISOCEP            USBFS_EnableOutEP
+
+#define USBFS_SetVector                  CyIntSetVector
+#define USBFS_SetPriority                CyIntSetPriority
+#define USBFS_EnableInt                  CyIntEnable
+
+
+/***************************************
+*          API Constants
+***************************************/
+
+#define USBFS_EP0                        (0u)
+#define USBFS_EP1                        (1u)
+#define USBFS_EP2                        (2u)
+#define USBFS_EP3                        (3u)
+#define USBFS_EP4                        (4u)
+#define USBFS_EP5                        (5u)
+#define USBFS_EP6                        (6u)
+#define USBFS_EP7                        (7u)
+#define USBFS_EP8                        (8u)
+#define USBFS_MAX_EP                     (9u)
+
+#define USBFS_TRUE                       (1u)
+#define USBFS_FALSE                      (0u)
+
+#define USBFS_NO_EVENT_ALLOWED           (2u)
+#define USBFS_EVENT_PENDING              (1u)
+#define USBFS_NO_EVENT_PENDING           (0u)
+
+#define USBFS_IN_BUFFER_FULL             USBFS_NO_EVENT_PENDING
+#define USBFS_IN_BUFFER_EMPTY            USBFS_EVENT_PENDING
+#define USBFS_OUT_BUFFER_FULL            USBFS_EVENT_PENDING
+#define USBFS_OUT_BUFFER_EMPTY           USBFS_NO_EVENT_PENDING
+
+#define USBFS_FORCE_J                    (0xA0u)
+#define USBFS_FORCE_K                    (0x80u)
+#define USBFS_FORCE_SE0                  (0xC0u)
+#define USBFS_FORCE_NONE                 (0x00u)
+
+#define USBFS_IDLE_TIMER_RUNNING         (0x02u)
+#define USBFS_IDLE_TIMER_EXPIRED         (0x01u)
+#define USBFS_IDLE_TIMER_INDEFINITE      (0x00u)
+
+#define USBFS_DEVICE_STATUS_BUS_POWERED  (0x00u)
+#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u)
+
+#define USBFS_3V_OPERATION               (0x00u)
+#define USBFS_5V_OPERATION               (0x01u)
+#define USBFS_DWR_VDDD_OPERATION         (0x02u)
+
+#define USBFS_MODE_DISABLE               (0x00u)
+#define USBFS_MODE_NAK_IN_OUT            (0x01u)
+#define USBFS_MODE_STATUS_OUT_ONLY       (0x02u)
+#define USBFS_MODE_STALL_IN_OUT          (0x03u)
+#define USBFS_MODE_RESERVED_0100         (0x04u)
+#define USBFS_MODE_ISO_OUT               (0x05u)
+#define USBFS_MODE_STATUS_IN_ONLY        (0x06u)
+#define USBFS_MODE_ISO_IN                (0x07u)
+#define USBFS_MODE_NAK_OUT               (0x08u)
+#define USBFS_MODE_ACK_OUT               (0x09u)
+#define USBFS_MODE_RESERVED_1010         (0x0Au)
+#define USBFS_MODE_ACK_OUT_STATUS_IN     (0x0Bu)
+#define USBFS_MODE_NAK_IN                (0x0Cu)
+#define USBFS_MODE_ACK_IN                (0x0Du)
+#define USBFS_MODE_RESERVED_1110         (0x0Eu)
+#define USBFS_MODE_ACK_IN_STATUS_OUT     (0x0Fu)
+#define USBFS_MODE_MASK                  (0x0Fu)
+#define USBFS_MODE_STALL_DATA_EP         (0x80u)
+
+#define USBFS_MODE_ACKD                  (0x10u)
+#define USBFS_MODE_OUT_RCVD              (0x20u)
+#define USBFS_MODE_IN_RCVD               (0x40u)
+#define USBFS_MODE_SETUP_RCVD            (0x80u)
+
+#define USBFS_RQST_TYPE_MASK             (0x60u)
+#define USBFS_RQST_TYPE_STD              (0x00u)
+#define USBFS_RQST_TYPE_CLS              (0x20u)
+#define USBFS_RQST_TYPE_VND              (0x40u)
+#define USBFS_RQST_DIR_MASK              (0x80u)
+#define USBFS_RQST_DIR_D2H               (0x80u)
+#define USBFS_RQST_DIR_H2D               (0x00u)
+#define USBFS_RQST_RCPT_MASK             (0x03u)
+#define USBFS_RQST_RCPT_DEV              (0x00u)
+#define USBFS_RQST_RCPT_IFC              (0x01u)
+#define USBFS_RQST_RCPT_EP               (0x02u)
+#define USBFS_RQST_RCPT_OTHER            (0x03u)
+
+/* USB Class Codes */
+#define USBFS_CLASS_DEVICE               (0x00u)     /* Use class code info from Interface Descriptors */
+#define USBFS_CLASS_AUDIO                (0x01u)     /* Audio device */
+#define USBFS_CLASS_CDC                  (0x02u)     /* Communication device class */
+#define USBFS_CLASS_HID                  (0x03u)     /* Human Interface Device */
+#define USBFS_CLASS_PDC                  (0x05u)     /* Physical device class */
+#define USBFS_CLASS_IMAGE                (0x06u)     /* Still Imaging device */
+#define USBFS_CLASS_PRINTER              (0x07u)     /* Printer device  */
+#define USBFS_CLASS_MSD                  (0x08u)     /* Mass Storage device  */
+#define USBFS_CLASS_HUB                  (0x09u)     /* Full/Hi speed Hub */
+#define USBFS_CLASS_CDC_DATA             (0x0Au)     /* CDC data device */
+#define USBFS_CLASS_SMART_CARD           (0x0Bu)     /* Smart Card device */
+#define USBFS_CLASS_CSD                  (0x0Du)     /* Content Security device */
+#define USBFS_CLASS_VIDEO                (0x0Eu)     /* Video device */
+#define USBFS_CLASS_PHD                  (0x0Fu)     /* Personal Healthcare device */
+#define USBFS_CLASS_WIRELESSD            (0xDCu)     /* Wireless Controller */
+#define USBFS_CLASS_MIS                  (0xE0u)     /* Miscellaneous */
+#define USBFS_CLASS_APP                  (0xEFu)     /* Application Specific */
+#define USBFS_CLASS_VENDOR               (0xFFu)     /* Vendor specific */
+
+
+/* Standard Request Types (Table 9-4) */
+#define USBFS_GET_STATUS                 (0x00u)
+#define USBFS_CLEAR_FEATURE              (0x01u)
+#define USBFS_SET_FEATURE                (0x03u)
+#define USBFS_SET_ADDRESS                (0x05u)
+#define USBFS_GET_DESCRIPTOR             (0x06u)
+#define USBFS_SET_DESCRIPTOR             (0x07u)
+#define USBFS_GET_CONFIGURATION          (0x08u)
+#define USBFS_SET_CONFIGURATION          (0x09u)
+#define USBFS_GET_INTERFACE              (0x0Au)
+#define USBFS_SET_INTERFACE              (0x0Bu)
+#define USBFS_SYNCH_FRAME                (0x0Cu)
+
+/* Vendor Specific Request Types */
+/* Request for Microsoft OS String Descriptor */
+#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u)
+
+/* Descriptor Types (Table 9-5) */
+#define USBFS_DESCR_DEVICE                   (1u)
+#define USBFS_DESCR_CONFIG                   (2u)
+#define USBFS_DESCR_STRING                   (3u)
+#define USBFS_DESCR_INTERFACE                (4u)
+#define USBFS_DESCR_ENDPOINT                 (5u)
+#define USBFS_DESCR_DEVICE_QUALIFIER         (6u)
+#define USBFS_DESCR_OTHER_SPEED              (7u)
+#define USBFS_DESCR_INTERFACE_POWER          (8u)
+
+/* Device Descriptor Defines */
+#define USBFS_DEVICE_DESCR_LENGTH            (18u)
+#define USBFS_DEVICE_DESCR_SN_SHIFT          (16u)
+
+/* Config Descriptor Shifts and Masks */
+#define USBFS_CONFIG_DESCR_LENGTH                (0u)
+#define USBFS_CONFIG_DESCR_TYPE                  (1u)
+#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW      (2u)
+#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI       (3u)
+#define USBFS_CONFIG_DESCR_NUM_INTERFACES        (4u)
+#define USBFS_CONFIG_DESCR_CONFIG_VALUE          (5u)
+#define USBFS_CONFIG_DESCR_CONFIGURATION         (6u)
+#define USBFS_CONFIG_DESCR_ATTRIB                (7u)
+#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED   (0x40u)
+#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN         (0x20u)
+
+/* Feature Selectors (Table 9-6) */
+#define USBFS_DEVICE_REMOTE_WAKEUP           (0x01u)
+#define USBFS_ENDPOINT_HALT                  (0x00u)
+#define USBFS_TEST_MODE                      (0x02u)
+
+/* USB Device Status (Figure 9-4) */
+#define USBFS_DEVICE_STATUS_BUS_POWERED      (0x00u)
+#define USBFS_DEVICE_STATUS_SELF_POWERED     (0x01u)
+#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP    (0x02u)
+
+/* USB Endpoint Status (Figure 9-4) */
+#define USBFS_ENDPOINT_STATUS_HALT           (0x01u)
+
+/* USB Endpoint Directions */
+#define USBFS_DIR_IN                         (0x80u)
+#define USBFS_DIR_OUT                        (0x00u)
+#define USBFS_DIR_UNUSED                     (0x7Fu)
+
+/* USB Endpoint Attributes */
+#define USBFS_EP_TYPE_CTRL                   (0x00u)
+#define USBFS_EP_TYPE_ISOC                   (0x01u)
+#define USBFS_EP_TYPE_BULK                   (0x02u)
+#define USBFS_EP_TYPE_INT                    (0x03u)
+#define USBFS_EP_TYPE_MASK                   (0x03u)
+
+#define USBFS_EP_SYNC_TYPE_NO_SYNC           (0x00u)
+#define USBFS_EP_SYNC_TYPE_ASYNC             (0x04u)
+#define USBFS_EP_SYNC_TYPE_ADAPTIVE          (0x08u)
+#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS       (0x0Cu)
+#define USBFS_EP_SYNC_TYPE_MASK              (0x0Cu)
+
+#define USBFS_EP_USAGE_TYPE_DATA             (0x00u)
+#define USBFS_EP_USAGE_TYPE_FEEDBACK         (0x10u)
+#define USBFS_EP_USAGE_TYPE_IMPLICIT         (0x20u)
+#define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
+#define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
+
+/* point Status defines */
+#define USBFS_EP_STATUS_LENGTH               (0x02u)
+
+/* point Device defines */
+#define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
+
+#define USBFS_STATUS_LENGTH_MAX \
+                 ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \
+                    USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH )
+/* Transfer Completion Notification */
+#define USBFS_XFER_IDLE                      (0x00u)
+#define USBFS_XFER_STATUS_ACK                (0x01u)
+#define USBFS_XFER_PREMATURE                 (0x02u)
+#define USBFS_XFER_ERROR                     (0x03u)
+
+/* Driver State defines */
+#define USBFS_TRANS_STATE_IDLE               (0x00u)
+#define USBFS_TRANS_STATE_CONTROL_READ       (0x02u)
+#define USBFS_TRANS_STATE_CONTROL_WRITE      (0x04u)
+#define USBFS_TRANS_STATE_NO_DATA_CONTROL    (0x06u)
+
+/* String Descriptor defines */
+#define USBFS_STRING_MSOS                    (0xEEu)
+#define USBFS_MSOS_DESCRIPTOR_LENGTH         (18u)
+#define USBFS_MSOS_CONF_DESCR_LENGTH         (40u)
+
+#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
+    /* DMA manual mode defines */
+    #define USBFS_DMA_BYTES_PER_BURST        (0u)
+    #define USBFS_DMA_REQUEST_PER_BURST      (0u)
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
+    /* DMA automatic mode defines */
+    #define USBFS_DMA_BYTES_PER_BURST        (32u)
+    #define USBFS_DMA_BYTES_REPEAT           (2u)
+    /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
+    #define USBFS_DMA_BUF_SIZE               (0x55u)
+    #define USBFS_DMA_REQUEST_PER_BURST      (1u)
+
+    #if(USBFS_DMA1_REMOVE == 0u)
+        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA1_REMOVE == 0u */
+    #if(USBFS_DMA2_REMOVE == 0u)
+        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA2_REMOVE == 0u */
+    #if(USBFS_DMA3_REMOVE == 0u)
+        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA3_REMOVE == 0u */
+    #if(USBFS_DMA4_REMOVE == 0u)
+        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA4_REMOVE == 0u */
+    #if(USBFS_DMA5_REMOVE == 0u)
+        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA5_REMOVE == 0u */
+    #if(USBFS_DMA6_REMOVE == 0u)
+        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA6_REMOVE == 0u */
+    #if(USBFS_DMA7_REMOVE == 0u)
+        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA7_REMOVE == 0u */
+    #if(USBFS_DMA8_REMOVE == 0u)
+        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA8_REMOVE == 0u */
+
+    #define     USBFS_EP17_SR_MASK           (0x7fu)
+    #define     USBFS_EP8_SR_MASK            (0x03u)
+
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+/* DIE ID string descriptor defines */
+#if defined(USBFS_ENABLE_IDSN_STRING)
+    #define USBFS_IDSN_DESCR_LENGTH          (0x22u)
+#endif /* USBFS_ENABLE_IDSN_STRING */
+
+
+/***************************************
+* External data references
+***************************************/
+
+extern uint8 USBFS_initVar;
+extern volatile uint8 USBFS_device;
+extern volatile uint8 USBFS_transferState;
+extern volatile uint8 USBFS_configuration;
+extern volatile uint8 USBFS_configurationChanged;
+extern volatile uint8 USBFS_deviceStatus;
+
+/* HID Variables */
+#if defined(USBFS_ENABLE_HID_CLASS)
+    extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];
+    extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];
+    extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER];
+#endif /* USBFS_ENABLE_HID_CLASS */
+
+
+/***************************************
+*              Registers
+***************************************/
+
+#define USBFS_ARB_CFG_PTR        (  (reg8 *) USBFS_USB__ARB_CFG)
+#define USBFS_ARB_CFG_REG        (* (reg8 *) USBFS_USB__ARB_CFG)
+
+#define USBFS_ARB_EP1_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP1_CFG)
+#define USBFS_ARB_EP1_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP1_CFG)
+#define USBFS_ARB_EP1_CFG_IND    USBFS_USB__ARB_EP1_CFG
+#define USBFS_ARB_EP1_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP1_INT_EN)
+#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN)
+#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN
+#define USBFS_ARB_EP1_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP1_SR)
+#define USBFS_ARB_EP1_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP1_SR)
+#define USBFS_ARB_EP1_SR_IND     USBFS_USB__ARB_EP1_SR
+
+#define USBFS_ARB_EP2_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP2_CFG)
+#define USBFS_ARB_EP2_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP2_CFG)
+#define USBFS_ARB_EP2_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP2_INT_EN)
+#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN)
+#define USBFS_ARB_EP2_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP2_SR)
+#define USBFS_ARB_EP2_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP2_SR)
+
+#define USBFS_ARB_EP3_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP3_CFG)
+#define USBFS_ARB_EP3_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP3_CFG)
+#define USBFS_ARB_EP3_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP3_INT_EN)
+#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN)
+#define USBFS_ARB_EP3_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP3_SR)
+#define USBFS_ARB_EP3_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP3_SR)
+
+#define USBFS_ARB_EP4_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP4_CFG)
+#define USBFS_ARB_EP4_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP4_CFG)
+#define USBFS_ARB_EP4_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP4_INT_EN)
+#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN)
+#define USBFS_ARB_EP4_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP4_SR)
+#define USBFS_ARB_EP4_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP4_SR)
+
+#define USBFS_ARB_EP5_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP5_CFG)
+#define USBFS_ARB_EP5_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP5_CFG)
+#define USBFS_ARB_EP5_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP5_INT_EN)
+#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN)
+#define USBFS_ARB_EP5_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP5_SR)
+#define USBFS_ARB_EP5_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP5_SR)
+
+#define USBFS_ARB_EP6_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP6_CFG)
+#define USBFS_ARB_EP6_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP6_CFG)
+#define USBFS_ARB_EP6_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP6_INT_EN)
+#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN)
+#define USBFS_ARB_EP6_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP6_SR)
+#define USBFS_ARB_EP6_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP6_SR)
+
+#define USBFS_ARB_EP7_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP7_CFG)
+#define USBFS_ARB_EP7_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP7_CFG)
+#define USBFS_ARB_EP7_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP7_INT_EN)
+#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN)
+#define USBFS_ARB_EP7_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP7_SR)
+#define USBFS_ARB_EP7_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP7_SR)
+
+#define USBFS_ARB_EP8_CFG_PTR    (  (reg8 *) USBFS_USB__ARB_EP8_CFG)
+#define USBFS_ARB_EP8_CFG_REG    (* (reg8 *) USBFS_USB__ARB_EP8_CFG)
+#define USBFS_ARB_EP8_INT_EN_PTR (  (reg8 *) USBFS_USB__ARB_EP8_INT_EN)
+#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN)
+#define USBFS_ARB_EP8_SR_PTR     (  (reg8 *) USBFS_USB__ARB_EP8_SR)
+#define USBFS_ARB_EP8_SR_REG     (* (reg8 *) USBFS_USB__ARB_EP8_SR)
+
+#define USBFS_ARB_INT_EN_PTR     (  (reg8 *) USBFS_USB__ARB_INT_EN)
+#define USBFS_ARB_INT_EN_REG     (* (reg8 *) USBFS_USB__ARB_INT_EN)
+#define USBFS_ARB_INT_SR_PTR     (  (reg8 *) USBFS_USB__ARB_INT_SR)
+#define USBFS_ARB_INT_SR_REG     (* (reg8 *) USBFS_USB__ARB_INT_SR)
+
+#define USBFS_ARB_RW1_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW1_DR)
+#define USBFS_ARB_RW1_DR_IND     USBFS_USB__ARB_RW1_DR
+#define USBFS_ARB_RW1_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW1_RA)
+#define USBFS_ARB_RW1_RA_IND     USBFS_USB__ARB_RW1_RA
+#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB)
+#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB
+#define USBFS_ARB_RW1_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW1_WA)
+#define USBFS_ARB_RW1_WA_IND     USBFS_USB__ARB_RW1_WA
+#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB)
+#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB
+
+#define USBFS_ARB_RW2_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW2_DR)
+#define USBFS_ARB_RW2_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW2_RA)
+#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB)
+#define USBFS_ARB_RW2_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW2_WA)
+#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB)
+
+#define USBFS_ARB_RW3_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW3_DR)
+#define USBFS_ARB_RW3_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW3_RA)
+#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB)
+#define USBFS_ARB_RW3_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW3_WA)
+#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB)
+
+#define USBFS_ARB_RW4_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW4_DR)
+#define USBFS_ARB_RW4_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW4_RA)
+#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB)
+#define USBFS_ARB_RW4_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW4_WA)
+#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB)
+
+#define USBFS_ARB_RW5_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW5_DR)
+#define USBFS_ARB_RW5_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW5_RA)
+#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB)
+#define USBFS_ARB_RW5_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW5_WA)
+#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB)
+
+#define USBFS_ARB_RW6_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW6_DR)
+#define USBFS_ARB_RW6_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW6_RA)
+#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB)
+#define USBFS_ARB_RW6_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW6_WA)
+#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB)
+
+#define USBFS_ARB_RW7_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW7_DR)
+#define USBFS_ARB_RW7_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW7_RA)
+#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB)
+#define USBFS_ARB_RW7_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW7_WA)
+#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB)
+
+#define USBFS_ARB_RW8_DR_PTR     ((reg8 *) USBFS_USB__ARB_RW8_DR)
+#define USBFS_ARB_RW8_RA_PTR     ((reg8 *) USBFS_USB__ARB_RW8_RA)
+#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB)
+#define USBFS_ARB_RW8_WA_PTR     ((reg8 *) USBFS_USB__ARB_RW8_WA)
+#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB)
+
+#define USBFS_BUF_SIZE_PTR       (  (reg8 *) USBFS_USB__BUF_SIZE)
+#define USBFS_BUF_SIZE_REG       (* (reg8 *) USBFS_USB__BUF_SIZE)
+#define USBFS_BUS_RST_CNT_PTR    (  (reg8 *) USBFS_USB__BUS_RST_CNT)
+#define USBFS_BUS_RST_CNT_REG    (* (reg8 *) USBFS_USB__BUS_RST_CNT)
+#define USBFS_CWA_PTR            (  (reg8 *) USBFS_USB__CWA)
+#define USBFS_CWA_REG            (* (reg8 *) USBFS_USB__CWA)
+#define USBFS_CWA_MSB_PTR        (  (reg8 *) USBFS_USB__CWA_MSB)
+#define USBFS_CWA_MSB_REG        (* (reg8 *) USBFS_USB__CWA_MSB)
+#define USBFS_CR0_PTR            (  (reg8 *) USBFS_USB__CR0)
+#define USBFS_CR0_REG            (* (reg8 *) USBFS_USB__CR0)
+#define USBFS_CR1_PTR            (  (reg8 *) USBFS_USB__CR1)
+#define USBFS_CR1_REG            (* (reg8 *) USBFS_USB__CR1)
+
+#define USBFS_DMA_THRES_PTR      (  (reg8 *) USBFS_USB__DMA_THRES)
+#define USBFS_DMA_THRES_REG      (* (reg8 *) USBFS_USB__DMA_THRES)
+#define USBFS_DMA_THRES_MSB_PTR  (  (reg8 *) USBFS_USB__DMA_THRES_MSB)
+#define USBFS_DMA_THRES_MSB_REG  (* (reg8 *) USBFS_USB__DMA_THRES_MSB)
+
+#define USBFS_EP_ACTIVE_PTR      (  (reg8 *) USBFS_USB__EP_ACTIVE)
+#define USBFS_EP_ACTIVE_REG      (* (reg8 *) USBFS_USB__EP_ACTIVE)
+#define USBFS_EP_TYPE_PTR        (  (reg8 *) USBFS_USB__EP_TYPE)
+#define USBFS_EP_TYPE_REG        (* (reg8 *) USBFS_USB__EP_TYPE)
+
+#define USBFS_EP0_CNT_PTR        (  (reg8 *) USBFS_USB__EP0_CNT)
+#define USBFS_EP0_CNT_REG        (* (reg8 *) USBFS_USB__EP0_CNT)
+#define USBFS_EP0_CR_PTR         (  (reg8 *) USBFS_USB__EP0_CR)
+#define USBFS_EP0_CR_REG         (* (reg8 *) USBFS_USB__EP0_CR)
+#define USBFS_EP0_DR0_PTR        (  (reg8 *) USBFS_USB__EP0_DR0)
+#define USBFS_EP0_DR0_REG        (* (reg8 *) USBFS_USB__EP0_DR0)
+#define USBFS_EP0_DR0_IND        USBFS_USB__EP0_DR0
+#define USBFS_EP0_DR1_PTR        (  (reg8 *) USBFS_USB__EP0_DR1)
+#define USBFS_EP0_DR1_REG        (* (reg8 *) USBFS_USB__EP0_DR1)
+#define USBFS_EP0_DR2_PTR        (  (reg8 *) USBFS_USB__EP0_DR2)
+#define USBFS_EP0_DR2_REG        (* (reg8 *) USBFS_USB__EP0_DR2)
+#define USBFS_EP0_DR3_PTR        (  (reg8 *) USBFS_USB__EP0_DR3)
+#define USBFS_EP0_DR3_REG        (* (reg8 *) USBFS_USB__EP0_DR3)
+#define USBFS_EP0_DR4_PTR        (  (reg8 *) USBFS_USB__EP0_DR4)
+#define USBFS_EP0_DR4_REG        (* (reg8 *) USBFS_USB__EP0_DR4)
+#define USBFS_EP0_DR5_PTR        (  (reg8 *) USBFS_USB__EP0_DR5)
+#define USBFS_EP0_DR5_REG        (* (reg8 *) USBFS_USB__EP0_DR5)
+#define USBFS_EP0_DR6_PTR        (  (reg8 *) USBFS_USB__EP0_DR6)
+#define USBFS_EP0_DR6_REG        (* (reg8 *) USBFS_USB__EP0_DR6)
+#define USBFS_EP0_DR7_PTR        (  (reg8 *) USBFS_USB__EP0_DR7)
+#define USBFS_EP0_DR7_REG        (* (reg8 *) USBFS_USB__EP0_DR7)
+
+#define USBFS_OSCLK_DR0_PTR      (  (reg8 *) USBFS_USB__OSCLK_DR0)
+#define USBFS_OSCLK_DR0_REG      (* (reg8 *) USBFS_USB__OSCLK_DR0)
+#define USBFS_OSCLK_DR1_PTR      (  (reg8 *) USBFS_USB__OSCLK_DR1)
+#define USBFS_OSCLK_DR1_REG      (* (reg8 *) USBFS_USB__OSCLK_DR1)
+
+#define USBFS_PM_ACT_CFG_PTR     (  (reg8 *) USBFS_USB__PM_ACT_CFG)
+#define USBFS_PM_ACT_CFG_REG     (* (reg8 *) USBFS_USB__PM_ACT_CFG)
+#define USBFS_PM_STBY_CFG_PTR    (  (reg8 *) USBFS_USB__PM_STBY_CFG)
+#define USBFS_PM_STBY_CFG_REG    (* (reg8 *) USBFS_USB__PM_STBY_CFG)
+
+#define USBFS_SIE_EP_INT_EN_PTR  (  (reg8 *) USBFS_USB__SIE_EP_INT_EN)
+#define USBFS_SIE_EP_INT_EN_REG  (* (reg8 *) USBFS_USB__SIE_EP_INT_EN)
+#define USBFS_SIE_EP_INT_SR_PTR  (  (reg8 *) USBFS_USB__SIE_EP_INT_SR)
+#define USBFS_SIE_EP_INT_SR_REG  (* (reg8 *) USBFS_USB__SIE_EP_INT_SR)
+
+#define USBFS_SIE_EP1_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP1_CNT0)
+#define USBFS_SIE_EP1_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP1_CNT0)
+#define USBFS_SIE_EP1_CNT0_IND   USBFS_USB__SIE_EP1_CNT0
+#define USBFS_SIE_EP1_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP1_CNT1)
+#define USBFS_SIE_EP1_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP1_CNT1)
+#define USBFS_SIE_EP1_CNT1_IND   USBFS_USB__SIE_EP1_CNT1
+#define USBFS_SIE_EP1_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP1_CR0)
+#define USBFS_SIE_EP1_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP1_CR0)
+#define USBFS_SIE_EP1_CR0_IND    USBFS_USB__SIE_EP1_CR0
+
+#define USBFS_SIE_EP2_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP2_CNT0)
+#define USBFS_SIE_EP2_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP2_CNT0)
+#define USBFS_SIE_EP2_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP2_CNT1)
+#define USBFS_SIE_EP2_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP2_CNT1)
+#define USBFS_SIE_EP2_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP2_CR0)
+#define USBFS_SIE_EP2_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP2_CR0)
+
+#define USBFS_SIE_EP3_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP3_CNT0)
+#define USBFS_SIE_EP3_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP3_CNT0)
+#define USBFS_SIE_EP3_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP3_CNT1)
+#define USBFS_SIE_EP3_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP3_CNT1)
+#define USBFS_SIE_EP3_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP3_CR0)
+#define USBFS_SIE_EP3_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP3_CR0)
+
+#define USBFS_SIE_EP4_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP4_CNT0)
+#define USBFS_SIE_EP4_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP4_CNT0)
+#define USBFS_SIE_EP4_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP4_CNT1)
+#define USBFS_SIE_EP4_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP4_CNT1)
+#define USBFS_SIE_EP4_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP4_CR0)
+#define USBFS_SIE_EP4_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP4_CR0)
+
+#define USBFS_SIE_EP5_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP5_CNT0)
+#define USBFS_SIE_EP5_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP5_CNT0)
+#define USBFS_SIE_EP5_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP5_CNT1)
+#define USBFS_SIE_EP5_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP5_CNT1)
+#define USBFS_SIE_EP5_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP5_CR0)
+#define USBFS_SIE_EP5_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP5_CR0)
+
+#define USBFS_SIE_EP6_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP6_CNT0)
+#define USBFS_SIE_EP6_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP6_CNT0)
+#define USBFS_SIE_EP6_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP6_CNT1)
+#define USBFS_SIE_EP6_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP6_CNT1)
+#define USBFS_SIE_EP6_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP6_CR0)
+#define USBFS_SIE_EP6_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP6_CR0)
+
+#define USBFS_SIE_EP7_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP7_CNT0)
+#define USBFS_SIE_EP7_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP7_CNT0)
+#define USBFS_SIE_EP7_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP7_CNT1)
+#define USBFS_SIE_EP7_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP7_CNT1)
+#define USBFS_SIE_EP7_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP7_CR0)
+#define USBFS_SIE_EP7_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP7_CR0)
+
+#define USBFS_SIE_EP8_CNT0_PTR   (  (reg8 *) USBFS_USB__SIE_EP8_CNT0)
+#define USBFS_SIE_EP8_CNT0_REG   (* (reg8 *) USBFS_USB__SIE_EP8_CNT0)
+#define USBFS_SIE_EP8_CNT1_PTR   (  (reg8 *) USBFS_USB__SIE_EP8_CNT1)
+#define USBFS_SIE_EP8_CNT1_REG   (* (reg8 *) USBFS_USB__SIE_EP8_CNT1)
+#define USBFS_SIE_EP8_CR0_PTR    (  (reg8 *) USBFS_USB__SIE_EP8_CR0)
+#define USBFS_SIE_EP8_CR0_REG    (* (reg8 *) USBFS_USB__SIE_EP8_CR0)
+
+#define USBFS_SOF0_PTR           (  (reg8 *) USBFS_USB__SOF0)
+#define USBFS_SOF0_REG           (* (reg8 *) USBFS_USB__SOF0)
+#define USBFS_SOF1_PTR           (  (reg8 *) USBFS_USB__SOF1)
+#define USBFS_SOF1_REG           (* (reg8 *) USBFS_USB__SOF1)
+
+#define USBFS_USB_CLK_EN_PTR     (  (reg8 *) USBFS_USB__USB_CLK_EN)
+#define USBFS_USB_CLK_EN_REG     (* (reg8 *) USBFS_USB__USB_CLK_EN)
+
+#define USBFS_USBIO_CR0_PTR      (  (reg8 *) USBFS_USB__USBIO_CR0)
+#define USBFS_USBIO_CR0_REG      (* (reg8 *) USBFS_USB__USBIO_CR0)
+#define USBFS_USBIO_CR1_PTR      (  (reg8 *) USBFS_USB__USBIO_CR1)
+#define USBFS_USBIO_CR1_REG      (* (reg8 *) USBFS_USB__USBIO_CR1)
+#if(!CY_PSOC5LP)
+    #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
+    #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
+#endif /*  CY_PSOC5LP */
+
+#define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
+
+#define USBFS_PM_USB_CR0_PTR     (  (reg8 *) CYREG_PM_USB_CR0)
+#define USBFS_PM_USB_CR0_REG     (* (reg8 *) CYREG_PM_USB_CR0)
+#define USBFS_DYN_RECONFIG_PTR   (  (reg8 *) USBFS_USB__DYN_RECONFIG)
+#define USBFS_DYN_RECONFIG_REG   (* (reg8 *) USBFS_USB__DYN_RECONFIG)
+
+#define USBFS_DM_INP_DIS_PTR     (  (reg8 *) USBFS_Dm__INP_DIS)
+#define USBFS_DM_INP_DIS_REG     (* (reg8 *) USBFS_Dm__INP_DIS)
+#define USBFS_DP_INP_DIS_PTR     (  (reg8 *) USBFS_Dp__INP_DIS)
+#define USBFS_DP_INP_DIS_REG     (* (reg8 *) USBFS_Dp__INP_DIS)
+#define USBFS_DP_INTSTAT_PTR     (  (reg8 *) USBFS_Dp__INTSTAT)
+#define USBFS_DP_INTSTAT_REG     (* (reg8 *) USBFS_Dp__INTSTAT)
+
+#if (USBFS_MON_VBUS == 1u)
+    #if (USBFS_EXTERN_VBUS == 0u)
+        #define USBFS_VBUS_DR_PTR        (  (reg8 *) USBFS_VBUS__DR)
+        #define USBFS_VBUS_DR_REG        (* (reg8 *) USBFS_VBUS__DR)
+        #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_VBUS__PS)
+        #define USBFS_VBUS_PS_REG        (* (reg8 *) USBFS_VBUS__PS)
+        #define USBFS_VBUS_MASK          USBFS_VBUS__MASK
+    #else
+        #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
+        #define USBFS_VBUS_MASK          (0x01u)
+    #endif /*  USBFS_EXTERN_VBUS == 0u */
+#endif /*  USBFS_MON_VBUS */
+
+/* Renamed Registers for backward compatibility.
+*  Should not be used in new designs.
+*/
+#define USBFS_ARB_CFG        USBFS_ARB_CFG_PTR
+
+#define USBFS_ARB_EP1_CFG    USBFS_ARB_EP1_CFG_PTR
+#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR
+#define USBFS_ARB_EP1_SR     USBFS_ARB_EP1_SR_PTR
+
+#define USBFS_ARB_EP2_CFG    USBFS_ARB_EP2_CFG_PTR
+#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR
+#define USBFS_ARB_EP2_SR     USBFS_ARB_EP2_SR_PTR
+
+#define USBFS_ARB_EP3_CFG    USBFS_ARB_EP3_CFG_PTR
+#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR
+#define USBFS_ARB_EP3_SR     USBFS_ARB_EP3_SR_PTR
+
+#define USBFS_ARB_EP4_CFG    USBFS_ARB_EP4_CFG_PTR
+#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR
+#define USBFS_ARB_EP4_SR     USBFS_ARB_EP4_SR_PTR
+
+#define USBFS_ARB_EP5_CFG    USBFS_ARB_EP5_CFG_PTR
+#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR
+#define USBFS_ARB_EP5_SR     USBFS_ARB_EP5_SR_PTR
+
+#define USBFS_ARB_EP6_CFG    USBFS_ARB_EP6_CFG_PTR
+#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR
+#define USBFS_ARB_EP6_SR     USBFS_ARB_EP6_SR_PTR
+
+#define USBFS_ARB_EP7_CFG    USBFS_ARB_EP7_CFG_PTR
+#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR
+#define USBFS_ARB_EP7_SR     USBFS_ARB_EP7_SR_PTR
+
+#define USBFS_ARB_EP8_CFG    USBFS_ARB_EP8_CFG_PTR
+#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR
+#define USBFS_ARB_EP8_SR     USBFS_ARB_EP8_SR_PTR
+
+#define USBFS_ARB_INT_EN     USBFS_ARB_INT_EN_PTR
+#define USBFS_ARB_INT_SR     USBFS_ARB_INT_SR_PTR
+
+#define USBFS_ARB_RW1_DR     USBFS_ARB_RW1_DR_PTR
+#define USBFS_ARB_RW1_RA     USBFS_ARB_RW1_RA_PTR
+#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR
+#define USBFS_ARB_RW1_WA     USBFS_ARB_RW1_WA_PTR
+#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR
+
+#define USBFS_ARB_RW2_DR     USBFS_ARB_RW2_DR_PTR
+#define USBFS_ARB_RW2_RA     USBFS_ARB_RW2_RA_PTR
+#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR
+#define USBFS_ARB_RW2_WA     USBFS_ARB_RW2_WA_PTR
+#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR
+
+#define USBFS_ARB_RW3_DR     USBFS_ARB_RW3_DR_PTR
+#define USBFS_ARB_RW3_RA     USBFS_ARB_RW3_RA_PTR
+#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR
+#define USBFS_ARB_RW3_WA     USBFS_ARB_RW3_WA_PTR
+#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR
+
+#define USBFS_ARB_RW4_DR     USBFS_ARB_RW4_DR_PTR
+#define USBFS_ARB_RW4_RA     USBFS_ARB_RW4_RA_PTR
+#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR
+#define USBFS_ARB_RW4_WA     USBFS_ARB_RW4_WA_PTR
+#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR
+
+#define USBFS_ARB_RW5_DR     USBFS_ARB_RW5_DR_PTR
+#define USBFS_ARB_RW5_RA     USBFS_ARB_RW5_RA_PTR
+#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR
+#define USBFS_ARB_RW5_WA     USBFS_ARB_RW5_WA_PTR
+#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR
+
+#define USBFS_ARB_RW6_DR     USBFS_ARB_RW6_DR_PTR
+#define USBFS_ARB_RW6_RA     USBFS_ARB_RW6_RA_PTR
+#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR
+#define USBFS_ARB_RW6_WA     USBFS_ARB_RW6_WA_PTR
+#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR
+
+#define USBFS_ARB_RW7_DR     USBFS_ARB_RW7_DR_PTR
+#define USBFS_ARB_RW7_RA     USBFS_ARB_RW7_RA_PTR
+#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR
+#define USBFS_ARB_RW7_WA     USBFS_ARB_RW7_WA_PTR
+#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR
+
+#define USBFS_ARB_RW8_DR     USBFS_ARB_RW8_DR_PTR
+#define USBFS_ARB_RW8_RA     USBFS_ARB_RW8_RA_PTR
+#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR
+#define USBFS_ARB_RW8_WA     USBFS_ARB_RW8_WA_PTR
+#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR
+
+#define USBFS_BUF_SIZE       USBFS_BUF_SIZE_PTR
+#define USBFS_BUS_RST_CNT    USBFS_BUS_RST_CNT_PTR
+#define USBFS_CR0            USBFS_CR0_PTR
+#define USBFS_CR1            USBFS_CR1_PTR
+#define USBFS_CWA            USBFS_CWA_PTR
+#define USBFS_CWA_MSB        USBFS_CWA_MSB_PTR
+
+#define USBFS_DMA_THRES      USBFS_DMA_THRES_PTR
+#define USBFS_DMA_THRES_MSB  USBFS_DMA_THRES_MSB_PTR
+
+#define USBFS_EP_ACTIVE      USBFS_EP_ACTIVE_PTR
+#define USBFS_EP_TYPE        USBFS_EP_TYPE_PTR
+
+#define USBFS_EP0_CNT        USBFS_EP0_CNT_PTR
+#define USBFS_EP0_CR         USBFS_EP0_CR_PTR
+#define USBFS_EP0_DR0        USBFS_EP0_DR0_PTR
+#define USBFS_EP0_DR1        USBFS_EP0_DR1_PTR
+#define USBFS_EP0_DR2        USBFS_EP0_DR2_PTR
+#define USBFS_EP0_DR3        USBFS_EP0_DR3_PTR
+#define USBFS_EP0_DR4        USBFS_EP0_DR4_PTR
+#define USBFS_EP0_DR5        USBFS_EP0_DR5_PTR
+#define USBFS_EP0_DR6        USBFS_EP0_DR6_PTR
+#define USBFS_EP0_DR7        USBFS_EP0_DR7_PTR
+
+#define USBFS_OSCLK_DR0      USBFS_OSCLK_DR0_PTR
+#define USBFS_OSCLK_DR1      USBFS_OSCLK_DR1_PTR
+
+#define USBFS_PM_ACT_CFG     USBFS_PM_ACT_CFG_PTR
+#define USBFS_PM_STBY_CFG    USBFS_PM_STBY_CFG_PTR
+
+#define USBFS_SIE_EP_INT_EN  USBFS_SIE_EP_INT_EN_PTR
+#define USBFS_SIE_EP_INT_SR  USBFS_SIE_EP_INT_SR_PTR
+
+#define USBFS_SIE_EP1_CNT0   USBFS_SIE_EP1_CNT0_PTR
+#define USBFS_SIE_EP1_CNT1   USBFS_SIE_EP1_CNT1_PTR
+#define USBFS_SIE_EP1_CR0    USBFS_SIE_EP1_CR0_PTR
+
+#define USBFS_SIE_EP2_CNT0   USBFS_SIE_EP2_CNT0_PTR
+#define USBFS_SIE_EP2_CNT1   USBFS_SIE_EP2_CNT1_PTR
+#define USBFS_SIE_EP2_CR0    USBFS_SIE_EP2_CR0_PTR
+
+#define USBFS_SIE_EP3_CNT0   USBFS_SIE_EP3_CNT0_PTR
+#define USBFS_SIE_EP3_CNT1   USBFS_SIE_EP3_CNT1_PTR
+#define USBFS_SIE_EP3_CR0    USBFS_SIE_EP3_CR0_PTR
+
+#define USBFS_SIE_EP4_CNT0   USBFS_SIE_EP4_CNT0_PTR
+#define USBFS_SIE_EP4_CNT1   USBFS_SIE_EP4_CNT1_PTR
+#define USBFS_SIE_EP4_CR0    USBFS_SIE_EP4_CR0_PTR
+
+#define USBFS_SIE_EP5_CNT0   USBFS_SIE_EP5_CNT0_PTR
+#define USBFS_SIE_EP5_CNT1   USBFS_SIE_EP5_CNT1_PTR
+#define USBFS_SIE_EP5_CR0    USBFS_SIE_EP5_CR0_PTR
+
+#define USBFS_SIE_EP6_CNT0   USBFS_SIE_EP6_CNT0_PTR
+#define USBFS_SIE_EP6_CNT1   USBFS_SIE_EP6_CNT1_PTR
+#define USBFS_SIE_EP6_CR0    USBFS_SIE_EP6_CR0_PTR
+
+#define USBFS_SIE_EP7_CNT0   USBFS_SIE_EP7_CNT0_PTR
+#define USBFS_SIE_EP7_CNT1   USBFS_SIE_EP7_CNT1_PTR
+#define USBFS_SIE_EP7_CR0    USBFS_SIE_EP7_CR0_PTR
+
+#define USBFS_SIE_EP8_CNT0   USBFS_SIE_EP8_CNT0_PTR
+#define USBFS_SIE_EP8_CNT1   USBFS_SIE_EP8_CNT1_PTR
+#define USBFS_SIE_EP8_CR0    USBFS_SIE_EP8_CR0_PTR
+
+#define USBFS_SOF0           USBFS_SOF0_PTR
+#define USBFS_SOF1           USBFS_SOF1_PTR
+
+#define USBFS_USB_CLK_EN     USBFS_USB_CLK_EN_PTR
+
+#define USBFS_USBIO_CR0      USBFS_USBIO_CR0_PTR
+#define USBFS_USBIO_CR1      USBFS_USBIO_CR1_PTR
+#define USBFS_USBIO_CR2      USBFS_USBIO_CR2_PTR
+
+#define USBFS_USB_MEM        ((reg8 *) CYDEV_USB_MEM_BASE)
+
+#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)
+    /* PSoC3 interrupt registers*/
+    #define USBFS_USB_ISR_PRIOR  ((reg8 *) CYDEV_INTC_PRIOR0)
+    #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)
+    #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)
+    #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_INTC_VECT_MBASE)
+#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)
+    /* PSoC5 interrupt registers*/
+    #define USBFS_USB_ISR_PRIOR  ((reg8 *) CYDEV_NVIC_PRI_0)
+    #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
+    #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
+    #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
+#endif /*  CYDEV_CHIP_DIE_EXPECT */
+
+
+/***************************************
+* Interrupt vectors, masks and priorities
+***************************************/
+
+#define USBFS_BUS_RESET_PRIOR    USBFS_bus_reset__INTC_PRIOR_NUM
+#define USBFS_BUS_RESET_MASK     USBFS_bus_reset__INTC_MASK
+#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER
+
+#define USBFS_SOF_PRIOR          USBFS_sof_int__INTC_PRIOR_NUM
+#define USBFS_SOF_MASK           USBFS_sof_int__INTC_MASK
+#define USBFS_SOF_VECT_NUM       USBFS_sof_int__INTC_NUMBER
+
+#define USBFS_EP_0_PRIOR         USBFS_ep_0__INTC_PRIOR_NUM
+#define USBFS_EP_0_MASK          USBFS_ep_0__INTC_MASK
+#define USBFS_EP_0_VECT_NUM      USBFS_ep_0__INTC_NUMBER
+
+#define USBFS_EP_1_PRIOR         USBFS_ep_1__INTC_PRIOR_NUM
+#define USBFS_EP_1_MASK          USBFS_ep_1__INTC_MASK
+#define USBFS_EP_1_VECT_NUM      USBFS_ep_1__INTC_NUMBER
+
+#define USBFS_EP_2_PRIOR         USBFS_ep_2__INTC_PRIOR_NUM
+#define USBFS_EP_2_MASK          USBFS_ep_2__INTC_MASK
+#define USBFS_EP_2_VECT_NUM      USBFS_ep_2__INTC_NUMBER
+
+#define USBFS_EP_3_PRIOR         USBFS_ep_3__INTC_PRIOR_NUM
+#define USBFS_EP_3_MASK          USBFS_ep_3__INTC_MASK
+#define USBFS_EP_3_VECT_NUM      USBFS_ep_3__INTC_NUMBER
+
+#define USBFS_EP_4_PRIOR         USBFS_ep_4__INTC_PRIOR_NUM
+#define USBFS_EP_4_MASK          USBFS_ep_4__INTC_MASK
+#define USBFS_EP_4_VECT_NUM      USBFS_ep_4__INTC_NUMBER
+
+#define USBFS_EP_5_PRIOR         USBFS_ep_5__INTC_PRIOR_NUM
+#define USBFS_EP_5_MASK          USBFS_ep_5__INTC_MASK
+#define USBFS_EP_5_VECT_NUM      USBFS_ep_5__INTC_NUMBER
+
+#define USBFS_EP_6_PRIOR         USBFS_ep_6__INTC_PRIOR_NUM
+#define USBFS_EP_6_MASK          USBFS_ep_6__INTC_MASK
+#define USBFS_EP_6_VECT_NUM      USBFS_ep_6__INTC_NUMBER
+
+#define USBFS_EP_7_PRIOR         USBFS_ep_7__INTC_PRIOR_NUM
+#define USBFS_EP_7_MASK          USBFS_ep_7__INTC_MASK
+#define USBFS_EP_7_VECT_NUM      USBFS_ep_7__INTC_NUMBER
+
+#define USBFS_EP_8_PRIOR         USBFS_ep_8__INTC_PRIOR_NUM
+#define USBFS_EP_8_MASK          USBFS_ep_8__INTC_MASK
+#define USBFS_EP_8_VECT_NUM      USBFS_ep_8__INTC_NUMBER
+
+#define USBFS_DP_INTC_PRIOR      USBFS_dp_int__INTC_PRIOR_NUM
+#define USBFS_DP_INTC_MASK       USBFS_dp_int__INTC_MASK
+#define USBFS_DP_INTC_VECT_NUM   USBFS_dp_int__INTC_NUMBER
+
+/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */
+#define USBFS_ARB_PRIOR          (0u)
+#define USBFS_ARB_MASK           USBFS_arb_int__INTC_MASK
+#define USBFS_ARB_VECT_NUM       USBFS_arb_int__INTC_NUMBER
+
+/***************************************
+ *  Endpoint 0 offsets (Table 9-2)
+ **************************************/
+
+#define USBFS_bmRequestType      USBFS_EP0_DR0_PTR
+#define USBFS_bRequest           USBFS_EP0_DR1_PTR
+#define USBFS_wValue             USBFS_EP0_DR2_PTR
+#define USBFS_wValueHi           USBFS_EP0_DR3_PTR
+#define USBFS_wValueLo           USBFS_EP0_DR2_PTR
+#define USBFS_wIndex             USBFS_EP0_DR4_PTR
+#define USBFS_wIndexHi           USBFS_EP0_DR5_PTR
+#define USBFS_wIndexLo           USBFS_EP0_DR4_PTR
+#define USBFS_length             USBFS_EP0_DR6_PTR
+#define USBFS_lengthHi           USBFS_EP0_DR7_PTR
+#define USBFS_lengthLo           USBFS_EP0_DR6_PTR
+
+
+/***************************************
+*       Register Constants
+***************************************/
+#define USBFS_VDDD_MV                    CYDEV_VDDD_MV
+#define USBFS_3500MV                     (3500u)
+
+#define USBFS_CR1_REG_ENABLE             (0x01u)
+#define USBFS_CR1_ENABLE_LOCK            (0x02u)
+#define USBFS_CR1_BUS_ACTIVITY_SHIFT     (0x02u)
+#define USBFS_CR1_BUS_ACTIVITY           ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT))
+#define USBFS_CR1_TRIM_MSB_EN            (0x08u)
+
+#define USBFS_EP0_CNT_DATA_TOGGLE        (0x80u)
+#define USBFS_EPX_CNT_DATA_TOGGLE        (0x80u)
+#define USBFS_EPX_CNT0_MASK              (0x0Fu)
+#define USBFS_EPX_CNTX_MSB_MASK          (0x07u)
+#define USBFS_EPX_CNTX_ADDR_SHIFT        (0x04u)
+#define USBFS_EPX_CNTX_ADDR_OFFSET       (0x10u)
+#define USBFS_EPX_CNTX_CRC_COUNT         (0x02u)
+#define USBFS_EPX_DATA_BUF_MAX           (512u)
+
+#define USBFS_CR0_ENABLE                 (0x80u)
+
+/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */
+#define USBFS_BUS_RST_COUNT              (0x0au)
+
+#define USBFS_USBIO_CR1_IOMODE           (0x20u)
+#define USBFS_USBIO_CR1_USBPUEN          (0x04u)
+#define USBFS_USBIO_CR1_DP0              (0x02u)
+#define USBFS_USBIO_CR1_DM0              (0x01u)
+
+#define USBFS_USBIO_CR0_TEN              (0x80u)
+#define USBFS_USBIO_CR0_TSE0             (0x40u)
+#define USBFS_USBIO_CR0_TD               (0x20u)
+#define USBFS_USBIO_CR0_RD               (0x01u)
+
+#define USBFS_FASTCLK_IMO_CR_USBCLK_ON   (0x40u)
+#define USBFS_FASTCLK_IMO_CR_XCLKEN      (0x20u)
+#define USBFS_FASTCLK_IMO_CR_FX2ON       (0x10u)
+
+#define USBFS_ARB_EPX_CFG_RESET          (0x08u)
+#define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
+#define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
+#define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
+                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
+
+#define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
+#define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
+#define USBFS_ARB_EPX_SR_BUF_OVER        (0x04u)
+#define USBFS_ARB_EPX_SR_BUF_UNDER       (0x08u)
+
+#define USBFS_ARB_CFG_AUTO_MEM           (0x10u)
+#define USBFS_ARB_CFG_MANUAL_DMA         (0x20u)
+#define USBFS_ARB_CFG_AUTO_DMA           (0x40u)
+#define USBFS_ARB_CFG_CFG_CPM            (0x80u)
+
+#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
+    #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
+#else
+    #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
+                                            (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
+                                            (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
+                                            (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \
+                                            (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \
+                                            (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \
+                                            (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \
+                                            (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) )
+
+#define USBFS_SIE_EP_INT_EP1_MASK        (0x01u)
+#define USBFS_SIE_EP_INT_EP2_MASK        (0x02u)
+#define USBFS_SIE_EP_INT_EP3_MASK        (0x04u)
+#define USBFS_SIE_EP_INT_EP4_MASK        (0x08u)
+#define USBFS_SIE_EP_INT_EP5_MASK        (0x10u)
+#define USBFS_SIE_EP_INT_EP6_MASK        (0x20u)
+#define USBFS_SIE_EP_INT_EP7_MASK        (0x40u)
+#define USBFS_SIE_EP_INT_EP8_MASK        (0x80u)
+
+#define USBFS_PM_ACT_EN_FSUSB            USBFS_USB__PM_ACT_MSK
+#define USBFS_PM_STBY_EN_FSUSB           USBFS_USB__PM_STBY_MSK
+#define USBFS_PM_AVAIL_EN_FSUSBIO        (0x10u)
+
+#define USBFS_PM_USB_CR0_REF_EN          (0x01u)
+#define USBFS_PM_USB_CR0_PD_N            (0x02u)
+#define USBFS_PM_USB_CR0_PD_PULLUP_N     (0x04u)
+
+#define USBFS_USB_CLK_ENABLE             (0x01u)
+
+#define USBFS_DM_MASK                    USBFS_Dm__0__MASK
+#define USBFS_DP_MASK                    USBFS_Dp__0__MASK
+
+#define USBFS_DYN_RECONFIG_ENABLE        (0x01u)
+#define USBFS_DYN_RECONFIG_EP_SHIFT      (0x01u)
+#define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
+
+
+#endif /*  CY_USBFS_USBFS_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c

@@ -1,146 +1,146 @@
-/*******************************************************************************
-* File Name: USBFS_Dm.c  
-* Version 2.10
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "USBFS_Dm.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: USBFS_Dm_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void USBFS_Dm_Write(uint8 value) 
-{
-    uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK));
-    USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Dm_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to one of the following drive modes.
-*
-*  USBFS_Dm_DM_STRONG     Strong Drive 
-*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
-*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
-*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
-*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
-*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
-*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
-*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void USBFS_Dm_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(USBFS_Dm_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Dm_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro USBFS_Dm_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 USBFS_Dm_Read(void) 
-{
-    return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: USBFS_Dm_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 USBFS_Dm_ReadDataReg(void) 
-{
-    return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(USBFS_Dm_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: USBFS_Dm_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 USBFS_Dm_ClearInterrupt(void) 
-    {
-        return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: USBFS_Dm.c  
+* Version 2.10
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "USBFS_Dm.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: USBFS_Dm_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void USBFS_Dm_Write(uint8 value) 
+{
+    uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK));
+    USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Dm_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dm_DM_STRONG     Strong Drive 
+*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void USBFS_Dm_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(USBFS_Dm_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Dm_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro USBFS_Dm_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 USBFS_Dm_Read(void) 
+{
+    return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_Dm_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 USBFS_Dm_ReadDataReg(void) 
+{
+    return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(USBFS_Dm_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: USBFS_Dm_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 USBFS_Dm_ClearInterrupt(void) 
+    {
+        return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h

@@ -1,130 +1,130 @@
-/*******************************************************************************
-* File Name: USBFS_Dm.h  
-* Version 2.10
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */
-#define CY_PINS_USBFS_Dm_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "USBFS_Dm_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    USBFS_Dm_Write(uint8 value) ;
-void    USBFS_Dm_SetDriveMode(uint8 mode) ;
-uint8   USBFS_Dm_ReadDataReg(void) ;
-uint8   USBFS_Dm_Read(void) ;
-uint8   USBFS_Dm_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define USBFS_Dm_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define USBFS_Dm_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define USBFS_Dm_DM_RES_UP          PIN_DM_RES_UP
-#define USBFS_Dm_DM_RES_DWN         PIN_DM_RES_DWN
-#define USBFS_Dm_DM_OD_LO           PIN_DM_OD_LO
-#define USBFS_Dm_DM_OD_HI           PIN_DM_OD_HI
-#define USBFS_Dm_DM_STRONG          PIN_DM_STRONG
-#define USBFS_Dm_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define USBFS_Dm_MASK               USBFS_Dm__MASK
-#define USBFS_Dm_SHIFT              USBFS_Dm__SHIFT
-#define USBFS_Dm_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define USBFS_Dm_PS                     (* (reg8 *) USBFS_Dm__PS)
-/* Data Register */
-#define USBFS_Dm_DR                     (* (reg8 *) USBFS_Dm__DR)
-/* Port Number */
-#define USBFS_Dm_PRT_NUM                (* (reg8 *) USBFS_Dm__PRT) 
-/* Connect to Analog Globals */                                                  
-#define USBFS_Dm_AG                     (* (reg8 *) USBFS_Dm__AG)                       
-/* Analog MUX bux enable */
-#define USBFS_Dm_AMUX                   (* (reg8 *) USBFS_Dm__AMUX) 
-/* Bidirectional Enable */                                                        
-#define USBFS_Dm_BIE                    (* (reg8 *) USBFS_Dm__BIE)
-/* Bit-mask for Aliased Register Access */
-#define USBFS_Dm_BIT_MASK               (* (reg8 *) USBFS_Dm__BIT_MASK)
-/* Bypass Enable */
-#define USBFS_Dm_BYP                    (* (reg8 *) USBFS_Dm__BYP)
-/* Port wide control signals */                                                   
-#define USBFS_Dm_CTL                    (* (reg8 *) USBFS_Dm__CTL)
-/* Drive Modes */
-#define USBFS_Dm_DM0                    (* (reg8 *) USBFS_Dm__DM0) 
-#define USBFS_Dm_DM1                    (* (reg8 *) USBFS_Dm__DM1)
-#define USBFS_Dm_DM2                    (* (reg8 *) USBFS_Dm__DM2) 
-/* Input Buffer Disable Override */
-#define USBFS_Dm_INP_DIS                (* (reg8 *) USBFS_Dm__INP_DIS)
-/* LCD Common or Segment Drive */
-#define USBFS_Dm_LCD_COM_SEG            (* (reg8 *) USBFS_Dm__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define USBFS_Dm_LCD_EN                 (* (reg8 *) USBFS_Dm__LCD_EN)
-/* Slew Rate Control */
-#define USBFS_Dm_SLW                    (* (reg8 *) USBFS_Dm__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define USBFS_Dm_PRTDSI__CAPS_SEL       (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define USBFS_Dm_PRTDSI__DBL_SYNC_IN    (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define USBFS_Dm_PRTDSI__OE_SEL0        (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) 
-#define USBFS_Dm_PRTDSI__OE_SEL1        (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define USBFS_Dm_PRTDSI__OUT_SEL0       (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) 
-#define USBFS_Dm_PRTDSI__OUT_SEL1       (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define USBFS_Dm_PRTDSI__SYNC_OUT       (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) 
-
-
-#if defined(USBFS_Dm__INTSTAT)  /* Interrupt Registers */
-
-    #define USBFS_Dm_INTSTAT                (* (reg8 *) USBFS_Dm__INTSTAT)
-    #define USBFS_Dm_SNAP                   (* (reg8 *) USBFS_Dm__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_USBFS_Dm_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: USBFS_Dm.h  
+* Version 2.10
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */
+#define CY_PINS_USBFS_Dm_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "USBFS_Dm_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    USBFS_Dm_Write(uint8 value) ;
+void    USBFS_Dm_SetDriveMode(uint8 mode) ;
+uint8   USBFS_Dm_ReadDataReg(void) ;
+uint8   USBFS_Dm_Read(void) ;
+uint8   USBFS_Dm_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define USBFS_Dm_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define USBFS_Dm_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define USBFS_Dm_DM_RES_UP          PIN_DM_RES_UP
+#define USBFS_Dm_DM_RES_DWN         PIN_DM_RES_DWN
+#define USBFS_Dm_DM_OD_LO           PIN_DM_OD_LO
+#define USBFS_Dm_DM_OD_HI           PIN_DM_OD_HI
+#define USBFS_Dm_DM_STRONG          PIN_DM_STRONG
+#define USBFS_Dm_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define USBFS_Dm_MASK               USBFS_Dm__MASK
+#define USBFS_Dm_SHIFT              USBFS_Dm__SHIFT
+#define USBFS_Dm_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define USBFS_Dm_PS                     (* (reg8 *) USBFS_Dm__PS)
+/* Data Register */
+#define USBFS_Dm_DR                     (* (reg8 *) USBFS_Dm__DR)
+/* Port Number */
+#define USBFS_Dm_PRT_NUM                (* (reg8 *) USBFS_Dm__PRT) 
+/* Connect to Analog Globals */                                                  
+#define USBFS_Dm_AG                     (* (reg8 *) USBFS_Dm__AG)                       
+/* Analog MUX bux enable */
+#define USBFS_Dm_AMUX                   (* (reg8 *) USBFS_Dm__AMUX) 
+/* Bidirectional Enable */                                                        
+#define USBFS_Dm_BIE                    (* (reg8 *) USBFS_Dm__BIE)
+/* Bit-mask for Aliased Register Access */
+#define USBFS_Dm_BIT_MASK               (* (reg8 *) USBFS_Dm__BIT_MASK)
+/* Bypass Enable */
+#define USBFS_Dm_BYP                    (* (reg8 *) USBFS_Dm__BYP)
+/* Port wide control signals */                                                   
+#define USBFS_Dm_CTL                    (* (reg8 *) USBFS_Dm__CTL)
+/* Drive Modes */
+#define USBFS_Dm_DM0                    (* (reg8 *) USBFS_Dm__DM0) 
+#define USBFS_Dm_DM1                    (* (reg8 *) USBFS_Dm__DM1)
+#define USBFS_Dm_DM2                    (* (reg8 *) USBFS_Dm__DM2) 
+/* Input Buffer Disable Override */
+#define USBFS_Dm_INP_DIS                (* (reg8 *) USBFS_Dm__INP_DIS)
+/* LCD Common or Segment Drive */
+#define USBFS_Dm_LCD_COM_SEG            (* (reg8 *) USBFS_Dm__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define USBFS_Dm_LCD_EN                 (* (reg8 *) USBFS_Dm__LCD_EN)
+/* Slew Rate Control */
+#define USBFS_Dm_SLW                    (* (reg8 *) USBFS_Dm__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define USBFS_Dm_PRTDSI__CAPS_SEL       (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define USBFS_Dm_PRTDSI__DBL_SYNC_IN    (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define USBFS_Dm_PRTDSI__OE_SEL0        (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) 
+#define USBFS_Dm_PRTDSI__OE_SEL1        (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define USBFS_Dm_PRTDSI__OUT_SEL0       (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) 
+#define USBFS_Dm_PRTDSI__OUT_SEL1       (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define USBFS_Dm_PRTDSI__SYNC_OUT       (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) 
+
+
+#if defined(USBFS_Dm__INTSTAT)  /* Interrupt Registers */
+
+    #define USBFS_Dm_INTSTAT                (* (reg8 *) USBFS_Dm__INTSTAT)
+    #define USBFS_Dm_SNAP                   (* (reg8 *) USBFS_Dm__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_USBFS_Dm_H */
+
+
+/* [] END OF FILE */