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@@ -30,8 +30,8 @@
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static uint8_t asyncTimings[][4] =
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{
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/* Speed, Assert, Deskew, Hold, Glitch */
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-{/*1.5MB/s*/ 28, 18, 13, 6},
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-{/*3.3MB/s*/ 13, 6, 6, 6},
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+{/*1.5MB/s*/ 28, 18, 13, 15},
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+{/*3.3MB/s*/ 13, 6, 6, 13},
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{/*5MB/s*/ 9, 6, 6, 6}, // 80ns
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{/*safe*/ 3, 6, 6, 6}, // Probably safe
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{/*turbo*/ 3, 3, 3, 2}
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@@ -481,6 +481,16 @@ scsiSetDefaultTiming()
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}
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void scsiEnterPhase(int newPhase)
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+{
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+ uint32_t delay = scsiEnterPhaseImmediate(newPhase);
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+ if (delay > 0)
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+ {
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+ s2s_delay_us(delay);
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+ }
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+}
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+
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+// Returns microsecond delay
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+uint32_t scsiEnterPhaseImmediate(int newPhase)
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{
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// ANSI INCITS 362-2002 SPI-3 10.7.1:
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// Phase changes are not allowed while REQ or ACK is asserted.
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@@ -569,22 +579,27 @@ void scsiEnterPhase(int newPhase)
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asyncTiming[3]);
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}
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+ uint32_t delayUs = 0;
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if (newPhase >= 0)
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{
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*SCSI_CTRL_PHASE = newPhase;
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- busSettleDelay();
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+ delayUs += 1; // busSettleDelay
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if (scsiDev.compatMode < COMPAT_SCSI2)
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{
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// EMU EMAX needs 100uS ! 10uS is not enough.
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- s2s_delay_us(100);
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+ delayUs += 100;
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}
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}
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else
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{
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*SCSI_CTRL_PHASE = 0;
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}
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+
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+ return delayUs;
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}
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+
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+ return 0; // No change
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}
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uint32_t s2s_getScsiRateMBs()
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