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+/* Synchronous mode SCSI implementation.
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+ *
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+ * In synchronous mode, the handshake mechanism is not used. Instead
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+ * either end of the communication will just send a bunch of bytes
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+ * and only afterwards checks that the number of acknowledgement
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+ * pulses matches.
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+ *
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+ * The receiving end should latch in the data at the falling edge of
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+ * the request pulse (on either REQ or ACK pin). We use the GD32 EXMC
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+ * peripheral to implement this latching with the NWAIT pin when
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+ * reading data from the host. NOE is used to generate the REQ pulses.
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+ *
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+ * Writing data to the host is simpler, as we can just write it out
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+ * from the GPIO port at our own pace. A timer is used for generating
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+ * the output pulses on REQ pin.
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+ */
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+
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+#include "scsi_accel_sync.h"
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+#include <AzulSCSI_log.h>
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+#include <gd32f20x_exmc.h>
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+
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+#ifndef SCSI_SYNC_MODE_AVAILABLE
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+
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+void scsi_accel_sync_init() {}
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+
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+void scsi_accel_sync_read(uint8_t *data, uint32_t count, int* parityError, volatile int *resetFlag) {}
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+void scsi_accel_sync_startWrite(const uint8_t* data, uint32_t count, volatile int *resetFlag) {}
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+void scsi_accel_sync_stopWrite() {}
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+void scsi_accel_sync_finishWrite(volatile int *resetFlag) {}
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+bool scsi_accel_sync_isWriteFinished(const uint8_t* data) { return true; }
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+
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+#else
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+
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+void scsi_accel_sync_init()
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+{
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+ rcu_periph_clock_enable(RCU_EXMC);
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+ rcu_periph_clock_enable(SCSI_TIMER_RCU);
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+
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+ exmc_norsram_timing_parameter_struct timing_param = {
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+ .asyn_access_mode = EXMC_ACCESS_MODE_A,
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+ .syn_data_latency = EXMC_DATALAT_2_CLK,
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+ .syn_clk_division = EXMC_SYN_CLOCK_RATIO_2_CLK,
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+ .bus_latency = 1,
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+ .asyn_data_setuptime = 2,
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+ .asyn_address_holdtime = 2,
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+ .asyn_address_setuptime = 1
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+ };
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+
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+ exmc_norsram_parameter_struct sram_param = {
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+ .norsram_region = EXMC_BANK0_NORSRAM_REGION0,
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+ .write_mode = EXMC_ASYN_WRITE,
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+ .extended_mode = DISABLE,
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+ .asyn_wait = ENABLE,
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+ .nwait_signal = ENABLE,
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+ .memory_write = DISABLE,
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+ .nwait_config = EXMC_NWAIT_CONFIG_DURING,
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+ .wrap_burst_mode = DISABLE,
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+ .nwait_polarity = EXMC_NWAIT_POLARITY_HIGH,
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+ .burst_mode = DISABLE,
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+ .databus_width = EXMC_NOR_DATABUS_WIDTH_16B,
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+ .memory_type = EXMC_MEMORY_TYPE_SRAM,
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+ .address_data_mux = DISABLE,
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+ .read_write_timing = &timing_param
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+ };
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+
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+ exmc_norsram_init(&sram_param);
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+
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+ gpio_init(SCSI_IN_ACK_EXMC_NWAIT_PORT, GPIO_MODE_IN_FLOATING, 0, SCSI_IN_ACK_EXMC_NWAIT_PIN);
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+}
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+
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+void scsi_accel_sync_read(uint8_t *data, uint32_t count, int* parityError, volatile int *resetFlag)
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+{
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+ exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION0);
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+ gpio_init(SCSI_OUT_REQ_EXMC_NOE_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, SCSI_OUT_REQ_EXMC_NOE_PIN);
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+
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+ for (int i = 0; i < count; i++)
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+ {
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+ uint32_t value = *(volatile uint32_t*)EXMC_NOR_PSRAM;
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+ data[i] = ~(value >> SCSI_EXMC_DATA_SHIFT) & 0xFF;
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+ }
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+
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+ gpio_init(SCSI_OUT_REQ_EXMC_NOE_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SCSI_OUT_REQ_EXMC_NOE_PIN);
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+ exmc_norsram_disable(EXMC_BANK0_NORSRAM_REGION0);
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+}
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+
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+void scsi_accel_sync_startWrite(const uint8_t* data, uint32_t count, volatile int *resetFlag)
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+{
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+ for (int i = 0; i < count; i++)
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+ {
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+ SCSI_OUT_DATA(data[i]);
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+ delay_100ns();
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+ SCSI_OUT(REQ, 1);
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+ delay_ns(200);
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+ SCSI_OUT(REQ, 0);
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+ delay_ns(500);
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+ }
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+ SCSI_RELEASE_DATA_REQ();
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+}
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+
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+void scsi_accel_sync_stopWrite()
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+{
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+
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+}
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+
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+void scsi_accel_sync_finishWrite(volatile int *resetFlag)
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+{
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+
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+}
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+
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+bool scsi_accel_sync_isWriteFinished(const uint8_t* data)
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+{
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+ return true;
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+}
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+
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+#endif
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Petteri Aimonen