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@@ -21,6 +21,7 @@
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#include "scsi.h"
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#include "scsiPhy.h"
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#include "bits.h"
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+#include "trace.h"
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#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)
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@@ -50,18 +51,21 @@ volatile uint8_t scsiTxDMAComplete;
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CY_ISR_PROTO(scsiRxCompleteISR);
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CY_ISR(scsiRxCompleteISR)
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{
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+ traceIrq(trace_scsiRxCompleteISR);
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scsiRxDMAComplete = 1;
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}
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CY_ISR_PROTO(scsiTxCompleteISR);
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CY_ISR(scsiTxCompleteISR)
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{
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+ traceIrq(trace_scsiTxCompleteISR);
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scsiTxDMAComplete = 1;
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}
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CY_ISR_PROTO(scsiResetISR);
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CY_ISR(scsiResetISR)
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{
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+ traceIrq(trace_scsiResetISR);
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scsiDev.resetFlag = 1;
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}
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@@ -82,13 +86,16 @@ scsiReadDBxPins()
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uint8_t
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scsiReadByte(void)
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{
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+ trace(trace_spinPhyTxFifo);
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while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
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scsiPhyTx(0);
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+ trace(trace_spinPhyRxFifo);
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while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}
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uint8_t val = scsiPhyRx();
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scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
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+ trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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return val;
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@@ -124,6 +131,7 @@ doRxSingleDMA(uint8* data, uint32 count)
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{
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// Prepare DMA transfer
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dmaInProgress = 1;
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+ trace(trace_doRxSingleDMA);
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CyDmaTdSetConfiguration(
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scsiDmaTxTd[0],
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@@ -184,6 +192,7 @@ scsiReadDMAPoll()
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{
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// Wait until our scsi signals are consistent. This should only be
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// a few cycles.
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+ trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
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if (likely(dmaSentCount == dmaTotalCount))
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@@ -219,12 +228,13 @@ scsiRead(uint8_t* data, uint32_t count)
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else
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{
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scsiReadDMA(data, count);
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-
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+
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// Wait for the next DMA interrupt (or the 1ms systick)
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// It's beneficial to halt the processor to
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// give the DMA controller more memory bandwidth to work with.
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__WFI();
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-
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+
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+ trace(trace_spinReadDMAPoll);
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while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};
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}
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}
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@@ -232,9 +242,11 @@ scsiRead(uint8_t* data, uint32_t count)
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void
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scsiWriteByte(uint8 value)
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{
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+ trace(trace_spinPhyTxFifo);
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while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
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scsiPhyTx(value);
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+ trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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scsiPhyRxFifoClear();
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}
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@@ -253,6 +265,7 @@ scsiWritePIO(const uint8_t* data, uint32_t count)
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}
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}
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+ trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
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scsiPhyRxFifoClear();
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}
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@@ -262,6 +275,7 @@ doTxSingleDMA(const uint8* data, uint32 count)
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{
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// Prepare DMA transfer
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dmaInProgress = 1;
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+ trace(trace_doTxSingleDMA);
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CyDmaTdSetConfiguration(
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scsiDmaTxTd[0],
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@@ -306,6 +320,7 @@ scsiWriteDMAPoll()
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{
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// Wait until our scsi signals are consistent. This should only be
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// a few cycles.
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+ trace(trace_spinTxComplete);
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while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
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if (likely(dmaSentCount == dmaTotalCount))
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@@ -341,12 +356,13 @@ scsiWrite(const uint8_t* data, uint32_t count)
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else
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{
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scsiWriteDMA(data, count);
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-
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+
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// Wait for the next DMA interrupt (or the 1ms systick)
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// It's beneficial to halt the processor to
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// give the DMA controller more memory bandwidth to work with.
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__WFI();
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+ trace(trace_spinWriteDMAPoll);
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while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};
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}
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}
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@@ -370,6 +386,7 @@ void scsiEnterPhase(int phase)
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void scsiPhyReset()
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{
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+ trace(trace_scsiPhyReset);
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if (dmaInProgress)
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{
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dmaInProgress = 0;
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@@ -378,6 +395,7 @@ void scsiPhyReset()
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dmaTotalCount = 0;
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CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);
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CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);
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+ trace(trace_spinDMAReset);
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while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}
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CyDmaChDisable(scsiDmaTxChan);
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