SCSI data read/write implemented using the PSoC datapath

Moved some configuration parameters into EEPROM

lib/SCSI2SD/STATUS

@@ -3,11 +3,12 @@ assignments are incorrect.
 
 - USB bootloader is not implemented yet.
 
-- Configuration options are not yet loaded from EEPROM.
 - Configuration options cannot be set via USB.
 	- SCSI ID hardcoded to 0
 	- Partity checking is on
 	- Unit Attention Condition is off
+	- SPI overclock to 32MHz off.
 
 - DMA is not used for SPI transfers
+- Parity checking not implemented for the PSoC Datapath implementation
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c

@@ -0,0 +1,511 @@
+/*******************************************************************************
+* File Name: CFG_EEPROM.c
+* Version 2.10
+*
+* Description:
+*  Provides the source code to the API for the EEPROM component.
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "CFG_EEPROM.h"
+
+
+#if (CY_PSOC3 || CY_PSOC5LP)
+
+    /*******************************************************************************
+    * Function Name: CFG_EEPROM_Enable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enable the EEPROM.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CFG_EEPROM_Enable(void) 
+    {
+        CyEEPROM_Start();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CFG_EEPROM_Start
+    ********************************************************************************
+    *
+    * Summary:
+    *  Starts EEPROM.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CFG_EEPROM_Start(void) 
+    {
+        /* Enable the EEPROM */
+        CFG_EEPROM_Enable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CFG_EEPROM_Stop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops and powers down EEPROM.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CFG_EEPROM_Stop (void) 
+    {
+        /* Disable EEPROM */
+        CyEEPROM_Stop();
+    }
+
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_EraseSector
+********************************************************************************
+*
+* Summary:
+*  Erases a sector of memory. This function blocks until the operation is
+*  complete.
+*
+* Parameters:
+*  sectorNumber:  Sector number to erase.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter sectorNumber out of range.
+*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) 
+{
+    cystatus status;
+
+    /* Start the SPC */
+    CySpcStart();
+
+    if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)
+    {
+        /* See if we can get the SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            #if(CY_PSOC5A)
+
+                /* Plan for failure */
+                status = CYRET_UNKNOWN;
+
+                /* Command to load a row of data */
+                if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+                {
+                    while(CY_SPC_BUSY)
+                    {
+                        /* Wait until SPC becomes idle */
+                    }
+
+                    /* SPC is idle now */
+                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                    {
+                        status = CYRET_SUCCESS;
+                    }
+                }
+
+                /* Command to erase a sector */
+                if(status == CYRET_SUCCESS)
+                {
+
+            #endif /* (CY_PSOC5A) */
+
+                    if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+
+            #if(CY_PSOC5A)
+
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+
+            #endif /* (CY_PSOC5A) */
+
+                /* Unlock the SPC so someone else can use it. */
+                CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_Write
+********************************************************************************
+*
+* Summary:
+*  Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is
+*  a blocking call. It will not return until the function succeeds or fails.
+*
+* Parameters:
+*  rowData:  Address of the data to write to the EEPROM.
+*  rowNumber:  EEPROM row number to program.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.
+*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) 
+{
+    cystatus status;
+
+    /* Start the SPC */
+    CySpcStart();
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get the SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
+                    dieTemperature[1]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock the SPC so someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_StartWrite
+********************************************************************************
+*
+* Summary:
+*  Starts the SPC write function. This function does not block, it returns
+*  once the command has begun the SPC write function. This function must be used
+*  in combination with CFG_EEPROM_QueryWrite(). Once this function has
+*  been called the SPC will be locked until CFG_EEPROM_QueryWrite()
+*  returns CYRET_SUCCESS.
+*
+* Parameters:
+*  rowData:  Address of buffer containing a row of data to write to the EEPROM.
+*  rowNumber:  EEPROM row number to program.
+*
+* Return:
+*  CYRET_STARTED, if the spc command to write was successfuly started.
+*  CYRET_BAD_PARAM, if the parameter rowNumber out of range.
+*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+
+{
+    cystatus status;
+
+    if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)
+    {
+        /* See if we can get the SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a row of data */
+            if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
+                    dieTemperature[1]) == CYRET_STARTED)
+                    {
+                        status = CYRET_STARTED;
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_QueryWrite
+********************************************************************************
+*
+* Summary:
+*  Checks the state of write to EEPROM. This function must be called until
+*  the return value is not CYRET_STARTED.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED, if the spc command is still processing.
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_QueryWrite(void) 
+{
+    cystatus status;
+
+    /* Check if SPC is idle */
+    if(CY_SPC_IDLE)
+    {
+        /* SPC is idle now */
+        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+        {
+            status = CYRET_SUCCESS;
+        }
+        else
+        {
+            status = CYRET_UNKNOWN;
+        }
+
+        /* Unlock the SPC so someone else can use it. */
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_STARTED;
+    }
+
+    return(status);
+}
+
+
+/*******************************************************************************
+* Function Name: CFG_EEPROM_ByteWrite
+********************************************************************************
+*
+* Summary:
+*  Writes a byte of data to the EEPROM. This is a blocking call. It will not
+*  return until the function succeeds or fails.
+*
+* Parameters:
+*  dataByte:  Byte of data to write to the EEPROM.
+*  rowNumber:  EEPROM row number to program.
+*  byteNumber:  Byte number within the row to program.
+*
+* Return:
+*  CYRET_SUCCESS, if the operation was successful.
+*  CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.
+*  CYRET_LOCKED, if the spc is being used.
+*  CYRET_UNKNOWN, if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+
+{
+    cystatus status;
+
+    /* Start the SPC */
+    CySpcStart();
+
+    if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))
+    {
+        /* See if we can get the SPC. */
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Plan for failure */
+            status = CYRET_UNKNOWN;
+
+            /* Command to load a byte of data */
+            if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\
+                                                                CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)
+            {
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait until SPC becomes idle */
+                }
+
+                /* SPC is idle now */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                {
+                    status = CYRET_SUCCESS;
+                }
+
+                /* Command to erase and program the row. */
+                if(status == CYRET_SUCCESS)
+                {
+                    if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],
+                    dieTemperature[1]) == CYRET_STARTED)
+                    {
+                        /* Plan for failure */
+                        status = CYRET_UNKNOWN;
+
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait until SPC becomes idle */
+                        }
+
+                        /* SPC is idle now */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                    }
+                    else
+                    {
+                        status = CYRET_UNKNOWN;
+                    }
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
+            }
+
+            /* Unlock the SPC so someone else can use it. */
+            CySpcUnlock();
+        }
+        else
+        {
+            status = CYRET_LOCKED;
+        }
+    }
+    else
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    return(status);
+}
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h

@@ -0,0 +1,60 @@
+/*******************************************************************************
+* File Name: CFG_EEPROM.h
+* Version 2.10
+*
+* Description:
+*  Provides the function definitions for the EEPROM APIs.
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_EEPROM_CFG_EEPROM_H)
+#define CY_EEPROM_CFG_EEPROM_H
+
+#include "cydevice_trm.h"
+#include "CyFlash.h"
+
+#if !defined(CY_PSOC5LP)
+    #error Component EEPROM_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+#if (CY_PSOC3 || CY_PSOC5LP) 
+    void CFG_EEPROM_Enable(void) ;
+    void CFG_EEPROM_Start(void); 
+    void CFG_EEPROM_Stop(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \
+            ;
+cystatus CFG_EEPROM_QueryWrite(void) ;
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \
+            ;
+
+
+/****************************************
+*           API Constants
+****************************************/
+
+#define CFG_EEPROM_EEPROM_SIZE    		CYDEV_EE_SIZE
+#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE    (0x01u)
+
+
+/*******************************************************************************
+* Following code are OBSOLETE and must not be used starting from EEPROM 2.10
+*******************************************************************************/
+#define SPC_BYTE_WRITE_SIZE             (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)
+
+#endif /* CY_EEPROM_CFG_EEPROM_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.c

@@ -1,137 +0,0 @@
-/*******************************************************************************
-* File Name: PARITY_EN.c  
-* Version 1.90
-*
-* Description:
-*  This file contains API to enable firmware control of a Pins component.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "cytypes.h"
-#include "PARITY_EN.h"
-
-/* APIs are not generated for P15[7:6] on PSoC 5 */
-#if !(CY_PSOC5A &&\
-	 PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))
-
-
-/*******************************************************************************
-* Function Name: PARITY_EN_Write
-********************************************************************************
-*
-* Summary:
-*  Assign a new value to the digital port's data output register.  
-*
-* Parameters:  
-*  prtValue:  The value to be assigned to the Digital Port. 
-*
-* Return: 
-*  None
-*  
-*******************************************************************************/
-void PARITY_EN_Write(uint8 value) 
-{
-    uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK));
-    PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: PARITY_EN_SetDriveMode
-********************************************************************************
-*
-* Summary:
-*  Change the drive mode on the pins of the port.
-* 
-* Parameters:  
-*  mode:  Change the pins to this drive mode.
-*
-* Return: 
-*  None
-*
-*******************************************************************************/
-void PARITY_EN_SetDriveMode(uint8 mode) 
-{
-	CyPins_SetPinDriveMode(PARITY_EN_0, mode);
-}
-
-
-/*******************************************************************************
-* Function Name: PARITY_EN_Read
-********************************************************************************
-*
-* Summary:
-*  Read the current value on the pins of the Digital Port in right justified 
-*  form.
-*
-* Parameters:  
-*  None
-*
-* Return: 
-*  Returns the current value of the Digital Port as a right justified number
-*  
-* Note:
-*  Macro PARITY_EN_ReadPS calls this function. 
-*  
-*******************************************************************************/
-uint8 PARITY_EN_Read(void) 
-{
-    return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
-}
-
-
-/*******************************************************************************
-* Function Name: PARITY_EN_ReadDataReg
-********************************************************************************
-*
-* Summary:
-*  Read the current value assigned to a Digital Port's data output register
-*
-* Parameters:  
-*  None 
-*
-* Return: 
-*  Returns the current value assigned to the Digital Port's data output register
-*  
-*******************************************************************************/
-uint8 PARITY_EN_ReadDataReg(void) 
-{
-    return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
-}
-
-
-/* If Interrupts Are Enabled for this Pins component */ 
-#if defined(PARITY_EN_INTSTAT) 
-
-    /*******************************************************************************
-    * Function Name: PARITY_EN_ClearInterrupt
-    ********************************************************************************
-    * Summary:
-    *  Clears any active interrupts attached to port and returns the value of the 
-    *  interrupt status register.
-    *
-    * Parameters:  
-    *  None 
-    *
-    * Return: 
-    *  Returns the value of the interrupt status register
-    *  
-    *******************************************************************************/
-    uint8 PARITY_EN_ClearInterrupt(void) 
-    {
-        return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT;
-    }
-
-#endif /* If Interrupts Are Enabled for this Pins component */ 
-
-#endif /* CY_PSOC5A... */
-
-    
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN.h

@@ -1,130 +0,0 @@
-/*******************************************************************************
-* File Name: PARITY_EN.h  
-* Version 1.90
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */
-#define CY_PINS_PARITY_EN_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "cypins.h"
-#include "PARITY_EN_aliases.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-/* APIs are not generated for P15[7:6] */
-#if !(CY_PSOC5A &&\
-	 PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))
-
-
-/***************************************
-*        Function Prototypes             
-***************************************/    
-
-void    PARITY_EN_Write(uint8 value) ;
-void    PARITY_EN_SetDriveMode(uint8 mode) ;
-uint8   PARITY_EN_ReadDataReg(void) ;
-uint8   PARITY_EN_Read(void) ;
-uint8   PARITY_EN_ClearInterrupt(void) ;
-
-
-/***************************************
-*           API Constants        
-***************************************/
-
-/* Drive Modes */
-#define PARITY_EN_DM_ALG_HIZ         PIN_DM_ALG_HIZ
-#define PARITY_EN_DM_DIG_HIZ         PIN_DM_DIG_HIZ
-#define PARITY_EN_DM_RES_UP          PIN_DM_RES_UP
-#define PARITY_EN_DM_RES_DWN         PIN_DM_RES_DWN
-#define PARITY_EN_DM_OD_LO           PIN_DM_OD_LO
-#define PARITY_EN_DM_OD_HI           PIN_DM_OD_HI
-#define PARITY_EN_DM_STRONG          PIN_DM_STRONG
-#define PARITY_EN_DM_RES_UPDWN       PIN_DM_RES_UPDWN
-
-/* Digital Port Constants */
-#define PARITY_EN_MASK               PARITY_EN__MASK
-#define PARITY_EN_SHIFT              PARITY_EN__SHIFT
-#define PARITY_EN_WIDTH              1u
-
-
-/***************************************
-*             Registers        
-***************************************/
-
-/* Main Port Registers */
-/* Pin State */
-#define PARITY_EN_PS                     (* (reg8 *) PARITY_EN__PS)
-/* Data Register */
-#define PARITY_EN_DR                     (* (reg8 *) PARITY_EN__DR)
-/* Port Number */
-#define PARITY_EN_PRT_NUM                (* (reg8 *) PARITY_EN__PRT) 
-/* Connect to Analog Globals */                                                  
-#define PARITY_EN_AG                     (* (reg8 *) PARITY_EN__AG)                       
-/* Analog MUX bux enable */
-#define PARITY_EN_AMUX                   (* (reg8 *) PARITY_EN__AMUX) 
-/* Bidirectional Enable */                                                        
-#define PARITY_EN_BIE                    (* (reg8 *) PARITY_EN__BIE)
-/* Bit-mask for Aliased Register Access */
-#define PARITY_EN_BIT_MASK               (* (reg8 *) PARITY_EN__BIT_MASK)
-/* Bypass Enable */
-#define PARITY_EN_BYP                    (* (reg8 *) PARITY_EN__BYP)
-/* Port wide control signals */                                                   
-#define PARITY_EN_CTL                    (* (reg8 *) PARITY_EN__CTL)
-/* Drive Modes */
-#define PARITY_EN_DM0                    (* (reg8 *) PARITY_EN__DM0) 
-#define PARITY_EN_DM1                    (* (reg8 *) PARITY_EN__DM1)
-#define PARITY_EN_DM2                    (* (reg8 *) PARITY_EN__DM2) 
-/* Input Buffer Disable Override */
-#define PARITY_EN_INP_DIS                (* (reg8 *) PARITY_EN__INP_DIS)
-/* LCD Common or Segment Drive */
-#define PARITY_EN_LCD_COM_SEG            (* (reg8 *) PARITY_EN__LCD_COM_SEG)
-/* Enable Segment LCD */
-#define PARITY_EN_LCD_EN                 (* (reg8 *) PARITY_EN__LCD_EN)
-/* Slew Rate Control */
-#define PARITY_EN_SLW                    (* (reg8 *) PARITY_EN__SLW)
-
-/* DSI Port Registers */
-/* Global DSI Select Register */
-#define PARITY_EN_PRTDSI__CAPS_SEL       (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL) 
-/* Double Sync Enable */
-#define PARITY_EN_PRTDSI__DBL_SYNC_IN    (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN) 
-/* Output Enable Select Drive Strength */
-#define PARITY_EN_PRTDSI__OE_SEL0        (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0) 
-#define PARITY_EN_PRTDSI__OE_SEL1        (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1) 
-/* Port Pin Output Select Registers */
-#define PARITY_EN_PRTDSI__OUT_SEL0       (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0) 
-#define PARITY_EN_PRTDSI__OUT_SEL1       (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1) 
-/* Sync Output Enable Registers */
-#define PARITY_EN_PRTDSI__SYNC_OUT       (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT) 
-
-
-#if defined(PARITY_EN__INTSTAT)  /* Interrupt Registers */
-
-    #define PARITY_EN_INTSTAT                (* (reg8 *) PARITY_EN__INTSTAT)
-    #define PARITY_EN_SNAP                   (* (reg8 *) PARITY_EN__SNAP)
-
-#endif /* Interrupt Registers */
-
-#endif /* CY_PSOC5A... */
-
-#endif /*  CY_PINS_PARITY_EN_H */
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c

@@ -0,0 +1,63 @@
+/*******************************************************************************
+* File Name: SCSI_CTL_IO.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_IO.h"
+
+#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_IO_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_CTL_IO_Write(uint8 control) 
+{
+    SCSI_CTL_IO_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_IO_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_CTL_IO_Read(void) 
+{
+    return SCSI_CTL_IO_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/PARITY_EN_aliases.h → lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
-* File Name: PARITY_EN.h  
-* Version 1.90
+* File Name: SCSI_CTL_IO.h  
+* Version 1.70
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -14,19 +14,29 @@
 * the software package with which this file was provided.
 *******************************************************************************/
 
-#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */
-#define CY_PINS_PARITY_EN_ALIASES_H
+#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */
+#define CY_CONTROL_REG_SCSI_CTL_IO_H
 
 #include "cytypes.h"
-#include "cyfitter.h"
 
 
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_CTL_IO_Write(uint8 control) ;
+uint8   SCSI_CTL_IO_Read(void) ;
+
 
 /***************************************
-*              Constants        
+*            Registers        
 ***************************************/
-#define PARITY_EN_0		PARITY_EN__0__PC
 
-#endif /* End Pins PARITY_EN_ALIASES_H */
+/* Control Register */
+#define SCSI_CTL_IO_Control        (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_CTL_IO_Control_PTR    (  (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */
+
 
 /* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ID_aliases.h

@@ -1,34 +0,0 @@
-/*******************************************************************************
-* File Name: SCSI_ID.h  
-* Version 1.90
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */
-#define CY_PINS_SCSI_ID_ALIASES_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-
-
-
-/***************************************
-*              Constants        
-***************************************/
-#define SCSI_ID_0		SCSI_ID__0__PC
-#define SCSI_ID_1		SCSI_ID__1__PC
-#define SCSI_ID_2		SCSI_ID__2__PC
-
-#endif /* End Pins SCSI_ID_ALIASES_H */
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h

@@ -36,7 +36,7 @@
 #define SCSI_Out_8		SCSI_Out__8__PC
 #define SCSI_Out_9		SCSI_Out__9__PC
 
-#define SCSI_Out_DBP		SCSI_Out__DBP__PC
+#define SCSI_Out_DBP_raw		SCSI_Out__DBP_raw__PC
 #define SCSI_Out_ATN		SCSI_Out__ATN__PC
 #define SCSI_Out_BSY		SCSI_Out__BSY__PC
 #define SCSI_Out_ACK		SCSI_Out__ACK__PC
@@ -45,7 +45,7 @@
 #define SCSI_Out_SEL		SCSI_Out__SEL__PC
 #define SCSI_Out_CD		SCSI_Out__CD__PC
 #define SCSI_Out_REQ		SCSI_Out__REQ__PC
-#define SCSI_Out_IO		SCSI_Out__IO__PC
+#define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
 
 #endif /* End Pins SCSI_Out_ALIASES_H */
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.c

@@ -1,1155 +0,0 @@
-/*******************************************************************************
-* File Name: SD.c
-* Version 2.40
-*
-* Description:
-*  This file provides all API functionality of the SPI Master component.
-*
-* Note:
-*  None.
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SD_PVT.h"
-
-#if(SD_TX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE] = {0u};
-    volatile uint8 SD_txBufferFull;
-    volatile uint8 SD_txBufferRead;
-    volatile uint8 SD_txBufferWrite;
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-#if(SD_RX_SOFTWARE_BUF_ENABLED)
-    volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE] = {0u};
-    volatile uint8 SD_rxBufferFull;
-    volatile uint8 SD_rxBufferRead;
-    volatile uint8 SD_rxBufferWrite;
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-uint8 SD_initVar = 0u;
-
-volatile uint8 SD_swStatusTx;
-volatile uint8 SD_swStatusRx;
-
-
-/*******************************************************************************
-* Function Name: SD_Init
-********************************************************************************
-*
-* Summary:
-*  Inits/Restores default SPIM configuration provided with customizer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  When this function is called it initializes all of the necessary parameters
-*  for execution. i.e. setting the initial interrupt mask, configuring the
-*  interrupt service routine, configuring the bit-counter parameters and
-*  clearing the FIFO and Status Register.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_Init(void) 
-{
-    /* Initialize the Bit counter */
-    SD_COUNTER_PERIOD_REG = SD_BITCTR_INIT;
-
-    /* Init TX ISR  */
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)
-        CyIntDisable         (SD_TX_ISR_NUMBER);
-        CyIntSetPriority     (SD_TX_ISR_NUMBER,  SD_TX_ISR_PRIORITY);
-        (void) CyIntSetVector(SD_TX_ISR_NUMBER, &SD_TX_ISR);
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */
-
-    /* Init RX ISR  */
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)
-        CyIntDisable         (SD_RX_ISR_NUMBER);
-        CyIntSetPriority     (SD_RX_ISR_NUMBER,  SD_RX_ISR_PRIORITY);
-        (void) CyIntSetVector(SD_RX_ISR_NUMBER, &SD_RX_ISR);
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */
-
-    /* Clear any stray data from the RX and TX FIFO */
-    SD_ClearFIFO();
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-        SD_rxBufferFull  = 0u;
-        SD_rxBufferRead  = 0u;
-        SD_rxBufferWrite = 0u;
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        SD_txBufferFull  = 0u;
-        SD_txBufferRead  = 0u;
-        SD_txBufferWrite = 0u;
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    (void) SD_ReadTxStatus(); /* Clear Tx status and swStatusTx */
-    (void) SD_ReadRxStatus(); /* Clear Rx status and swStatusRx */
-
-    /* Configure TX and RX interrupt mask */
-    SD_TX_STATUS_MASK_REG = SD_TX_INIT_INTERRUPTS_MASK;
-    SD_RX_STATUS_MASK_REG = SD_RX_INIT_INTERRUPTS_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Enable
-********************************************************************************
-*
-* Summary:
-*  Enable SPIM component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SD_Enable(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    SD_COUNTER_CONTROL_REG |= SD_CNTR_ENABLE;
-    SD_TX_STATUS_ACTL_REG  |= SD_INT_ENABLE;
-    SD_RX_STATUS_ACTL_REG  |= SD_INT_ENABLE;
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(0u != SD_INTERNAL_CLOCK)
-        SD_IntClock_Enable();
-    #endif /* (0u != SD_INTERNAL_CLOCK) */
-
-    SD_EnableTxInt();
-    SD_EnableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Start
-********************************************************************************
-*
-* Summary:
-*  Initialize and Enable the SPI Master component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_initVar - used to check initial configuration, modified on
-*  first function call.
-*
-* Theory:
-*  Enable the clock input to enable operation.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_Start(void) 
-{
-    if(0u == SD_initVar)
-    {
-        SD_Init();
-        SD_initVar = 1u;
-    }
-
-    SD_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Stop
-********************************************************************************
-*
-* Summary:
-*  Disable the SPI Master component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the clock input to enable operation.
-*
-*******************************************************************************/
-void SD_Stop(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    SD_TX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);
-    SD_RX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(0u != SD_INTERNAL_CLOCK)
-        SD_IntClock_Disable();
-    #endif /* (0u != SD_INTERNAL_CLOCK) */
-
-    SD_DisableTxInt();
-    SD_DisableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_EnableTxInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal Tx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal Tx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_EnableTxInt(void) 
-{
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)
-        CyIntEnable(SD_TX_ISR_NUMBER);
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_EnableRxInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal Rx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal Rx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_EnableRxInt(void) 
-{
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)
-        CyIntEnable(SD_RX_ISR_NUMBER);
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_DisableTxInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal Tx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal Tx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_DisableTxInt(void) 
-{
-    #if(0u != SD_INTERNAL_TX_INT_ENABLED)
-        CyIntDisable(SD_TX_ISR_NUMBER);
-    #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_DisableRxInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal Rx interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal Rx interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_DisableRxInt(void) 
-{
-    #if(0u != SD_INTERNAL_RX_INT_ENABLED)
-        CyIntDisable(SD_RX_ISR_NUMBER);
-    #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SetTxInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SD_SetTxInterruptMode(uint8 intSrc) 
-{
-    SD_TX_STATUS_MASK_REG = intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SetRxInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SD_SetRxInterruptMode(uint8 intSrc) 
-{
-    SD_RX_STATUS_MASK_REG  = intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ReadTxStatus
-********************************************************************************
-*
-* Summary:
-*  Read the Tx status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the Tx status register.
-*
-* Global variables:
-*  SD_swStatusTx - used to store in software status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the Tx status register for error
-*  detection and flow control.
-*
-* Side Effects:
-*  Clear Tx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SD_ReadTxStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SD_DisableTxInt();
-
-        tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);
-        SD_swStatusTx = 0u;
-
-        SD_EnableTxInt();
-
-    #else
-
-        tmpStatus = SD_TX_STATUS_REG;
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ReadRxStatus
-********************************************************************************
-*
-* Summary:
-*  Read the Rx status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the Rx status register.
-*
-* Global variables:
-*  SD_swStatusRx - used to store in software Rx status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the Rx status register for error
-*  detection and flow control.
-*
-* Side Effects:
-*  Clear Rx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SD_ReadRxStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-        /* Disable RX interrupt to protect global veriables */
-        SD_DisableRxInt();
-
-        tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);
-        SD_swStatusRx = 0u;
-
-        SD_EnableRxInt();
-
-    #else
-
-        tmpStatus = SD_RX_STATUS_REG;
-
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_WriteTxData
-********************************************************************************
-*
-* Summary:
-*  Write a byte of data to be sent across the SPI.
-*
-* Parameters:
-*  txDataByte: The data value to send across the SPI.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer, modified every function
-*  call if TX Software Buffer is used.
-*  SD_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer.
-*  SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store
-*  data to sending, modified every function call if TX Software Buffer is used.
-*
-* Theory:
-*  Allows the user to transmit any byte of data in a single transfer.
-*
-* Side Effects:
-*  If this function is called again before the previous byte is finished then
-*  the next byte will be appended to the transfer with no time between
-*  the byte transfers. Clear Tx status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_WriteTxData(uint8 txData) 
-{
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-
-        uint8 tempStatus;
-        uint8 tmpTxBufferRead;
-
-        /* Block if TX buffer is FULL: don't overwrite */
-        do
-        {
-            tmpTxBufferRead = SD_txBufferRead;
-            if(0u == tmpTxBufferRead)
-            {
-                tmpTxBufferRead = (SD_TX_BUFFER_SIZE - 1u);
-            }
-            else
-            {
-                tmpTxBufferRead--;
-            }
-
-        }while(tmpTxBufferRead == SD_txBufferWrite);
-
-        /* Disable TX interrupt to protect global veriables */
-        SD_DisableTxInt();
-
-        tempStatus = SD_GET_STATUS_TX(SD_swStatusTx);
-        SD_swStatusTx = tempStatus;
-
-
-        if((SD_txBufferRead == SD_txBufferWrite) &&
-           (0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL)))
-        {
-            /* Add directly to the TX FIFO */
-            CY_SET_REG8(SD_TXDATA_PTR, txData);
-        }
-        else
-        {
-            /* Add to the TX software buffer */
-            SD_txBufferWrite++;
-            if(SD_txBufferWrite >= SD_TX_BUFFER_SIZE)
-            {
-                SD_txBufferWrite = 0u;
-            }
-
-            if(SD_txBufferWrite == SD_txBufferRead)
-            {
-                SD_txBufferRead++;
-                if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)
-                {
-                    SD_txBufferRead = 0u;
-                }
-                SD_txBufferFull = 1u;
-            }
-
-            SD_txBuffer[SD_txBufferWrite] = txData;
-
-            SD_TX_STATUS_MASK_REG |= SD_STS_TX_FIFO_NOT_FULL;
-        }
-
-        SD_EnableTxInt();
-
-    #else
-
-        while(0u == (SD_TX_STATUS_REG & SD_STS_TX_FIFO_NOT_FULL))
-        {
-            ; /* Wait for room in FIFO */
-        }
-
-        /* Put byte in TX FIFO */
-        CY_SET_REG8(SD_TXDATA_PTR, txData);
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ReadRxData
-********************************************************************************
-*
-* Summary:
-*  Read the next byte of data received across the SPI.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  The next byte of data read from the FIFO.
-*
-* Global variables:
-*  SD_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer.
-*  SD_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified every function
-*  call if RX Software Buffer is used.
-*  SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store
-*  received data.
-*
-* Theory:
-*  Allows the user to read a byte of data received.
-*
-* Side Effects:
-*  Will return invalid data if the FIFO is empty. The user should Call
-*  GetRxBufferSize() and if it returns a non-zero value then it is safe to call
-*  ReadByte() function.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SD_ReadRxData(void) 
-{
-    uint8 rxData;
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-
-        /* Disable RX interrupt to protect global veriables */
-        SD_DisableRxInt();
-
-        if(SD_rxBufferRead != SD_rxBufferWrite)
-        {
-            if(0u == SD_rxBufferFull)
-            {
-                SD_rxBufferRead++;
-                if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)
-                {
-                    SD_rxBufferRead = 0u;
-                }
-            }
-            else
-            {
-                SD_rxBufferFull = 0u;
-            }
-        }
-
-        rxData = SD_rxBuffer[SD_rxBufferRead];
-
-        SD_EnableRxInt();
-
-    #else
-
-        rxData = CY_GET_REG8(SD_RXDATA_PTR);
-
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(rxData);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_GetRxBufferSize
-********************************************************************************
-*
-* Summary:
-*  Returns the number of bytes/words of data currently held in the RX buffer.
-*  If RX Software Buffer not used then function return 0 if FIFO empty or 1 if
-*  FIFO not empty. In another case function return size of RX Software Buffer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Integer count of the number of bytes/words in the RX buffer.
-*
-* Global variables:
-*  SD_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer.
-*  SD_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-uint8 SD_GetRxBufferSize(void) 
-{
-    uint8 size;
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-
-        /* Disable RX interrupt to protect global veriables */
-        SD_DisableRxInt();
-
-        if(SD_rxBufferRead == SD_rxBufferWrite)
-        {
-            size = 0u;
-        }
-        else if(SD_rxBufferRead < SD_rxBufferWrite)
-        {
-            size = (SD_rxBufferWrite - SD_rxBufferRead);
-        }
-        else
-        {
-            size = (SD_RX_BUFFER_SIZE - SD_rxBufferRead) + SD_rxBufferWrite;
-        }
-
-        SD_EnableRxInt();
-
-    #else
-
-        /* We can only know if there is data in the RX FIFO */
-        size = (0u != (SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(size);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_GetTxBufferSize
-********************************************************************************
-*
-* Summary:
-*  Returns the number of bytes/words of data currently held in the TX buffer.
-*  If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if
-*  FIFO not full, 4 - if FIFO full. In another case function return size of TX
-*  Software Buffer.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Integer count of the number of bytes/words in the TX buffer.
-*
-* Global variables:
-*  SD_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer.
-*  SD_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-uint8  SD_GetTxBufferSize(void) 
-{
-    uint8 size;
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SD_DisableTxInt();
-
-        if(SD_txBufferRead == SD_txBufferWrite)
-        {
-            size = 0u;
-        }
-        else if(SD_txBufferRead < SD_txBufferWrite)
-        {
-            size = (SD_txBufferWrite - SD_txBufferRead);
-        }
-        else
-        {
-            size = (SD_TX_BUFFER_SIZE - SD_txBufferRead) + SD_txBufferWrite;
-        }
-
-        SD_EnableTxInt();
-
-    #else
-
-        size = SD_TX_STATUS_REG;
-
-        if(0u != (size & SD_STS_TX_FIFO_EMPTY))
-        {
-            size = 0u;
-        }
-        else if(0u != (size & SD_STS_TX_FIFO_NOT_FULL))
-        {
-            size = 1u;
-        }
-        else
-        {
-            size = SD_FIFO_SIZE;
-        }
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    return(size);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ClearRxBuffer
-********************************************************************************
-*
-* Summary:
-*  Clear the RX RAM buffer by setting the read and write pointers both to zero.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer, modified every function
-*  call - resets to zero.
-*  SD_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified every function call -
-*  resets to zero.
-*
-* Theory:
-*  Setting the pointers to zero makes the system believe there is no data to
-*  read and writing will resume at address 0 overwriting any data that may have
-*  remained in the RAM.
-*
-* Side Effects:
-*  Any received data not read from the RAM buffer will be lost when overwritten.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_ClearRxBuffer(void) 
-{
-    /* Clear Hardware RX FIFO */
-    while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))
-    {
-        (void) CY_GET_REG8(SD_RXDATA_PTR);
-    }
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-        /* Disable RX interrupt to protect global veriables */
-        SD_DisableRxInt();
-
-        SD_rxBufferFull  = 0u;
-        SD_rxBufferRead  = 0u;
-        SD_rxBufferWrite = 0u;
-
-        SD_EnableRxInt();
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ClearTxBuffer
-********************************************************************************
-*
-* Summary:
-*  Clear the TX RAM buffer by setting the read and write pointers both to zero.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer, modified every function
-*  call - resets to zero.
-*  SD_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer, modified every function call -
-*  resets to zero.
-*
-* Theory:
-*  Setting the pointers to zero makes the system believe there is no data to
-*  read and writing will resume at address 0 overwriting any data that may have
-*  remained in the RAM.
-*
-* Side Effects:
-*  Any data not yet transmitted from the RAM buffer will be lost when
-*  overwritten.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_ClearTxBuffer(void) 
-{
-    uint8 enableInterrupts;
-
-    enableInterrupts = CyEnterCriticalSection();
-    /* Clear TX FIFO */
-    SD_AUX_CONTROL_DP0_REG |= ((uint8)  SD_TX_FIFO_CLR);
-    SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);
-
-    #if(SD_USE_SECOND_DATAPATH)
-        /* Clear TX FIFO for 2nd Datapath */
-        SD_AUX_CONTROL_DP1_REG |= ((uint8)  SD_TX_FIFO_CLR);
-        SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);
-    #endif /* (SD_USE_SECOND_DATAPATH) */
-    CyExitCriticalSection(enableInterrupts);
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        /* Disable TX interrupt to protect global veriables */
-        SD_DisableTxInt();
-
-        SD_txBufferFull  = 0u;
-        SD_txBufferRead  = 0u;
-        SD_txBufferWrite = 0u;
-
-        /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */
-        SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);
-
-        SD_EnableTxInt();
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-}
-
-
-#if(0u != SD_BIDIRECTIONAL_MODE)
-    /*******************************************************************************
-    * Function Name: SD_TxEnable
-    ********************************************************************************
-    *
-    * Summary:
-    *  If the SPI master is configured to use a single bi-directional pin then this
-    *  will set the bi-directional pin to transmit.
-    *
-    * Parameters:
-    *  None.
-    *
-    * Return:
-    *  None.
-    *
-    *******************************************************************************/
-    void SD_TxEnable(void) 
-    {
-        SD_CONTROL_REG |= SD_CTRL_TX_SIGNAL_EN;
-    }
-
-
-    /*******************************************************************************
-    * Function Name: SD_TxDisable
-    ********************************************************************************
-    *
-    * Summary:
-    *  If the SPI master is configured to use a single bi-directional pin then this
-    *  will set the bi-directional pin to receive.
-    *
-    * Parameters:
-    *  None.
-    *
-    * Return:
-    *  None.
-    *
-    *******************************************************************************/
-    void SD_TxDisable(void) 
-    {
-        SD_CONTROL_REG &= ((uint8) ~SD_CTRL_TX_SIGNAL_EN);
-    }
-
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */
-
-
-/*******************************************************************************
-* Function Name: SD_PutArray
-********************************************************************************
-*
-* Summary:
-*  Write available data from ROM/RAM to the TX buffer while space is available
-*  in the TX buffer. Keep trying until all data is passed to the TX buffer.
-*
-* Parameters:
-*  *buffer: Pointer to the location in RAM containing the data to send
-*  byteCount: The number of bytes to move to the transmit buffer.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  Will stay in this routine until all data has been sent.  May get locked in
-*  this loop if data is not being initiated by the master if there is not
-*  enough room in the TX FIFO.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_PutArray(const uint8 buffer[], uint8 byteCount)
-                                                                          
-{
-    uint8 bufIndex;
-
-    bufIndex = 0u;
-
-    while(byteCount > 0u)
-    {
-        SD_WriteTxData(buffer[bufIndex]);
-        bufIndex++;
-        byteCount--;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ClearFIFO
-********************************************************************************
-*
-* Summary:
-*  Clear the RX and TX FIFO's of all data for a fresh start.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-*******************************************************************************/
-void SD_ClearFIFO(void) 
-{
-    uint8 enableInterrupts;
-
-    /* Clear Hardware RX FIFO */
-    while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))
-    {
-        (void) CY_GET_REG8(SD_RXDATA_PTR);
-    }
-
-    enableInterrupts = CyEnterCriticalSection();
-    /* Clear TX FIFO */
-    SD_AUX_CONTROL_DP0_REG |= ((uint8)  SD_TX_FIFO_CLR);
-    SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);
-
-    #if(SD_USE_SECOND_DATAPATH)
-        /* Clear TX FIFO for 2nd Datapath */
-        SD_AUX_CONTROL_DP1_REG |= ((uint8)  SD_TX_FIFO_CLR);
-        SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);
-    #endif /* (SD_USE_SECOND_DATAPATH) */
-    CyExitCriticalSection(enableInterrupts);
-}
-
-
-/* Following functions are for version Compatibility, they are obsolete.
-*  Please do not use it in new projects.
-*/
-
-
-/*******************************************************************************
-* Function Name: SD_EnableInt
-********************************************************************************
-*
-* Summary:
-*  Enable internal interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enable the internal interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_EnableInt(void) 
-{
-    SD_EnableRxInt();
-    SD_EnableTxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_DisableInt
-********************************************************************************
-*
-* Summary:
-*  Disable internal interrupt generation.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Disable the internal interrupt output -or- the interrupt component itself.
-*
-*******************************************************************************/
-void SD_DisableInt(void) 
-{
-    SD_DisableTxInt();
-    SD_DisableRxInt();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_SetInterruptMode
-********************************************************************************
-*
-* Summary:
-*  Configure which status bits trigger an interrupt event.
-*
-* Parameters:
-*  intSrc: An or'd combination of the desired status bit masks (defined in the
-*  header file).
-*
-* Return:
-*  None.
-*
-* Theory:
-*  Enables the output of specific status bits to the interrupt controller.
-*
-*******************************************************************************/
-void SD_SetInterruptMode(uint8 intSrc) 
-{
-    SD_TX_STATUS_MASK_REG  = (intSrc & ((uint8) ~SD_STS_SPI_IDLE));
-    SD_RX_STATUS_MASK_REG  =  intSrc;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_ReadStatus
-********************************************************************************
-*
-* Summary:
-*  Read the status register for the component.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Contents of the status register.
-*
-* Global variables:
-*  SD_swStatus - used to store in software status register,
-*  modified every function call - resets to zero.
-*
-* Theory:
-*  Allows the user and the API to read the status register for error detection
-*  and flow control.
-*
-* Side Effects:
-*  Clear status register of the component.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-uint8 SD_ReadStatus(void) 
-{
-    uint8 tmpStatus;
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED)
-
-        SD_DisableInt();
-
-        tmpStatus  = SD_GET_STATUS_RX(SD_swStatusRx);
-        tmpStatus |= SD_GET_STATUS_TX(SD_swStatusTx);
-        tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);
-
-        SD_swStatusTx = 0u;
-        SD_swStatusRx = 0u;
-
-        SD_EnableInt();
-
-    #else
-
-        tmpStatus  = SD_RX_STATUS_REG;
-        tmpStatus |= SD_TX_STATUS_REG;
-        tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    return(tmpStatus);
-}
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD.h

@@ -1,389 +0,0 @@
-/*******************************************************************************
-* File Name: SD.h
-* Version 2.40
-*
-* Description:
-*  Contains the function prototypes, constants and register definition
-*  of the SPI Master Component.
-*
-* Note:
-*  None
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_SPIM_SD_H)
-#define CY_SPIM_SD_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h"
-
-/* Check to see if required defines such as CY_PSOC5A are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5A)
-    #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5A) */
-
-
-/***************************************
-*   Conditional Compilation Parameters
-***************************************/
-
-#define SD_INTERNAL_CLOCK             (0u)
-
-#if(0u != SD_INTERNAL_CLOCK)
-    #include "SD_IntClock.h"
-#endif /* (0u != SD_INTERNAL_CLOCK) */
-
-#define SD_MODE                       (1u)
-#define SD_DATA_WIDTH                 (8u)
-#define SD_MODE_USE_ZERO              (1u)
-#define SD_BIDIRECTIONAL_MODE         (0u)
-
-/* Internal interrupt handling */
-#define SD_TX_BUFFER_SIZE             (4u)
-#define SD_RX_BUFFER_SIZE             (4u)
-#define SD_INTERNAL_TX_INT_ENABLED    (0u)
-#define SD_INTERNAL_RX_INT_ENABLED    (0u)
-
-#define SD_SINGLE_REG_SIZE            (8u)
-#define SD_USE_SECOND_DATAPATH        (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)
-
-#define SD_FIFO_SIZE                  (4u)
-#define SD_TX_SOFTWARE_BUF_ENABLED    ((0u != SD_INTERNAL_TX_INT_ENABLED) && \
-                                                     (SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))
-
-#define SD_RX_SOFTWARE_BUF_ENABLED    ((0u != SD_INTERNAL_RX_INT_ENABLED) && \
-                                                     (SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))
-
-
-/***************************************
-*        Data Struct Definition
-***************************************/
-
-/* Sleep Mode API Support */
-typedef struct
-{
-    uint8 enableState;
-    uint8 cntrPeriod;
-    #if(CY_UDB_V0)
-        uint8 saveSrTxIntMask;
-        uint8 saveSrRxIntMask;
-    #endif /* (CY_UDB_V0) */
-
-} SD_BACKUP_STRUCT;
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void  SD_Init(void)                           ;
-void  SD_Enable(void)                         ;
-void  SD_Start(void)                          ;
-void  SD_Stop(void)                           ;
-
-void  SD_EnableTxInt(void)                    ;
-void  SD_EnableRxInt(void)                    ;
-void  SD_DisableTxInt(void)                   ;
-void  SD_DisableRxInt(void)                   ;
-
-void  SD_Sleep(void)                          ;
-void  SD_Wakeup(void)                         ;
-void  SD_SaveConfig(void)                     ;
-void  SD_RestoreConfig(void)                  ;
-
-void  SD_SetTxInterruptMode(uint8 intSrc)     ;
-void  SD_SetRxInterruptMode(uint8 intSrc)     ;
-uint8 SD_ReadTxStatus(void)                   ;
-uint8 SD_ReadRxStatus(void)                   ;
-void  SD_WriteTxData(uint8 txData)  \
-                                                            ;
-uint8 SD_ReadRxData(void) \
-                                                            ;
-uint8 SD_GetRxBufferSize(void)                ;
-uint8 SD_GetTxBufferSize(void)                ;
-void  SD_ClearRxBuffer(void)                  ;
-void  SD_ClearTxBuffer(void)                  ;
-void  SD_ClearFIFO(void)                              ;
-void  SD_PutArray(const uint8 buffer[], uint8 byteCount) \
-                                                            ;
-
-#if(0u != SD_BIDIRECTIONAL_MODE)
-    void  SD_TxEnable(void)                   ;
-    void  SD_TxDisable(void)                  ;
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */
-
-CY_ISR_PROTO(SD_TX_ISR);
-CY_ISR_PROTO(SD_RX_ISR);
-
-
-/**********************************
-*   Variable with external linkage
-**********************************/
-
-extern uint8 SD_initVar;
-
-
-/***************************************
-*           API Constants
-***************************************/
-
-#define SD_TX_ISR_NUMBER     ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))
-#define SD_RX_ISR_NUMBER     ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))
-
-#define SD_TX_ISR_PRIORITY   ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))
-#define SD_RX_ISR_PRIORITY   ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))
-
-
-/***************************************
-*    Initial Parameter Constants
-***************************************/
-
-#define SD_INT_ON_SPI_DONE    ((uint8) (0u   << SD_STS_SPI_DONE_SHIFT))
-#define SD_INT_ON_TX_EMPTY    ((uint8) (0u   << SD_STS_TX_FIFO_EMPTY_SHIFT))
-#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \
-                                                                           SD_STS_TX_FIFO_NOT_FULL_SHIFT))
-#define SD_INT_ON_BYTE_COMP   ((uint8) (0u  << SD_STS_BYTE_COMPLETE_SHIFT))
-#define SD_INT_ON_SPI_IDLE    ((uint8) (0u   << SD_STS_SPI_IDLE_SHIFT))
-
-/* Disable TX_NOT_FULL if software buffer is used */
-#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \
-                                                                        (0u) : (SD_INT_ON_TX_NOT_FULL))
-
-/* TX interrupt mask */
-#define SD_TX_INIT_INTERRUPTS_MASK    (SD_INT_ON_SPI_DONE  | \
-                                                     SD_INT_ON_TX_EMPTY  | \
-                                                     SD_INT_ON_TX_NOT_FULL_DEF | \
-                                                     SD_INT_ON_BYTE_COMP | \
-                                                     SD_INT_ON_SPI_IDLE)
-
-#define SD_INT_ON_RX_FULL         ((uint8) (0u << \
-                                                                          SD_STS_RX_FIFO_FULL_SHIFT))
-#define SD_INT_ON_RX_NOT_EMPTY    ((uint8) (0u << \
-                                                                          SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
-#define SD_INT_ON_RX_OVER         ((uint8) (0u << \
-                                                                          SD_STS_RX_FIFO_OVERRUN_SHIFT))
-
-/* RX interrupt mask */
-#define SD_RX_INIT_INTERRUPTS_MASK    (SD_INT_ON_RX_FULL      | \
-                                                     SD_INT_ON_RX_NOT_EMPTY | \
-                                                     SD_INT_ON_RX_OVER)
-/* Nubmer of bits to receive/transmit */
-#define SD_BITCTR_INIT            (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)
-
-
-/***************************************
-*             Registers
-***************************************/
-
-#if(CY_PSOC3 || CY_PSOC5)
-    #define SD_TXDATA_REG (* (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)
-    #define SD_TXDATA_PTR (  (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)
-    #define SD_RXDATA_REG (* (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)
-    #define SD_RXDATA_PTR (  (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)
-#else   /* PSOC4 */
-    #if(SD_USE_SECOND_DATAPATH)
-        #define SD_TXDATA_REG (* (reg16 *) \
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
-        #define SD_TXDATA_PTR (  (reg16 *) \
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
-        #define SD_RXDATA_REG (* (reg16 *) \
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
-        #define SD_RXDATA_PTR         (  (reg16 *) \
-                                          SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
-    #else
-        #define SD_TXDATA_REG (* (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)
-        #define SD_TXDATA_PTR (  (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F0_REG)
-        #define SD_RXDATA_REG (* (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)
-        #define SD_RXDATA_PTR (  (reg8 *) \
-                                                SD_BSPIM_sR8_Dp_u0__F1_REG)
-    #endif /* (SD_USE_SECOND_DATAPATH) */
-#endif     /* (CY_PSOC3 || CY_PSOC5) */
-
-#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \
-                                        SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
-#define SD_AUX_CONTROL_DP0_PTR (  (reg8 *) \
-                                        SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
-
-#if(SD_USE_SECOND_DATAPATH)
-    #define SD_AUX_CONTROL_DP1_REG  (* (reg8 *) \
-                                        SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
-    #define SD_AUX_CONTROL_DP1_PTR  (  (reg8 *) \
-                                        SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
-#endif /* (SD_USE_SECOND_DATAPATH) */
-
-#define SD_COUNTER_PERIOD_REG     (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
-#define SD_COUNTER_PERIOD_PTR     (  (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
-#define SD_COUNTER_CONTROL_REG    (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
-#define SD_COUNTER_CONTROL_PTR    (  (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
-
-#define SD_TX_STATUS_REG          (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
-#define SD_TX_STATUS_PTR          (  (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
-#define SD_RX_STATUS_REG          (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
-#define SD_RX_STATUS_PTR          (  (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
-
-#define SD_CONTROL_REG            (* (reg8 *) \
-                                      SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
-#define SD_CONTROL_PTR            (  (reg8 *) \
-                                      SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
-
-#define SD_TX_STATUS_MASK_REG     (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
-#define SD_TX_STATUS_MASK_PTR     (  (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
-#define SD_RX_STATUS_MASK_REG     (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
-#define SD_RX_STATUS_MASK_PTR     (  (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
-
-#define SD_TX_STATUS_ACTL_REG     (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
-#define SD_TX_STATUS_ACTL_PTR     (  (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
-#define SD_RX_STATUS_ACTL_REG     (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
-#define SD_RX_STATUS_ACTL_PTR     (  (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
-
-#if(SD_USE_SECOND_DATAPATH)
-    #define SD_AUX_CONTROLDP1     (SD_AUX_CONTROL_DP1_REG)
-#endif /* (SD_USE_SECOND_DATAPATH) */
-
-
-/***************************************
-*       Register Constants
-***************************************/
-
-/* Status Register Definitions */
-#define SD_STS_SPI_DONE_SHIFT             (0x00u)
-#define SD_STS_TX_FIFO_EMPTY_SHIFT        (0x01u)
-#define SD_STS_TX_FIFO_NOT_FULL_SHIFT     (0x02u)
-#define SD_STS_BYTE_COMPLETE_SHIFT        (0x03u)
-#define SD_STS_SPI_IDLE_SHIFT             (0x04u)
-#define SD_STS_RX_FIFO_FULL_SHIFT         (0x04u)
-#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT    (0x05u)
-#define SD_STS_RX_FIFO_OVERRUN_SHIFT      (0x06u)
-
-#define SD_STS_SPI_DONE           ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))
-#define SD_STS_TX_FIFO_EMPTY      ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))
-#define SD_STS_TX_FIFO_NOT_FULL   ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))
-#define SD_STS_BYTE_COMPLETE      ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))
-#define SD_STS_SPI_IDLE           ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))
-#define SD_STS_RX_FIFO_FULL       ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))
-#define SD_STS_RX_FIFO_NOT_EMPTY  ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
-#define SD_STS_RX_FIFO_OVERRUN    ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))
-
-/* TX and RX masks for clear on read bits */
-#define SD_TX_STS_CLR_ON_RD_BYTES_MASK    (0x09u)
-#define SD_RX_STS_CLR_ON_RD_BYTES_MASK    (0x40u)
-
-/* StatusI Register Interrupt Enable Control Bits */
-/* As defined by the Register map for the AUX Control Register */
-#define SD_INT_ENABLE     (0x10u) /* Enable interrupt from statusi */
-#define SD_TX_FIFO_CLR    (0x01u) /* F0 - TX FIFO */
-#define SD_RX_FIFO_CLR    (0x02u) /* F1 - RX FIFO */
-#define SD_FIFO_CLR       (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)
-
-/* Bit Counter (7-bit) Control Register Bit Definitions */
-/* As defined by the Register map for the AUX Control Register */
-#define SD_CNTR_ENABLE    (0x20u) /* Enable CNT7 */
-
-/* Bi-Directional mode control bit */
-#define SD_CTRL_TX_SIGNAL_EN  (0x01u)
-
-/* Datapath Auxillary Control Register definitions */
-#define SD_AUX_CTRL_FIFO0_CLR         (0x01u)
-#define SD_AUX_CTRL_FIFO1_CLR         (0x02u)
-#define SD_AUX_CTRL_FIFO0_LVL         (0x04u)
-#define SD_AUX_CTRL_FIFO1_LVL         (0x08u)
-#define SD_STATUS_ACTL_INT_EN_MASK    (0x10u)
-
-/* Component disabled */
-#define SD_DISABLED   (0u)
-
-
-/***************************************
-*       Macros
-***************************************/
-
-/* Returns true if componentn enabled */
-#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))
-
-/* Retuns TX status register */
-#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \
-                                                          ((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )
-/* Retuns RX status register */
-#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \
-                                                          ((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )
-
-
-/***************************************
-*       Obsolete definitions
-***************************************/
-
-/* Following definitions are for version compatibility.
-*  They are obsolete in SPIM v2_30.
-*  Please do not use it in new projects
-*/
-
-#define SD_WriteByte   SD_WriteTxData
-#define SD_ReadByte    SD_ReadRxData
-void  SD_SetInterruptMode(uint8 intSrc)       ;
-uint8 SD_ReadStatus(void)                     ;
-void  SD_EnableInt(void)                      ;
-void  SD_DisableInt(void)                     ;
-
-/* Obsolete register names. Not to be used in new designs */
-#define SD_TXDATA                 (SD_TXDATA_REG)
-#define SD_RXDATA                 (SD_RXDATA_REG)
-#define SD_AUX_CONTROLDP0         (SD_AUX_CONTROL_DP0_REG)
-#define SD_TXBUFFERREAD           (SD_txBufferRead)
-#define SD_TXBUFFERWRITE          (SD_txBufferWrite)
-#define SD_RXBUFFERREAD           (SD_rxBufferRead)
-#define SD_RXBUFFERWRITE          (SD_rxBufferWrite)
-
-#define SD_COUNTER_PERIOD         (SD_COUNTER_PERIOD_REG)
-#define SD_COUNTER_CONTROL        (SD_COUNTER_CONTROL_REG)
-#define SD_STATUS                 (SD_TX_STATUS_REG)
-#define SD_CONTROL                (SD_CONTROL_REG)
-#define SD_STATUS_MASK            (SD_TX_STATUS_MASK_REG)
-#define SD_STATUS_ACTL            (SD_TX_STATUS_ACTL_REG)
-
-#define SD_INIT_INTERRUPTS_MASK  (SD_INT_ON_SPI_DONE     | \
-                                                SD_INT_ON_TX_EMPTY     | \
-                                                SD_INT_ON_TX_NOT_FULL_DEF  | \
-                                                SD_INT_ON_RX_FULL      | \
-                                                SD_INT_ON_RX_NOT_EMPTY | \
-                                                SD_INT_ON_RX_OVER      | \
-                                                SD_INT_ON_BYTE_COMP)
-                                                
-/* Following definitions are for version Compatibility.
-*  They are obsolete in SPIM v2_40.
-*  Please do not use it in new projects
-*/
-
-#define SD_DataWidth                  (SD_DATA_WIDTH)
-#define SD_InternalClockUsed          (SD_INTERNAL_CLOCK)
-#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)
-#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)
-#define SD_ModeUseZero                (SD_MODE_USE_ZERO)
-#define SD_BidirectionalMode          (SD_BIDIRECTIONAL_MODE)
-#define SD_Mode                       (SD_MODE)
-#define SD_DATAWIDHT                  (SD_DATA_WIDTH)
-#define SD_InternalInterruptEnabled   (0u)
-
-#define SD_TXBUFFERSIZE   (SD_TX_BUFFER_SIZE)
-#define SD_RXBUFFERSIZE   (SD_RX_BUFFER_SIZE)
-
-#define SD_TXBUFFER       SD_txBuffer
-#define SD_RXBUFFER       SD_rxBuffer
-
-#endif /* (CY_SPIM_SD_H) */
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_INT.c

@@ -1,189 +0,0 @@
-/*******************************************************************************
-* File Name: SD_INT.c
-* Version 2.40
-*
-* Description:
-*  This file provides all Interrupt Service Routine (ISR) for the SPI Master
-*  component.
-*
-* Note:
-*  None.
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SD_PVT.h"
-
-/* User code required at start of ISR */
-/* `#START SD_ISR_START_DEF` */
-
-/* `#END` */
-
-
-/*******************************************************************************
-* Function Name: SD_TX_ISR
-********************************************************************************
-*
-* Summary:
-*  Interrupt Service Routine for TX portion of the SPI Master.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_txBufferWrite - used for the account of the bytes which
-*  have been written down in the TX software buffer.
-*  SD_txBufferRead - used for the account of the bytes which
-*  have been read from the TX software buffer, modified when exist data to
-*  sending and FIFO Not Full.
-*  SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store
-*  data to sending.
-*  All described above Global variables are used when Software Buffer is used.
-*
-*******************************************************************************/
-CY_ISR(SD_TX_ISR)
-{
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        uint8 tmpStatus;
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at start of ISR */
-    /* `#START SD_TX_ISR_START` */
-
-    /* `#END` */
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        /* Check if TX data buffer is not empty and there is space in TX FIFO */
-        while(SD_txBufferRead != SD_txBufferWrite)
-        {
-            tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);
-            SD_swStatusTx = tmpStatus;
-
-            if(0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL))
-            {
-                if(0u == SD_txBufferFull)
-                {
-                   SD_txBufferRead++;
-
-                    if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)
-                    {
-                        SD_txBufferRead = 0u;
-                    }
-                }
-                else
-                {
-                    SD_txBufferFull = 0u;
-                }
-
-                /* Move data from the Buffer to the FIFO */
-                CY_SET_REG8(SD_TXDATA_PTR,
-                    SD_txBuffer[SD_txBufferRead]);
-            }
-            else
-            {
-                break;
-            }
-        }
-
-        if(SD_txBufferRead == SD_txBufferWrite)
-        {
-            /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */
-            SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);
-        }
-
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at end of ISR (Optional) */
-    /* `#START SD_TX_ISR_END` */
-
-    /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RX_ISR
-********************************************************************************
-*
-* Summary:
-*  Interrupt Service Routine for RX portion of the SPI Master.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global variables:
-*  SD_rxBufferWrite - used for the account of the bytes which
-*  have been written down in the RX software buffer modified when FIFO contains
-*  new data.
-*  SD_rxBufferRead - used for the account of the bytes which
-*  have been read from the RX software buffer, modified when overflow occurred.
-*  SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store
-*  received data, modified when FIFO contains new data.
-*  All described above Global variables are used when Software Buffer is used.
-*
-*******************************************************************************/
-CY_ISR(SD_RX_ISR)
-{
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-        uint8 tmpStatus;
-        uint8 rxData;
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at start of ISR */
-    /* `#START SD_RX_ISR_START` */
-
-    /* `#END` */
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-
-        tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);
-        SD_swStatusRx = tmpStatus;
-
-        /* Check if RX data FIFO has some data to be moved into the RX Buffer */
-        while(0u != (SD_swStatusRx & SD_STS_RX_FIFO_NOT_EMPTY))
-        {
-            rxData = CY_GET_REG8(SD_RXDATA_PTR);
-
-            /* Set next pointer. */
-            SD_rxBufferWrite++;
-            if(SD_rxBufferWrite >= SD_RX_BUFFER_SIZE)
-            {
-                SD_rxBufferWrite = 0u;
-            }
-
-            if(SD_rxBufferWrite == SD_rxBufferRead)
-            {
-                SD_rxBufferRead++;
-                if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)
-                {
-                    SD_rxBufferRead = 0u;
-                }
-
-                SD_rxBufferFull = 1u;
-            }
-
-            /* Move data from the FIFO to the Buffer */
-            SD_rxBuffer[SD_rxBufferWrite] = rxData;
-
-            tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);
-            SD_swStatusRx = tmpStatus;
-        }
-
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    /* User code required at end of ISR (Optional) */
-    /* `#START SD_RX_ISR_END` */
-
-    /* `#END` */
-}
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.c

@@ -1,521 +0,0 @@
-/*******************************************************************************
-* File Name: SD_IntClock.c
-* Version 2.0
-*
-*  Description:
-*   This file provides the source code to the API for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include <cydevice_trm.h>
-#include "SD_IntClock.h"
-
-/* Clock Distribution registers. */
-#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
-#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
-#define BCFG2_MASK               (0x80u)
-#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
-#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
-
-#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_Start
-********************************************************************************
-*
-* Summary:
-*  Starts the clock. Note that on startup, clocks may be already running if the
-*  "Start on Reset" option is enabled in the DWR.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_Start(void) 
-{
-    /* Set the bit to enable the clock. */
-    SD_IntClock_CLKEN |= SD_IntClock_CLKEN_MASK;
-	SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_Stop
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and returns immediately. This API does not require the
-*  source clock to be running but may return before the hardware is actually
-*  disabled. If the settings of the clock are changed after calling this
-*  function, the clock may glitch when it is started. To avoid the clock
-*  glitch, use the StopBlock function.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_Stop(void) 
-{
-    /* Clear the bit to disable the clock. */
-    SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);
-	SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);
-}
-
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_StopBlock
-********************************************************************************
-*
-* Summary:
-*  Stops the clock and waits for the hardware to actually be disabled before
-*  returning. This ensures that the clock is never truncated (high part of the
-*  cycle will terminate before the clock is disabled and the API returns).
-*  Note that the source clock must be running or this API will never return as
-*  a stopped clock cannot be disabled.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_StopBlock(void) 
-{
-    if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)
-    {
-#if HAS_CLKDIST_LD_DISABLE
-        uint16 oldDivider;
-
-        CLK_DIST_LD = 0u;
-
-        /* Clear all the mask bits except ours. */
-#if defined(SD_IntClock__CFG3)
-        CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;
-        CLK_DIST_DMASK = 0x00u;
-#else
-        CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;
-        CLK_DIST_AMASK = 0x00u;
-#endif /* SD_IntClock__CFG3 */
-
-        /* Clear mask of bus clock. */
-        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-        oldDivider = CY_GET_REG16(SD_IntClock_DIV_PTR);
-        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
-
-        /* Wait for clock to be disabled */
-        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-        /* Clear the bit to disable the clock. */
-        SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);
-        SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-        /* Clear the disable bit */
-        CLK_DIST_LD = 0x00u;
-        CY_SET_REG16(SD_IntClock_DIV_PTR, oldDivider);
-#endif /* HAS_CLKDIST_LD_DISABLE */
-    }
-}
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_StandbyPower
-********************************************************************************
-*
-* Summary:
-*  Sets whether the clock is active in standby mode.
-*
-* Parameters:
-*  state:  0 to disable clock during standby, nonzero to enable.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_StandbyPower(uint8 state) 
-{
-    if(state == 0u)
-    {
-        SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);
-    }
-    else
-    {
-        SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_SetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Modifies the clock divider and, thus, the frequency. When the clock divider
-*  register is set to zero or changed from zero, the clock will be temporarily
-*  disabled in order to change the SSS mode bit. If the clock is enabled when
-*  SetDividerRegister is called, then the source clock must be running.
-*
-* Parameters:
-*  clkDivider:  Divider register value (0-65,535). This value is NOT the
-*    divider; the clock hardware divides by clkDivider plus one. For example,
-*    to divide the clock by 2, this parameter should be set to 1.
-*  restart:  If nonzero, restarts the clock divider: the current clock cycle
-*   will be truncated and the new divide value will take effect immediately. If
-*   zero, the new divide value will take effect at the end of the current clock
-*   cycle.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart)
-                                
-{
-    uint8 enabled;
-
-    uint8 currSrc = SD_IntClock_GetSourceRegister();
-    uint16 oldDivider = SD_IntClock_GetDividerRegister();
-
-    if (clkDivider != oldDivider)
-    {
-        enabled = SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK;
-
-        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
-        {
-            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
-            if (oldDivider == 0u)
-            {
-                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
-                /* don't halt the clock.  Using the shadow load isn't required as the       */
-                /* divider is ignored while SSS is set.                                     */
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);
-                SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);
-            }
-            else
-            {
-                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
-                /* it without bothering with the shadow load.                               */
-                SD_IntClock_MOD_SRC |= CYCLK_SSS;
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);
-            }
-        }
-        else
-        {
-			
-            if (enabled != 0u)
-            {
-                CLK_DIST_LD = 0x00u;
-
-                /* Clear all the mask bits except ours. */
-#if defined(SD_IntClock__CFG3)
-                CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;
-                CLK_DIST_DMASK = 0x00u;
-#else
-                CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;
-                CLK_DIST_AMASK = 0x00u;
-#endif /* SD_IntClock__CFG3 */
-                /* Clear mask of bus clock. */
-                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
-
-                /* If clock is currently enabled, disable it if async or going from N-to-1*/
-                if (((SD_IntClock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
-                {
-#if HAS_CLKDIST_LD_DISABLE
-                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
-                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
-
-                    /* Wait for clock to be disabled */
-                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-#endif /* HAS_CLKDIST_LD_DISABLE */
-
-                    SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);
-
-#if HAS_CLKDIST_LD_DISABLE
-                    /* Clear the disable bit */
-                    CLK_DIST_LD = 0x00u;
-#endif /* HAS_CLKDIST_LD_DISABLE */
-                }
-            }
-
-            /* Load divide value. */
-            if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)
-            {
-                /* If the clock is still enabled, use the shadow registers */
-                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
-
-                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
-                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
-            }
-            else
-            {
-                /* If the clock is disabled, set the divider directly */
-                CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);
-				SD_IntClock_CLKEN |= enabled;
-            }
-        }
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_GetDividerRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock divider register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Divide value of the clock minus 1. For example, if the clock is set to
-*  divide by 2, the return value will be 1.
-*
-*******************************************************************************/
-uint16 SD_IntClock_GetDividerRegister(void) 
-{
-    return CY_GET_REG16(SD_IntClock_DIV_PTR);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_SetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Sets flags that control the operating mode of the clock. This function only
-*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
-*  To clear flags, use the ClearModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) 
-{
-    SD_IntClock_MOD_SRC |= modeBitMask & (uint8)SD_IntClock_MODE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_ClearModeRegister
-********************************************************************************
-*
-* Summary:
-*  Clears flags that control the operating mode of the clock. This function
-*  only changes flags from 1 to 0; flags that are already 0 will remain
-*  unchanged. To set flags, use the SetModeRegister function. The clock must be
-*  disabled before changing the mode.
-*
-* Parameters:
-*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
-*   clkMode should be a set of the following optional bits or'ed together.
-*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
-*                 occur when the divider count reaches half of the divide
-*                 value.
-*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
-*                 is asserted for approximately half of its period. When
-*                 disabled, the output clock is asserted for one period of the
-*                 source clock.
-*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
-*                 be enabled for all synchronous clocks.
-*   See the Technical Reference Manual for details about setting the mode of
-*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) 
-{
-    SD_IntClock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_IntClock_MODE_MASK));
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_GetModeRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the clock mode register value.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Bit mask representing the enabled mode bits. See the SetModeRegister and
-*  ClearModeRegister descriptions for details about the mode bits.
-*
-*******************************************************************************/
-uint8 SD_IntClock_GetModeRegister(void) 
-{
-    return SD_IntClock_MOD_SRC & (uint8)(SD_IntClock_MODE_MASK);
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_SetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the input source of the clock. The clock must be disabled before
-*  changing the source. The old and new clock sources must be running.
-*
-* Parameters:
-*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
-*   following input sources:
-*   - CYCLK_SRC_SEL_SYNC_DIG
-*   - CYCLK_SRC_SEL_IMO
-*   - CYCLK_SRC_SEL_XTALM
-*   - CYCLK_SRC_SEL_ILO
-*   - CYCLK_SRC_SEL_PLL
-*   - CYCLK_SRC_SEL_XTALK
-*   - CYCLK_SRC_SEL_DSI_G
-*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
-*   See the Technical Reference Manual for details on clock sources.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_SetSourceRegister(uint8 clkSource) 
-{
-    uint16 currDiv = SD_IntClock_GetDividerRegister();
-    uint8 oldSrc = SD_IntClock_GetSourceRegister();
-
-    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching to Master and divider is 1, set SSS, which will output master, */
-        /* then set the source so we are consistent.                                */
-        SD_IntClock_MOD_SRC |= CYCLK_SSS;
-        SD_IntClock_MOD_SRC =
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;
-    }
-    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
-            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
-    {
-        /* Switching from Master to not and divider is 1, set source, so we don't   */
-        /* lock when we clear SSS.                                                  */
-        SD_IntClock_MOD_SRC =
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;
-        SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);
-    }
-    else
-    {
-        SD_IntClock_MOD_SRC =
-            (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_GetSourceRegister
-********************************************************************************
-*
-* Summary:
-*  Gets the input source of the clock.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  The input source of the clock. See SetSourceRegister for details.
-*
-*******************************************************************************/
-uint8 SD_IntClock_GetSourceRegister(void) 
-{
-    return SD_IntClock_MOD_SRC & SD_IntClock_SRC_SEL_MSK;
-}
-
-
-#if defined(SD_IntClock__CFG3)
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_SetPhaseRegister
-********************************************************************************
-*
-* Summary:
-*  Sets the phase delay of the analog clock. This function is only available
-*  for analog clocks. The clock must be disabled before changing the phase
-*  delay to avoid glitches.
-*
-* Parameters:
-*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
-*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
-*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
-*   produces a 10ns delay.
-*
-* Returns:
-*  None
-*
-*******************************************************************************/
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) 
-{
-    SD_IntClock_PHASE = clkPhase & SD_IntClock_PHASE_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SD_IntClock_GetPhase
-********************************************************************************
-*
-* Summary:
-*  Gets the phase delay of the analog clock. This function is only available
-*  for analog clocks.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  Phase of the analog clock. See SetPhaseRegister for details.
-*
-*******************************************************************************/
-uint8 SD_IntClock_GetPhaseRegister(void) 
-{
-    return SD_IntClock_PHASE & SD_IntClock_PHASE_MASK;
-}
-
-#endif /* SD_IntClock__CFG3 */
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_IntClock.h

@@ -1,124 +0,0 @@
-/*******************************************************************************
-* File Name: SD_IntClock.h
-* Version 2.0
-*
-*  Description:
-*   Provides the function and constant definitions for the clock component.
-*
-*  Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CLOCK_SD_IntClock_H)
-#define CY_CLOCK_SD_IntClock_H
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-
-/***************************************
-* Conditional Compilation Parameters
-***************************************/
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_0 requires cy_boot v3.0 or later
-#endif /* (CY_PSOC5LP) */
-
-
-/***************************************
-*        Function Prototypes
-***************************************/
-
-void SD_IntClock_Start(void) ;
-void SD_IntClock_Stop(void) ;
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-void SD_IntClock_StopBlock(void) ;
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
-
-void SD_IntClock_StandbyPower(uint8 state) ;
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) 
-                                ;
-uint16 SD_IntClock_GetDividerRegister(void) ;
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) ;
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) ;
-uint8 SD_IntClock_GetModeRegister(void) ;
-void SD_IntClock_SetSourceRegister(uint8 clkSource) ;
-uint8 SD_IntClock_GetSourceRegister(void) ;
-#if defined(SD_IntClock__CFG3)
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) ;
-uint8 SD_IntClock_GetPhaseRegister(void) ;
-#endif /* defined(SD_IntClock__CFG3) */
-
-#define SD_IntClock_Enable()                       SD_IntClock_Start()
-#define SD_IntClock_Disable()                      SD_IntClock_Stop()
-#define SD_IntClock_SetDivider(clkDivider)         SD_IntClock_SetDividerRegister(clkDivider, 1)
-#define SD_IntClock_SetDividerValue(clkDivider)    SD_IntClock_SetDividerRegister((clkDivider) - 1, 1)
-#define SD_IntClock_SetMode(clkMode)               SD_IntClock_SetModeRegister(clkMode)
-#define SD_IntClock_SetSource(clkSource)           SD_IntClock_SetSourceRegister(clkSource)
-#if defined(SD_IntClock__CFG3)
-#define SD_IntClock_SetPhase(clkPhase)             SD_IntClock_SetPhaseRegister(clkPhase)
-#define SD_IntClock_SetPhaseValue(clkPhase)        SD_IntClock_SetPhaseRegister((clkPhase) + 1)
-#endif /* defined(SD_IntClock__CFG3) */
-
-
-/***************************************
-*             Registers
-***************************************/
-
-/* Register to enable or disable the clock */
-#define SD_IntClock_CLKEN              (* (reg8 *) SD_IntClock__PM_ACT_CFG)
-#define SD_IntClock_CLKEN_PTR          ((reg8 *) SD_IntClock__PM_ACT_CFG)
-
-/* Register to enable or disable the clock */
-#define SD_IntClock_CLKSTBY            (* (reg8 *) SD_IntClock__PM_STBY_CFG)
-#define SD_IntClock_CLKSTBY_PTR        ((reg8 *) SD_IntClock__PM_STBY_CFG)
-
-/* Clock LSB divider configuration register. */
-#define SD_IntClock_DIV_LSB            (* (reg8 *) SD_IntClock__CFG0)
-#define SD_IntClock_DIV_LSB_PTR        ((reg8 *) SD_IntClock__CFG0)
-#define SD_IntClock_DIV_PTR            ((reg16 *) SD_IntClock__CFG0)
-
-/* Clock MSB divider configuration register. */
-#define SD_IntClock_DIV_MSB            (* (reg8 *) SD_IntClock__CFG1)
-#define SD_IntClock_DIV_MSB_PTR        ((reg8 *) SD_IntClock__CFG1)
-
-/* Mode and source configuration register */
-#define SD_IntClock_MOD_SRC            (* (reg8 *) SD_IntClock__CFG2)
-#define SD_IntClock_MOD_SRC_PTR        ((reg8 *) SD_IntClock__CFG2)
-
-#if defined(SD_IntClock__CFG3)
-/* Analog clock phase configuration register */
-#define SD_IntClock_PHASE              (* (reg8 *) SD_IntClock__CFG3)
-#define SD_IntClock_PHASE_PTR          ((reg8 *) SD_IntClock__CFG3)
-#endif /* defined(SD_IntClock__CFG3) */
-
-
-/**************************************
-*       Register Constants
-**************************************/
-
-/* Power manager register masks */
-#define SD_IntClock_CLKEN_MASK         SD_IntClock__PM_ACT_MSK
-#define SD_IntClock_CLKSTBY_MASK       SD_IntClock__PM_STBY_MSK
-
-/* CFG2 field masks */
-#define SD_IntClock_SRC_SEL_MSK        SD_IntClock__CFG2_SRC_SEL_MASK
-#define SD_IntClock_MODE_MASK          (~(SD_IntClock_SRC_SEL_MSK))
-
-#if defined(SD_IntClock__CFG3)
-/* CFG3 phase mask */
-#define SD_IntClock_PHASE_MASK         SD_IntClock__CFG3_PHASE_DLY_MASK
-#endif /* defined(SD_IntClock__CFG3) */
-
-#endif /* CY_CLOCK_SD_IntClock_H */
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PM.c

@@ -1,180 +0,0 @@
-/*******************************************************************************
-* File Name: SD_PM.c
-* Version 2.40
-*
-* Description:
-*  This file contains the setup, control and status commands to support
-*  component operations in low power mode.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SD_PVT.h"
-
-static SD_BACKUP_STRUCT SD_backup =
-{
-    SD_DISABLED,
-    SD_BITCTR_INIT,
-    #if(CY_UDB_V0)
-        SD_TX_INIT_INTERRUPTS_MASK,
-        SD_RX_INIT_INTERRUPTS_MASK
-    #endif /* CY_UDB_V0 */
-};
-
-
-/*******************************************************************************
-* Function Name: SD_SaveConfig
-********************************************************************************
-*
-* Summary:
-*  Saves SPIM configuration.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SD_backup - modified when non-retention registers are saved.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_SaveConfig(void) 
-{
-    /* Store Status Mask registers */
-    #if(CY_UDB_V0)
-       SD_backup.cntrPeriod      = SD_COUNTER_PERIOD_REG;
-       SD_backup.saveSrTxIntMask = SD_TX_STATUS_MASK_REG;
-       SD_backup.saveSrRxIntMask = SD_RX_STATUS_MASK_REG;
-    #endif /* (CY_UDB_V0) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_RestoreConfig
-********************************************************************************
-*
-* Summary:
-*  Restores SPIM configuration.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SD_backup - used when non-retention registers are restored.
-*
-* Side Effects:
-*  If this API is called without first calling SaveConfig then in the following
-*  registers will be default values from Customizer:
-*  SD_STATUS_MASK_REG and SD_COUNTER_PERIOD_REG.
-*
-*******************************************************************************/
-void SD_RestoreConfig(void) 
-{
-    /* Restore the data, saved by SaveConfig() function */
-    #if(CY_UDB_V0)
-        SD_COUNTER_PERIOD_REG = SD_backup.cntrPeriod;
-        SD_TX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrTxIntMask);
-        SD_RX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrRxIntMask);
-    #endif /* (CY_UDB_V0) */
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Sleep
-********************************************************************************
-*
-* Summary:
-*  Prepare SPIM Component goes to sleep.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SD_backup - modified when non-retention registers are saved.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_Sleep(void) 
-{
-    /* Save components enable state */
-    SD_backup.enableState = ((uint8) SD_IS_ENABLED);
-
-    SD_Stop();
-    SD_SaveConfig();
-}
-
-
-/*******************************************************************************
-* Function Name: SD_Wakeup
-********************************************************************************
-*
-* Summary:
-*  Prepare SPIM Component to wake up.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  None.
-*
-* Global Variables:
-*  SD_backup - used when non-retention registers are restored.
-*  SD_txBufferWrite - modified every function call - resets to
-*  zero.
-*  SD_txBufferRead - modified every function call - resets to
-*  zero.
-*  SD_rxBufferWrite - modified every function call - resets to
-*  zero.
-*  SD_rxBufferRead - modified every function call - resets to
-*  zero.
-*
-* Reentrant:
-*  No.
-*
-*******************************************************************************/
-void SD_Wakeup(void) 
-{
-    SD_RestoreConfig();
-
-    #if(SD_RX_SOFTWARE_BUF_ENABLED)
-        SD_rxBufferFull  = 0u;
-        SD_rxBufferRead  = 0u;
-        SD_rxBufferWrite = 0u;
-    #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-    #if(SD_TX_SOFTWARE_BUF_ENABLED)
-        SD_txBufferFull  = 0u;
-        SD_txBufferRead  = 0u;
-        SD_txBufferWrite = 0u;
-    #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-    /* Clear any data from the RX and TX FIFO */
-    SD_ClearFIFO();
-
-    /* Restore components block enable state */
-    if(0u != SD_backup.enableState)
-    {
-        SD_Enable();
-    }
-}
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_PVT.h

@@ -1,53 +0,0 @@
-/*******************************************************************************
-* File Name: .h
-* Version 2.40
-*
-* Description:
-*  This private header file contains internal definitions for the SPIM
-*  component. Do not use these definitions directly in your application.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_SPIM_PVT_SD_H)
-#define CY_SPIM_PVT_SD_H
-
-#include "SD.h"
-
-
-/**********************************
-*   Functions with external linkage
-**********************************/
-
-
-/**********************************
-*   Variables with external linkage
-**********************************/
-
-extern volatile uint8 SD_swStatusTx;
-extern volatile uint8 SD_swStatusRx;
-
-#if(SD_TX_SOFTWARE_BUF_ENABLED)
-    extern volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE];
-    extern volatile uint8 SD_txBufferRead;
-    extern volatile uint8 SD_txBufferWrite;
-    extern volatile uint8 SD_txBufferFull;
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */
-
-#if(SD_RX_SOFTWARE_BUF_ENABLED)
-    extern volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE];
-    extern volatile uint8 SD_rxBufferRead;
-    extern volatile uint8 SD_rxBufferWrite;
-    extern volatile uint8 SD_rxBufferFull;
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */
-
-#endif /* CY_SPIM_PVT_SD_H */
-
-
-/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex

@@ -1,33 +1,69 @@
-:20000000014500400752004001640040020301403F0401402A05014003060140410701400F
-:20002000010D014009150140431601403A17014002400140014101400142014002430140D6
-:200040000244014002450140044801400E4901400450014001510140360214FF1804190CB8
-:200060001CE12CFF34F06410860F9840B04000011D012D013001310139023E01560858047F
-:20008000590B5B045C905D905F01806C814184688604886C89818B408D41910492029410DC
-:2000A00095E296689708981099889AC59B619C6C9D479F98A06CA110A404A541A893A94076
-:2000C000AA20AC0FAD01AE90AF40B278B407B5C0B680B73FB980BA38BB20BE40BF40D4095A
-:2000E000D80BD90BDB0BDC99DD90DF010001042806800C020D010E2917691A801D301E28DE
-:200100001F40210222022590270829402FAA3180360637603C803D203E814BC058405D2493
-:200120005E025F406001664078027C029840C078C2F0C4F0CAF8CCF8CEB0D6F8D818DE812A
-:20014000D608DB04DD9000010240051007610D020E210F08171A1D402401250C26022760CD
-:200160002A022B802C022E012F2836463C803D28448045A84C804D044E02540256105784A2
-:200180005980600266206C146EA16F3B744077027C0294289504960199109B089C029D4007
-:2001A0009E409F61A132A204A442A601A7AAAA40AD21C0F0C2F0C470CAF0CCD0CE70D0F068
-:2001C000D210D608D828DE80EA80848089409C80A140AA40AD01B085B210E620000402082A
-:2001E00004100518060C0725082009200A0C0B180E030F011108120413331403192E1A30C8
-:200200001B101C032003260128032E4830403201343C3538360237073B203E445440580BDF
-:20022000590B5B0B5C995D905F018001820288068B078E1091019208970298029A01A1074D
-:20024000A801A904AA04AC08AE10B007B107B207B618B80ABE40BF01D80BD904DB04DC092E
-:20026000DF010010014003400510076109200A800E691002120813201612171218101981F1
-:200280001D841E4A1F102101254027082911320A351036023B203D883E20462047086405E1
-:2002A0006504680278027C028D409201980299109A129B739C809D809E20A080A124A21286
-:2002C000A580A601C0FBC2FAC4F3CA05CCA3CE74D870DE81E0403340CC109F409F40AB40E5
-:2002E000EE801440C404B040EA01201026808E80C86008025B205F4084028B209340A810AD
-:20030000AF40C210D480D620E440EC80EE4001010B0111011B0100031F0020000091FF6E98
-:200320007F248000906C400000716082C01008EF00009F00C06C0200C06C0100802400485E
-:20034000C000046C00480000000F00F00000FF1000080000000040403205100004FEDBCBA0
-:200360003FFFFFFF2200F0080400000000000224040B0B0B909900010000C000400110118C
-:20038000C0010011400140010000000000000000000000000000000000FFFF00000000000B
-:2003A0000800300008000000000000000000000010000000FF000000000000010200F10EEC
-:2003C0000E000C000000000000FCFC0000000000F0000FF00000000000010000F00F0F000D
-:2003E0000000000100000000000000000000000000000000000000000000000000000000FC
+:20000000024500400852004002640040450001403201014044020140540301403D0401407E
+:200020005B0501400B0601404E070140100901403C0A01403F0B01400A0D0140020F014021
+:2000400003150140481601404317014003190140021B0140074001401041014008420140AD
+:20006000054301400844014013450140064601400147014008480140094901400650014000
+:200080003602650200C9019C180819041CE12104300431083403820F0140060C07180A60EB
+:2000A0000C020F201090124814901624172419241A101B091F03230426802A902C012D243E
+:2000C0002F1230013140321C333834E0360237073E413F01580459045B045C995F01850148
+:2000E000872C880889328B018F089004920296039740980499069A019E04A008A408A501D5
+:20010000A71AAA04AB40AC08B207B307B408B540B738B820B908BE10BF10D804D90BDC9953
+:20012000DF010128030205100A780C800D100E60120C1348149016041740184019A81B2021
+:200140001E201F14218422012540271429012B012E14318032183608371039483A083B01AF
+:200160003D803F1469806B017E808180830485408B108F01C047C2FEC4F7CA69CC6ECE7B6C
+:20018000DE80E001E220040F055506F007AA0BFF0EFF10FF13FF150F16FF17F01D691F9657
+:2001A0002433253326CC27CC28552AAA2BFF2C962E6931FF34FF3E103F015602572C5804AF
+:2001C00059045B0B5D905F01843885108A458E38900792409406964098089C029D039F0CC7
+:2001E000A002A105A30AA610A820A906AB09AC01AE02B007B10FB240B510B638BE44BF11DE
+:20020000D440D804D904DB0BDC09DD90DF01020A0310050807010A640B020C020E201001FD
+:20022000124013141504160817801A501B411D10200423802740284029202D042F24318070
+:20024000350837813A043C203E086120632167806C206D916F027602770278027A037E80FC
+:200260008120820483408480861088108E4090409180920293089560966C97149801998828
+:200280009A089B119C909D119F48A180A210A320A480A688A701AF01B001B340B702C0A74B
+:2002A000C23FC4EFCA65CCD8CE62D88EDE81E201E408E603E80200030A010F081528174463
+:2002C000192C1B811E031F0320032403278028032B042DD42F22300233E03401351836025E
+:2002E00037073B303E5140644102423045E2460D47CF483749FF4AFF4BFF4F2C5601580455
+:2003000059045A045B045C905D095F0162C06680684069406E0888018A069405960298035D
+:200320009A049C049E03B607BA80D80BDC09DF0101010204051009400E010F141020111056
+:20034000130219421B101E011F4021102258232029042A202B01304032583980411042505D
+:20036000484049044A0851085240530159A85A026064618069406A086B8870907101722003
+:200380007E80810883018580882089108C108E409044919192529560962C979799809A022E
+:2003A0009B029C429D019E409F08A020A140A323A490A520A689A710AB80AF20B012B508E0
+:2003C000B608C04AC2E1C40ECA0ECC0ECE08D007D204D60FD80FDE80E001E210E404E602DE
+:2003E000E801EA50EE8010041202160318041A012A042E04320758045C095F010008010130
+:20040000030A09080A840D100E6010221112130217A018201C201E202040210422402A823F
+:200420002B16302231083240386039013B044108420443014804494850425120524558804B
+:200440006002628078029131924096049714988099429A029BA29C029D109E04A020A140AB
+:20046000A302A410A520A681A880A908AA04AB01AC50AD20B240B540B608B720C00FC27EB0
+:20048000C4CFCA0FCC0FCE0FD007D20CD608D808DE01E440E80AEE078E019E41A402A841DE
+:2004A000AB08AE09AF82B201B441B510B620B704E440E840EA01ECD00001013303CC0802A2
+:2004C0000FFF1196136917FF1D551FAA21FF290F2BF0340135FF36023E503F1058045904F0
+:2004E0005F0182028533868087CC88808A408BFF8E0891FF92049406950F960897F0988074
+:200500009A209D559E609FAAA002A204A410A969AA80AB96AC01ADFFB001B20EB410B6E04B
+:20052000B7FFBE15BF40D804D904DB04DC09DF0100010120066107080C020E220F04158058
+:20054000161017111A0A1C481E021F0822202640280829022C082F023102320833403408FA
+:200560003502374038823D203F085D085E015FA06E206F018128832084048A048B048D40F0
+:200580008F10980899029A109B48A008A102A661A808A902B408B740C0FAC2F0C4F0CA3575
+:2005A000CCDBCE69D6F0E280E460E601E8508201850286308A408F08E223E440E802EA2094
+:2005C000EE60E001E610A840AB20EC8000D00424064308110A220CD0102012D0142816838E
+:2005E00018D01E0C20D0260128D02E0230F0360F3A02580B5C095F018038814684438539DD
+:20060000863C870688488A208B468D048F20903894619501961E975E982399429A449B04F1
+:200620009C189E20A010A146A428A542A610A820A977AA18AB08AD46B108B260B370B41E38
+:20064000B50FB601B920BA08BB0CBE40BF01D409D80BD90BDB0BDC99DD90DF0100080101A9
+:200660000308040405100680070209490A040C200E420F1010201110124015191601195473
+:200680001A041B1C1E42200C2108239429142A022B0230203108388039113B04590A5BA0DB
+:2006A000614078027E808B0190809119960497149802990A9AC39B029D109F01A020A14170
+:2006C000A280A302A404A508A601A71CC0FEC2FFC4FECA0FCC06CE0FD60FD808DE81E420A3
+:2006E000EC80A402B240EC80B002EC805810808086808810D480E240E6805381570A5904F8
+:200700005C026008648081048240840898809A80D4E0D6E0D8C0E220E6908C0292409A8036
+:200720009C02AF80B302B709EE1023088F0892409A80C8100C015102542080208C40C204ED
+:20074000D403E608020403100480074009020B010C188008850294809C109F10AD02B011C7
+:20076000B710C00FC20FEA04EE0683408E0493019A049B40E608AB01231027088801924077
+:2007800097109A80B310C860080156805A4092409A809C01B308C210D4C0010109010B0172
+:2007A0000D0111011B010000C00102000008FF218040000090404000001060807F22800829
+:2007C0001F01200000040000C0010100C0070418C001080000019F00003FFF8000000040C9
+:2007E000008200000000040163025000040EFCBD3DFFFFFF2200F008040000000000080092
+:20080000040B0B04909900010000C00040011011C00100114001400100000000000000001A
+:20082000000000000000000000FFFF00FF000000080030000800000000000000000000007B
+:2008400010000000FF000000000000010200F10E0E000C000000000000FCFC000400000071
+:200860000F00000000000001F00F0F000C000001000000000000000000000000000000004D
 :00000001FF

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.c

@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
-  clrex
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-  __ASM("bx lr"); 
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result=0;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-    uint8_t result=0;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-    uint16_t result=0;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-    uint32_t result=0;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h

@@ -5331,6 +5331,7 @@
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000u
 #define CYDEV_FLS_ROW_SIZE 0x00000100u
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000u
 #define CYDEV_ECC_ROW_SIZE 0x00000020u
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h

@@ -5331,6 +5331,7 @@
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000u
 #define CYDEV_FLS_ROW_SIZE 0x00000100u
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000u
 #define CYDEV_ECC_ROW_SIZE 0x00000020u
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc

@@ -5329,6 +5329,7 @@
 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE
 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000
 .set CYDEV_FLS_ROW_SIZE, 0x00000100
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001
 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000
 .set CYDEV_ECC_ROW_SIZE, 0x00000020
 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc

@@ -5329,6 +5329,7 @@
 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE
 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000
 .set CYDEV_FLS_ROW_SIZE, 0x00000100
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001
 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000
 .set CYDEV_ECC_ROW_SIZE, 0x00000020
 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc

@@ -5328,6 +5328,7 @@
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000
 #define CYDEV_FLS_ROW_SIZE 0x00000100
+#define CYDEV_ALLOCATE_EEPROM 0x00000001
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000
 #define CYDEV_ECC_ROW_SIZE 0x00000020
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc

@@ -5328,6 +5328,7 @@
 #define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
 #define CYDEV_FLS_SECTOR_SIZE 0x00010000
 #define CYDEV_FLS_ROW_SIZE 0x00000100
+#define CYDEV_ALLOCATE_EEPROM 0x00000001
 #define CYDEV_ECC_SECTOR_SIZE 0x00002000
 #define CYDEV_ECC_ROW_SIZE 0x00000020
 #define CYDEV_EEPROM_SECTOR_SIZE 0x00000400

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc

@@ -15957,6 +15957,9 @@ CYDEV_FLS_SECTOR_SIZE EQU 0x00010000
     ENDIF
     IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE
 CYDEV_FLS_ROW_SIZE EQU 0x00000100
+    ENDIF
+    IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001
     ENDIF
     IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE
 CYDEV_ECC_SECTOR_SIZE EQU 0x00002000

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc

@@ -15957,6 +15957,9 @@ CYDEV_FLS_SECTOR_SIZE EQU 0x00010000
     ENDIF
     IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE
 CYDEV_FLS_ROW_SIZE EQU 0x00000100
+    ENDIF
+    IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001
     ENDIF
     IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE
 CYDEV_ECC_SECTOR_SIZE EQU 0x00002000

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */
 #define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_ATN_ISR__INTC_MASK 0x01u
-#define SCSI_ATN_ISR__INTC_NUMBER 0u
+#define SCSI_ATN_ISR__INTC_MASK 0x800u
+#define SCSI_ATN_ISR__INTC_NUMBER 11u
 #define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11
 #define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
@@ -116,34 +116,34 @@
 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB02_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB02_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB02_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -151,13 +151,13 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB03_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB03_ST
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@@ -167,28 +167,48 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1
+
+/* SCSI_CTL_IO */
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
 
 /* SCSI_In_DBx */
 #define SCSI_In_DBx__0__MASK 0x01u
@@ -304,59 +324,94 @@
 #define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
 #define SD_Init_Clk__PM_STBY_MSK 0x02u
 
+/* scsiTarget */
+#define scsiTarget_StatusReg__0__MASK 0x01u
+#define scsiTarget_StatusReg__0__POS 0
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_StatusReg__1__MASK 0x02u
+#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__2__MASK 0x04u
+#define scsiTarget_StatusReg__2__POS 2
+#define scsiTarget_StatusReg__3__MASK 0x08u
+#define scsiTarget_StatusReg__3__POS 3
+#define scsiTarget_StatusReg__MASK 0x0Fu
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+
 /* SD_Clk_Ctl */
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-
-/* PARITY_EN */
-#define PARITY_EN__0__MASK 0x10u
-#define PARITY_EN__0__PC CYREG_PRT5_PC4
-#define PARITY_EN__0__PORT 5u
-#define PARITY_EN__0__SHIFT 4
-#define PARITY_EN__AG CYREG_PRT5_AG
-#define PARITY_EN__AMUX CYREG_PRT5_AMUX
-#define PARITY_EN__BIE CYREG_PRT5_BIE
-#define PARITY_EN__BIT_MASK CYREG_PRT5_BIT_MASK
-#define PARITY_EN__BYP CYREG_PRT5_BYP
-#define PARITY_EN__CTL CYREG_PRT5_CTL
-#define PARITY_EN__DM0 CYREG_PRT5_DM0
-#define PARITY_EN__DM1 CYREG_PRT5_DM1
-#define PARITY_EN__DM2 CYREG_PRT5_DM2
-#define PARITY_EN__DR CYREG_PRT5_DR
-#define PARITY_EN__INP_DIS CYREG_PRT5_INP_DIS
-#define PARITY_EN__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define PARITY_EN__LCD_EN CYREG_PRT5_LCD_EN
-#define PARITY_EN__MASK 0x10u
-#define PARITY_EN__PORT 5u
-#define PARITY_EN__PRT CYREG_PRT5_PRT
-#define PARITY_EN__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define PARITY_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define PARITY_EN__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define PARITY_EN__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define PARITY_EN__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define PARITY_EN__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define PARITY_EN__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define PARITY_EN__PS CYREG_PRT5_PS
-#define PARITY_EN__SHIFT 4
-#define PARITY_EN__SLW CYREG_PRT5_SLW
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__MASK 0x02u
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__POS 1
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x03u
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
 
 /* SCSI_ATN */
 #define SCSI_ATN__0__MASK 0x20u
@@ -372,6 +427,7 @@
 #define SCSI_ATN__DM2 CYREG_PRT12_DM2
 #define SCSI_ATN__DR CYREG_PRT12_DR
 #define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT
 #define SCSI_ATN__INT__MASK 0x20u
 #define SCSI_ATN__INT__PC CYREG_PRT12_PC5
 #define SCSI_ATN__INT__PORT 12u
@@ -392,6 +448,7 @@
 #define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
 #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
 #define SCSI_ATN__SLW CYREG_PRT12_SLW
+#define SCSI_ATN__SNAP CYREG_PICU12_SNAP
 
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT4_AG
@@ -772,60 +829,60 @@
 #define SCSI_Out__CD__PS CYREG_PRT6_PS
 #define SCSI_Out__CD__SHIFT 1
 #define SCSI_Out__CD__SLW CYREG_PRT6_SLW
-#define SCSI_Out__DBP__AG CYREG_PRT4_AG
-#define SCSI_Out__DBP__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__DBP__BIE CYREG_PRT4_BIE
-#define SCSI_Out__DBP__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__DBP__BYP CYREG_PRT4_BYP
-#define SCSI_Out__DBP__CTL CYREG_PRT4_CTL
-#define SCSI_Out__DBP__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__DBP__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__DBP__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__DBP__DR CYREG_PRT4_DR
-#define SCSI_Out__DBP__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__DBP__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__DBP__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__DBP__MASK 0x04u
-#define SCSI_Out__DBP__PC CYREG_PRT4_PC2
-#define SCSI_Out__DBP__PORT 4u
-#define SCSI_Out__DBP__PRT CYREG_PRT4_PRT
-#define SCSI_Out__DBP__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__DBP__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__DBP__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__DBP__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__DBP__PS CYREG_PRT4_PS
-#define SCSI_Out__DBP__SHIFT 2
-#define SCSI_Out__DBP__SLW CYREG_PRT4_SLW
-#define SCSI_Out__IO__AG CYREG_PRT6_AG
-#define SCSI_Out__IO__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__IO__BIE CYREG_PRT6_BIE
-#define SCSI_Out__IO__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__IO__BYP CYREG_PRT6_BYP
-#define SCSI_Out__IO__CTL CYREG_PRT6_CTL
-#define SCSI_Out__IO__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__IO__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__IO__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__IO__DR CYREG_PRT6_DR
-#define SCSI_Out__IO__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__IO__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__IO__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__IO__MASK 0x08u
-#define SCSI_Out__IO__PC CYREG_PRT6_PC3
-#define SCSI_Out__IO__PORT 6u
-#define SCSI_Out__IO__PRT CYREG_PRT6_PRT
-#define SCSI_Out__IO__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__IO__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__IO__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__IO__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__IO__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__IO__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__IO__PS CYREG_PRT6_PS
-#define SCSI_Out__IO__SHIFT 3
-#define SCSI_Out__IO__SLW CYREG_PRT6_SLW
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__DBP_raw__MASK 0x04u
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC2
+#define SCSI_Out__DBP_raw__PORT 4u
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS
+#define SCSI_Out__DBP_raw__SHIFT 2
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW
+#define SCSI_Out__IO_raw__AG CYREG_PRT6_AG
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__IO_raw__BIE CYREG_PRT6_BIE
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__IO_raw__BYP CYREG_PRT6_BYP
+#define SCSI_Out__IO_raw__CTL CYREG_PRT6_CTL
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__IO_raw__DR CYREG_PRT6_DR
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__IO_raw__MASK 0x08u
+#define SCSI_Out__IO_raw__PC CYREG_PRT6_PC3
+#define SCSI_Out__IO_raw__PORT 6u
+#define SCSI_Out__IO_raw__PRT CYREG_PRT6_PRT
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__IO_raw__PS CYREG_PRT6_PS
+#define SCSI_Out__IO_raw__SHIFT 3
+#define SCSI_Out__IO_raw__SLW CYREG_PRT6_SLW
 #define SCSI_Out__MSG__AG CYREG_PRT4_AG
 #define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX
 #define SCSI_Out__MSG__BIE CYREG_PRT4_BIE
@@ -973,44 +1030,6 @@
 #define SCSI_RST__SLW CYREG_PRT6_SLW
 #define SCSI_RST__SNAP CYREG_PICU6_SNAP
 
-/* SCSI_ID */
-#define SCSI_ID__0__MASK 0x80u
-#define SCSI_ID__0__PC CYREG_PRT5_PC7
-#define SCSI_ID__0__PORT 5u
-#define SCSI_ID__0__SHIFT 7
-#define SCSI_ID__1__MASK 0x40u
-#define SCSI_ID__1__PC CYREG_PRT5_PC6
-#define SCSI_ID__1__PORT 5u
-#define SCSI_ID__1__SHIFT 6
-#define SCSI_ID__2__MASK 0x20u
-#define SCSI_ID__2__PC CYREG_PRT5_PC5
-#define SCSI_ID__2__PORT 5u
-#define SCSI_ID__2__SHIFT 5
-#define SCSI_ID__AG CYREG_PRT5_AG
-#define SCSI_ID__AMUX CYREG_PRT5_AMUX
-#define SCSI_ID__BIE CYREG_PRT5_BIE
-#define SCSI_ID__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_ID__BYP CYREG_PRT5_BYP
-#define SCSI_ID__CTL CYREG_PRT5_CTL
-#define SCSI_ID__DM0 CYREG_PRT5_DM0
-#define SCSI_ID__DM1 CYREG_PRT5_DM1
-#define SCSI_ID__DM2 CYREG_PRT5_DM2
-#define SCSI_ID__DR CYREG_PRT5_DR
-#define SCSI_ID__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_ID__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_ID__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_ID__PORT 5u
-#define SCSI_ID__PRT CYREG_PRT5_PRT
-#define SCSI_ID__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_ID__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_ID__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_ID__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_ID__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_ID__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_ID__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_ID__PS CYREG_PRT5_PS
-#define SCSI_ID__SLW CYREG_PRT5_SLW
-
 /* SCSI_In */
 #define SCSI_In__0__AG CYREG_PRT12_AG
 #define SCSI_In__0__BIE CYREG_PRT12_BIE
@@ -1805,7 +1824,7 @@
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x1000
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x00000001u
+#define CYDEV_INTR_RISING 0x00000000u
 #define CYDEV_PROJ_TYPE 0
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1
 #define CYDEV_PROJ_TYPE_LOADABLE 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c

@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }
 #endif
 
-#define CY_CFG_BASE_ADDR_COUNT 22u
+#define CY_CFG_BASE_ADDR_COUNT 32u
 CYPACKED typedef struct
 {
 	uint8 offset;
@@ -129,34 +129,34 @@ CYPACKED typedef struct
 } CYPACKED_ATTR cy_cfg_addrvalue_t;
 
 #define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)
-#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000080u)
 
-/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */
-#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)
+/* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */
+#define BS_UDB_1_2_0_CONFIG_VAL ((const uint8 CYFAR *)0x480007A8u)
 
 /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000828u)
 
 /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
-#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000830u)
 
 /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */
-#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x4800083Cu)
 
 /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000844u)
 
 /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
-#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x4800084Cu)
 
 /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000858u)
 
-/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */
-#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)
+/* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x48000860u)
 
 /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000868u)
 
 
 /*******************************************************************************
@@ -369,8 +369,8 @@ void cyfitter_cfg(void)
 			/* address, size */
 			{(void CYFAR *)(CYREG_PRT1_DR), 16u},
 			{(void CYFAR *)(CYREG_PRT15_DR), 16u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},
 			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
@@ -379,7 +379,7 @@ void cyfitter_cfg(void)
 
 		static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
 			/* dest, src, size */
-			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},
 		};
 
 		uint8 CYDATA i;
@@ -419,7 +419,7 @@ void cyfitter_cfg(void)
 	CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);
 	CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);
 	CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DM0), (const void CYFAR *)(BS_IOPINS0_4_VAL), 8u);
-	CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DR), (const void CYFAR *)(BS_IOPINS0_5_VAL), 10u);
+	CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DM0), (const void CYFAR *)(BS_IOPINS0_5_VAL), 8u);
 	CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);
 
 	/* Switch Boost to the precision bandgap reference from its internal reference */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */
 .set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_ATN_ISR__INTC_MASK, 0x01
-.set SCSI_ATN_ISR__INTC_NUMBER, 0
+.set SCSI_ATN_ISR__INTC_MASK, 0x800
+.set SCSI_ATN_ISR__INTC_NUMBER, 11
 .set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_11
 .set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
@@ -116,34 +116,34 @@
 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB02_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB02_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -151,13 +151,13 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB03_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB03_ST
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@@ -167,28 +167,48 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1
+
+/* SCSI_CTL_IO */
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
 
 /* SCSI_In_DBx */
 .set SCSI_In_DBx__0__MASK, 0x01
@@ -304,59 +324,94 @@
 .set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
 .set SD_Init_Clk__PM_STBY_MSK, 0x02
 
+/* scsiTarget */
+.set scsiTarget_StatusReg__0__MASK, 0x01
+.set scsiTarget_StatusReg__0__POS, 0
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_StatusReg__1__MASK, 0x02
+.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__2__MASK, 0x04
+.set scsiTarget_StatusReg__2__POS, 2
+.set scsiTarget_StatusReg__3__MASK, 0x08
+.set scsiTarget_StatusReg__3__POS, 3
+.set scsiTarget_StatusReg__MASK, 0x0F
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+
 /* SD_Clk_Ctl */
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-
-/* PARITY_EN */
-.set PARITY_EN__0__MASK, 0x10
-.set PARITY_EN__0__PC, CYREG_PRT5_PC4
-.set PARITY_EN__0__PORT, 5
-.set PARITY_EN__0__SHIFT, 4
-.set PARITY_EN__AG, CYREG_PRT5_AG
-.set PARITY_EN__AMUX, CYREG_PRT5_AMUX
-.set PARITY_EN__BIE, CYREG_PRT5_BIE
-.set PARITY_EN__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set PARITY_EN__BYP, CYREG_PRT5_BYP
-.set PARITY_EN__CTL, CYREG_PRT5_CTL
-.set PARITY_EN__DM0, CYREG_PRT5_DM0
-.set PARITY_EN__DM1, CYREG_PRT5_DM1
-.set PARITY_EN__DM2, CYREG_PRT5_DM2
-.set PARITY_EN__DR, CYREG_PRT5_DR
-.set PARITY_EN__INP_DIS, CYREG_PRT5_INP_DIS
-.set PARITY_EN__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set PARITY_EN__LCD_EN, CYREG_PRT5_LCD_EN
-.set PARITY_EN__MASK, 0x10
-.set PARITY_EN__PORT, 5
-.set PARITY_EN__PRT, CYREG_PRT5_PRT
-.set PARITY_EN__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set PARITY_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set PARITY_EN__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set PARITY_EN__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set PARITY_EN__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set PARITY_EN__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set PARITY_EN__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set PARITY_EN__PS, CYREG_PRT5_PS
-.set PARITY_EN__SHIFT, 4
-.set PARITY_EN__SLW, CYREG_PRT5_SLW
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__MASK, 0x02
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__POS, 1
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x03
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
 
 /* SCSI_ATN */
 .set SCSI_ATN__0__MASK, 0x20
@@ -372,6 +427,7 @@
 .set SCSI_ATN__DM2, CYREG_PRT12_DM2
 .set SCSI_ATN__DR, CYREG_PRT12_DR
 .set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_ATN__INTSTAT, CYREG_PICU12_INTSTAT
 .set SCSI_ATN__INT__MASK, 0x20
 .set SCSI_ATN__INT__PC, CYREG_PRT12_PC5
 .set SCSI_ATN__INT__PORT, 12
@@ -392,6 +448,7 @@
 .set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
 .set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 .set SCSI_ATN__SLW, CYREG_PRT12_SLW
+.set SCSI_ATN__SNAP, CYREG_PICU12_SNAP
 
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT4_AG
@@ -772,60 +829,60 @@
 .set SCSI_Out__CD__PS, CYREG_PRT6_PS
 .set SCSI_Out__CD__SHIFT, 1
 .set SCSI_Out__CD__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__DBP__AG, CYREG_PRT4_AG
-.set SCSI_Out__DBP__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__DBP__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__DBP__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__DBP__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__DBP__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__DBP__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__DBP__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__DBP__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__DBP__DR, CYREG_PRT4_DR
-.set SCSI_Out__DBP__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__DBP__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__DBP__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__DBP__MASK, 0x04
-.set SCSI_Out__DBP__PC, CYREG_PRT4_PC2
-.set SCSI_Out__DBP__PORT, 4
-.set SCSI_Out__DBP__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__DBP__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__DBP__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__DBP__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__DBP__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__DBP__PS, CYREG_PRT4_PS
-.set SCSI_Out__DBP__SHIFT, 2
-.set SCSI_Out__DBP__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__IO__AG, CYREG_PRT6_AG
-.set SCSI_Out__IO__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__IO__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__IO__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__IO__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__IO__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__IO__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__IO__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__IO__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__IO__DR, CYREG_PRT6_DR
-.set SCSI_Out__IO__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__IO__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__IO__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__IO__MASK, 0x08
-.set SCSI_Out__IO__PC, CYREG_PRT6_PC3
-.set SCSI_Out__IO__PORT, 6
-.set SCSI_Out__IO__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__IO__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__IO__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__IO__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__IO__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__IO__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__IO__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__IO__PS, CYREG_PRT6_PS
-.set SCSI_Out__IO__SHIFT, 3
-.set SCSI_Out__IO__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__DBP_raw__MASK, 0x04
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC2
+.set SCSI_Out__DBP_raw__PORT, 4
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS
+.set SCSI_Out__DBP_raw__SHIFT, 2
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__IO_raw__AG, CYREG_PRT6_AG
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__IO_raw__DR, CYREG_PRT6_DR
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__IO_raw__MASK, 0x08
+.set SCSI_Out__IO_raw__PC, CYREG_PRT6_PC3
+.set SCSI_Out__IO_raw__PORT, 6
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__IO_raw__PS, CYREG_PRT6_PS
+.set SCSI_Out__IO_raw__SHIFT, 3
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT6_SLW
 .set SCSI_Out__MSG__AG, CYREG_PRT4_AG
 .set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX
 .set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE
@@ -973,44 +1030,6 @@
 .set SCSI_RST__SLW, CYREG_PRT6_SLW
 .set SCSI_RST__SNAP, CYREG_PICU6_SNAP
 
-/* SCSI_ID */
-.set SCSI_ID__0__MASK, 0x80
-.set SCSI_ID__0__PC, CYREG_PRT5_PC7
-.set SCSI_ID__0__PORT, 5
-.set SCSI_ID__0__SHIFT, 7
-.set SCSI_ID__1__MASK, 0x40
-.set SCSI_ID__1__PC, CYREG_PRT5_PC6
-.set SCSI_ID__1__PORT, 5
-.set SCSI_ID__1__SHIFT, 6
-.set SCSI_ID__2__MASK, 0x20
-.set SCSI_ID__2__PC, CYREG_PRT5_PC5
-.set SCSI_ID__2__PORT, 5
-.set SCSI_ID__2__SHIFT, 5
-.set SCSI_ID__AG, CYREG_PRT5_AG
-.set SCSI_ID__AMUX, CYREG_PRT5_AMUX
-.set SCSI_ID__BIE, CYREG_PRT5_BIE
-.set SCSI_ID__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_ID__BYP, CYREG_PRT5_BYP
-.set SCSI_ID__CTL, CYREG_PRT5_CTL
-.set SCSI_ID__DM0, CYREG_PRT5_DM0
-.set SCSI_ID__DM1, CYREG_PRT5_DM1
-.set SCSI_ID__DM2, CYREG_PRT5_DM2
-.set SCSI_ID__DR, CYREG_PRT5_DR
-.set SCSI_ID__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_ID__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_ID__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_ID__PORT, 5
-.set SCSI_ID__PRT, CYREG_PRT5_PRT
-.set SCSI_ID__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_ID__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_ID__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_ID__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_ID__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_ID__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_ID__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_ID__PS, CYREG_PRT5_PS
-.set SCSI_ID__SLW, CYREG_PRT5_SLW
-
 /* SCSI_In */
 .set SCSI_In__0__AG, CYREG_PRT12_AG
 .set SCSI_In__0__BIE, CYREG_PRT12_BIE
@@ -1805,7 +1824,7 @@
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x1000
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x00000001
+.set CYDEV_INTR_RISING, 0x00000000
 .set CYDEV_PROJ_TYPE, 0
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1
 .set CYDEV_PROJ_TYPE_LOADABLE, 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -6,10 +6,10 @@
 /* SCSI_ATN_ISR */
 SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_ATN_ISR__INTC_MASK EQU 0x01
-SCSI_ATN_ISR__INTC_NUMBER EQU 0
+SCSI_ATN_ISR__INTC_MASK EQU 0x800
+SCSI_ATN_ISR__INTC_NUMBER EQU 11
 SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11
 SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
@@ -116,34 +116,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@@ -167,28 +167,48 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+
+/* SCSI_CTL_IO */
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
 
 /* SCSI_In_DBx */
 SCSI_In_DBx__0__MASK EQU 0x01
@@ -304,59 +324,94 @@ SD_Init_Clk__PM_ACT_MSK EQU 0x02
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 SD_Init_Clk__PM_STBY_MSK EQU 0x02
 
+/* scsiTarget */
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__MASK EQU 0x0F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+
 /* SD_Clk_Ctl */
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-
-/* PARITY_EN */
-PARITY_EN__0__MASK EQU 0x10
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4
-PARITY_EN__0__PORT EQU 5
-PARITY_EN__0__SHIFT EQU 4
-PARITY_EN__AG EQU CYREG_PRT5_AG
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX
-PARITY_EN__BIE EQU CYREG_PRT5_BIE
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-PARITY_EN__BYP EQU CYREG_PRT5_BYP
-PARITY_EN__CTL EQU CYREG_PRT5_CTL
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2
-PARITY_EN__DR EQU CYREG_PRT5_DR
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN
-PARITY_EN__MASK EQU 0x10
-PARITY_EN__PORT EQU 5
-PARITY_EN__PRT EQU CYREG_PRT5_PRT
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-PARITY_EN__PS EQU CYREG_PRT5_PS
-PARITY_EN__SHIFT EQU 4
-PARITY_EN__SLW EQU CYREG_PRT5_SLW
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
 
 /* SCSI_ATN */
 SCSI_ATN__0__MASK EQU 0x20
@@ -372,6 +427,7 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2
 SCSI_ATN__DR EQU CYREG_PRT12_DR
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT
 SCSI_ATN__INT__MASK EQU 0x20
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5
 SCSI_ATN__INT__PORT EQU 12
@@ -392,6 +448,7 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP
 
 /* SCSI_Out */
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
@@ -772,60 +829,60 @@ SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_Out__CD__PS EQU CYREG_PRT6_PS
 SCSI_Out__CD__SHIFT EQU 1
 SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__DBP__MASK EQU 0x04
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2
-SCSI_Out__DBP__PORT EQU 4
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS
-SCSI_Out__DBP__SHIFT EQU 2
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__IO__MASK EQU 0x08
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3
-SCSI_Out__IO__PORT EQU 6
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS
-SCSI_Out__IO__SHIFT EQU 3
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x04
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2
+SCSI_Out__DBP_raw__PORT EQU 4
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__DBP_raw__SHIFT EQU 2
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x08
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3
+SCSI_Out__IO_raw__PORT EQU 6
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS
+SCSI_Out__IO_raw__SHIFT EQU 3
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW
 SCSI_Out__MSG__AG EQU CYREG_PRT4_AG
 SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX
 SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE
@@ -973,44 +1030,6 @@ SCSI_RST__SHIFT EQU 6
 SCSI_RST__SLW EQU CYREG_PRT6_SLW
 SCSI_RST__SNAP EQU CYREG_PICU6_SNAP
 
-/* SCSI_ID */
-SCSI_ID__0__MASK EQU 0x80
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7
-SCSI_ID__0__PORT EQU 5
-SCSI_ID__0__SHIFT EQU 7
-SCSI_ID__1__MASK EQU 0x40
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6
-SCSI_ID__1__PORT EQU 5
-SCSI_ID__1__SHIFT EQU 6
-SCSI_ID__2__MASK EQU 0x20
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5
-SCSI_ID__2__PORT EQU 5
-SCSI_ID__2__SHIFT EQU 5
-SCSI_ID__AG EQU CYREG_PRT5_AG
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX
-SCSI_ID__BIE EQU CYREG_PRT5_BIE
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_ID__BYP EQU CYREG_PRT5_BYP
-SCSI_ID__CTL EQU CYREG_PRT5_CTL
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2
-SCSI_ID__DR EQU CYREG_PRT5_DR
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_ID__PORT EQU 5
-SCSI_ID__PRT EQU CYREG_PRT5_PRT
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_ID__PS EQU CYREG_PRT5_PS
-SCSI_ID__SLW EQU CYREG_PRT5_SLW
-
 /* SCSI_In */
 SCSI_In__0__AG EQU CYREG_PRT12_AG
 SCSI_In__0__BIE EQU CYREG_PRT12_BIE
@@ -1805,7 +1824,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x1000
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x00000001
+CYDEV_INTR_RISING EQU 0x00000000
 CYDEV_PROJ_TYPE EQU 0
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
 CYDEV_PROJ_TYPE_LOADABLE EQU 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -6,10 +6,10 @@ INCLUDED_CYFITTERRV_INC EQU 1
 ; SCSI_ATN_ISR
 SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_ATN_ISR__INTC_MASK EQU 0x01
-SCSI_ATN_ISR__INTC_NUMBER EQU 0
+SCSI_ATN_ISR__INTC_MASK EQU 0x800
+SCSI_ATN_ISR__INTC_NUMBER EQU 11
 SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11
 SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
@@ -116,34 +116,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@@ -167,28 +167,48 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+
+; SCSI_CTL_IO
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
 
 ; SCSI_In_DBx
 SCSI_In_DBx__0__MASK EQU 0x01
@@ -304,59 +324,94 @@ SD_Init_Clk__PM_ACT_MSK EQU 0x02
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 SD_Init_Clk__PM_STBY_MSK EQU 0x02
 
+; scsiTarget
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__MASK EQU 0x0F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+
 ; SD_Clk_Ctl
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-
-; PARITY_EN
-PARITY_EN__0__MASK EQU 0x10
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4
-PARITY_EN__0__PORT EQU 5
-PARITY_EN__0__SHIFT EQU 4
-PARITY_EN__AG EQU CYREG_PRT5_AG
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX
-PARITY_EN__BIE EQU CYREG_PRT5_BIE
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-PARITY_EN__BYP EQU CYREG_PRT5_BYP
-PARITY_EN__CTL EQU CYREG_PRT5_CTL
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2
-PARITY_EN__DR EQU CYREG_PRT5_DR
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN
-PARITY_EN__MASK EQU 0x10
-PARITY_EN__PORT EQU 5
-PARITY_EN__PRT EQU CYREG_PRT5_PRT
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-PARITY_EN__PS EQU CYREG_PRT5_PS
-PARITY_EN__SHIFT EQU 4
-PARITY_EN__SLW EQU CYREG_PRT5_SLW
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
 
 ; SCSI_ATN
 SCSI_ATN__0__MASK EQU 0x20
@@ -372,6 +427,7 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2
 SCSI_ATN__DR EQU CYREG_PRT12_DR
 SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT
 SCSI_ATN__INT__MASK EQU 0x20
 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5
 SCSI_ATN__INT__PORT EQU 12
@@ -392,6 +448,7 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP
 
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
@@ -772,60 +829,60 @@ SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_Out__CD__PS EQU CYREG_PRT6_PS
 SCSI_Out__CD__SHIFT EQU 1
 SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__DBP__MASK EQU 0x04
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2
-SCSI_Out__DBP__PORT EQU 4
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS
-SCSI_Out__DBP__SHIFT EQU 2
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__IO__MASK EQU 0x08
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3
-SCSI_Out__IO__PORT EQU 6
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS
-SCSI_Out__IO__SHIFT EQU 3
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x04
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2
+SCSI_Out__DBP_raw__PORT EQU 4
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__DBP_raw__SHIFT EQU 2
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x08
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3
+SCSI_Out__IO_raw__PORT EQU 6
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS
+SCSI_Out__IO_raw__SHIFT EQU 3
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW
 SCSI_Out__MSG__AG EQU CYREG_PRT4_AG
 SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX
 SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE
@@ -973,44 +1030,6 @@ SCSI_RST__SHIFT EQU 6
 SCSI_RST__SLW EQU CYREG_PRT6_SLW
 SCSI_RST__SNAP EQU CYREG_PICU6_SNAP
 
-; SCSI_ID
-SCSI_ID__0__MASK EQU 0x80
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7
-SCSI_ID__0__PORT EQU 5
-SCSI_ID__0__SHIFT EQU 7
-SCSI_ID__1__MASK EQU 0x40
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6
-SCSI_ID__1__PORT EQU 5
-SCSI_ID__1__SHIFT EQU 6
-SCSI_ID__2__MASK EQU 0x20
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5
-SCSI_ID__2__PORT EQU 5
-SCSI_ID__2__SHIFT EQU 5
-SCSI_ID__AG EQU CYREG_PRT5_AG
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX
-SCSI_ID__BIE EQU CYREG_PRT5_BIE
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_ID__BYP EQU CYREG_PRT5_BYP
-SCSI_ID__CTL EQU CYREG_PRT5_CTL
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2
-SCSI_ID__DR EQU CYREG_PRT5_DR
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_ID__PORT EQU 5
-SCSI_ID__PRT EQU CYREG_PRT5_PRT
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_ID__PS EQU CYREG_PRT5_PS
-SCSI_ID__SLW EQU CYREG_PRT5_SLW
-
 ; SCSI_In
 SCSI_In__0__AG EQU CYREG_PRT12_AG
 SCSI_In__0__BIE EQU CYREG_PRT12_BIE
@@ -1805,7 +1824,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x1000
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x00000001
+CYDEV_INTR_RISING EQU 0x00000000
 CYDEV_PROJ_TYPE EQU 0
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
 CYDEV_PROJ_TYPE_LOADABLE EQU 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c

@@ -26,131 +26,276 @@ __attribute__ ((__section__(".cyconfigecc"), used))
 #error "Unsupported toolchain"
 #endif
 const uint8 cy_meta_configecc[] = {
-    0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,
-    0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,
-    0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,
-    0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,
-    0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,
-    0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,
-    0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,
-    0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,
-    0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,
-    0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,
-    0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,
-    0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,
-    0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,
-    0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,
-    0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,
-    0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,
-    0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,
-    0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,
-    0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,
-    0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,
-    0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,
-    0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,
-    0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,
-    0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,
-    0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,
-    0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,
-    0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,
-    0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,
+    0x02u, 0x45u, 0x00u, 0x40u, 0x08u, 0x52u, 0x00u, 0x40u,
+    0x02u, 0x64u, 0x00u, 0x40u, 0x45u, 0x00u, 0x01u, 0x40u,
+    0x32u, 0x01u, 0x01u, 0x40u, 0x44u, 0x02u, 0x01u, 0x40u,
+    0x54u, 0x03u, 0x01u, 0x40u, 0x3Du, 0x04u, 0x01u, 0x40u,
+    0x5Bu, 0x05u, 0x01u, 0x40u, 0x0Bu, 0x06u, 0x01u, 0x40u,
+    0x4Eu, 0x07u, 0x01u, 0x40u, 0x10u, 0x09u, 0x01u, 0x40u,
+    0x3Cu, 0x0Au, 0x01u, 0x40u, 0x3Fu, 0x0Bu, 0x01u, 0x40u,
+    0x0Au, 0x0Du, 0x01u, 0x40u, 0x02u, 0x0Fu, 0x01u, 0x40u,
+    0x03u, 0x15u, 0x01u, 0x40u, 0x48u, 0x16u, 0x01u, 0x40u,
+    0x43u, 0x17u, 0x01u, 0x40u, 0x03u, 0x19u, 0x01u, 0x40u,
+    0x02u, 0x1Bu, 0x01u, 0x40u, 0x07u, 0x40u, 0x01u, 0x40u,
+    0x10u, 0x41u, 0x01u, 0x40u, 0x08u, 0x42u, 0x01u, 0x40u,
+    0x05u, 0x43u, 0x01u, 0x40u, 0x08u, 0x44u, 0x01u, 0x40u,
+    0x13u, 0x45u, 0x01u, 0x40u, 0x06u, 0x46u, 0x01u, 0x40u,
+    0x01u, 0x47u, 0x01u, 0x40u, 0x08u, 0x48u, 0x01u, 0x40u,
+    0x09u, 0x49u, 0x01u, 0x40u, 0x06u, 0x50u, 0x01u, 0x40u,
+    0x36u, 0x02u, 0x65u, 0x02u, 0x00u, 0xC9u, 0x01u, 0x9Cu,
+    0x18u, 0x08u, 0x19u, 0x04u, 0x1Cu, 0xE1u, 0x21u, 0x04u,
+    0x30u, 0x04u, 0x31u, 0x08u, 0x34u, 0x03u, 0x82u, 0x0Fu,
+    0x01u, 0x40u, 0x06u, 0x0Cu, 0x07u, 0x18u, 0x0Au, 0x60u,
+    0x0Cu, 0x02u, 0x0Fu, 0x20u, 0x10u, 0x90u, 0x12u, 0x48u,
+    0x14u, 0x90u, 0x16u, 0x24u, 0x17u, 0x24u, 0x19u, 0x24u,
+    0x1Au, 0x10u, 0x1Bu, 0x09u, 0x1Fu, 0x03u, 0x23u, 0x04u,
+    0x26u, 0x80u, 0x2Au, 0x90u, 0x2Cu, 0x01u, 0x2Du, 0x24u,
+    0x2Fu, 0x12u, 0x30u, 0x01u, 0x31u, 0x40u, 0x32u, 0x1Cu,
+    0x33u, 0x38u, 0x34u, 0xE0u, 0x36u, 0x02u, 0x37u, 0x07u,
+    0x3Eu, 0x41u, 0x3Fu, 0x01u, 0x58u, 0x04u, 0x59u, 0x04u,
+    0x5Bu, 0x04u, 0x5Cu, 0x99u, 0x5Fu, 0x01u, 0x85u, 0x01u,
+    0x87u, 0x2Cu, 0x88u, 0x08u, 0x89u, 0x32u, 0x8Bu, 0x01u,
+    0x8Fu, 0x08u, 0x90u, 0x04u, 0x92u, 0x02u, 0x96u, 0x03u,
+    0x97u, 0x40u, 0x98u, 0x04u, 0x99u, 0x06u, 0x9Au, 0x01u,
+    0x9Eu, 0x04u, 0xA0u, 0x08u, 0xA4u, 0x08u, 0xA5u, 0x01u,
+    0xA7u, 0x1Au, 0xAAu, 0x04u, 0xABu, 0x40u, 0xACu, 0x08u,
+    0xB2u, 0x07u, 0xB3u, 0x07u, 0xB4u, 0x08u, 0xB5u, 0x40u,
+    0xB7u, 0x38u, 0xB8u, 0x20u, 0xB9u, 0x08u, 0xBEu, 0x10u,
+    0xBFu, 0x10u, 0xD8u, 0x04u, 0xD9u, 0x0Bu, 0xDCu, 0x99u,
+    0xDFu, 0x01u, 0x01u, 0x28u, 0x03u, 0x02u, 0x05u, 0x10u,
+    0x0Au, 0x78u, 0x0Cu, 0x80u, 0x0Du, 0x10u, 0x0Eu, 0x60u,
+    0x12u, 0x0Cu, 0x13u, 0x48u, 0x14u, 0x90u, 0x16u, 0x04u,
+    0x17u, 0x40u, 0x18u, 0x40u, 0x19u, 0xA8u, 0x1Bu, 0x20u,
+    0x1Eu, 0x20u, 0x1Fu, 0x14u, 0x21u, 0x84u, 0x22u, 0x01u,
+    0x25u, 0x40u, 0x27u, 0x14u, 0x29u, 0x01u, 0x2Bu, 0x01u,
+    0x2Eu, 0x14u, 0x31u, 0x80u, 0x32u, 0x18u, 0x36u, 0x08u,
+    0x37u, 0x10u, 0x39u, 0x48u, 0x3Au, 0x08u, 0x3Bu, 0x01u,
+    0x3Du, 0x80u, 0x3Fu, 0x14u, 0x69u, 0x80u, 0x6Bu, 0x01u,
+    0x7Eu, 0x80u, 0x81u, 0x80u, 0x83u, 0x04u, 0x85u, 0x40u,
+    0x8Bu, 0x10u, 0x8Fu, 0x01u, 0xC0u, 0x47u, 0xC2u, 0xFEu,
+    0xC4u, 0xF7u, 0xCAu, 0x69u, 0xCCu, 0x6Eu, 0xCEu, 0x7Bu,
+    0xDEu, 0x80u, 0xE0u, 0x01u, 0xE2u, 0x20u, 0x04u, 0x0Fu,
+    0x05u, 0x55u, 0x06u, 0xF0u, 0x07u, 0xAAu, 0x0Bu, 0xFFu,
+    0x0Eu, 0xFFu, 0x10u, 0xFFu, 0x13u, 0xFFu, 0x15u, 0x0Fu,
+    0x16u, 0xFFu, 0x17u, 0xF0u, 0x1Du, 0x69u, 0x1Fu, 0x96u,
+    0x24u, 0x33u, 0x25u, 0x33u, 0x26u, 0xCCu, 0x27u, 0xCCu,
+    0x28u, 0x55u, 0x2Au, 0xAAu, 0x2Bu, 0xFFu, 0x2Cu, 0x96u,
+    0x2Eu, 0x69u, 0x31u, 0xFFu, 0x34u, 0xFFu, 0x3Eu, 0x10u,
+    0x3Fu, 0x01u, 0x56u, 0x02u, 0x57u, 0x2Cu, 0x58u, 0x04u,
+    0x59u, 0x04u, 0x5Bu, 0x0Bu, 0x5Du, 0x90u, 0x5Fu, 0x01u,
+    0x84u, 0x38u, 0x85u, 0x10u, 0x8Au, 0x45u, 0x8Eu, 0x38u,
+    0x90u, 0x07u, 0x92u, 0x40u, 0x94u, 0x06u, 0x96u, 0x40u,
+    0x98u, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x03u, 0x9Fu, 0x0Cu,
+    0xA0u, 0x02u, 0xA1u, 0x05u, 0xA3u, 0x0Au, 0xA6u, 0x10u,
+    0xA8u, 0x20u, 0xA9u, 0x06u, 0xABu, 0x09u, 0xACu, 0x01u,
+    0xAEu, 0x02u, 0xB0u, 0x07u, 0xB1u, 0x0Fu, 0xB2u, 0x40u,
+    0xB5u, 0x10u, 0xB6u, 0x38u, 0xBEu, 0x44u, 0xBFu, 0x11u,
+    0xD4u, 0x40u, 0xD8u, 0x04u, 0xD9u, 0x04u, 0xDBu, 0x0Bu,
+    0xDCu, 0x09u, 0xDDu, 0x90u, 0xDFu, 0x01u, 0x02u, 0x0Au,
+    0x03u, 0x10u, 0x05u, 0x08u, 0x07u, 0x01u, 0x0Au, 0x64u,
+    0x0Bu, 0x02u, 0x0Cu, 0x02u, 0x0Eu, 0x20u, 0x10u, 0x01u,
+    0x12u, 0x40u, 0x13u, 0x14u, 0x15u, 0x04u, 0x16u, 0x08u,
+    0x17u, 0x80u, 0x1Au, 0x50u, 0x1Bu, 0x41u, 0x1Du, 0x10u,
+    0x20u, 0x04u, 0x23u, 0x80u, 0x27u, 0x40u, 0x28u, 0x40u,
+    0x29u, 0x20u, 0x2Du, 0x04u, 0x2Fu, 0x24u, 0x31u, 0x80u,
+    0x35u, 0x08u, 0x37u, 0x81u, 0x3Au, 0x04u, 0x3Cu, 0x20u,
+    0x3Eu, 0x08u, 0x61u, 0x20u, 0x63u, 0x21u, 0x67u, 0x80u,
+    0x6Cu, 0x20u, 0x6Du, 0x91u, 0x6Fu, 0x02u, 0x76u, 0x02u,
+    0x77u, 0x02u, 0x78u, 0x02u, 0x7Au, 0x03u, 0x7Eu, 0x80u,
+    0x81u, 0x20u, 0x82u, 0x04u, 0x83u, 0x40u, 0x84u, 0x80u,
+    0x86u, 0x10u, 0x88u, 0x10u, 0x8Eu, 0x40u, 0x90u, 0x40u,
+    0x91u, 0x80u, 0x92u, 0x02u, 0x93u, 0x08u, 0x95u, 0x60u,
+    0x96u, 0x6Cu, 0x97u, 0x14u, 0x98u, 0x01u, 0x99u, 0x88u,
+    0x9Au, 0x08u, 0x9Bu, 0x11u, 0x9Cu, 0x90u, 0x9Du, 0x11u,
+    0x9Fu, 0x48u, 0xA1u, 0x80u, 0xA2u, 0x10u, 0xA3u, 0x20u,
+    0xA4u, 0x80u, 0xA6u, 0x88u, 0xA7u, 0x01u, 0xAFu, 0x01u,
+    0xB0u, 0x01u, 0xB3u, 0x40u, 0xB7u, 0x02u, 0xC0u, 0xA7u,
+    0xC2u, 0x3Fu, 0xC4u, 0xEFu, 0xCAu, 0x65u, 0xCCu, 0xD8u,
+    0xCEu, 0x62u, 0xD8u, 0x8Eu, 0xDEu, 0x81u, 0xE2u, 0x01u,
+    0xE4u, 0x08u, 0xE6u, 0x03u, 0xE8u, 0x02u, 0x00u, 0x03u,
+    0x0Au, 0x01u, 0x0Fu, 0x08u, 0x15u, 0x28u, 0x17u, 0x44u,
+    0x19u, 0x2Cu, 0x1Bu, 0x81u, 0x1Eu, 0x03u, 0x1Fu, 0x03u,
+    0x20u, 0x03u, 0x24u, 0x03u, 0x27u, 0x80u, 0x28u, 0x03u,
+    0x2Bu, 0x04u, 0x2Du, 0xD4u, 0x2Fu, 0x22u, 0x30u, 0x02u,
+    0x33u, 0xE0u, 0x34u, 0x01u, 0x35u, 0x18u, 0x36u, 0x02u,
+    0x37u, 0x07u, 0x3Bu, 0x30u, 0x3Eu, 0x51u, 0x40u, 0x64u,
+    0x41u, 0x02u, 0x42u, 0x30u, 0x45u, 0xE2u, 0x46u, 0x0Du,
+    0x47u, 0xCFu, 0x48u, 0x37u, 0x49u, 0xFFu, 0x4Au, 0xFFu,
+    0x4Bu, 0xFFu, 0x4Fu, 0x2Cu, 0x56u, 0x01u, 0x58u, 0x04u,
+    0x59u, 0x04u, 0x5Au, 0x04u, 0x5Bu, 0x04u, 0x5Cu, 0x90u,
+    0x5Du, 0x09u, 0x5Fu, 0x01u, 0x62u, 0xC0u, 0x66u, 0x80u,
+    0x68u, 0x40u, 0x69u, 0x40u, 0x6Eu, 0x08u, 0x88u, 0x01u,
+    0x8Au, 0x06u, 0x94u, 0x05u, 0x96u, 0x02u, 0x98u, 0x03u,
+    0x9Au, 0x04u, 0x9Cu, 0x04u, 0x9Eu, 0x03u, 0xB6u, 0x07u,
+    0xBAu, 0x80u, 0xD8u, 0x0Bu, 0xDCu, 0x09u, 0xDFu, 0x01u,
+    0x01u, 0x01u, 0x02u, 0x04u, 0x05u, 0x10u, 0x09u, 0x40u,
+    0x0Eu, 0x01u, 0x0Fu, 0x14u, 0x10u, 0x20u, 0x11u, 0x10u,
+    0x13u, 0x02u, 0x19u, 0x42u, 0x1Bu, 0x10u, 0x1Eu, 0x01u,
+    0x1Fu, 0x40u, 0x21u, 0x10u, 0x22u, 0x58u, 0x23u, 0x20u,
+    0x29u, 0x04u, 0x2Au, 0x20u, 0x2Bu, 0x01u, 0x30u, 0x40u,
+    0x32u, 0x58u, 0x39u, 0x80u, 0x41u, 0x10u, 0x42u, 0x50u,
+    0x48u, 0x40u, 0x49u, 0x04u, 0x4Au, 0x08u, 0x51u, 0x08u,
+    0x52u, 0x40u, 0x53u, 0x01u, 0x59u, 0xA8u, 0x5Au, 0x02u,
+    0x60u, 0x64u, 0x61u, 0x80u, 0x69u, 0x40u, 0x6Au, 0x08u,
+    0x6Bu, 0x88u, 0x70u, 0x90u, 0x71u, 0x01u, 0x72u, 0x20u,
+    0x7Eu, 0x80u, 0x81u, 0x08u, 0x83u, 0x01u, 0x85u, 0x80u,
+    0x88u, 0x20u, 0x89u, 0x10u, 0x8Cu, 0x10u, 0x8Eu, 0x40u,
+    0x90u, 0x44u, 0x91u, 0x91u, 0x92u, 0x52u, 0x95u, 0x60u,
+    0x96u, 0x2Cu, 0x97u, 0x97u, 0x99u, 0x80u, 0x9Au, 0x02u,
+    0x9Bu, 0x02u, 0x9Cu, 0x42u, 0x9Du, 0x01u, 0x9Eu, 0x40u,
+    0x9Fu, 0x08u, 0xA0u, 0x20u, 0xA1u, 0x40u, 0xA3u, 0x23u,
+    0xA4u, 0x90u, 0xA5u, 0x20u, 0xA6u, 0x89u, 0xA7u, 0x10u,
+    0xABu, 0x80u, 0xAFu, 0x20u, 0xB0u, 0x12u, 0xB5u, 0x08u,
+    0xB6u, 0x08u, 0xC0u, 0x4Au, 0xC2u, 0xE1u, 0xC4u, 0x0Eu,
+    0xCAu, 0x0Eu, 0xCCu, 0x0Eu, 0xCEu, 0x08u, 0xD0u, 0x07u,
+    0xD2u, 0x04u, 0xD6u, 0x0Fu, 0xD8u, 0x0Fu, 0xDEu, 0x80u,
+    0xE0u, 0x01u, 0xE2u, 0x10u, 0xE4u, 0x04u, 0xE6u, 0x02u,
+    0xE8u, 0x01u, 0xEAu, 0x50u, 0xEEu, 0x80u, 0x10u, 0x04u,
+    0x12u, 0x02u, 0x16u, 0x03u, 0x18u, 0x04u, 0x1Au, 0x01u,
+    0x2Au, 0x04u, 0x2Eu, 0x04u, 0x32u, 0x07u, 0x58u, 0x04u,
+    0x5Cu, 0x09u, 0x5Fu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,
+    0x03u, 0x0Au, 0x09u, 0x08u, 0x0Au, 0x84u, 0x0Du, 0x10u,
+    0x0Eu, 0x60u, 0x10u, 0x22u, 0x11u, 0x12u, 0x13u, 0x02u,
+    0x17u, 0xA0u, 0x18u, 0x20u, 0x1Cu, 0x20u, 0x1Eu, 0x20u,
+    0x20u, 0x40u, 0x21u, 0x04u, 0x22u, 0x40u, 0x2Au, 0x82u,
+    0x2Bu, 0x16u, 0x30u, 0x22u, 0x31u, 0x08u, 0x32u, 0x40u,
+    0x38u, 0x60u, 0x39u, 0x01u, 0x3Bu, 0x04u, 0x41u, 0x08u,
+    0x42u, 0x04u, 0x43u, 0x01u, 0x48u, 0x04u, 0x49u, 0x48u,
+    0x50u, 0x42u, 0x51u, 0x20u, 0x52u, 0x45u, 0x58u, 0x80u,
+    0x60u, 0x02u, 0x62u, 0x80u, 0x78u, 0x02u, 0x91u, 0x31u,
+    0x92u, 0x40u, 0x96u, 0x04u, 0x97u, 0x14u, 0x98u, 0x80u,
+    0x99u, 0x42u, 0x9Au, 0x02u, 0x9Bu, 0xA2u, 0x9Cu, 0x02u,
+    0x9Du, 0x10u, 0x9Eu, 0x04u, 0xA0u, 0x20u, 0xA1u, 0x40u,
+    0xA3u, 0x02u, 0xA4u, 0x10u, 0xA5u, 0x20u, 0xA6u, 0x81u,
+    0xA8u, 0x80u, 0xA9u, 0x08u, 0xAAu, 0x04u, 0xABu, 0x01u,
+    0xACu, 0x50u, 0xADu, 0x20u, 0xB2u, 0x40u, 0xB5u, 0x40u,
+    0xB6u, 0x08u, 0xB7u, 0x20u, 0xC0u, 0x0Fu, 0xC2u, 0x7Eu,
+    0xC4u, 0xCFu, 0xCAu, 0x0Fu, 0xCCu, 0x0Fu, 0xCEu, 0x0Fu,
+    0xD0u, 0x07u, 0xD2u, 0x0Cu, 0xD6u, 0x08u, 0xD8u, 0x08u,
+    0xDEu, 0x01u, 0xE4u, 0x40u, 0xE8u, 0x0Au, 0xEEu, 0x07u,
+    0x8Eu, 0x01u, 0x9Eu, 0x41u, 0xA4u, 0x02u, 0xA8u, 0x41u,
+    0xABu, 0x08u, 0xAEu, 0x09u, 0xAFu, 0x82u, 0xB2u, 0x01u,
+    0xB4u, 0x41u, 0xB5u, 0x10u, 0xB6u, 0x20u, 0xB7u, 0x04u,
+    0xE4u, 0x40u, 0xE8u, 0x40u, 0xEAu, 0x01u, 0xECu, 0xD0u,
+    0x00u, 0x01u, 0x01u, 0x33u, 0x03u, 0xCCu, 0x08u, 0x02u,
+    0x0Fu, 0xFFu, 0x11u, 0x96u, 0x13u, 0x69u, 0x17u, 0xFFu,
+    0x1Du, 0x55u, 0x1Fu, 0xAAu, 0x21u, 0xFFu, 0x29u, 0x0Fu,
+    0x2Bu, 0xF0u, 0x34u, 0x01u, 0x35u, 0xFFu, 0x36u, 0x02u,
+    0x3Eu, 0x50u, 0x3Fu, 0x10u, 0x58u, 0x04u, 0x59u, 0x04u,
+    0x5Fu, 0x01u, 0x82u, 0x02u, 0x85u, 0x33u, 0x86u, 0x80u,
+    0x87u, 0xCCu, 0x88u, 0x80u, 0x8Au, 0x40u, 0x8Bu, 0xFFu,
+    0x8Eu, 0x08u, 0x91u, 0xFFu, 0x92u, 0x04u, 0x94u, 0x06u,
+    0x95u, 0x0Fu, 0x96u, 0x08u, 0x97u, 0xF0u, 0x98u, 0x80u,
+    0x9Au, 0x20u, 0x9Du, 0x55u, 0x9Eu, 0x60u, 0x9Fu, 0xAAu,
+    0xA0u, 0x02u, 0xA2u, 0x04u, 0xA4u, 0x10u, 0xA9u, 0x69u,
+    0xAAu, 0x80u, 0xABu, 0x96u, 0xACu, 0x01u, 0xADu, 0xFFu,
+    0xB0u, 0x01u, 0xB2u, 0x0Eu, 0xB4u, 0x10u, 0xB6u, 0xE0u,
+    0xB7u, 0xFFu, 0xBEu, 0x15u, 0xBFu, 0x40u, 0xD8u, 0x04u,
+    0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u, 0xDFu, 0x01u,
+    0x00u, 0x01u, 0x01u, 0x20u, 0x06u, 0x61u, 0x07u, 0x08u,
+    0x0Cu, 0x02u, 0x0Eu, 0x22u, 0x0Fu, 0x04u, 0x15u, 0x80u,
+    0x16u, 0x10u, 0x17u, 0x11u, 0x1Au, 0x0Au, 0x1Cu, 0x48u,
+    0x1Eu, 0x02u, 0x1Fu, 0x08u, 0x22u, 0x20u, 0x26u, 0x40u,
+    0x28u, 0x08u, 0x29u, 0x02u, 0x2Cu, 0x08u, 0x2Fu, 0x02u,
+    0x31u, 0x02u, 0x32u, 0x08u, 0x33u, 0x40u, 0x34u, 0x08u,
+    0x35u, 0x02u, 0x37u, 0x40u, 0x38u, 0x82u, 0x3Du, 0x20u,
+    0x3Fu, 0x08u, 0x5Du, 0x08u, 0x5Eu, 0x01u, 0x5Fu, 0xA0u,
+    0x6Eu, 0x20u, 0x6Fu, 0x01u, 0x81u, 0x28u, 0x83u, 0x20u,
+    0x84u, 0x04u, 0x8Au, 0x04u, 0x8Bu, 0x04u, 0x8Du, 0x40u,
+    0x8Fu, 0x10u, 0x98u, 0x08u, 0x99u, 0x02u, 0x9Au, 0x10u,
+    0x9Bu, 0x48u, 0xA0u, 0x08u, 0xA1u, 0x02u, 0xA6u, 0x61u,
+    0xA8u, 0x08u, 0xA9u, 0x02u, 0xB4u, 0x08u, 0xB7u, 0x40u,
+    0xC0u, 0xFAu, 0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0x35u,
+    0xCCu, 0xDBu, 0xCEu, 0x69u, 0xD6u, 0xF0u, 0xE2u, 0x80u,
+    0xE4u, 0x60u, 0xE6u, 0x01u, 0xE8u, 0x50u, 0x82u, 0x01u,
+    0x85u, 0x02u, 0x86u, 0x30u, 0x8Au, 0x40u, 0x8Fu, 0x08u,
+    0xE2u, 0x23u, 0xE4u, 0x40u, 0xE8u, 0x02u, 0xEAu, 0x20u,
+    0xEEu, 0x60u, 0xE0u, 0x01u, 0xE6u, 0x10u, 0xA8u, 0x40u,
+    0xABu, 0x20u, 0xECu, 0x80u, 0x00u, 0xD0u, 0x04u, 0x24u,
+    0x06u, 0x43u, 0x08u, 0x11u, 0x0Au, 0x22u, 0x0Cu, 0xD0u,
+    0x10u, 0x20u, 0x12u, 0xD0u, 0x14u, 0x28u, 0x16u, 0x83u,
+    0x18u, 0xD0u, 0x1Eu, 0x0Cu, 0x20u, 0xD0u, 0x26u, 0x01u,
+    0x28u, 0xD0u, 0x2Eu, 0x02u, 0x30u, 0xF0u, 0x36u, 0x0Fu,
+    0x3Au, 0x02u, 0x58u, 0x0Bu, 0x5Cu, 0x09u, 0x5Fu, 0x01u,
+    0x80u, 0x38u, 0x81u, 0x46u, 0x84u, 0x43u, 0x85u, 0x39u,
+    0x86u, 0x3Cu, 0x87u, 0x06u, 0x88u, 0x48u, 0x8Au, 0x20u,
+    0x8Bu, 0x46u, 0x8Du, 0x04u, 0x8Fu, 0x20u, 0x90u, 0x38u,
+    0x94u, 0x61u, 0x95u, 0x01u, 0x96u, 0x1Eu, 0x97u, 0x5Eu,
+    0x98u, 0x23u, 0x99u, 0x42u, 0x9Au, 0x44u, 0x9Bu, 0x04u,
+    0x9Cu, 0x18u, 0x9Eu, 0x20u, 0xA0u, 0x10u, 0xA1u, 0x46u,
+    0xA4u, 0x28u, 0xA5u, 0x42u, 0xA6u, 0x10u, 0xA8u, 0x20u,
+    0xA9u, 0x77u, 0xAAu, 0x18u, 0xABu, 0x08u, 0xADu, 0x46u,
+    0xB1u, 0x08u, 0xB2u, 0x60u, 0xB3u, 0x70u, 0xB4u, 0x1Eu,
+    0xB5u, 0x0Fu, 0xB6u, 0x01u, 0xB9u, 0x20u, 0xBAu, 0x08u,
+    0xBBu, 0x0Cu, 0xBEu, 0x40u, 0xBFu, 0x01u, 0xD4u, 0x09u,
     0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,
-    0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,
-    0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,
-    0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,
-    0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,
-    0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,
-    0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,
-    0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,
-    0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,
-    0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,
-    0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,
-    0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,
-    0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,
-    0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,
-    0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,
-    0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,
-    0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,
-    0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,
-    0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,
-    0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,
-    0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,
-    0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,
-    0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,
-    0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,
-    0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,
-    0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,
-    0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,
-    0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,
-    0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,
-    0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,
-    0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,
-    0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,
-    0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,
-    0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,
-    0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,
-    0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,
-    0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,
-    0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,
-    0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,
-    0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,
-    0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,
-    0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,
-    0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,
-    0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,
-    0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,
-    0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,
-    0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,
-    0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,
-    0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,
-    0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,
-    0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,
-    0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,
-    0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,
-    0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,
-    0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,
-    0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,
-    0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,
-    0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,
-    0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,
-    0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,
-    0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,
-    0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,
-    0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,
-    0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,
-    0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,
-    0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,
-    0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,
-    0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,
-    0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,
-    0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,
-    0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,
-    0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,
-    0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,
-    0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,
-    0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,
-    0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,
-    0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,
-    0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,
-    0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,
-    0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,
-    0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
-    0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,
-    0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,
+    0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,
+    0x03u, 0x08u, 0x04u, 0x04u, 0x05u, 0x10u, 0x06u, 0x80u,
+    0x07u, 0x02u, 0x09u, 0x49u, 0x0Au, 0x04u, 0x0Cu, 0x20u,
+    0x0Eu, 0x42u, 0x0Fu, 0x10u, 0x10u, 0x20u, 0x11u, 0x10u,
+    0x12u, 0x40u, 0x15u, 0x19u, 0x16u, 0x01u, 0x19u, 0x54u,
+    0x1Au, 0x04u, 0x1Bu, 0x1Cu, 0x1Eu, 0x42u, 0x20u, 0x0Cu,
+    0x21u, 0x08u, 0x23u, 0x94u, 0x29u, 0x14u, 0x2Au, 0x02u,
+    0x2Bu, 0x02u, 0x30u, 0x20u, 0x31u, 0x08u, 0x38u, 0x80u,
+    0x39u, 0x11u, 0x3Bu, 0x04u, 0x59u, 0x0Au, 0x5Bu, 0xA0u,
+    0x61u, 0x40u, 0x78u, 0x02u, 0x7Eu, 0x80u, 0x8Bu, 0x01u,
+    0x90u, 0x80u, 0x91u, 0x19u, 0x96u, 0x04u, 0x97u, 0x14u,
+    0x98u, 0x02u, 0x99u, 0x0Au, 0x9Au, 0xC3u, 0x9Bu, 0x02u,
+    0x9Du, 0x10u, 0x9Fu, 0x01u, 0xA0u, 0x20u, 0xA1u, 0x41u,
+    0xA2u, 0x80u, 0xA3u, 0x02u, 0xA4u, 0x04u, 0xA5u, 0x08u,
+    0xA6u, 0x01u, 0xA7u, 0x1Cu, 0xC0u, 0xFEu, 0xC2u, 0xFFu,
+    0xC4u, 0xFEu, 0xCAu, 0x0Fu, 0xCCu, 0x06u, 0xCEu, 0x0Fu,
+    0xD6u, 0x0Fu, 0xD8u, 0x08u, 0xDEu, 0x81u, 0xE4u, 0x20u,
+    0xECu, 0x80u, 0xA4u, 0x02u, 0xB2u, 0x40u, 0xECu, 0x80u,
+    0xB0u, 0x02u, 0xECu, 0x80u, 0x58u, 0x10u, 0x80u, 0x80u,
+    0x86u, 0x80u, 0x88u, 0x10u, 0xD4u, 0x80u, 0xE2u, 0x40u,
+    0xE6u, 0x80u, 0x53u, 0x81u, 0x57u, 0x0Au, 0x59u, 0x04u,
+    0x5Cu, 0x02u, 0x60u, 0x08u, 0x64u, 0x80u, 0x81u, 0x04u,
+    0x82u, 0x40u, 0x84u, 0x08u, 0x98u, 0x80u, 0x9Au, 0x80u,
+    0xD4u, 0xE0u, 0xD6u, 0xE0u, 0xD8u, 0xC0u, 0xE2u, 0x20u,
+    0xE6u, 0x90u, 0x8Cu, 0x02u, 0x92u, 0x40u, 0x9Au, 0x80u,
+    0x9Cu, 0x02u, 0xAFu, 0x80u, 0xB3u, 0x02u, 0xB7u, 0x09u,
+    0xEEu, 0x10u, 0x23u, 0x08u, 0x8Fu, 0x08u, 0x92u, 0x40u,
+    0x9Au, 0x80u, 0xC8u, 0x10u, 0x0Cu, 0x01u, 0x51u, 0x02u,
+    0x54u, 0x20u, 0x80u, 0x20u, 0x8Cu, 0x40u, 0xC2u, 0x04u,
+    0xD4u, 0x03u, 0xE6u, 0x08u, 0x02u, 0x04u, 0x03u, 0x10u,
+    0x04u, 0x80u, 0x07u, 0x40u, 0x09u, 0x02u, 0x0Bu, 0x01u,
+    0x0Cu, 0x18u, 0x80u, 0x08u, 0x85u, 0x02u, 0x94u, 0x80u,
+    0x9Cu, 0x10u, 0x9Fu, 0x10u, 0xADu, 0x02u, 0xB0u, 0x11u,
+    0xB7u, 0x10u, 0xC0u, 0x0Fu, 0xC2u, 0x0Fu, 0xEAu, 0x04u,
+    0xEEu, 0x06u, 0x83u, 0x40u, 0x8Eu, 0x04u, 0x93u, 0x01u,
+    0x9Au, 0x04u, 0x9Bu, 0x40u, 0xE6u, 0x08u, 0xABu, 0x01u,
+    0x23u, 0x10u, 0x27u, 0x08u, 0x88u, 0x01u, 0x92u, 0x40u,
+    0x97u, 0x10u, 0x9Au, 0x80u, 0xB3u, 0x10u, 0xC8u, 0x60u,
+    0x08u, 0x01u, 0x56u, 0x80u, 0x5Au, 0x40u, 0x92u, 0x40u,
+    0x9Au, 0x80u, 0x9Cu, 0x01u, 0xB3u, 0x08u, 0xC2u, 0x10u,
+    0xD4u, 0xC0u, 0x01u, 0x01u, 0x09u, 0x01u, 0x0Bu, 0x01u,
+    0x0Du, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x00u,
+    0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x08u, 0xFFu, 0x21u,
+    0x80u, 0x40u, 0x00u, 0x00u, 0x90u, 0x40u, 0x40u, 0x00u,
+    0x00u, 0x10u, 0x60u, 0x80u, 0x7Fu, 0x22u, 0x80u, 0x08u,
+    0x1Fu, 0x01u, 0x20u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u,
+    0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x07u, 0x04u, 0x18u,
+    0xC0u, 0x01u, 0x08u, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u,
+    0x00u, 0x3Fu, 0xFFu, 0x80u, 0x00u, 0x00u, 0x00u, 0x40u,
+    0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u,
+    0x63u, 0x02u, 0x50u, 0x00u, 0x04u, 0x0Eu, 0xFCu, 0xBDu,
+    0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+    0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u,
+    0x04u, 0x0Bu, 0x0Bu, 0x04u, 0x90u, 0x99u, 0x00u, 0x01u,
     0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,
     0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0xFFu, 0xFFu, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,
     0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,
     0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x01u
+    0x00u, 0xFCu, 0xFCu, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u,
+    0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,
+    0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u
 };
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
@@ -175,6 +320,272 @@ const uint8 cy_meta_wonvl[] = {
     0xBCu, 0x90u, 0xACu, 0xAFu
 };
 
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cyeeprom"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cyeeprom"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_eeprom[] = {
+    0x00u, 0x20u, 0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u,
+    0x63u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u,
+    0x20u, 0x20u, 0x53u, 0x43u, 0x53u, 0x49u, 0x32u, 0x53u,
+    0x44u, 0x32u, 0x2Eu, 0x30u, 0x61u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u, 0x63u, 0x5Fu,
+    0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x31u,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,
+    0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu
+};
+
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
 __attribute__ ((__section__(".cyflashprotect"), used))
 #elif defined(__ICCARM__)

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex

@@ -0,0 +1,33 @@
+:400000000020636F646573726320202020202020202053435349325344322E30610000000000000000000000000000000000000000000000000000000000000000000000B1
+:40004000636F64657372635F3030303030303031FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED
+:40008000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80
+:4000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40
+:40010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+:40014000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF
+:40018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F
+:4001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F
+:40020000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
+:40024000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE
+:40028000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7E
+:4002C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E
+:40030000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD
+:40034000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBD
+:40038000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D
+:4003C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D
+:40040000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC
+:40044000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBC
+:40048000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C
+:4004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C
+:40050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB
+:40054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB
+:40058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
+:4005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:40060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
+:40064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:40068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:4006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:40070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
+:40074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
+:40078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79
+:4007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39
+:00000001FF

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/post_link.bat

@@ -1,19 +0,0 @@
-@REM This script allows a 3rd party IDE to use CyHexTool to perform
-@REM any post processing that is necessary to convert the raw flash
-@REM image into a complete hex file to use in programming the PSoC.
-@REM USAGE: post_link.bat
-@REM    arg1: Persistant path back to the directory containing the app project.
-@REM    arg2: Path (relative to arg1) of the directory where the hex files go.
-@REM    arg3: Name of the project.
-@REM NOTE: This script is auto generated. Do not modify.
-
-"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyvalidateide.exe" -dev CY8C5268AXI-LP047 -ide "%~1\%~3" -flsAddr 0x0 -flsSize 0x40000 -sramAddr 0x1FFF8000 -sramSize 0x10000
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% 
-move "%~1\%~2\%~n3.hex" "%~1\%~2\%~n3.ihx"
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% 
-"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyhextool" -o "%~1\%~2\%~n3.hex" -f "%~1\%~2\%~n3.ihx" -prot "%~dp0protect.hex" -id 2E12F069 -a EEPROM=90200000:800,PROGRAM=00000000:40000,CONFIG=80000000:8000,PROTECT=90400000:100 -meta 0001 -cunv 00004005 -wonv BC90ACAF -ecc "%~dp0config.hex" 
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% 
-CD /D "C:\Keil\UV4"
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% 
-IF NOT EXIST "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.svd" rem "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.sfr"
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -23,40 +23,39 @@
 #include <SCSI_In_DBx.h>
 #include <SCSI_Out_DBx_aliases.h>
 #include <SCSI_Out_DBx.h>
-#include <SDCard.h>
-#include <SDCard_PVT.h>
-#include <SD_MISO_aliases.h>
-#include <SD_MISO.h>
-#include <SD_MOSI_aliases.h>
-#include <SD_MOSI.h>
-#include <SD_SCK_aliases.h>
-#include <SD_SCK.h>
-#include <SD_CS_aliases.h>
-#include <SD_CS.h>
-#include <SD_DAT1_aliases.h>
-#include <SD_DAT1.h>
-#include <SD_DAT2_aliases.h>
-#include <SD_DAT2.h>
-#include <SD_WP_aliases.h>
-#include <SD_WP.h>
+#include <SD_Clk_Ctl.h>
+#include <SD_Data_Clk.h>
+#include <SD_Init_Clk.h>
 #include <SD_CD_aliases.h>
 #include <SD_CD.h>
-#include <SCSI_ID_aliases.h>
-#include <PARITY_EN_aliases.h>
-#include <PARITY_EN.h>
+#include <SD_WP_aliases.h>
+#include <SD_WP.h>
+#include <SD_DAT2_aliases.h>
+#include <SD_DAT2.h>
+#include <SD_DAT1_aliases.h>
+#include <SD_DAT1.h>
+#include <SCSI_CTL_IO.h>
 #include <SCSI_In_aliases.h>
 #include <SCSI_Out_aliases.h>
-#include <LED1_aliases.h>
-#include <LED1.h>
-#include <SD_Init_Clk.h>
-#include <SD_Data_Clk.h>
-#include <SD_Clk_Ctl.h>
+#include <CFG_EEPROM.h>
+#include <SD_CS_aliases.h>
+#include <SD_CS.h>
+#include <SD_SCK_aliases.h>
+#include <SD_SCK.h>
+#include <SD_MOSI_aliases.h>
+#include <SD_MOSI.h>
 #include <SCSI_RST_aliases.h>
 #include <SCSI_RST.h>
 #include <SCSI_ATN_aliases.h>
 #include <SCSI_ATN.h>
 #include <SCSI_RST_ISR.h>
 #include <SCSI_ATN_ISR.h>
+#include <LED1_aliases.h>
+#include <LED1.h>
+#include <SDCard.h>
+#include <SDCard_PVT.h>
+#include <SD_MISO_aliases.h>
+#include <SD_MISO.h>
 #include <core_cm3_psoc5.h>
 #include <core_cm3.h>
 #include <CyDmac.h>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml

@@ -1,208 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
-<PSoCCreatorIdeExport Version="1">
-  <Device Part="CY8C5268AXI-LP047" Processor="CortexM3" DeviceID="2E12F069" />
-  <Toolchains>
-    <Toolchain Name="ARM GCC" Selected="True">
-      <Tool Name="prebuild" Command="" Options="" />
-      <Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
-      <Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />
-      <Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
-      <Tool Name="postbuild" Command="" Options="" />
-    </Toolchain>
-    <Toolchain Name="ARM Keil MDK" Selected="False">
-      <Tool Name="prebuild" Command="" Options="" />
-      <Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
-      <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
-      <Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
-      <Tool Name="postbuild" Command="" Options="" />
-    </Toolchain>
-  </Toolchains>
-  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" Version="4.0" Type="Normal">
-    <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
-    <Datasheet>SCSI2SD_datasheet.pdf</Datasheet>
-    <LinkerFiles>
-      <LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
-      <LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
-      <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
-    </LinkerFiles>
-    <Folders>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="">.\main.c</File>
-          <File BuildType="BUILD" Toolchain="">.\loopback.c</File>
-          <File BuildType="BUILD" Toolchain="">.\blinky.c</File>
-          <File BuildType="BUILD" Toolchain="">.\bits.c</File>
-          <File BuildType="BUILD" Toolchain="">.\device.h</File>
-          <File BuildType="BUILD" Toolchain="">.\blinky.h</File>
-          <File BuildType="BUILD" Toolchain="">.\loopback.h</File>
-          <File BuildType="BUILD" Toolchain="">.\bits.h</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="BUILD" Path="\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.c</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\led.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sense.h</File>
-          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.h</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice_trm.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu_trm.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv_trm.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfittergnu.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitterrv.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ID_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Cm3Start.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3_psoc5.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3.h</File>
-          <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\CyBootAsmGnu.s</File>
-          <File BuildType="BUILD" Toolchain="ARM RVDS">.\Generated_Source\PSoC5\CyBootAsmRv.s</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cypins.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cytypes.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyutils.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmFunc.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmInstr.h</File>
-          <File BuildType="BUILD" Toolchain="IAR EWARM">.\Generated_Source\PSoC5\CyBootAsmIar.s</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\project.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Init_Clk.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Init_Clk.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Clk_Ctl.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Clk_Ctl.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PM.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_INT.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PVT.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar_trm.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitteriar.inc</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydisabledsheets.h</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
-          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
-          <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
-        </Files>
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\codegentemp">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\DP8051">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\CortexM0">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-      <Folder BuildType="EXCLUDE" Path=".\CortexM3">
-        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
-      </Folder>
-    </Folders>
-  </Project>
-</PSoCCreatorIdeExport>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/OddParityGen/OddParityGen.v

@@ -0,0 +1,44 @@
+
+//`#start header` -- edit after this line, do not edit this line
+//	Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+//	This file is part of SCSI2SD.
+//
+//	SCSI2SD is free software: you can redistribute it and/or modify
+//	it under the terms of the GNU General Public License as published by
+//	the Free Software Foundation, either version 3 of the License, or
+//	(at your option) any later version.
+//
+//	SCSI2SD is distributed in the hope that it will be useful,
+//	but WITHOUT ANY WARRANTY; without even the implied warranty of
+//	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//	GNU General Public License for more details.
+//
+//	You should have received a copy of the GNU General Public License
+//	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 10/15/2013 at 22:01
+// Component: OddParityGen
+module OddParityGen (
+	output  DBP,
+	input  [7:0] DBx,
+	input   EN
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+	// For some reason the "simple" implementation uses up about 34% of all
+	// PLD resources on a PSoC 5LP
+	// 1 ^ DBx[0] ^ DBx[1] ^ DBx[2] ^ DBx[3] ^ DBx[4] ^ DBx[5] ^ DBx[6] ^ DBx[7]
+
+	// Breaking the expression up into parts seems to use much less resources.
+	wire tmp = 1 ^ DBx[0];
+	wire tmpa = DBx[1] ^ DBx[2];
+	wire tmpb = DBx[3] ^ DBx[4];
+	wire tmpc = DBx[5] ^ DBx[6] ^ DBx[7];
+	assign DBP = EN ? tmp ^ tmpa ^ tmpb ^ tmpc : 0;
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="utf-8"?>
+<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
+  <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  </block>
+  <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_ATN_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+  </block>
+  <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_Overclock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />
+  </block>
+  <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+</blockRegMap>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -102,6 +102,13 @@
 <build_action v="C_FILE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="config.c" persistent=".\config.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -217,6 +224,13 @@
 <build_action v="NONE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="config.h" persistent=".\config.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -841,14 +855,14 @@
 <CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ID" persistent="">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
 <dependencies>
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ID_aliases.h" persistent=".\Generated_Source\PSoC5\SCSI_ID_aliases.h">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="NONE" />
 <PropertyDeltas />
@@ -862,14 +876,14 @@
 <CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="PARITY_EN" persistent="">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
 <dependencies>
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="PARITY_EN_aliases.h" persistent=".\Generated_Source\PSoC5\PARITY_EN_aliases.h">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="NONE" />
 <PropertyDeltas />
@@ -878,7 +892,7 @@
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="PARITY_EN.c" persistent=".\Generated_Source\PSoC5\PARITY_EN.c">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="ARM_C_FILE" />
 <PropertyDeltas />
@@ -887,7 +901,7 @@
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="PARITY_EN.h" persistent=".\Generated_Source\PSoC5\PARITY_EN.h">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="NONE" />
 <PropertyDeltas />
@@ -1594,6 +1608,156 @@
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="CFG_EEPROM" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="CFG_EEPROM.c" persistent=".\Generated_Source\PSoC5\CFG_EEPROM.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="CFG_EEPROM.h" persistent=".\Generated_Source\PSoC5\CFG_EEPROM.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_IO" persistent="">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_IO.c" persistent=".\Generated_Source\PSoC5\SCSI_REG_IO.c">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_IO.h" persistent=".\Generated_Source\PSoC5\SCSI_REG_IO.h">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_DBx" persistent="">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_DBx.c" persistent=".\Generated_Source\PSoC5\SCSI_REG_DBx.c">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_REG_DBx.h" persistent=".\Generated_Source\PSoC5\SCSI_REG_DBx.h">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_PHY_CTL" persistent="">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_PHY_CTL.c" persistent=".\Generated_Source\PSoC5\SCSI_PHY_CTL.c">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_PHY_CTL.h" persistent=".\Generated_Source\PSoC5\SCSI_PHY_CTL.h">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.h" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -1608,6 +1772,66 @@
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>
 </CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d>
+<CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponent" version="1">
+<CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhyFolder" version="1">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen" persistent=".\OddParityGen">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen.cysym" persistent=".\OddParityGen\OddParityGen.cysym">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen.v" persistent=".\OddParityGen\OddParityGen.v">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>
+</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>
+<CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponent" version="1">
+<CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhyFolder" version="1">
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget" persistent=".\scsiTarget">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget.cysym" persistent=".\scsiTarget\scsiTarget.cysym">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget.v" persistent=".\scsiTarget\scsiTarget.v">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>
+</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -1803,6 +2027,6 @@
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
 <boot_component v="cy_boot_v4_0" />
 <BootloaderTag hexFile="" elfFile="" />
-<current_generation v="0" />
+<current_generation v="2" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd

@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+  <name>CY8C5268AXI_LP047</name>
+  <version>0.1</version>
+  <description>CY8C52LP</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <peripherals>
+    <peripheral>
+      <name>SD_Clk_Ctl</name>
+      <description>No description available</description>
+      <baseAddress>0x4000647B</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SD_Clk_Ctl_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SCSI_CTL_IO</name>
+      <description>No description available</description>
+      <baseAddress>0x40006470</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x1</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCSI_CTL_IO_CONTROL_REG</name>
+          <description>No description available</description>
+          <addressOffset>0x0</addressOffset>
+          <size>8</size>
+          <access>read-write</access>
+          <resetValue>0</resetValue>
+          <resetMask>0</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/config.c

@@ -0,0 +1,75 @@
+//	Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+//	This file is part of SCSI2SD.
+//
+//	SCSI2SD is free software: you can redistribute it and/or modify
+//	it under the terms of the GNU General Public License as published by
+//	the Free Software Foundation, either version 3 of the License, or
+//	(at your option) any later version.
+//
+//	SCSI2SD is distributed in the hope that it will be useful,
+//	but WITHOUT ANY WARRANTY; without even the implied warranty of
+//	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//	GNU General Public License for more details.
+//
+//	You should have received a copy of the GNU General Public License
+//	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+
+#include "device.h"
+#include "config.h"
+
+#include <string.h>
+
+// CYDEV_EEPROM_ROW_SIZE == 16.
+static char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000001";
+
+// Config shadow RAM (copy of EEPROM)
+static Config shadow =
+{
+	0, // SCSI ID
+	" codesrc", // vendor  (68k Apple Drive Setup: Set to " SEAGATE")
+	"         SCSI2SD", //prodId (68k Apple Drive Setup: Set to "          ST225N")
+	"2.0a", // revision (68k Apple Drive Setup: Set to "1.0 ")
+	1, // enable parity
+	0, // disable unit attention,
+	0, // overclock SPI
+	0, // Max blocks (0 == disabled)
+	"" // reserved
+};
+
+// Global
+Config* config = NULL;
+
+void configInit()
+{
+	// We could map cfgPtr directly into the EEPROM memory,
+	// but that would waste power. Copy it to RAM then turn off
+	// the EEPROM. 	
+	CFG_EEPROM_Start();
+	CyDelayUs(5); // 5us to start per datasheet.
+	
+	// Check magic
+	int shadowRows = (sizeof(shadow) / CYDEV_EEPROM_ROW_SIZE) + 1;
+	int shadowBytes = CYDEV_EEPROM_ROW_SIZE * shadowRows;
+	uint8* eeprom = (uint8*)CYDEV_EE_BASE;	
+	if (memcmp(eeprom + shadowBytes, magic, sizeof(magic))) 
+	{
+		CySetTemp();
+		int row;
+		int status = CYRET_SUCCESS;
+		for (row = 0; (row < shadowRows) && (status == CYRET_SUCCESS); ++row)
+		{
+			CFG_EEPROM_Write(((uint8*)&shadow) + (row * CYDEV_EEPROM_ROW_SIZE), row);
+		}
+		if (status == CYRET_SUCCESS)
+		{
+			CFG_EEPROM_Write((uint8*)magic, row);
+		}
+	}
+	else
+	{
+		memcpy(&shadow, eeprom, sizeof(shadow));
+	}
+	config = &shadow;
+	CFG_EEPROM_Stop();
+}

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/config.h

@@ -0,0 +1,41 @@
+//	Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+//	This file is part of SCSI2SD.
+//
+//	SCSI2SD is free software: you can redistribute it and/or modify
+//	it under the terms of the GNU General Public License as published by
+//	the Free Software Foundation, either version 3 of the License, or
+//	(at your option) any later version.
+//
+//	SCSI2SD is distributed in the hope that it will be useful,
+//	but WITHOUT ANY WARRANTY; without even the implied warranty of
+//	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//	GNU General Public License for more details.
+//
+//	You should have received a copy of the GNU General Public License
+//	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#ifndef Config_H
+#define Config_H
+
+#include "device.h"
+
+typedef struct
+{
+	uint8 scsiId;
+	char vendor[8];
+	char prodId[16];
+	char revision[4];
+	uint8 enableParity;
+	uint8 enableUnitAttention;
+	uint8 overclockSPI;
+	uint32 maxBlocks;
+
+	// Pad to 64 bytes, which is what we can fit into a USB HID packet.
+	char reserved[28]; 
+} Config;
+
+extern Config* config;
+
+void configInit();
+
+#endif

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/disk.c

@@ -17,6 +17,7 @@
 
 #include "device.h"
 #include "scsi.h"
+#include "config.h"
 #include "disk.h"
 #include "sd.h"
 
@@ -33,8 +34,10 @@ static int doSdInit()
 	{
 		blockDev.state = blockDev.state | DISK_INITIALISED;
 		
-		// TODO artificially limit this value according to EEPROM config.
-		blockDev.capacity = sdDev.capacity;
+		// artificially limit this value according to EEPROM config.
+		blockDev.capacity =
+			(config->maxBlocks && (sdDev.capacity > config->maxBlocks))
+				? config->maxBlocks : sdDev.capacity;
 	}
 	return result;
 }

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c

@@ -17,11 +17,12 @@
 
 #include "device.h"
 #include "scsi.h"
+#include "config.h"
 #include "inquiry.h"
 
 #include <string.h>
 
-static const uint8 StandardResponse[] =
+static uint8 StandardResponse[] =
 {
 0x00, // "Direct-access device". AKA standard hard disk
 0x00, // device type qualifier
@@ -29,16 +30,11 @@ static const uint8 StandardResponse[] =
 0x02, // SCSI-2 Inquiry response
 31, // standard length
 0, 0, //Reserved
-0, // We don't support anything at all
-/* TODO testing Apple Drive Setup. Make configurable!
-'c','o','d','e','s','r','c',' ',
-'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',
-'2','.','0','a'
-*/
-' ','S','E','A','G','A','T','E',
-' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','S','T','2','2','5','N',
-'1','.','0',' '
+0 // We don't support anything at all
 };
+// Vendor set by config 'c','o','d','e','s','r','c',' ',
+// prodId set by config'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',
+// Revision set by config'2','.','0','a'
 
 static const uint8 SupportedVitalPages[] =
 {
@@ -103,7 +99,14 @@ void scsiInquiry()
 		else
 		{
 			memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));
-			scsiDev.dataLen = sizeof(StandardResponse);
+			uint8* out = scsiDev.data + sizeof(StandardResponse);
+			memcpy(out, config->vendor, sizeof(config->vendor));
+			out += sizeof(config->vendor);
+			memcpy(out, config->prodId, sizeof(config->prodId));
+			out += sizeof(config->prodId);
+			memcpy(out, config->revision, sizeof(config->revision));
+			out += sizeof(config->revision);			
+			scsiDev.dataLen = out - scsiDev.data;
 			scsiDev.phase = DATA_IN;
 			
 			if (!lun) scsiDev.unitAttention = 0;

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/main.c

@@ -20,6 +20,7 @@
 #include "loopback.h"
 #include "scsi.h"
 #include "scsiPhy.h"
+#include "config.h"
 #include "disk.h"
 #include "led.h"
 
@@ -41,6 +42,8 @@ int main()
 	// Will not return if uncommented.
 	// scsi2sd_test_loopback();
 	
+	configInit();
+	
 	scsiInit(0, 1); // ID 0 is mac boot disk
 	scsiDiskInit();
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsi.c

@@ -18,6 +18,7 @@
 #include "device.h"
 #include "scsi.h"
 #include "scsiPhy.h"
+#include "config.h"
 #include "bits.h"
 #include "diagnostic.h"
 #include "disk.h"
@@ -64,7 +65,7 @@ static void enter_MessageIn(uint8 message)
 static void process_MessageIn()
 {
 	scsiEnterPhase(MESSAGE_IN);
-	scsiWrite(scsiDev.msgIn);
+	scsiWriteByte(scsiDev.msgIn);
 
 	if (scsiDev.atnFlag)
 	{
@@ -79,10 +80,17 @@ static void process_MessageIn()
 	else
 	{
 		// MESSAGE_REJECT. Go back to command phase
+		// TODO MESSAGE_REJECT moved to messageReject method.
 		scsiDev.phase = COMMAND;
 	}
 }
 
+static void messageReject()
+{
+	scsiEnterPhase(MESSAGE_IN);
+	scsiWriteByte(MSG_REJECT);
+}
+
 static void enter_Status(uint8 status)
 {
 	scsiDev.status = status;
@@ -92,7 +100,7 @@ static void enter_Status(uint8 status)
 static void process_Status()
 {
 	scsiEnterPhase(STATUS);
-	scsiWrite(scsiDev.status);
+	scsiWriteByte(scsiDev.status);
 
 	// Command Complete occurs AFTER a valid status has been
 	// sent. then we go bus-free.
@@ -113,13 +121,11 @@ static void process_DataIn()
 	}
 
 	scsiEnterPhase(DATA_IN);
-	while ((scsiDev.dataPtr < scsiDev.dataLen) &&
-		!scsiDev.resetFlag &&
-		!scsiDev.atnFlag)
-	{
-		scsiWrite(scsiDev.data[scsiDev.dataPtr]);
-		++scsiDev.dataPtr;
-	}
+
+	uint32 len = scsiDev.dataLen - scsiDev.dataPtr;
+	scsiWrite(scsiDev.data + scsiDev.dataPtr, len);
+	scsiDev.dataPtr += len;
+
 
 	if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
 		(transfer.currentBlock == transfer.blocks))
@@ -136,21 +142,18 @@ static void process_DataOut()
 	}
 
 	scsiEnterPhase(DATA_OUT);
-	while ((scsiDev.dataPtr < scsiDev.dataLen) &&
-		!scsiDev.resetFlag &&
-		!scsiDev.atnFlag)
-	{
-		scsiDev.parityError = 0;
-		scsiDev.data[scsiDev.dataPtr] = scsiRead();
 
-		if (scsiDev.parityError)
-		{
-			scsiDev.sense.code = ABORTED_COMMAND;
-			scsiDev.sense.asc = SCSI_PARITY_ERROR;
-			enter_Status(CHECK_CONDITION);
-			break;
-		}
-		++scsiDev.dataPtr;
+	scsiDev.parityError = 0;
+	uint32 len = scsiDev.dataLen - scsiDev.dataPtr;
+	scsiRead(scsiDev.data + scsiDev.dataPtr, len);
+	scsiDev.dataPtr += len;
+
+	// TODO re-implement parity checking
+	if (0 && scsiDev.parityError && config->enableParity)
+	{
+		scsiDev.sense.code = ABORTED_COMMAND;
+		scsiDev.sense.asc = SCSI_PARITY_ERROR;
+		enter_Status(CHECK_CONDITION);
 	}
 
 	if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
@@ -167,15 +170,11 @@ static void process_Command()
 	scsiDev.parityError = 0;
 
 	memset(scsiDev.cdb, 0, sizeof(scsiDev.cdb));
-	scsiDev.cdb[0] = scsiRead();
+	scsiDev.cdb[0] = scsiReadByte();
 
 	int group = scsiDev.cdb[0] >> 5;
 	int cmdSize = CmdGroupBytes[group];
-	int i;
-	for (i = 1; i < cmdSize; ++i)
-	{
-		scsiDev.cdb[i] = scsiRead();
-	}
+	scsiRead(scsiDev.cdb + 1, cmdSize - 1);
 
 	uint8 command = scsiDev.cdb[0];
 	uint8 lun = scsiDev.cdb[1] >> 5;
@@ -214,14 +213,13 @@ static void process_Command()
 	}
 	// Some old SCSI drivers do NOT properly support
 	// unitAttention. OTOH, Linux seems to require it
-	// TODO MAKE CONFIGURABLE.
-	/* confirmed LCIII with unknown scsi driver fials here.
-	else if (scsiDev.unitAttention)
+	// confirmed LCIII with unknown scsi driver fials here.
+	else if (scsiDev.unitAttention && config->enableUnitAttention)
 	{
 		scsiDev.sense.code = UNIT_ATTENTION;
 		scsiDev.sense.asc = scsiDev.unitAttention;
 		enter_Status(CHECK_CONDITION);
-	}*/
+	}
 	else if (lun)
 	{
 		scsiDev.sense.code = ILLEGAL_REQUEST;
@@ -319,8 +317,8 @@ static void doReserveRelease()
 static void scsiReset()
 {
 	ledOff();
-	SCSI_Out_DBx_Write(0);
-	SCSI_ClearPin(SCSI_Out_DBP);
+	// done in verilog SCSI_Out_DBx_Write(0);
+	SCSI_CTL_IO_Write(0);
 	SCSI_ClearPin(SCSI_Out_ATN);
 	SCSI_ClearPin(SCSI_Out_BSY);
 	SCSI_ClearPin(SCSI_Out_ACK);
@@ -329,11 +327,10 @@ static void scsiReset()
 	SCSI_ClearPin(SCSI_Out_REQ);
 	SCSI_ClearPin(SCSI_Out_MSG);
 	SCSI_ClearPin(SCSI_Out_CD);
-	SCSI_ClearPin(SCSI_Out_IO);
 
 	scsiDev.parityError = 0;
 	scsiDev.phase = BUS_FREE;
-	
+
 	if (scsiDev.unitAttention != POWER_ON_RESET)
 	{
 		scsiDev.unitAttention = SCSI_BUS_RESET;
@@ -354,9 +351,9 @@ static void scsiReset()
 		CyDelay(10); // 10ms.
 		reset = SCSI_ReadPin(SCSI_RST_INT);
 	} while (reset);
-	
+
 	scsiDev.resetFlag = 0;
-	scsiDev.atnFlag = 0;	
+	scsiDev.atnFlag = 0;
 }
 
 static void enter_SelectionPhase()
@@ -394,6 +391,7 @@ static void process_SelectionPhase()
 		// Wait until the end of the selection phase.
 		while (!scsiDev.resetFlag)
 		{
+			scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);
 			if (!SCSI_ReadPin(SCSI_In_SEL))
 			{
 				break;
@@ -428,7 +426,7 @@ static void process_MessageOut()
 
 	scsiDev.atnFlag = 0;
 	scsiDev.parityError = 0;
-	scsiDev.msgOut = scsiRead();
+	scsiDev.msgOut = scsiReadByte();
 
 	if (scsiDev.parityError)
 	{
@@ -437,7 +435,7 @@ static void process_MessageOut()
 		// same set of messages.
 		while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)
 		{
-			scsiRead();
+			scsiReadByte();
 		}
 
 		// Go-back and try the message again.
@@ -515,18 +513,18 @@ static void process_MessageOut()
 	else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)
 	{
 		// Two byte message. We don't support these. read and discard.
-		scsiRead();
+		scsiReadByte();
 	}
 	else if (scsiDev.msgOut == 0x01)
 	{
 		// Extended message.
-		int msgLen = scsiRead();
+		int msgLen = scsiReadByte();
 		if (msgLen == 0) msgLen = 256;
 		int i;
 		for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i)
 		{
 			// Discard bytes.
-			scsiRead();
+			scsiReadByte();
 		}
 
 		// We don't support ANY extended messages.
@@ -536,15 +534,16 @@ static void process_MessageOut()
 		// We don't support any 2-byte messages either.
 		// And we don't support any optional 1-byte messages.
 		// In each case, the correct response is MESSAGE REJECT.
-		enter_MessageIn(MSG_REJECT);
+		messageReject();
 	}
 	else
 	{
-		enter_MessageIn(MSG_REJECT);
+		messageReject();
 	}
 	
 	// Re-check the ATN flag. We won't get another interrupt if
 	// it stays asserted.
+	CyDelayUs(2); // DODGY HACK
 	scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);
 }
 
@@ -553,6 +552,7 @@ static void process_MessageOut()
 // This is a hack until I work out why the ATN ISR isn't
 // running when it should.
 static int atnErrCount = 0;
+static int atnHitCount = 0;
 static void checkATN()
 {
 	int atn = SCSI_ReadPin(SCSI_ATN_INT);
@@ -561,6 +561,10 @@ static void checkATN()
 		atnErrCount++;
 		scsiDev.atnFlag = 1;
 	}
+	else if (atn && scsiDev.atnFlag)
+	{
+		atnHitCount++;
+	}
 }
 
 void scsiPoll(void)
@@ -671,10 +675,9 @@ void scsiPoll(void)
 	}
 }
 
-void scsiInit(int scsiId, int enableParity)
+void scsiInit()
 {
-	scsiDev.scsiIdMask = 1 << scsiId;
-	scsiDev.enableParity = enableParity;
+	scsiDev.scsiIdMask = 1 << (config->scsiId);
 
 	scsiDev.atnFlag = 0;
 	scsiDev.resetFlag = 1;

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsi.h

@@ -66,7 +66,6 @@ typedef enum
 typedef struct
 {
 	uint8_t scsiIdMask;
-	int enableParity;
 
 	// Set to true (1) if the ATN flag was set, and we need to
 	// enter the MESSAGE_OUT phase.
@@ -107,7 +106,7 @@ typedef struct
 
 extern ScsiDevice scsiDev;
 
-void scsiInit(int scsiId, int enableParity);
+void scsiInit();
 void scsiPoll(void);
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c

@@ -31,72 +31,67 @@ CY_ISR_PROTO(scsiAttentionISR);
 CY_ISR(scsiAttentionISR)
 {
 	scsiDev.atnFlag = 1;
-	// Not needed when using pin value for interrupt SCSI_ATN_ClearInterrupt();
+	SCSI_ATN_ClearInterrupt();
 }
 
-// Spins until the SCSI pin is true, or the reset flag is set.
-static inline void waitForPinTrue(int pin)
+uint8 scsiReadByte(void)
 {
-	int finished = SCSI_ReadPin(pin);
-	while (!finished && !scsiDev.resetFlag)
-	{
-		finished = SCSI_ReadPin(pin);
-	}
+	while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}
+	CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);
+	while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}
+	uint8 value = CY_GET_REG8(scsiTarget_datapath__F1_REG);
+	return value;
 }
 
-// Spins until the SCSI pin is true, or the reset flag is set.
-static inline void waitForPinFalse(int pin)
+void scsiRead(uint8* data, uint32 count)
 {
-	int finished = !SCSI_ReadPin(pin);
-	while (!finished && !scsiDev.resetFlag)
+	int prep = 0;
+	int i = 0;
+
+	while (i < count)
 	{
-		finished = !SCSI_ReadPin(pin);
+		if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))
+		{
+			CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);
+			++prep;
+		}
+		if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))
+		{
+			data[i] =  CY_GET_REG8(scsiTarget_datapath__F1_REG);
+			++i;
+		}
 	}
 }
 
-static inline void deskewDelay(void)
+void scsiWriteByte(uint8 value)
 {
-	// Delay for deskew + cable skew. total 55 nanoseconds.
-	// Assumes 66MHz.
-	CyDelayCycles(4);
-}
-
-uint8 scsiRead(void)
-{
-	SCSI_SetPin(SCSI_Out_REQ);
-	waitForPinTrue(SCSI_In_ACK);
-	deskewDelay();
-
-	uint8 value = ~SCSI_In_DBx_Read();
-	scsiDev.parityError = scsiDev.parityError ||
-		(Lookup_OddParity[value] != SCSI_ReadPin(SCSI_In_DBP));
+	while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}
+	CY_SET_REG8(scsiTarget_datapath__F0_REG, value);
 
-	SCSI_ClearPin(SCSI_Out_REQ);
-	waitForPinFalse(SCSI_In_ACK);
-	return value;
+	// TODO maybe move this TX EMPTY check to scsiEnterPhase ?
+	//while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {}
+	while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}
+	value = CY_GET_REG8(scsiTarget_datapath__F1_REG);	
 }
 
-void scsiWrite(uint8 value)
+void scsiWrite(uint8* data, uint32 count)
 {
-	SCSI_Out_DBx_Write(value);
-	if (Lookup_OddParity[value])
+	int prep = 0;
+	int i = 0;
+
+	while (i < count)
 	{
-		SCSI_SetPin(SCSI_Out_DBP);
+		if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))
+		{
+			CY_SET_REG8(scsiTarget_datapath__F0_REG, data[prep]);
+			++prep;
+		}
+		if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))
+		{
+			CY_GET_REG8(scsiTarget_datapath__F1_REG);
+			++i;
+		}
 	}
-	deskewDelay();
-
-	SCSI_SetPin(SCSI_Out_REQ);
-
-	// Initiator reads data here.
-
-	waitForPinTrue(SCSI_In_ACK);
-
-	SCSI_ClearPin(SCSI_Out_DBP);
-	SCSI_Out_DBx_Write(0);
-	SCSI_ClearPin(SCSI_Out_REQ);
-
-	// Wait for ACK to clear.
-	waitForPinFalse(SCSI_In_ACK);
 }
 
 static void busSettleDelay(void)
@@ -128,20 +123,13 @@ void scsiEnterPhase(int phase)
 			SCSI_ClearPin(SCSI_Out_CD);
 		}
 
-		if (phase & __scsiphase_io)
-		{
-			SCSI_SetPin(SCSI_Out_IO);
-		}
-		else
-		{
-			SCSI_ClearPin(SCSI_Out_IO);
-		}
+		SCSI_CTL_IO_Write(phase & __scsiphase_io ? 1 : 0);
 	}
 	else
 	{
 		SCSI_ClearPin(SCSI_Out_MSG);
 		SCSI_ClearPin(SCSI_Out_CD);
-		SCSI_ClearPin(SCSI_Out_IO);
+		SCSI_CTL_IO_Write(0);
 	}
 	busSettleDelay();
 }
@@ -150,9 +138,9 @@ void scsiPhyInit()
 {
 	SCSI_RST_ISR_StartEx(scsiResetISR);
 	SCSI_ATN_ISR_StartEx(scsiAttentionISR);
-	
+
 	// Interrupts may have already been directed to the (empty)
 	// standard ISR generated by PSoC Creator.
 	SCSI_RST_ClearInterrupt();
-	// Not needed for pin level interrupt SCSI_ATN_ClearInterrupt();	
-}
+	SCSI_ATN_ClearInterrupt();
+}

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h

@@ -31,11 +31,10 @@
 extern const uint8 Lookup_OddParity[256];
 
 void scsiPhyInit();
-uint8 scsiRead(void);
-void scsiWrite(uint8 value);
-
-// Returns true if the ATN flag becomes set, indicating a parity error.
-int scsiWriteMsg(uint8 msg);
+uint8 scsiReadByte(void);
+void scsiRead(uint8* data, uint32 count);
+void scsiWriteByte(uint8 value);
+void scsiWrite(uint8* data, uint32 count);
 
 void scsiEnterPhase(int phase);
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v

@@ -0,0 +1,320 @@
+
+//`#start header` -- edit after this line, do not edit this line
+//	Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+//	This file is part of SCSI2SD.
+//
+//	SCSI2SD is free software: you can redistribute it and/or modify
+//	it under the terms of the GNU General Public License as published by
+//	the Free Software Foundation, either version 3 of the License, or
+//	(at your option) any later version.
+//
+//	SCSI2SD is distributed in the hope that it will be useful,
+//	but WITHOUT ANY WARRANTY; without even the implied warranty of
+//	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//	GNU General Public License for more details.
+//
+//	You should have received a copy of the GNU General Public License
+//	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 10/16/2013 at 00:01
+// Component: scsiTarget
+module scsiTarget (
+	output [7:0] DBx_out, // Active High, connected to SCSI bus via inverter
+	output  REQ, // Active High, connected to SCSI bus via inverter
+	input   nACK, // Active LOW, connected directly to SCSI bus.
+	input  [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.
+	input   IO, // Active High, set by CPU via status register.
+	input   nRST, // Active LOW, connected directly to SCSI bus.
+	input   clk
+);
+
+
+//`#start body` -- edit after this line, do not edit this line
+
+/////////////////////////////////////////////////////////////////////////////
+// Force Clock Sync
+/////////////////////////////////////////////////////////////////////////////
+// The udb_clock_enable primitive component is used to indicate that the input
+// clock must always be synchronous and if not implement synchronizers to make
+// it synchronous.
+wire op_clk;
+cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
+(
+    .clock_in(clk),
+    .enable(1'b1),
+    .clock_out(op_clk)
+);
+
+/////////////////////////////////////////////////////////////////////////////
+// FIFO Status Register
+/////////////////////////////////////////////////////////////////////////////
+// Status Register: scsiTarget_StatusReg__STATUS_REG
+//     Bit 0: Tx FIFO not full
+//     Bit 1: Rx FIFO not empty
+//     Bit 2: Tx FIFO empty
+//     Bit 3: Rx FIFO full
+//
+// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG
+// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG
+// Use with CY_GET_REG8 and CY_SET_REG8
+wire f0_bus_stat;   // Tx FIFO not full
+wire f0_blk_stat;	// Tx FIFO empty
+wire f1_bus_stat;	// Rx FIFO not empty
+wire f1_blk_stat;	// Rx FIFO full
+cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
+(
+    /* input          */  .clock(op_clk),
+    /* input  [04:00] */  .status({4'b0, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})
+);
+
+/////////////////////////////////////////////////////////////////////////////
+// CONSTANTS
+/////////////////////////////////////////////////////////////////////////////
+localparam IO_WRITE = 1'b1;
+localparam IO_READ = 1'b0;
+
+/////////////////////////////////////////////////////////////////////////////
+// STATE MACHINE
+/////////////////////////////////////////////////////////////////////////////
+// TX States:
+// IDLE
+//     Wait for an entry in the FIFO, and for the SCSI Initiator to be ready
+// FIFOLOAD
+//     Load F0 into A0. Feed (old) A0 into the ALU SRCA.
+// TX
+//     Load data register from PO. PO is fed by A0 going into the ALU via SRCA
+//     A0 must remain unchanged.
+// DESKEW_INIT
+//     DBx output signals will be output in this state
+//     Load deskew clock count into A0 from D0
+// DESKEW
+//     DBx output signals will be output in this state
+//     Wait for the SCSI deskew time of 55ms. (DEC A0).
+//     A1 must be fed into SRCA, so PO is now useless.
+// READY
+//     REQ and DBx output signals will be output in this state
+//     Wait for acknowledgement from the SCSI initiator.
+// RX
+//     Dummy state for flow control.
+//     REQ signal will be output in this state
+//     PI enabled for input into ALU "PASS" operation, storing into F1.
+//
+// RX States:
+// IDLE
+//     Wait for a dummy "enabling" entry in the input FIFO, and wait for space
+//     in output the FIFO, and for the SCSI Initiator to be ready
+// FIFOLOAD
+//     Load F0 into A0.
+//     The input FIFO is used to control the number of bytes we attempt to
+//     read from the SCSI bus.
+// READY
+//     REQ signal will be output in this state
+//     Wait for the initiator to send a byte on the SCSI bus.
+// RX
+//     REQ signal will be output in this state
+//     PI enabled for input into ALU "PASS" operation, storing into F1.
+
+
+localparam STATE_IDLE = 3'b000;
+localparam STATE_FIFOLOAD = 3'b001;
+localparam STATE_TX = 3'b010;
+localparam STATE_DESKEW_INIT = 3'b011;
+localparam STATE_DESKEW = 3'b100;
+// This state intentionally not used.
+localparam STATE_READY = 3'b110;
+localparam STATE_RX = 3'b111;
+
+// state selects the datapath register.
+reg[2:0] state;
+
+// Data being read/written from/to the SCSI bus
+reg[7:0] data;
+
+// Set by the datapath zero detector (z1). High when A1 counts down to zero.
+// D1 set to constant by .d1_init_a(4) (55ns at 66MHz)
+wire deskewComplete;
+
+// Parallel input to the datapath SRCA.
+// Selected for input through to the ALU if CFB EN bit set for the datapath
+// state and enabled by PI DYN bit in CFG15-14
+wire[7:0] pi;
+
+// Parallel output from the selected SRCA value (A0 or A1) to the ALU.
+wire[7:0] po;
+
+// Set true to trigger storing A1 into F1.
+wire fifoStore;
+
+// Set Output Pins
+assign REQ = state[1] & state[2]; // STATE_READY & STATE_RX
+assign DBx_out[7:0] = data;
+assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus
+assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0;
+
+always @(posedge op_clk) begin
+	case (state)
+		STATE_IDLE:
+		begin
+			// Check that SCSI initiator is ready, and input FIFO is not empty,
+			// and output FIFO is not full.
+			// Note that output FIFO is unused in TX mode.
+			if (nACK & !f0_blk_stat && !f1_blk_stat)
+				state <= STATE_FIFOLOAD;
+			else
+				state <= STATE_IDLE;
+
+			// Clear our output pins
+			data <= 8'b0;
+		end
+
+		STATE_FIFOLOAD:
+			state <= IO == IO_WRITE ? STATE_TX : STATE_READY;
+
+		STATE_TX:
+		begin
+			state <= STATE_DESKEW_INIT;
+			data <= po;
+		end
+
+		STATE_DESKEW_INIT: state <= STATE_DESKEW;
+
+		STATE_DESKEW:
+			if(deskewComplete) state <= STATE_READY;
+			else state <= STATE_DESKEW;
+
+		STATE_READY:
+			//if ((IO == IO_WRITE) & ~nACK) state <= STATE_IDLE;
+			//else if ((IO == IO_READ) & ~nACK) state <= STATE_RX;
+			if (~nACK) state <= STATE_RX;
+			else state <= STATE_READY;
+
+		STATE_RX: state <= STATE_IDLE;
+
+		default: state <= STATE_IDLE;
+	endcase
+end
+
+cy_psoc3_dp #(.d1_init(3), 
+.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0:       IDLE*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1:       FIFO Load*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:       TX*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:       DESKEW INIT*/
+    `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:       DESKEW*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:       READY*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:       RX*/
+    8'hFF, 8'h00,  /*CFG9:          */
+    8'hFF, 8'hFF,  /*CFG11-10:          */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:          */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
+    1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:          */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:          */
+}
+)) datapath(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(op_clk),
+        /*  input   [02:00]         */  .cs_addr(state),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(fifoStore),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(deskewComplete),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(f0_bus_stat),
+        /*  output                  */  .f0_blk_stat(f0_blk_stat),
+        /*  output                  */  .f1_bus_stat(f1_bus_stat),
+        /*  output                  */  .f1_blk_stat(f1_blk_stat),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),         // Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(pi),     // Parallel data port
+        /* output [07:00]           */  .po(po)          // Parallel data port
+);
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/sd.c

@@ -17,6 +17,7 @@
 
 #include "device.h"
 #include "scsi.h"
+#include "config.h"
 #include "disk.h"
 #include "sd.h"
 
@@ -169,24 +170,21 @@ int sdIsReadReady()
 
 void sdReadSector()
 {
-	// We have a spi FIFO of 4 bytes. use it.
-	// This is much better, byut after 4 bytes we're still
-	// blocking a bit.
-	int i;
-	for (i = 0; i < SCSI_BLOCK_SIZE; i+=4)
+	int prep = 0;
+	int i = 0;
+	while (i < SCSI_BLOCK_SIZE)
 	{
-		SDCard_WriteTxData(0xFF);
-		SDCard_WriteTxData(0xFF);
-		SDCard_WriteTxData(0xFF);
-		SDCard_WriteTxData(0xFF);
-
-		while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))
-		{}
-		scsiDev.data[i] = SDCard_ReadRxData();
-		scsiDev.data[i+1] = SDCard_ReadRxData();
-		scsiDev.data[i+2] = SDCard_ReadRxData();
-		scsiDev.data[i+3] = SDCard_ReadRxData();
+		if (prep < SCSI_BLOCK_SIZE && (SDCard_ReadTxStatus() & SDCard_STS_TX_FIFO_NOT_FULL))
+		{
+			SDCard_WriteTxData(0xFF);
+			prep++;
+		}
 
+		if(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)
+		{
+			scsiDev.data[i] = SDCard_ReadRxData();
+			i++;
+		}
 	}
 
 
@@ -213,21 +211,18 @@ int sdWriteSector()
 
 		sdSpiByte(0xFC); // MULTIPLE byte start token
 		int i;
-		for (i = 0; i < SCSI_BLOCK_SIZE; i+=4)
+		for (i = 0; i < SCSI_BLOCK_SIZE; i++)
 		{
-			SDCard_WriteTxData(scsiDev.data[i]);
-			SDCard_WriteTxData(scsiDev.data[i+1]);
-			SDCard_WriteTxData(scsiDev.data[i+2]);
-			SDCard_WriteTxData(scsiDev.data[i+3]);
-
-			while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))
+			while(!(SDCard_ReadTxStatus() & SDCard_STS_TX_FIFO_NOT_FULL))
 			{}
+			SDCard_WriteTxData(scsiDev.data[i]);
 		}
-				
-			SDCard_ReadRxData();
-			SDCard_ReadRxData();
-			SDCard_ReadRxData();
-			SDCard_ReadRxData();
+		while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))
+		{}
+		SDCard_ReadRxData();
+		SDCard_ReadRxData();
+		SDCard_ReadRxData();
+		SDCard_ReadRxData();
 
 		sdSpiByte(0x00); // CRC
 		sdSpiByte(0x00); // CRC
@@ -430,7 +425,7 @@ int sdInit()
 
 	// now set the sd card up for full speed
 	SD_Data_Clk_Start(); // Turn on the fast clock
-	SD_Clk_Ctl_Write(1); // Select the fast clock source.
+	SD_Clk_Ctl_Write(config->overclockSPI ? 2 : 1); // Select the fast clock source.
 	SD_Init_Clk_Stop(); // Stop the slow clock.
 
 	if (!sdReadCSD()) goto bad;
@@ -446,7 +441,6 @@ out:
 
 }
 
-
 void sdPrepareWrite()
 {
 	// Set the number of blocks to pre-erase by the multiple block write command

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/sd.h

@@ -46,7 +46,7 @@ typedef struct
 {
 	int version; // SDHC = version 2.
 	int ccs; // Card Capacity Status. 1 = SDHC or SDXC
-	int capacity; // in 512 byte blocks
+	uint32 capacity; // in 512 byte blocks
 } SdDevice;
 
 extern SdDevice sdDev;