Write performance improvements.

- Multi-sector SD card writes supported.
- Updated to PSoC Creator 3.0

lib/SCSI2SD/STATUS

@@ -9,7 +9,5 @@ assignments are incorrect.
 	- Partity checking is on
 	- Unit Attention Condition is off
 
-- Write performance is not adequate
-	- Multi-sector SD commands are not yet supported.
-	- DMA is not used for SPI transfers
+- DMA is not used for SPI transfers
 

lib/SCSI2SD/readme.txt

@@ -42,10 +42,18 @@ Dimensions
 Performance
 
 As currently implemented:
-Sequential read: 250kb/sec Sequential write: 50kb/sec
 
-These numbers are dreadful. I am working on updating the slow polling SD card
-communication to use DMA. I expect the performance to reach 1.8Mb/sec.
+Sequential read: 250kb/sec Sequential write: 240kb/sec
+
+Tested with a 16GB class 10 SD card, via the commands:
+
+ # WRITE TEST
+ sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync
+
+ # READ TEST
+ sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null
+
+I am working on updating the slow polling SD card communication to use DMA. I expect the performance to reach 1Mb/sec. 
 
 
 Compatibility

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf

@@ -0,0 +1,113 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__   = 262144 - 1;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (65536 / 2);
+define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (65536 / 2) - 1;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x4000;
+define symbol __ICFEDIT_size_heap__   = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+/******** Definitions ********/
+define symbol CY_APPL_LOADABLE  = 0;
+define symbol CY_APPL_LOADER    = 0;
+define symbol CY_APPL_NUM       = 1;
+define symbol CY_APPL_MAX       = 1;
+define symbol CY_METADATA_SIZE  = 64;
+define symbol CY_EE_IN_BTLDR    = 0x0;
+define symbol CY_EE_SIZE        = 2048;
+
+if (!CY_APPL_LOADABLE) {
+    define symbol CYDEV_BTLDR_SIZE = 0;
+}
+
+define symbol CY_FLASH_SIZE     = 262144;
+define symbol CY_APPL_ORIGIN    = 0; 
+define symbol CY_FLASH_ROW_SIZE = 256;
+define symbol CY_ECC_ROW_SIZE   = 32;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
+define block HSTACK      {block HEAP, last block CSTACK};
+
+define block LOADER     { readonly section .cybootloader };
+define block APPL       with fixed order {readonly section .romvectors, readonly};
+
+/* The address of Flash row next after Bootloader image */
+define symbol CY_BTLDR_END      = CYDEV_BTLDR_SIZE +
+                                    ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
+                                    (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
+
+/* The start address of Standard/Loader/Loadable#1 image */
+define symbol CY_APPL1_START    = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
+
+/* The number of metadata records located at the end of Flash */
+define symbol CY_METADATA_CNT   = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
+
+/* The application area size measured in rows */
+define symbol CY_APPL_ROW_CNT   = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
+
+/* The start address of Loadable#2 image if any */
+define symbol CY_APPL2_START    = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
+
+/* The current image (Standard/Loader/Loadable) start address */
+define symbol CY_APPL_START     = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
+
+/* The ECC data placement address */
+define exported symbol CY_ECC_OFFSET     = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
+
+/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
+define symbol CY_EE_OFFSET      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
+define symbol CY_EE_IN_USE      = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
+
+/* Define EEPROM region */
+define region EEPROM_region     = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
+
+/* Define APPL region that will limit application size */
+define region APPL_region       = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
+
+
+/****** Initializations ******/
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { readwrite section .ramvectors };
+
+/******** Placements *********/
+".cybootloader"    : place at start of ROM_region {block LOADER};
+"APPL"             : place at start of APPL_region {block APPL};
+
+"RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
+"readwrite"        : place in RAM_region          { readwrite };
+"HSTACK"           : place at end of RAM_region   { block HSTACK};
+
+keep {  section .cybootloader, 
+        section .cyloadermeta, 
+        section .cyloadablemeta,
+        section .cyconfigecc, 
+        section .cycustnvl, 
+        section .cywolatch,
+        section .cyeeprom, 
+        section .cyflashprotect,
+        section .cymeta };
+
+".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
+".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
+".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
+".cyeeprom"       : place in EEPROM_region { readonly section .cyeeprom };
+".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
+".cymeta"         : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+/* EOF */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat

@@ -1,6 +1,10 @@
+#! armcc -E
+; The first line specifies a preprocessor command that the linker invokes 
+; to pass a scatter file through a C preprocessor.
+
 ;********************************************************************************
 ;* File Name: Cm3RealView.scat
-;* Version 3.40
+;* Version 4.0
 ;*
 ;*  Description:
 ;*  This Linker Descriptor file describes the memory layout of the PSoC5
@@ -26,8 +30,62 @@
 ;* disclaimers, and limitations in the end user license agreement accompanying
 ;* the software package with which this file was provided.
 ;********************************************************************************/
+#include "cyfitter.h"
+
+#define CY_FLASH_SIZE       262144
+#define CY_APPL_ORIGIN      0
+#define CY_FLASH_ROW_SIZE   256
+#define CY_ECC_ROW_SIZE     32
+#define CY_EE_SIZE          2048
+#define CY_METADATA_SIZE    64
+
+
+; Define application base address
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+    #define CY_APPL_NUM     1
+    #define CY_APPL_MAX     1
+    #define CY_EE_IN_BTLDR  
+
+    #if CY_APPL_ORIGIN
+        #define APPL1_START     CY_APPL_ORIGIN
+    #else
+        #define APPL1_START     AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
+    #endif
+
+    #define APPL_START      (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
+    #define ECC_OFFSET      ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
+    #define EE_OFFSET       (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
+    #define EE_SIZE         (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
+
+#else
+
+    #define APPL_START      0
+    #define ECC_OFFSET      0
+    #define EE_OFFSET       0
+    #define EE_SIZE         CY_EE_SIZE
+
+#endif
+
+
+; Place Bootloader at the beginning of Flash
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+    CYBOOTLOADER 0
+    {
+        .cybootloader +0
+        {
+            * (.cybootloader)
+        }
+    }
 
-LOAD_ROM 0 (262144 - 0)
+    #if CY_APPL_ORIGIN
+        ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))
+    #endif
+
+#endif
+
+
+APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
 {
     VECTORS +0
     {
@@ -51,7 +109,7 @@ LOAD_ROM 0 (262144 - 0)
 
     DATA +0
     {
-        * (+RW, +ZI)
+        .ANY (+RW, +ZI)
     }
 
     ARM_LIB_HEAP (0x20000000 + (65536 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
@@ -62,3 +120,71 @@ LOAD_ROM 0 (262144 - 0)
     {
     }
 }
+
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)
+
+    CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#else
+
+    #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+        CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
+        {
+            .cyloadablemeta +0 { * (.cyloadablemeta) }
+        }
+    
+    #endif
+
+#endif
+
+#if (CYDEV_ECC_ENABLE == 0)
+
+    CYCONFIGECC (0x80000000 + ECC_OFFSET)
+    {
+        .cyconfigecc +0 { * (.cyconfigecc) }
+    }
+
+#endif
+
+CYCUSTNVL 0x90000000
+{
+    .cycustnvl +0 { * (.cycustnvl) }
+}
+
+CYWOLATCH 0x90100000
+{
+    .cywolatch +0 { * (.cywolatch) }
+}
+
+#if defined(CYDEV_ALLOCATE_EEPROM)
+
+    CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
+    {
+        .cyeeprom +0 { * (.cyeeprom) }
+    }
+
+#endif
+
+CYFLASHPROTECT 0x90400000
+{
+    .cyflashprotect +0 { * (.cyflashprotect) }
+}
+
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
+
+    CYLOADERMETA +0
+    {
+        .cyloadermeta +0 { * (.cyloadermeta) }
+    }
+
+#endif

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Cm3Start.c
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *  Startup code for the ARM CM3.
@@ -12,6 +12,7 @@
 * the software package with which this file was provided.
 *******************************************************************************/
 
+#include <limits.h>
 #include "cydevice_trm.h"
 #include "cytypes.h"
 #include "cyfitter_cfg.h"
@@ -19,14 +20,15 @@
 #include "CyDmac.h"
 #include "cyfitter.h"
 
-#define NUM_INTERRUPTS              32u
-#define NUM_VECTORS                 (CYINT_IRQ_BASE+NUM_INTERRUPTS)
-#define NUM_ROM_VECTORS             4u
-#define NVIC_APINT                  ((reg32 *) CYREG_NVIC_APPLN_INTR)
-#define NVIC_CFG_CTRL               ((reg32 *) CYREG_NVIC_CFG_CONTROL)
-#define NVIC_APINT_PRIGROUP_3_5     0x00000400u  /* Priority group 3.5 split */
-#define NVIC_APINT_VECTKEY          0x05FA0000u  /* This key is required in order to write the NVIC_APINT register */
-#define NVIC_CFG_STACKALIGN         0x00000200u  /* This specifies that the exception stack must be 8 byte aligned */
+#define CY_NUM_INTERRUPTS           (32u)
+#define CY_NUM_VECTORS              (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
+#define CY_NUM_ROM_VECTORS          (4u)
+#define CY_NVIC_APINT_PTR           ((reg32 *) CYREG_NVIC_APPLN_INTR)
+#define CY_NVIC_CFG_CTRL_PTR        ((reg32 *) CYREG_NVIC_CFG_CONTROL)
+#define CY_NVIC_APINT_PRIGROUP_3_5  (0x00000400u)  /* Priority group 3.5 split */
+#define CY_NVIC_APINT_VECTKEY       (0x05FA0000u)  /* This key is required in order to write the NVIC_APINT register */
+#define CY_NVIC_CFG_STACKALIGN      (0x00000200u)  /* This specifies that the exception stack must be 8 byte aligned */
+
 
 /* Extern functions */
 extern void CyBtldr_CheckLaunch(void);
@@ -38,26 +40,35 @@ void Reset(void);
 CY_ISR(IntDefaultHandler);
 
 #if defined(__ARMCC_VERSION)
-    #define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit
+    #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
 #elif defined (__GNUC__)
-    #define INITIAL_STACK_POINTER __cs3_stack
+    #define INITIAL_STACK_POINTER (&__cy_stack)
+#elif defined (__ICCARM__)
+    #pragma language=extended
+    #pragma segment="CSTACK"
+    #define INITIAL_STACK_POINTER  { .__ptr = __sfe( "CSTACK" ) }
+
+    extern void __iar_program_start( void );
+    extern void __iar_data_init3 (void);
 #endif  /* (__ARMCC_VERSION) */
 
 /* Global variables */
-CY_NOINIT static uint32 cySysNoInitDataValid;
+#if !defined (__ICCARM__)
+    CY_NOINIT static uint32 cySysNoInitDataValid;
+#endif  /* !defined (__ICCARM__) */
 
 
 /*******************************************************************************
 * Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
 *******************************************************************************/
-
-__attribute__ ((section(".ramvectors")))
-#if defined(__ARMCC_VERSION)
-__align(256)
-#elif defined (__GNUC__)
-__attribute__ ((aligned(256)))
-#endif
-cyisraddress CyRamVectors[NUM_VECTORS];
+#if defined (__ICCARM__)
+    #pragma location=".ramvectors"
+    #pragma data_alignment=256
+#else
+    CY_SECTION(".ramvectors")
+    CY_ALIGN(256)
+#endif  /* defined (__ICCARM__) */
+cyisraddress CyRamVectors[CY_NUM_VECTORS];
 
 
 /*******************************************************************************
@@ -121,42 +132,27 @@ extern int __main(void);
 *  None
 *
 *******************************************************************************/
-__asm void Reset(void)
+void Reset(void)
 {
-    PRESERVE8
-    EXTERN __main
-    EXTERN CyResetStatus
-
-    #if(CYDEV_BOOTLOADER_ENABLE)
-        EXTERN CyBtldr_CheckLaunch
-    #endif  /* (CYDEV_BOOTLOADER_ENABLE) */
-
-
     #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
-        #if(CYDEV_DEBUGGING_ENABLE)
-            ldr  r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */
-            ldrb r4, [r3, #0]
-            orr  r4, r4, #01
-            strb r4, [r3, #0]
-debugEnabled
-        #endif    /* (CYDEV_DEBUGGING_ENABLE) */
 
-        ldr  r3, =0x400046fa /* CYREG_RESET_SR0 */
-        ldrb r2, [r3, #0]
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
 
-    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
 
-    ldr  r3, =0x400076BC /* CYREG_PHUB_CFGMEM23_CFG1 */
-    strb r2, [r3, #0]
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
 
     #if(CYDEV_BOOTLOADER_ENABLE)
-        bl CyBtldr_CheckLaunch
+        CyBtldr_CheckLaunch();
     #endif /* (CYDEV_BOOTLOADER_ENABLE) */
 
-    /* Let RealView setup the libraries. */
-    bl __main
-
-    ALIGN
+    __main();
 }
 
 
@@ -181,14 +177,38 @@ void $Sub$$main(void)
     /* Call original main */
     $Super$$main();
 
-    /* If main returns it is undefined what we should do. */
-    while (1);
+    while (1)
+    {
+        /* If main returns it is undefined what we should do. */
+    }
 }
 
 #elif defined(__GNUC__)
 
-extern void __cs3_stack(void);
-extern void __cs3_start_c(void);
+void Start_c(void);
+
+/* Stack Base address */
+extern void __cy_stack(void);
+
+/* Application entry point. */
+extern int main(void);
+
+/* The static objects constructors initializer */
+extern void __libc_init_array(void);
+
+typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
+
+struct __cy_region
+{
+    __cy_byte_align8 *init; /* Initial contents of this region.  */
+    __cy_byte_align8 *data; /* Start address of region.  */
+    size_t init_size;       /* Size of initial data.  */
+    size_t zero_size;       /* Additional size to be zeroed.  */
+};
+
+extern const struct __cy_region __cy_regions[];
+extern const char __cy_region_num __attribute__((weak));
+#define __cy_region_num ((size_t)&__cy_region_num)
 
 
 /*******************************************************************************
@@ -196,7 +216,7 @@ extern void __cs3_start_c(void);
 ********************************************************************************
 *
 * Summary:
-*  This function handles the reset interrupt for the GCC toolchain.  This is the
+*  This function handles the reset interrupt for the GCC toolchain. This is the
 *  first bit of code that is executed at startup.
 *
 * Parameters:
@@ -206,34 +226,140 @@ extern void __cs3_start_c(void);
 *  None
 *
 *******************************************************************************/
-__attribute__ ((naked))
 void Reset(void)
 {
-    __asm volatile(
-#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
-
-  #if(CYDEV_DEBUGGING_ENABLE)
-    "    ldr  r3, =%0\n"
-    "    ldrb r4, [r3, #0]\n"
-    "    orr  r4, r4, #01\n"
-    "    strb r4, [r3, #0]\n"
-    "debugEnabled:\n"
-  #endif    /* (CYDEV_DEBUGGING_ENABLE) */
-
-    "    ldr  r3, =%1\n"
-    "    ldrb r2, [r3, #0]\n"
-    "    uxtb r2, r2\n"
-#endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
-
-    "    ldr  r3, =%2\n"
-    "    strb r2, [r3, #0]\n"
-
-#if(CYDEV_BOOTLOADER_ENABLE)
-    "    bl CyBtldr_CheckLaunch\n"
-#endif /* (CYDEV_BOOTLOADER_ENABLE) */
-
-    /*  Switch to C initialization phase */
-    "    bl __cs3_start_c\n" : : "i" (CYDEV_DEBUG_ENABLE_REGISTER), "i" (CYREG_RESET_SR0), "i" (CYREG_PHUB_CFGMEM23_CFG1));
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+
+    #if(CYDEV_BOOTLOADER_ENABLE)
+        CyBtldr_CheckLaunch();
+    #endif /* (CYDEV_BOOTLOADER_ENABLE) */
+
+    Start_c();
+}
+
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause a divide by 0 exception */
+    int x = status / INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+    }
+}
+
+/*******************************************************************************
+* Function Name: Start_c
+********************************************************************************
+*
+* Summary:
+*  This function handles initializing the .data and .bss sections in
+*  preperation for running standard C code.  Once initialization is complete
+*  it will call main(). This function will never return.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void Start_c(void)  __attribute__ ((noreturn));
+void Start_c(void)
+{
+    unsigned regions = __cy_region_num;
+    const struct __cy_region *rptr = __cy_regions;
+
+    /* Initialize memory */
+    for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+    {
+        uint32 *src = (uint32 *)rptr->init;
+        uint32 *dst = (uint32 *)rptr->data;
+        unsigned limit = rptr->init_size;
+        unsigned count;
+
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst++ = *src++;
+        }
+        limit = rptr->zero_size;
+        for (count = 0u; count != limit; count += sizeof (uint32))
+        {
+            *dst++ = 0u;
+        }
+    }
+
+    /* Invoke static objects constructors */
+    __libc_init_array();
+    (void) main();
+
+    while (1)
+    {
+        /* If main returns, make sure we don't return. */
+    }
+}
+
+
+#elif defined (__ICCARM__)
+
+/*******************************************************************************
+* Function Name: __low_level_init
+********************************************************************************
+*
+* Summary:
+*  This function perform early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of reset interrupt handler
+*  before the data sections are initialized.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  The value that determines whether or not data sections should be initialized
+*  by the system startup code:
+*    0 - skip data sections initialization;
+*    1 - initialize data sections;
+*
+*******************************************************************************/
+int __low_level_init(void)
+{
+    #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
+
+        /* For PSoC 5LP, debugging is enabled by default */
+        #if(CYDEV_DEBUGGING_ENABLE == 0)
+            *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
+        #endif /* (CYDEV_DEBUGGING_ENABLE) */
+
+        /* Reset Status Register has Read-to-clear SW access mode.
+        * Preserve current RESET_SR0 state to make it available for next reading.
+        */
+        *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
+
+    #endif  /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
+
+    #if (CYDEV_BOOTLOADER_ENABLE)
+        CyBtldr_CheckLaunch();
+    #endif /* CYDEV_BOOTLOADER_ENABLE */
+
+    /* Initialize data sections */
+    __iar_data_init3();
+
+    initialize_psoc();
+
+    return 0;
 }
 
 #endif /* __GNUC__ */
@@ -245,21 +371,32 @@ void Reset(void)
 *
 *******************************************************************************/
 #if defined(__ARMCC_VERSION)
+    /* Suppress diagnostic message 1296-D: extended constant initialiser used */
     #pragma diag_suppress 1296
-#endif
-__attribute__ ((section(".romvectors")))
-const cyisraddress RomVectors[NUM_ROM_VECTORS] =
+#endif  /* defined(__ARMCC_VERSION) */
+
+#if defined (__ICCARM__)
+    #pragma location=".romvectors"
+    const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
+#else
+    CY_SECTION(".romvectors")
+    const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
+#endif  /* defined (__ICCARM__) */
 {
-    #if defined(__ARMCC_VERSION)
-        INITIAL_STACK_POINTER,           /* The initial stack pointer  0 */
-    #elif defined (__GNUC__)
-        &INITIAL_STACK_POINTER,          /* The initial stack pointer  0 */
-    #endif  /* (__ARMCC_VERSION) */
-    (cyisraddress)&Reset,    /* The reset handler          1 */
+    INITIAL_STACK_POINTER,   /* The initial stack pointer  0 */
+    #if defined (__ICCARM__) /* The reset handler          1 */
+        __iar_program_start,
+    #else
+        (cyisraddress)&Reset,
+    #endif  /* defined (__ICCARM__) */
     &IntDefaultHandler,      /* The NMI handler            2 */
     &IntDefaultHandler,      /* The hard fault handler     3 */
 };
 
+#if defined(__ARMCC_VERSION)
+    #pragma diag_default 1296
+#endif  /* defined(__ARMCC_VERSION) */
+
 
 /*******************************************************************************
 * Function Name: initialize_psoc
@@ -278,7 +415,6 @@ const cyisraddress RomVectors[NUM_ROM_VECTORS] =
 #if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
 __attribute__ ((constructor(101)))
 #endif
-
 void initialize_psoc(void)
 {
     uint32 i;
@@ -286,13 +422,17 @@ void initialize_psoc(void)
     /* Set Priority group 5. */
 
     /* Writes to NVIC_APINT register require the VECTKEY in the upper half */
-    *NVIC_APINT = NVIC_APINT_VECTKEY | NVIC_APINT_PRIGROUP_3_5;
-    *NVIC_CFG_CTRL |= NVIC_CFG_STACKALIGN;
+    *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
+    *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
 
     /* Set Ram interrupt vectors to default functions. */
-    for(i = 0u; i < NUM_VECTORS; i++)
+    for (i = 0u; i < CY_NUM_VECTORS; i++)
     {
-        CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
+        #if defined (__ICCARM__)
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
+        #else
+            CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
+        #endif  /* defined (__ICCARM__) */
     }
 
     /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
@@ -310,9 +450,11 @@ void initialize_psoc(void)
         CyDmacConfigure();
 
     #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
-    
-    /* Actually, no need to clean this variable, just to make compiler happy. */
-    cySysNoInitDataValid = 0u;
+
+    #if !defined (__ICCARM__)
+        /* Actually, no need to clean this variable, just to make compiler happy. */
+        cySysNoInitDataValid = 0u;
+    #endif  /* !defined (__ICCARM__) */
 }
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyBootAsmGnu.s
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Assembly routines for GNU as.
@@ -12,6 +12,8 @@
 * the software package with which this file was provided.
 *******************************************************************************/
 
+.include "cyfittergnu.inc"
+
 .syntax unified
 .text
 .thumb
@@ -38,16 +40,68 @@
 .type CyDelayCycles, %function
 .thumb_func
 CyDelayCycles:              /* cycles bytes */
-	ADDS r0, r0, #2         /*	1	2	Round to nearest multiple of 4 */
-	LSRS r0, r0, #2         /*	1	2	Divide by 4 and set flags */
-	BEQ CyDelayCycles_done  /*	2	2	Skip if 0 */
-	NOP                     /*	1	2	Loop alignment padding */
+/* If ICache is enabled */
+.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
+
+    ADDS r0, r0, #2           /*  1    2   Round to nearest multiple of 4 */
+    LSRS r0, r0, #2           /*  1    2   Divide by 4 and set flags */
+    BEQ CyDelayCycles_done    /*  2    2   Skip if 0 */
+    NOP                       /*  1    2   Loop alignment padding */
+
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           /*  1    2 */
+    MOV r0, r0                /*  1    2   Pad loop to power of two cycles */
+    BNE CyDelayCycles_loop    /*  2    2 */
+
+CyDelayCycles_done:
+    BX lr                     /*  3    2 */
+
+.else
+
+    CMP r0, #20               /*  1    2   If delay is short - jump to cycle */
+    BLS CyDelayCycles_short   /*  1    2  */
+    PUSH {r1}                 /*  2    2   PUSH r1 to stack */
+    MOVS r1, #1               /*  1    2  */
+
+    SUBS r0, r0, #20          /*  1    2   Subtract overhead */
+    LDR r1,=CYREG_CACHE_CC_CTL/*  2    2   Load flash wait cycles value */
+    LDRB r1, [r1, #0]         /*  2    2  */
+    ANDS r1, #0xC0            /*  1    2  */
+
+    LSRS r1, r1, #6           /*  1    2  */
+    PUSH {r2}                 /*  1    2   PUSH r2 to stack */
+    LDR r2, =cy_flash_cycles  /*  2    2  */
+    LDRB r1, [r2, r1]         /*  2    2  */
+
+    POP {r2}                  /*  2    2   POP r2 from stack */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
 CyDelayCycles_loop:
-	SUBS r0, r0, #1         /*	1	2 */
-	MOV r0, r0              /*	1	2	Pad loop to power of two cycles */
-	BNE CyDelayCycles_loop  /*	2	2 */
+    SBCS r0, r0, r1           /*  1    2  */
+    BPL CyDelayCycles_loop    /*  3    2  */
+    NOP                       /*  1    2   Loop alignment padding */
+    NOP                       /*  1    2   Loop alignment padding */
+
+    POP {r1}                  /*  2    2   POP r1 from stack */
 CyDelayCycles_done:
-	BX lr                   /*	3	2 */
+    BX lr                     /*  3    2  */
+    NOP                       /*  1    2   Alignment padding */
+    NOP                       /*  1    2   Alignment padding */
+
+CyDelayCycles_short:
+    SBCS r0, r0, #4           /*  1    2  */
+    BPL CyDelayCycles_short   /*  3    2  */
+    BX lr                     /*  3    2  */
+
+cy_flash_cycles:
+.byte 0x0B
+.byte 0x05
+.byte 0x07
+.byte 0x09
+.endif
+
 .endfunc
 
 
@@ -81,9 +135,9 @@ CyDelayCycles_done:
 .type CyEnterCriticalSection, %function
 .thumb_func
 CyEnterCriticalSection:
-	MRS r0, PRIMASK         /* Save and return interrupt state */
-	CPSID I                 /* Disable interrupts */
-	BX lr
+    MRS r0, PRIMASK         /* Save and return interrupt state */
+    CPSID I                 /* Disable interrupts */
+    BX lr
 .endfunc
 
 
@@ -110,8 +164,8 @@ CyEnterCriticalSection:
 .type CyExitCriticalSection, %function
 .thumb_func
 CyExitCriticalSection:
-	MSR PRIMASK, r0         /* Restore interrupt state */
-	BX lr
+    MSR PRIMASK, r0         /* Restore interrupt state */
+    BX lr
 .endfunc
 
 .end

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s

@@ -0,0 +1,156 @@
+;-------------------------------------------------------------------------------
+; FILENAME: CyBootAsmIar.s
+; Version 4.0
+;
+;  DESCRIPTION:
+;    Assembly routines for IAR Embedded Workbench IDE.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions,
+; disclaimers, and limitations in the end user license agreement accompanying
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+    SECTION .text:CODE:ROOT(4)
+    PUBLIC CyDelayCycles
+    PUBLIC CyEnterCriticalSection
+    PUBLIC CyExitCriticalSection
+    INCLUDE cyfitteriar.inc
+    THUMB
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyEnterCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyEnterCriticalSection disables interrupts and returns a value indicating
+;  whether interrupts were previously enabled.
+;
+;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
+;  with interrupts still enabled. The test and set of the interrupt bits is not
+;  atomic. Therefore, to avoid corrupting processor state, it must be the policy 
+;  that all interrupt routines restore the interrupt enable bits as they were 
+;  found on entry.
+;
+; Parameters:
+;  None
+;
+; Return:
+;  uint8
+;   Returns 0 if interrupts were previously enabled or 1 if interrupts
+;   were previously disabled.
+;
+;-------------------------------------------------------------------------------
+; uint8 CyEnterCriticalSection(void)
+
+CyEnterCriticalSection:
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyExitCriticalSection
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  CyExitCriticalSection re-enables interrupts if they were enabled before
+;  CyEnterCriticalSection was called. The argument should be the value returned
+;  from CyEnterCriticalSection.
+;
+; Parameters:
+;  uint8 savedIntrStatus:
+;   Saved interrupt status returned by the CyEnterCriticalSection function.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyExitCriticalSection(uint8 savedIntrStatus)
+
+CyExitCriticalSection:
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+
+
+;-------------------------------------------------------------------------------
+; Function Name: CyDelayCycles
+;-------------------------------------------------------------------------------
+;
+; Summary:
+;  Delays for the specified number of cycles.
+;
+; Parameters:
+;  uint32 cycles: number of cycles to delay.
+;
+; Return:
+;  None
+;
+;-------------------------------------------------------------------------------
+; void CyDelayCycles(uint32 cycles)
+
+CyDelayCycles: 
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
+CyDelayCycles_loop:
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    
+    ELSE
+    
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, r1, #0xC0        ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop:
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done:
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+CyDelayCycles_short:
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+    NOP                       ;   1   2   Loop alignment padding
+
+    DATA
+cy_flash_cycles:
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+
+    END

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s

@@ -1,6 +1,6 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmRv.s
-; Version 3.40
+; Version 4.0
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for RealView.
@@ -12,9 +12,11 @@
 ; the software package with which this file was provided.
 ;-------------------------------------------------------------------------------
 
-	AREA |.text|,CODE,ALIGN=3
-	THUMB
-	EXTERN Reset
+    AREA |.text|,CODE,ALIGN=3
+    THUMB
+    EXTERN Reset
+
+    GET cyfitterrv.inc
 
 ;-------------------------------------------------------------------------------
 ; Function Name: CyDelayCycles
@@ -31,21 +33,70 @@
 ;
 ;-------------------------------------------------------------------------------
 ; void CyDelayCycles(uint32 cycles)
-	ALIGN 8
+    ALIGN 8
 CyDelayCycles FUNCTION
-	EXPORT CyDelayCycles
-	                        ; cycles bytes
-	ADDS r0, r0, #2         ;	1	2	Round to nearest multiple of 4
-	LSRS r0, r0, #2         ;	1	2	Divide by 4 and set flags
-	BEQ CyDelayCycles_done  ;	2	2	Skip if 0
-	NOP                     ;	1	2	Loop alignment padding
+    EXPORT CyDelayCycles
+    IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
+                              ; cycles bytes
+    ADDS r0, r0, #2           ;   1   2  Round to nearest multiple of 4
+    LSRS r0, r0, #2           ;   1   2  Divide by 4 and set flags
+    BEQ CyDelayCycles_done    ;   2   2  Skip if 0
+    NOP                       ;   1   2  Loop alignment padding
 CyDelayCycles_loop
-	SUBS r0, r0, #1         ;	1	2
-	MOV r0, r0              ;	1	2	Pad loop to power of two cycles
-	BNE CyDelayCycles_loop  ;	2	2
+    SUBS r0, r0, #1           ;   1   2
+    MOV r0, r0                ;   1   2  Pad loop to power of two cycles
+    BNE CyDelayCycles_loop    ;   2   2
+    NOP                       ;   1   2  Loop alignment padding
 CyDelayCycles_done
-	BX lr                   ;	3	2
-	ENDFUNC
+    BX lr                     ;   3   2
+
+    ELSE
+
+    CMP r0, #20               ;   1   2  If delay is short - jump to cycle
+    BLS CyDelayCycles_short   ;   1   2
+    PUSH {r1}                 ;   2   2  PUSH r1 to stack
+    MOVS r1, #1               ;   1   2
+
+    SUBS r0, r0, #20          ;   1   2  Subtract overhead
+    LDR r1,=CYREG_CACHE_CC_CTL;   2   2  Load flash wait cycles value
+    LDRB r1, [r1, #0]         ;   2   2
+    ANDS r1, #0xC0            ;   1   2
+
+    LSRS r1, r1, #6           ;   1   2
+    PUSH {r2}                 ;   1   2  PUSH r2 to stack
+    LDR r2, =cy_flash_cycles  ;   2   2
+    LDRB r1, [r2, r1]         ;   2   2
+
+    POP {r2}                  ;   2   2  POP r2 from stack
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_loop
+    SBCS r0, r0, r1           ;   1   2
+    BPL CyDelayCycles_loop    ;   3   2
+    NOP                       ;   1   2  Loop alignment padding
+    NOP                       ;   1   2  Loop alignment padding
+
+    POP {r1}                  ;   2   2  POP r1 from stack
+CyDelayCycles_done
+    BX lr                     ;   3   2
+    NOP                       ;   1   2  Alignment padding
+    NOP                       ;   1   2  Alignment padding
+
+CyDelayCycles_short
+    SBCS r0, r0, #4           ;   1   2
+    BPL CyDelayCycles_short   ;   3   2
+    BX lr                     ;   3   2
+
+cy_flash_cycles
+byte_1 DCB 0x0B
+byte_2 DCB 0x05
+byte_3 DCB 0x07
+byte_4 DCB 0x09
+
+    ENDIF
+    ENDFUNC
 
 
 ;-------------------------------------------------------------------------------
@@ -74,11 +125,11 @@ CyDelayCycles_done
 ;-------------------------------------------------------------------------------
 ; uint8 CyEnterCriticalSection(void)
 CyEnterCriticalSection FUNCTION
-	EXPORT CyEnterCriticalSection
-	MRS r0, PRIMASK         ; Save and return interrupt state
-	CPSID I                 ; Disable interrupts
-	BX lr
-	ENDFUNC
+    EXPORT CyEnterCriticalSection
+    MRS r0, PRIMASK         ; Save and return interrupt state
+    CPSID I                 ; Disable interrupts
+    BX lr
+    ENDFUNC
 
 
 ;-------------------------------------------------------------------------------
@@ -100,11 +151,11 @@ CyEnterCriticalSection FUNCTION
 ;-------------------------------------------------------------------------------
 ; void CyExitCriticalSection(uint8 savedIntrStatus)
 CyExitCriticalSection FUNCTION
-	EXPORT CyExitCriticalSection
-	MSR PRIMASK, r0         ; Restore interrupt state
-	BX lr
-	ENDFUNC
+    EXPORT CyExitCriticalSection
+    MSR PRIMASK, r0         ; Restore interrupt state
+    BX lr
+    ENDFUNC
 
-	END
+    END
 
 ; [] END OF FILE

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.c
-* Version 3.40
+* Version 4.0
 *
 * Description:
 *  Provides an API for the DMAC component. The API includes functions for the
@@ -29,9 +29,17 @@
 
 #include "CyDmac.h"
 
-static uint8  CyDmaTdCurrentNumber;                      /* Current Number of free elements in the list */
-static uint8  CyDmaTdFreeIndex;                          /* Index of the first available TD */
-static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;  /* Bit map of DMA channel ownership */
+
+/*******************************************************************************
+* The following variables are initialized from CyDmacConfigure() function that
+* is executed from initialize_psoc() at the early initialization stage.
+* In case of IAR EW IDE, initialize_psoc() is executed before the data sections
+* are initialized. To avoid zeroing, these variables should be initialized
+* properly during segments initialization as well.
+*******************************************************************************/
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements in the list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
 
 
 /*******************************************************************************
@@ -55,13 +63,13 @@ void CyDmacConfigure(void)
     uint8 dmaIndex;
 
     /* Set TD list variables. */
-    CyDmaTdFreeIndex     = ((uint8) (CY_DMA_NUMBEROF_TDS - 1u));
+    CyDmaTdFreeIndex     = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);
     CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;
 
     /* Make TD free list. */
-    for(dmaIndex = ((uint8)(CY_DMA_NUMBEROF_TDS - 1u)); dmaIndex != 0u; dmaIndex--)
+    for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)
     {
-        CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = ((uint8)(dmaIndex - 1u));
+        CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
     }
 
     /* Make the last one point to zero. */
@@ -299,8 +307,22 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
 
     if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
     {
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =
-                (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~0x20u))) | ((0u != preserveTds) ? 0x21u : 0x01u);
+        if (0u != preserveTds)
+        {
+            /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve the original TD chain
+            */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
+        }
+        else
+        {
+            /* Store the intermediate and final TD states on top of the original TD chain */
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
+        }
+
+        /* Enable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;
+
         status = CYRET_SUCCESS;
     }
 
@@ -335,7 +357,16 @@ cystatus CyDmaChDisable(uint8 chHandle)
 
     if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
     {
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~0x21u));
+        /***********************************************************************
+        * Should not change configuration information of a DMA channel when it
+        * is active (or vulnerable to becoming active).
+        ***********************************************************************/
+
+        /* Disable channel */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
+
+        /* Store the intermediate and final TD states on top of the original TD chain */
+        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
         status = CYRET_SUCCESS;
     }
 
@@ -440,6 +471,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
     
 {
     cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
 
     #if(CY_PSOC5)
 
@@ -460,11 +492,12 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
     if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
     {
         /* Set source address */
-        reg16 *convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
         CY_SET_REG16(convert, source);
 
         /* Set destination address */
-        CY_SET_REG16((reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2], destination);
+        convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];
+        CY_SET_REG16(convert, destination);
         status = CYRET_SUCCESS;
     }
 
@@ -570,7 +603,7 @@ cystatus CyDmaChGetRequest(uint8 chHandle)
 
     if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
     {
-        status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & 
+        status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
                             (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));
     }
 
@@ -977,15 +1010,17 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
 cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) 
 {
     cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
         /* Set source address */
-        reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
         CY_SET_REG16(convert, source);
 
         /* Set destination address */
-        CY_SET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2], destination);
+        convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+        CY_SET_REG16(convert, destination);
 
         status = CYRET_SUCCESS;
     }
@@ -1023,6 +1058,7 @@ cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination)
 cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) 
 {
     cystatus status = CYRET_BAD_PARAM;
+    reg16 *convert;
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
@@ -1030,7 +1066,7 @@ cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination
         if(NULL != source)
         {
             /* Get source address */
-            reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
             *source = CY_GET_REG16(convert);
         }
 
@@ -1038,7 +1074,8 @@ cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination
         if(NULL != destination)
         {
             /* Get Destination address. */
-            *destination = CY_GET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2]);
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
+            *destination = CY_GET_REG16(convert);
         }
 
         status = CYRET_SUCCESS;
@@ -1075,9 +1112,14 @@ cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR)
 
     if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
     {
-        CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =
-                (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &  ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))) |
-                ((0u != enableRR) ? CY_DMA_ROUND_ROBIN_ENABLE : ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE)));
+        if (0u != enableRR)
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;
+        }
+        else
+        {
+            CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);
+        }
 
         status = CYRET_SUCCESS;
     }

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.h
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Provides the function definitions for the DMA Controller.
@@ -43,20 +43,24 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
 cystatus CyDmaChDisable(uint8 chHandle) ;
 cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
 cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
-cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination);
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
+;
 cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
 cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
 cystatus CyDmaChGetRequest(uint8 chHandle) ;
 cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
-cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ;
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
+                                 uint8 tdDone1, uint8 tdStop) ;
 cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
 
 /* Transfer Descriptor functions. */
 uint8    CyDmaTdAllocate(void) ;
 void     CyDmaTdFree(uint8 tdHandle) ;
 uint8    CyDmaTdFreeCount(void) ;
-cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ;
-cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ;
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
+;
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
+;
 cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
 cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
 
@@ -108,10 +112,7 @@ typedef struct dmac_tdmem2_struct
 #define CY_DMA_INVALID_CHANNEL      0xFFu   /* Invalid Channel ID */
 #define CY_DMA_INVALID_TD           0xFFu   /* Invalid TD */
 #define CY_DMA_END_CHAIN_TD         0xFFu   /* End of chain TD */
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-    #define CY_DMA_DISABLE_TD       0xFEu
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+#define CY_DMA_DISABLE_TD           0xFEu
 
 #define CY_DMA_TD_SIZE              0x08u
 
@@ -146,6 +147,13 @@ typedef struct dmac_tdmem2_struct
 #define CY_DMA_ROUND_ROBIN_ENABLE   ((uint8)(1u << 4u))
 
 
+/*******************************************************************************
+* CyDmaChEnable() / CyDmaChDisable() API constants
+*******************************************************************************/
+#define CY_DMA_CH_BASIC_CFG_EN           (0x01u)
+#define CY_DMA_CH_BASIC_CFG_WORK_SEP     (0x20u)
+
+
 /***************************************
 * Registers
 ***************************************/
@@ -195,9 +203,7 @@ typedef struct dmac_tdmem2_struct
 #define DMAC_UNPOP_ACC              (CY_DMA_UNPOP_ACC)
 #define DMAC_PERIPH_ERR             (CY_DMA_PERIPH_ERR)
 #define ROUND_ROBIN_ENABLE          (CY_DMA_ROUND_ROBIN_ENABLE)
-#if(CY_PSOC3 || CY_PSOC5LP)
-    #define DMA_DISABLE_TD          (CY_DMA_DISABLE_TD)
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+#define DMA_DISABLE_TD              (CY_DMA_DISABLE_TD)
 
 #define DMAC_CFG                    (CY_DMA_CFG_PTR)
 #define DMAC_ERR                    (CY_DMA_ERR_PTR)

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.c
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Provides an API for the FLASH/EEPROM.
@@ -42,10 +42,7 @@ static cystatus CySetTempInt(void);
 ********************************************************************************
 *
 * Summary:
-*  Enable the EEPROM/Flash.
-*
-*  Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and
-*  PSOC 5LP  this will enable only Flash.
+*  Enable the Flash.
 *
 * Parameters:
 *  None
@@ -56,25 +53,11 @@ static cystatus CySetTempInt(void);
 *******************************************************************************/
 void CyFlash_Start(void) 
 {
-    #if(CY_PSOC5A)
-
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
-
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
-
-    #endif  /* (CY_PSOC5A) */
-
-    #if(CY_PSOC3 || CY_PSOC5LP)
+    /* Active Power Mode */
+    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
 
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
-
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
-
-    #endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+    /* Standby Power Mode */
+    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
 
     CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
 }
@@ -85,11 +68,7 @@ void CyFlash_Start(void)
 ********************************************************************************
 *
 * Summary:
-*  Disable the EEPROM/Flash.
-*
-*  Note:
-*  PSoC 5: disable both Flash and EEPROM.
-*  PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM.
+*  Disable the Flash.
 *
 * Parameters:
 *  None
@@ -104,25 +83,11 @@ void CyFlash_Start(void)
 *******************************************************************************/
 void CyFlash_Stop(void) 
 {
-    #if (CY_PSOC5A)
+    /* Active Power Mode */
+    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
 
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
-
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
-
-    #endif  /* (CY_PSOC5A) */
-
-    #if (CY_PSOC3 || CY_PSOC5LP)
-
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
-
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
-
-    #endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+    /* Standby Power Mode */
+    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
 }
 
 
@@ -158,30 +123,26 @@ static cystatus CySetTempInt(void)
     if(CySpcLock() == CYRET_SUCCESS)
     {
         /* Write the command. */
-        #if(CY_PSOC5A)
-            if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT))
-        #else
-            if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
-        #endif  /* (CY_PSOC5A) */
+        if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
+        {
+            do
             {
-                do
+                if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
                 {
-                    if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
-                    {
-                        status = CYRET_SUCCESS;
+                    status = CYRET_SUCCESS;
 
-                        while(CY_SPC_BUSY)
-                        {
-                            /* Spin until idle. */
-                            CyDelayUs(1u);
-                        }
-                        break;
+                    while(CY_SPC_BUSY)
+                    {
+                        /* Spin until idle. */
+                        CyDelayUs(1u);
                     }
+                    break;
+                }
 
-                } while(CY_SPC_BUSY);
-            }
+            } while(CY_SPC_BUSY);
+        }
 
-            CySpcUnlock();
+        CySpcUnlock();
     }
     else
     {
@@ -288,15 +249,17 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *   Sends a command to the SPC to load and program a row of data in flash.
+    *  Sends a command to the SPC to load and program a row of data in
+    *  Flash or EEPROM.
     *
     * Parameters:
-    *  arrayID:
-    *   ID of the array to write.
-    *  rowAddress:
-    *   rowAddress of flash row to program.
-    *  rowData:
-    *   Array of bytes to write.
+    *  arrayID:    ID of the array to write.
+    *   The type of write, Flash or EEPROM, is determined from the array ID.
+    *   The arrays in the part are sequential starting at the first ID for the
+    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+    *  rowAddress: rowAddress of flash row to program.
+    *  rowData:    Array of bytes to write.
     *
     * Return:
     *  status:
@@ -324,10 +287,15 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *   Sends a command to the SPC to load and program a row of data in flash.
+    *   Sends a command to the SPC to load and program a row of data in
+    *   Flash or EEPROM.
     *
     * Parameters:
     *  arrayID      : ID of the array to write.
+    *   The type of write, Flash or EEPROM, is determined from the array ID.
+    *   The arrays in the part are sequential starting at the first ID for the
+    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
     *  rowAddress   : rowAddress of flash row to program.
     *  rowData      : Array of bytes to write.
     *
@@ -346,30 +314,41 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
         uint16 rowSize;
         cystatus status;
 
-        rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \
-                    CYDEV_EEPROM_ROW_SIZE : \
-                    (CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
-
-        if(rowSize != CYDEV_EEPROM_ROW_SIZE)
+        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
+        if(NULL != rowBuffer)
         {
-            /* Save the ECC area. */
-            offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) +
-                    ((uint32) rowAddress * CYDEV_ECC_ROW_SIZE);
-
-            for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+            if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
             {
-                *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                rowSize = CYDEV_EEPROM_ROW_SIZE;
             }
-        }
+            else
+            {
+                rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
 
-        /* Copy the rowdata to the temporary buffer. */
+                /* Save the ECC area. */
+                offset = CYDEV_ECC_BASE +
+                        ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
+                        ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
+
+                for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                {
+                    *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                }
+            }
+
+            /* Copy the rowdata to the temporary buffer. */
         #if(CY_PSOC3)
             (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
         #else
             (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
         #endif  /* (CY_PSOC3) */
 
-        status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
+            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
+        }
+        else
+        {
+            status = CYRET_UNKNOWN;
+        }
 
         return(status);
     }
@@ -388,12 +367,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *  This function is only valid for Flash array IDs (not for EEPROM).
     *
     * Parameters:
-    *  arrayId:
-    *   ID of the array to write
-    *  rowAddress:
-    *   Address of the sector to erase.
-    *  rowECC:
-    *   Array of bytes to write.
+    *  arrayId:      ID of the array to write
+    *   The arrays in the part are sequential starting at the first ID for the
+    *   specific memory type. The array ID for the Flash memory lasts
+    *   from 0x00 to 0x3F.
+    *  rowAddress:   Address of the sector to erase.
+    *  rowECC:       Array of bytes to write.
     *
     * Return:
     *  status:
@@ -403,32 +382,45 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *   CYRET_UNKNOWN if there was an SPC error.
     *
     *******************************************************************************/
-    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) 
+    cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
+    
     {
         uint32 offset;
         uint16 i;
         cystatus status;
 
-        /* Read the existing flash data. */
-        offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) +
-            ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE);
-            
-        #if (CYDEV_FLS_BASE != 0u)
-            offset += CYDEV_FLS_BASE;
-        #endif
-
-        for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
+        if(NULL != rowBuffer)
         {
-            rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-        }
+            /* Read the existing flash data. */
+            offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
+                     ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
 
-        #if(CY_PSOC3)
-            (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE);
-        #else
-            (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE);
-        #endif  /* (CY_PSOC3) */
+            #if (CYDEV_FLS_BASE != 0u)
+                offset += CYDEV_FLS_BASE;
+            #endif  /* (CYDEV_FLS_BASE != 0u) */
 
-        status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
+            for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+            {
+                rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+            }
+
+            #if(CY_PSOC3)
+                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
+                              (void *)(uint32)rowECC,
+                              (int16)CYDEV_ECC_ROW_SIZE);
+            #else
+                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
+                              (const void *)rowECC,
+                              CYDEV_ECC_ROW_SIZE);
+            #endif  /* (CY_PSOC3) */
+
+            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
+        }
+        else
+        {
+            status = CYRET_UNKNOWN;
+        }
 
         return (status);
     }
@@ -441,20 +433,20 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 * Function Name: CyWriteRowFull
 ********************************************************************************
 * Summary:
-*   Sends a command to the SPC to load and program a row of data in flash.
-*   rowData array is expected to contain Flash and ECC data if needed.
+*  Sends a command to the SPC to load and program a row of data in flash.
+*  rowData array is expected to contain Flash and ECC data if needed.
 *
 * Parameters:
-*       arrayId: FLASH or EEPROM array id.
-*       rowData: pointer to a row of data to write.
-*       rowNumber: Zero based number of the row.
-*       rowSize: Size of the row.
+*  arrayId:    FLASH or EEPROM array id.
+*  rowData:    Pointer to a row of data to write.
+*  rowNumber:  Zero based number of the row.
+*  rowSize:    Size of the row.
 *
 * Return:
-*   CYRET_SUCCESS if successful.
-*   CYRET_LOCKED if the SPC is already in use.
-*   CYRET_CANCELED if command not accepted
-*   CYRET_UNKNOWN if there was an SPC error.
+*  CYRET_SUCCESS if successful.
+*  CYRET_LOCKED if the SPC is already in use.
+*  CYRET_CANCELED if command not accepted
+*  CYRET_UNKNOWN if there was an SPC error.
 *
 *******************************************************************************/
 cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
@@ -575,7 +567,7 @@ void CyFlash_SetWaitCycles(uint8 freq)
     #endif  /* (CY_PSOC3) */
 
 
-    #if (CY_PSOC5A)
+    #if (CY_PSOC5)
 
         if (freq <= 16u)
         {
@@ -598,89 +590,59 @@ void CyFlash_SetWaitCycles(uint8 freq)
                 ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
         }
 
-    #endif  /* (CY_PSOC5A) */
-
-
-    #if (CY_PSOC5LP)
-
-        if (freq <= 16u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 33u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 50u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC5LP) */
+    #endif  /* (CY_PSOC5) */
 
     /* Restore global interrupt enable state */
     CyExitCriticalSection(interruptState);
 }
 
 
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    /*******************************************************************************
-    * Function Name: CyEEPROM_Start
-    ********************************************************************************
-    *
-    * Summary:
-    *  Enable the EEPROM.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CyEEPROM_Start(void) 
-    {
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
-
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
-    }
+/*******************************************************************************
+* Function Name: CyEEPROM_Start
+********************************************************************************
+*
+* Summary:
+*  Enable the EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_Start(void) 
+{
+    /* Active Power Mode */
+    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
 
+    /* Standby Power Mode */
+    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+}
 
-    /*******************************************************************************
-    * Function Name: CyEEPROM_Stop
-    ********************************************************************************
-    *
-    * Summary:
-    *  Disable the EEPROM.
-    *
-    * Parameters:
-    *  None
-    *
-    * Return:
-    *  None
-    *
-    *******************************************************************************/
-    void CyEEPROM_Stop (void) 
-    {
-        /* Active Power Mode */
-        *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
 
-        /* Standby Power Mode */
-        *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
-    }
+/*******************************************************************************
+* Function Name: CyEEPROM_Stop
+********************************************************************************
+*
+* Summary:
+*  Disable the EEPROM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+void CyEEPROM_Stop (void) 
+{
+    /* Active Power Mode */
+    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
 
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+    /* Standby Power Mode */
+    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+}
 
 
 /*******************************************************************************

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.h
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Provides the function definitions for the FLASH/EEPROM.
@@ -75,10 +75,8 @@ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
 void CyFlash_SetWaitCycles(uint8 freq) ;
 
 /* EEPROM Functions */
-#if (CY_PSOC3 || CY_PSOC5LP)
-    void CyEEPROM_Start(void) ;
-    void CyEEPROM_Stop(void) ;
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+void CyEEPROM_Start(void) ;
+void CyEEPROM_Stop(void) ;
 
 void CyEEPROM_ReadReserve(void) ;
 void CyEEPROM_ReadRelease(void) ;
@@ -87,31 +85,13 @@ void CyEEPROM_ReadRelease(void) ;
 /***************************************
 *     Registers
 ***************************************/
+/* Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
 
-#if (CY_PSOC5A)
-
-    /* Active Power Mode Configuration Register 0 */
-    #define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG0)
-    #define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG0)
-
-    /* Alternate Active Power Mode Configuration Register 0 */
-    #define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG0)
-    #define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG0)
-
-#endif  /* (CY_PSOC5A) */
-
-
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    /* Active Power Mode Configuration Register 12 */
-    #define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-    #define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
-
-    /* Alternate Active Power Mode Configuration Register 12 */
-    #define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-    #define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+/* Alternate Active Power Mode Configuration Register 12 */
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
 
 
 /* Cache Control Register */
@@ -139,19 +119,8 @@ void CyEEPROM_ReadRelease(void) ;
 ***************************************/
 
 /* Power Mode Masks */
-#if(CY_PSOC5A)
-
-    #define CY_FLASH_PM_FLASH_EE_MASK           (0x80u)
-
-#endif  /* (CY_PSOC5A) */
-
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    #define CY_FLASH_PM_EE_MASK                 (0x10u)
-    #define CY_FLASH_PM_FLASH_MASK              (0x01u)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
-
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
 
 /* Frequency Constants */
 #if (CY_PSOC3)
@@ -162,23 +131,14 @@ void CyEEPROM_ReadRelease(void) ;
 
 #endif  /* (CY_PSOC3) */
 
-#if (CY_PSOC5A)
-
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-
-#endif  /* (CY_PSOC5A) */
-
-#if (CY_PSOC5LP)
+#if (CY_PSOC5)
 
     #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
     #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
     #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
     #define CY_FLASH_GREATER_51MHz              (0x00u)
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 #define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
 #define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
@@ -238,37 +198,14 @@ void CyEEPROM_ReadRelease(void) ;
 #define ECC_ADDR                    (0x80u)
 
 
-#if (CY_PSOC5A)
-
-    #define PM_ACT_EEFLASH          (CY_FLASH_PM_ACT_EEFLASH_PTR)
-    #define PM_STBY_EEFLASH         (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
-
-#endif  /* (CY_PSOC5A) */
-
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    #define PM_ACT_EE_PTR           (CY_FLASH_PM_ACT_EEFLASH_PTR)
-    #define PM_ACT_FLASH_PTR        (CY_FLASH_PM_ACT_EEFLASH_PTR)
-
-    #define PM_STBY_EE_PTR          (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
-    #define PM_STBY_FLASH_PTR       (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-#if(CY_PSOC5A)
-
-    #define PM_FLASH_EE_MASK        (CY_FLASH_PM_FLASH_EE_MASK)
+#define PM_ACT_EE_PTR           (CY_FLASH_PM_ACT_EEFLASH_PTR)
+#define PM_ACT_FLASH_PTR        (CY_FLASH_PM_ACT_EEFLASH_PTR)
 
-#endif  /* (CY_PSOC5A) */
-
-#if (CY_PSOC3 || CY_PSOC5LP)
-
-    #define PM_EE_MASK              (CY_FLASH_PM_EE_MASK)
-    #define PM_FLASH_MASK           (CY_FLASH_PM_FLASH_MASK)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+#define PM_STBY_EE_PTR          (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
+#define PM_STBY_FLASH_PTR       (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
 
+#define PM_EE_MASK              (CY_FLASH_PM_EE_MASK)
+#define PM_FLASH_MASK           (CY_FLASH_PM_FLASH_MASK)
 
 #define FLASH_CYCLES_MASK_SHIFT     (CY_FLASH_CYCLES_MASK_SHIFT)
 #define FLASH_CYCLES_MASK           (CY_FLASH_CYCLES_MASK)
@@ -282,16 +219,7 @@ void CyEEPROM_ReadRelease(void) ;
 
 #endif  /* (CY_PSOC3) */
 
-#if (CY_PSOC5A)
-
-    #define LESSER_OR_EQUAL_16MHz   (CY_FLASH_LESSER_OR_EQUAL_16MHz)
-    #define LESSER_OR_EQUAL_33MHz   (CY_FLASH_LESSER_OR_EQUAL_33MHz)
-    #define LESSER_OR_EQUAL_50MHz   (CY_FLASH_LESSER_OR_EQUAL_50MHz)
-    #define GREATER_51MHz           (CY_FLASH_GREATER_51MHz)
-
-#endif  /* (CY_PSOC5A) */
-
-#if (CY_PSOC5LP)
+#if (CY_PSOC5)
 
     #define LESSER_OR_EQUAL_16MHz   (CY_FLASH_LESSER_OR_EQUAL_16MHz)
     #define LESSER_OR_EQUAL_33MHz   (CY_FLASH_LESSER_OR_EQUAL_33MHz)
@@ -300,7 +228,7 @@ void CyEEPROM_ReadRelease(void) ;
     #define GREATER_67MHz           (CY_FLASH_GREATER_67MHz)
     #define GREATER_51MHz           (CY_FLASH_GREATER_51MHz)
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 #define AHUB_EE_REQ_ACK_PTR         (CY_FLASH_EE_SCR_PTR)
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyLib.h
-* Version 3.40
+* Version 4.0
 *
 * Description:
 *  Provides the function definitions for the system, clocking, interrupts and
@@ -34,31 +34,23 @@
 #endif  /* (CY_PSOC3) */
 
 
-#if(!CY_PSOC5A)
+#if(CYDEV_VARIABLE_VDDA == 1)
 
-    #if(CYDEV_VARIABLE_VDDA == 1)
+    #include "CyScBoostClk.h"
 
-        #include "CyScBoostClk.h"
-
-    #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-#endif /* (!CY_PSOC5A) */
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
 /* Global variable with preserved reset status */
 extern uint8 CYXDATA CyResetStatus;
 
 
-#if(!CY_PSOC5A)
-
-    /* Variable Vdda */
-    #if(CYDEV_VARIABLE_VDDA == 1)
-
-        extern uint8 CyScPumpEnabled;
+/* Variable Vdda */
+#if(CYDEV_VARIABLE_VDDA == 1)
 
-    #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+    extern uint8 CyScPumpEnabled;
 
-#endif /* (!CY_PSOC5A) */
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
 /* Do not use these definitions directly in your application */
@@ -110,18 +102,15 @@ void  CyXTAL_32KHZ_Stop(void) ;
 cystatus CyXTAL_Start(uint8 wait) ;
 void  CyXTAL_Stop(void) ;
 void  CyXTAL_SetStartup(uint8 setting) ;
-#if(!CY_PSOC5A)
-    void  CyXTAL_EnableErrStatus(void) ;
-    void  CyXTAL_DisableErrStatus(void) ;
-    uint8 CyXTAL_ReadStatus(void) ;
-    void  CyXTAL_EnableFaultRecovery(void) ;
-    void  CyXTAL_DisableFaultRecovery(void) ;
-#endif  /* (!CY_PSOC5A) */
-
-#if(CY_PSOC3 || CY_PSOC5LP)
-    void CyXTAL_SetFbVoltage(uint8 setting) ;
-    void CyXTAL_SetWdVoltage(uint8 setting) ;
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void  CyXTAL_EnableErrStatus(void) ;
+void  CyXTAL_DisableErrStatus(void) ;
+uint8 CyXTAL_ReadStatus(void) ;
+void  CyXTAL_EnableFaultRecovery(void) ;
+void  CyXTAL_DisableFaultRecovery(void) ;
+
+void CyXTAL_SetFbVoltage(uint8 setting) ;
+void CyXTAL_SetWdVoltage(uint8 setting) ;
 
 void CyWdtStart(uint8 ticks, uint8 lpMode) ;
 void CyWdtClear(void) ;
@@ -172,11 +161,7 @@ void CyVdHvAnalogDisable(void) ;
 uint8 CyVdStickyStatus(uint8 mask) ;
 uint8 CyVdRealTimeStatus(void) ;
 
-#if(!CY_PSOC5A)
-
-    void CySetScPumps(uint8 enable) ;
-
-#endif /* (!CY_PSOC5A) */
+void CySetScPumps(uint8 enable) ;
 
 
 /***************************************
@@ -207,7 +192,6 @@ uint8 CyVdRealTimeStatus(void) ;
 *******************************************************************************/
 #define CY_XTAL32K_ANA_STAT             (0x20u)
 
-
 #define CY_CLK_XTAL32_CR_LPM            (0x02u)
 #define CY_CLK_XTAL32_CR_EN             (0x01u)
 #if(CY_PSOC3)
@@ -285,49 +269,48 @@ uint8 CyVdRealTimeStatus(void) ;
 
 
 /*******************************************************************************
-*    Variable VDDA
+*    Variable VDDA API Constants
 *******************************************************************************/
-#if(!CY_PSOC5A)
-
-    #if(CYDEV_VARIABLE_VDDA == 1)
+#if(CYDEV_VARIABLE_VDDA == 1)
 
-        /* Active Power Mode Configuration Register 9 */
-        #define CY_LIB_ACT_CFG9_SWCAP0_EN        (0x01u)
-        #define CY_LIB_ACT_CFG9_SWCAP1_EN        (0x02u)
-        #define CY_LIB_ACT_CFG9_SWCAP2_EN        (0x04u)
-        #define CY_LIB_ACT_CFG9_SWCAP3_EN        (0x08u)
-        #define CY_LIB_ACT_CFG9_SWCAPS_MASK      (0x0Fu)
+    /* Active Power Mode Configuration Register 9 */
+    #define CY_LIB_ACT_CFG9_SWCAP0_EN        (0x01u)
+    #define CY_LIB_ACT_CFG9_SWCAP1_EN        (0x02u)
+    #define CY_LIB_ACT_CFG9_SWCAP2_EN        (0x04u)
+    #define CY_LIB_ACT_CFG9_SWCAP3_EN        (0x08u)
+    #define CY_LIB_ACT_CFG9_SWCAPS_MASK      (0x0Fu)
 
-        /* Switched Cap Miscellaneous Control Register */
-        #define CY_LIB_SC_MISC_PUMP_FORCE        (0x20u)
+    /* Switched Cap Miscellaneous Control Register */
+    #define CY_LIB_SC_MISC_PUMP_FORCE        (0x20u)
 
-        /* Switched Capacitor 0 Boost Clock Selection Register */
-        #define CY_LIB_SC_BST_CLK_EN             (0x08u)
-        #define CY_LIB_SC_BST_CLK_INDEX_MASK     (0xF8u)
+    /* Switched Capacitor 0 Boost Clock Selection Register */
+    #define CY_LIB_SC_BST_CLK_EN             (0x08u)
+    #define CY_LIB_SC_BST_CLK_INDEX_MASK     (0xF8u)
 
-    #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
-
-#endif /* (!CY_PSOC5A) */
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
 /*******************************************************************************
-* Clock Distribution Constants
+* Clock Distribution API Constants
 *******************************************************************************/
 #define CY_LIB_CLKDIST_AMASK_MASK       (0xF0u)
 #define CY_LIB_CLKDIST_DMASK_MASK       (0x00u)
 #define CY_LIB_CLKDIST_LD_LOAD          (0x01u)
-#define CY_LIB_CLKDIST_BCFG2_MASK       (0x80u) /* Enable shadow loads */
+#define CY_LIB_CLKDIST_BCFG2_MASK       (0x80u)
 #define CY_LIB_CLKDIST_MASTERCLK_DIV    (7u)
-#define CY_LIB_CLKDIST_BCFG2_SSS        (0x40u) /* Sync source is same frequency */
+#define CY_LIB_CLKDIST_BCFG2_SSS        (0x40u)
 #define CY_LIB_CLKDIST_MSTR1_SRC_MASK   (0xFCu)
 #define CY_LIB_FASTCLK_IMO_DOUBLER      (0x10u)
 #define CY_LIB_FASTCLK_IMO_IMO          (0x20u)
 #define CY_LIB_CLKDIST_CR_IMO2X         (0x40u)
 #define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)
 
-#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK   (0xFCu)
+#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK  (0xFCu)
 
-#define ILO_CONTROL_PD_MODE             (0x10u)
+
+/* CyILO_SetPowerMode() */
+#define CY_ILO_CONTROL_PD_MODE          (0x10u)
+#define CY_ILO_CONTROL_PD_POSITION      (4u)
 
 #define CY_ILO_SOURCE_100K              (0u)
 #define CY_ILO_SOURCE_33K               (1u)
@@ -341,7 +324,6 @@ uint8 CyVdRealTimeStatus(void) ;
 #define CY_ILO_SOURCE_33K_SET           (0x04u)
 #define CY_ILO_SOURCE_100K_SET          (0x00u)
 
-
 #define CY_MASTER_SOURCE_IMO            (0u)
 #define CY_MASTER_SOURCE_PLL            (1u)
 #define CY_MASTER_SOURCE_XTAL           (2u)
@@ -350,16 +332,21 @@ uint8 CyVdRealTimeStatus(void) ;
 #define CY_IMO_SOURCE_IMO               (0u)
 #define CY_IMO_SOURCE_XTAL              (1u)
 #define CY_IMO_SOURCE_DSI               (2u)
-#define IMO_PM_ENABLE                   (0x10u)    /* Enable IMO clock source. */
-#define FASTCLK_IMO_USBCLK_ON_SET       (0x40u)
 
-#define CLOCK_IMO_3MHZ_VALUE            (0x03u)
-#define CLOCK_IMO_6MHZ_VALUE            (0x01u)
-#define CLOCK_IMO_12MHZ_VALUE           (0x00u)
-#define CLOCK_IMO_24MHZ_VALUE           (0x02u)
-#define CLOCK_IMO_48MHZ_VALUE           (0x04u)
-#define CLOCK_IMO_62MHZ_VALUE           (0x05u)
-#define CLOCK_IMO_74MHZ_VALUE           (0x06u)
+
+/* CyIMO_Start() */
+#define CY_LIB_PM_ACT_CFG0_IMO_EN       (0x10u)
+#define CY_LIB_PM_STBY_CFG0_IMO_EN      (0x10u)
+#define CY_LIB_CLK_IMO_FTW_TIMEOUT      (0x00u)
+
+#define CY_LIB_IMO_3MHZ_VALUE           (0x03u)
+#define CY_LIB_IMO_6MHZ_VALUE           (0x01u)
+#define CY_LIB_IMO_12MHZ_VALUE          (0x00u)
+#define CY_LIB_IMO_24MHZ_VALUE          (0x02u)
+#define CY_LIB_IMO_48MHZ_VALUE          (0x04u)
+#define CY_LIB_IMO_62MHZ_VALUE          (0x05u)
+#define CY_LIB_IMO_74MHZ_VALUE          (0x06u)
+
 
 /* CyIMO_SetFreq() */
 #define CY_IMO_FREQ_3MHZ                (0u)
@@ -367,42 +354,48 @@ uint8 CyVdRealTimeStatus(void) ;
 #define CY_IMO_FREQ_12MHZ               (2u)
 #define CY_IMO_FREQ_24MHZ               (3u)
 #define CY_IMO_FREQ_48MHZ               (4u)
-#if(!CY_PSOC5A)
-    #define CY_IMO_FREQ_62MHZ           (5u)
-#endif  /* (!CY_PSOC5A) */
+#define CY_IMO_FREQ_62MHZ               (5u)
+#if(CY_PSOC5)
+    #define CY_IMO_FREQ_74MHZ           (6u)
+#endif  /* (CY_PSOC5) */
 #define CY_IMO_FREQ_USB                 (8u)
 
+#define CY_LIB_IMO_USBCLK_ON_SET        (0x40u)
 
-#define SFR_USER_CPUCLK_DIV_MASK        (0x0Fu)
-#define CLKDIST_DIV_POSITION            (4u)
-#define CLKDIST_MSTR1_DIV_CLEAR         (0x0Fu)
-#define CLOCK_USB_ENABLE                (0x02u)
-#define CLOCK_IMO_OUT_X2                (0x10u)
-#define CLOCK_IMO_OUT_X1                ((uint8)(~CLOCK_IMO_OUT_X2))
+
+/* CyCpuClk_SetDivider() */
+#define CY_LIB_CLKDIST_DIV_POSITION     (4u)
+#define CY_LIB_CLKDIST_MSTR1_DIV_MASK   (0x0Fu)
+
+
+/* CyIMO_SetTrimValue() */
+#define CY_LIB_USB_CLK_EN               (0x02u)
+
+
+/* CyPLL_OUT_SetSource() - parameters */
 #define CY_PLL_SOURCE_IMO               (0u)
 #define CY_PLL_SOURCE_XTAL              (1u)
 #define CY_PLL_SOURCE_DSI               (2u)
 
-#define CLOCK_IMO2X_ECO                 ((uint8)(~CLOCK_IMO2X_DSI))
 
-#define ILO_CONTROL_PD_POSITION         (4u)
-#define ILO_CONTROL_1KHZ_ON             (0x02u)
-#define ILO_CONTROL_100KHZ_ON           (0x04u)
-#define ILO_CONTROL_33KHZ_ON            (0x20u)
+/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ   (0x02u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ  (0x20u)
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)
 
-#define USB_CLKDIST_CONFIG_MASK         (0x03u)
-#define USB_CLK_IMO2X                   (0x00u)
-#define USB_CLK_IMO                     (0x01u)
-#define USB_CLK_PLL                     (0x02u)
-#define USB_CLK_DSI                     (0x03u)
-#define USB_CLK_DIV2_ON                 (0x04u)
-#define USB_CLK_STOP_FLAG               (0x00u)
-#define USB_CLK_START_FLAG              (0x01u)
 
-#define FTW_CLEAR_ALL_BITS              (0x00u) /* To clear all bits of PM_TW_CFG2 */
-#define FTW_CLEAR_FTW_BITS              (0xFCu) /* To clear FTW bits of PM_TW_CFG2 */
-#define FTW_ENABLE                      (0x01u) /* To enable FTW, no interrupt */
+/* CyUsbClk_SetSource() */
+#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)
+
 
+/* CyUsbClk_SetSource() - parameters */
+#define CY_LIB_USB_CLK_IMO2X            (0x00u)
+#define CY_LIB_USB_CLK_IMO              (0x01u)
+#define CY_LIB_USB_CLK_PLL              (0x02u)
+#define CY_LIB_USB_CLK_DSI              (0x03u)
+
+
+/* CyUSB_PowerOnCheck() */
 #define CY_ACT_USB_ENABLED              (0x01u)
 #define CY_ALT_ACT_USB_ENABLED          (0x01u)
 
@@ -412,6 +405,72 @@ uint8 CyVdRealTimeStatus(void) ;
 ***************************************/
 
 
+/*******************************************************************************
+* System Registers
+*******************************************************************************/
+
+/* Software Reset Control Register */
+#define CY_LIB_RESET_CR2_REG         (* (reg8 *) CYREG_RESET_CR2)
+#define CY_LIB_RESET_CR2_PTR         (  (reg8 *) CYREG_RESET_CR2)
+
+/* Timewheel Configuration Register 0 */
+#define CY_LIB_PM_TW_CFG0_REG           (*(reg8 *) CYREG_PM_TW_CFG0)
+#define CY_LIB_PM_TW_CFG0_PTR           ( (reg8 *) CYREG_PM_TW_CFG0)
+
+/* Timewheel Configuration Register 2 */
+#define CY_LIB_PM_TW_CFG2_REG           (*(reg8 *) CYREG_PM_TW_CFG2)
+#define CY_LIB_PM_TW_CFG2_PTR           ( (reg8 *) CYREG_PM_TW_CFG2)
+
+/* USB Configuration Register */
+#define CY_LIB_CLKDIST_UCFG_REG         (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CY_LIB_CLKDIST_UCFG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
+
+/* Internal Main Oscillator Trim Register 1 */
+#define CY_LIB_IMO_TR1_REG              (*(reg8 *) CYREG_IMO_TR1)
+#define CY_LIB_IMO_TR1_PTR              ( (reg8 *) CYREG_IMO_TR1)
+
+/* USB control 1 Register */
+#define CY_LIB_USB_CR1_REG              (*(reg8 *) CYREG_USB_CR1 )
+#define CY_LIB_USB_CR1_PTR              ( (reg8 *) CYREG_USB_CR1 )
+
+/* Active Power Mode Configuration Register 0 */
+#define CY_LIB_PM_ACT_CFG0_REG          (*(reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_LIB_PM_ACT_CFG0_PTR          ( (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Standby Power Mode Configuration Register 0 */
+#define CY_LIB_PM_STBY_CFG0_REG          (*(reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_LIB_PM_STBY_CFG0_PTR          ( (reg8 *) CYREG_PM_STBY_CFG0)
+
+/* Active Power Mode Configuration Register 5 */
+#define CY_LIB_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_LIB_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
+
+/* Standby Power Mode Configuration Register 5 */
+#define CY_LIB_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
+#define CY_LIB_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
+
+/* CyIMO_SetTrimValue() */
+#if(CY_PSOC3)
+    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define CY_LIB_TRIM_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define CY_LIB_TRIM_IMO_TR1_PTR          ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+ #else
+    #define CY_LIB_TRIM_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define CY_LIB_TRIM_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define CY_LIB_TRIM_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define CY_LIB_TRIM_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define CY_LIB_TRIM_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define CY_LIB_TRIM_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define CY_LIB_TRIM_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define CY_LIB_TRIM_IMO_TR1_PTR          ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+#endif  /* (CY_PSOC3) */
+
+
 /*******************************************************************************
 * PLL Registers
 *******************************************************************************/
@@ -442,16 +501,16 @@ uint8 CyVdRealTimeStatus(void) ;
 *******************************************************************************/
 
 /* External MHz Crystal Oscillator Status and Control Register */
-#define CY_CLK_XMHZ_CSR_REG           (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
-#define CY_CLK_XMHZ_CSR_PTR           ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
+#define CY_CLK_XMHZ_CSR_REG         (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
+#define CY_CLK_XMHZ_CSR_PTR         ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
 
 /* External MHz Crystal Oscillator Configuration Register 0 */
-#define CY_CLK_XMHZ_CFG0_REG           (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
-#define CY_CLK_XMHZ_CFG0_PTR           ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
+#define CY_CLK_XMHZ_CFG0_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
+#define CY_CLK_XMHZ_CFG0_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
 
 /* External MHz Crystal Oscillator Configuration Register 1 */
-#define CY_CLK_XMHZ_CFG1_REG           (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
-#define CY_CLK_XMHZ_CFG1_PTR           ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
+#define CY_CLK_XMHZ_CFG1_REG        (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
+#define CY_CLK_XMHZ_CFG1_PTR        ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
 
 
 /*******************************************************************************
@@ -459,20 +518,20 @@ uint8 CyVdRealTimeStatus(void) ;
 *******************************************************************************/
 
 /* 32 kHz Watch Crystal Oscillator Trim Register */
-#define CY_CLK_XTAL32_TR_REG            (*(reg8 *) CYREG_X32_TR)
-#define CY_CLK_XTAL32_TR_PTR            ( (reg8 *) CYREG_X32_TR)
+#define CY_CLK_XTAL32_TR_REG        (*(reg8 *) CYREG_X32_TR)
+#define CY_CLK_XTAL32_TR_PTR        ( (reg8 *) CYREG_X32_TR)
 
 /* External 32kHz Crystal Oscillator Test Register */
-#define CY_CLK_XTAL32_TST_REG           (*(reg8 *) CYREG_SLOWCLK_X32_TST)
-#define CY_CLK_XTAL32_TST_PTR           ( (reg8 *) CYREG_SLOWCLK_X32_TST)
+#define CY_CLK_XTAL32_TST_REG       (*(reg8 *) CYREG_SLOWCLK_X32_TST)
+#define CY_CLK_XTAL32_TST_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_TST)
 
 /* External 32kHz Crystal Oscillator Control Register */
-#define CY_CLK_XTAL32_CR_REG            (*(reg8 *) CYREG_SLOWCLK_X32_CR)
-#define CY_CLK_XTAL32_CR_PTR            ( (reg8 *) CYREG_SLOWCLK_X32_CR)
+#define CY_CLK_XTAL32_CR_REG        (*(reg8 *) CYREG_SLOWCLK_X32_CR)
+#define CY_CLK_XTAL32_CR_PTR        ( (reg8 *) CYREG_SLOWCLK_X32_CR)
 
 /* External 32kHz Crystal Oscillator Configuration Register */
-#define CY_CLK_XTAL32_CFG_REG           (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
-#define CY_CLK_XTAL32_CFG_PTR           ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
+#define CY_CLK_XTAL32_CFG_REG       (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
+#define CY_CLK_XTAL32_CFG_PTR       ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
 
 
 /*******************************************************************************
@@ -492,56 +551,52 @@ uint8 CyVdRealTimeStatus(void) ;
 *    LVI/HVI Registers
 *******************************************************************************/
 
-#define CY_VD_LVI_TRIP_REG             (* (reg8 *) CYDEV_RESET_CR0)
-#define CY_VD_LVI_TRIP_PTR             (  (reg8 *) CYDEV_RESET_CR0)
+#define CY_VD_LVI_TRIP_REG          (* (reg8 *) CYREG_RESET_CR0)
+#define CY_VD_LVI_TRIP_PTR          (  (reg8 *) CYREG_RESET_CR0)
 
-#define CY_VD_LVI_HVI_CONTROL_REG      (* (reg8 *) CYDEV_RESET_CR1)
-#define CY_VD_LVI_HVI_CONTROL_PTR      (  (reg8 *) CYDEV_RESET_CR1)
+#define CY_VD_LVI_HVI_CONTROL_REG   (* (reg8 *) CYREG_RESET_CR1)
+#define CY_VD_LVI_HVI_CONTROL_PTR   (  (reg8 *) CYREG_RESET_CR1)
 
-#define CY_VD_PRES_CONTROL_REG         (* (reg8 *) CYDEV_RESET_CR3)
-#define CY_VD_PRES_CONTROL_PTR         (  (reg8 *) CYDEV_RESET_CR3)
+#define CY_VD_PRES_CONTROL_REG      (* (reg8 *) CYREG_RESET_CR3)
+#define CY_VD_PRES_CONTROL_PTR      (  (reg8 *) CYREG_RESET_CR3)
 
-#define CY_VD_PERSISTENT_STATUS_REG    (* (reg8 *) CYDEV_RESET_SR0)
-#define CY_VD_PERSISTENT_STATUS_PTR    (  (reg8 *) CYDEV_RESET_SR0)
+#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0)
+#define CY_VD_PERSISTENT_STATUS_PTR (  (reg8 *) CYREG_RESET_SR0)
 
-#define CY_VD_RT_STATUS_REG            (* (reg8 *) CYDEV_RESET_SR2)
-#define CY_VD_RT_STATUS_PTR            (  (reg8 *) CYDEV_RESET_SR2)
+#define CY_VD_RT_STATUS_REG         (* (reg8 *) CYREG_RESET_SR2)
+#define CY_VD_RT_STATUS_PTR         (  (reg8 *) CYREG_RESET_SR2)
 
 
 /*******************************************************************************
 *    Variable VDDA
 *******************************************************************************/
-#if(!CY_PSOC5A)
-
-    #if(CYDEV_VARIABLE_VDDA == 1)
-
-        /* Active Power Mode Configuration Register 9 */
-        #define CY_LIB_ACT_CFG9_REG             (* (reg8 *) CYREG_PM_ACT_CFG9 )
-        #define CY_LIB_ACT_CFG9_PTR             (  (reg8 *) CYREG_PM_ACT_CFG9 )
+#if(CYDEV_VARIABLE_VDDA == 1)
 
-        /* Switched Capacitor 0 Boost Clock Selection Register */
-        #define CY_LIB_SC0_BST_REG             (* (reg8 *) CYREG_SC0_BST )
-        #define CY_LIB_SC0_BST_PTR             (  (reg8 *) CYREG_SC0_BST )
+    /* Active Power Mode Configuration Register 9 */
+    #define CY_LIB_ACT_CFG9_REG            (* (reg8 *) CYREG_PM_ACT_CFG9 )
+    #define CY_LIB_ACT_CFG9_PTR            (  (reg8 *) CYREG_PM_ACT_CFG9 )
 
-        /* Switched Capacitor 1 Boost Clock Selection Register */
-        #define CY_LIB_SC1_BST_REG             (* (reg8 *) CYREG_SC1_BST )
-        #define CY_LIB_SC1_BST_PTR             (  (reg8 *) CYREG_SC1_BST )
+    /* Switched Capacitor 0 Boost Clock Selection Register */
+    #define CY_LIB_SC0_BST_REG             (* (reg8 *) CYREG_SC0_BST )
+    #define CY_LIB_SC0_BST_PTR             (  (reg8 *) CYREG_SC0_BST )
 
-        /* Switched Capacitor 2 Boost Clock Selection Register */
-        #define CY_LIB_SC2_BST_REG             (* (reg8 *) CYREG_SC2_BST )
-        #define CY_LIB_SC2_BST_PTR             (  (reg8 *) CYREG_SC2_BST )
+    /* Switched Capacitor 1 Boost Clock Selection Register */
+    #define CY_LIB_SC1_BST_REG             (* (reg8 *) CYREG_SC1_BST )
+    #define CY_LIB_SC1_BST_PTR             (  (reg8 *) CYREG_SC1_BST )
 
-        /* Switched Capacitor 3 Boost Clock Selection Register */
-        #define CY_LIB_SC3_BST_REG             (* (reg8 *) CYREG_SC3_BST )
-        #define CY_LIB_SC3_BST_PTR             (  (reg8 *) CYREG_SC3_BST )
+    /* Switched Capacitor 2 Boost Clock Selection Register */
+    #define CY_LIB_SC2_BST_REG             (* (reg8 *) CYREG_SC2_BST )
+    #define CY_LIB_SC2_BST_PTR             (  (reg8 *) CYREG_SC2_BST )
 
-        /* Switched Cap Miscellaneous Control Register */
-        #define CY_LIB_SC_MISC_REG             (* (reg8 *) CYREG_SC_MISC )
-        #define CY_LIB_SC_MISC_PTR             (  (reg8 *) CYREG_SC_MISC )
+    /* Switched Capacitor 3 Boost Clock Selection Register */
+    #define CY_LIB_SC3_BST_REG             (* (reg8 *) CYREG_SC3_BST )
+    #define CY_LIB_SC3_BST_PTR             (  (reg8 *) CYREG_SC3_BST )
 
-    #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
+    /* Switched Cap Miscellaneous Control Register */
+    #define CY_LIB_SC_MISC_REG             (* (reg8 *) CYREG_SC_MISC )
+    #define CY_LIB_SC_MISC_PTR             (  (reg8 *) CYREG_SC_MISC )
 
-#endif /* (!CY_PSOC5A) */
+#endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
 /*******************************************************************************
@@ -596,71 +651,9 @@ uint8 CyVdRealTimeStatus(void) ;
 #define CY_LIB_CLKDIST_CR_REG           (*(reg8 *) CYREG_CLKDIST_CR)
 #define CY_LIB_CLKDIST_CR_PTR           ( (reg8 *) CYREG_CLKDIST_CR)
 
-
-#define SLOWCLK_ILO_CR0_PTR            ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
-#define SLOWCLK_ILO_CR0                (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
-#define CLKDIST_UCFG_PTR               ( (reg8 *) CYREG_CLKDIST_UCFG)
-#define CLKDIST_UCFG                   (*(reg8 *) CYREG_CLKDIST_UCFG)
-
-#define PM_TW_CFG0_PTR                 ( (reg8 *) CYREG_PM_TW_CFG0)
-#define PM_TW_CFG0                     (*(reg8 *) CYREG_PM_TW_CFG0)
-
-#define PM_TW_CFG2_PTR                 ( (reg8 *) CYREG_PM_TW_CFG2)
-#define PM_TW_CFG2                     (*(reg8 *) CYREG_PM_TW_CFG2)
-
-#define CLKDIST_MSTR1_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR1)
-#define CLKDIST_MSTR1                  (*(reg8 *) CYREG_CLKDIST_MSTR1)
-
-
-
-#define SFR_USER_CPUCLK_DIV_PTR        ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
-
-#define CLOCK_CONTROL                  ( (reg8 *) CYREG_CLKDIST_CR)
-#define IMO_TR1_PTR                    ( (reg8 *) CYREG_IMO_TR1)
-#define IMO_TR1                        (*(reg8 *) CYREG_IMO_TR1)
-#define CY_USB_CR1_PTR                 ( (reg8 *) CYREG_USB_CR1 )
-#define CY_USB_CR1                     (*(reg8 *) CYREG_USB_CR1 )
-
-#define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
-#define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
-#define PM_STBY_CFG0_PTR               ( (reg8 *) CYREG_PM_STBY_CFG0)
-#define PM_STBY_CFG0                   (*(reg8 *) CYREG_PM_STBY_CFG0)
-#define PM_AVAIL_CR2_PTR               ( (reg8 *) CYREG_PM_AVAIL_CR2)
-#define PM_AVAIL_CR2                   (*(reg8 *) CYREG_PM_AVAIL_CR2)
-
-
-/* Active Power Mode Configuration Register 5 */
-#define CY_PM_ACT_CFG5_REG             (* (reg8 *) CYREG_PM_ACT_CFG5 )
-#define CY_PM_ACT_CFG5_PTR             (  (reg8 *) CYREG_PM_ACT_CFG5 )
-
-/* Standby Power Mode Configuration Register 5 */
-#define CY_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
-#define CY_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
-
-
-#if(CY_PSOC3)
-    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
-    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
- #else
-    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
-    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
-    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
-    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
-    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
-    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
-    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
-    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
-#endif  /* (CY_PSOC3) */
-
-
-#define USB_CLKDIST_CONFIG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
-#define USB_CLKDIST_CONFIG             (*(reg8 *) CYREG_CLKDIST_UCFG)
+/* Internal Low-speed Oscillator Control Register 0 */
+#define CY_LIB_SLOWCLK_ILO_CR0_REG      (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define CY_LIB_SLOWCLK_ILO_CR0_PTR      ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
 
 
 /*******************************************************************************
@@ -709,33 +702,33 @@ uint8 CyVdRealTimeStatus(void) ;
     #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
     #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
 
-    #define CY_INT_SET_EN0_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
-    #define CY_INT_SET_EN0_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
+    #define CY_INT_SET_EN0_REG          (* (reg8 *) CYREG_INTC_SET_EN0)
+    #define CY_INT_SET_EN0_PTR          (  (reg8 *) CYREG_INTC_SET_EN0)
 
-    #define CY_INT_SET_EN1_REG           (* (reg8 *) CYREG_INTC_SET_EN1)
-    #define CY_INT_SET_EN1_PTR           (  (reg8 *) CYREG_INTC_SET_EN1)
+    #define CY_INT_SET_EN1_REG          (* (reg8 *) CYREG_INTC_SET_EN1)
+    #define CY_INT_SET_EN1_PTR          (  (reg8 *) CYREG_INTC_SET_EN1)
 
-    #define CY_INT_SET_EN2_REG           (* (reg8 *) CYREG_INTC_SET_EN2)
-    #define CY_INT_SET_EN2_PTR           (  (reg8 *) CYREG_INTC_SET_EN2)
+    #define CY_INT_SET_EN2_REG          (* (reg8 *) CYREG_INTC_SET_EN2)
+    #define CY_INT_SET_EN2_PTR          (  (reg8 *) CYREG_INTC_SET_EN2)
 
-    #define CY_INT_SET_EN3_REG           (* (reg8 *) CYREG_INTC_SET_EN3)
-    #define CY_INT_SET_EN3_PTR           (  (reg8 *) CYREG_INTC_SET_EN3)
+    #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
+    #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
 
     /* Interrrupt Controller Clear Enable Registers */
     #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
     #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
 
-    #define CY_INT_CLR_EN0_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
-    #define CY_INT_CLR_EN0_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
+    #define CY_INT_CLR_EN0_REG          (* (reg8 *) CYREG_INTC_CLR_EN0)
+    #define CY_INT_CLR_EN0_PTR          (  (reg8 *) CYREG_INTC_CLR_EN0)
 
-    #define CY_INT_CLR_EN1_REG            (* (reg8 *) CYREG_INTC_CLR_EN1)
-    #define CY_INT_CLR_EN1_PTR            (  (reg8 *) CYREG_INTC_CLR_EN1)
+    #define CY_INT_CLR_EN1_REG          (* (reg8 *) CYREG_INTC_CLR_EN1)
+    #define CY_INT_CLR_EN1_PTR          (  (reg8 *) CYREG_INTC_CLR_EN1)
 
-    #define CY_INT_CLR_EN2_REG            (* (reg8 *) CYREG_INTC_CLR_EN2)
-    #define CY_INT_CLR_EN2_PTR            (  (reg8 *) CYREG_INTC_CLR_EN2)
+    #define CY_INT_CLR_EN2_REG          (* (reg8 *) CYREG_INTC_CLR_EN2)
+    #define CY_INT_CLR_EN2_PTR          (  (reg8 *) CYREG_INTC_CLR_EN2)
 
-    #define CY_INT_CLR_EN3_REG            (* (reg8 *) CYREG_INTC_CLR_EN3)
-    #define CY_INT_CLR_EN3_PTR            (  (reg8 *) CYREG_INTC_CLR_EN3)
+    #define CY_INT_CLR_EN3_REG          (* (reg8 *) CYREG_INTC_CLR_EN3)
+    #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
 
 
     /* Interrrupt Controller Set Pend Registers */
@@ -810,7 +803,7 @@ uint8 CyVdRealTimeStatus(void) ;
 #if defined(__ARMCC_VERSION)
     #define CyGlobalIntEnable           {__enable_irq();}
     #define CyGlobalIntDisable          {__disable_irq();}
-#elif defined(__GNUC__)
+#elif defined(__GNUC__) || defined (__ICCARM__)
     #define CyGlobalIntEnable           {__asm("CPSIE   i");}
     #define CyGlobalIntDisable          {__asm("CPSID   i");}
 #elif defined(__C51__)
@@ -824,6 +817,10 @@ uint8 CyVdRealTimeStatus(void) ;
                                             CY_NOP; \
                                             EA = 0u;\
                                         }
+#else
+    #error No compiler toolchain defined
+    #define CyGlobalIntEnable
+    #define CyGlobalIntDisable
 #endif  /* (__ARMCC_VERSION) */
 
 
@@ -840,13 +837,12 @@ uint8 CyVdRealTimeStatus(void) ;
     #define CYDEV_CHIP_REV_ACTUAL       (CY_GET_REG8(CYREG_MLOGIC_REV_ID))
 #endif  /* (CYREG_MLOGIC_REV_ID_REV_ID) */
 
-#define RESET_CR2               ((reg8 *) CYREG_RESET_CR2)
-
 
 /*******************************************************************************
 * System API constants
 *******************************************************************************/
 #define CY_CACHE_CONTROL_FLUSH          (0x0004u)
+#define CY_LIB_RESET_CR2_RESET          (0x01u)
 
 
 /*******************************************************************************
@@ -1057,9 +1053,7 @@ uint8 CyVdRealTimeStatus(void) ;
 #define X32_CONTROL_LPM                 (CY_CLK_XTAL32_CR_LPM)
 #define X32_CONTROL_LPM_POSITION        (1u)
 #define X32_CONTROL_X32EN               (CY_CLK_XTAL32_CR_EN)
-#if(CY_PSOC3 || CY_PSOC5LP)
-    #define X32_CONTROL_PDBEN           (CY_CLK_XTAL32_CR_PDBEN)
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+#define X32_CONTROL_PDBEN           (CY_CLK_XTAL32_CR_PDBEN)
 #define X32_TR_DPMODE                   (CY_CLK_XTAL32_TR_STARTUP)
 #define X32_TR_CLEAR                    (CY_CLK_XTAL32_TR_POWERDOWN)
 #define X32_TR_HPMODE                   (CY_CLK_XTAL32_TR_HIGH_POWER)
@@ -1195,6 +1189,92 @@ uint8 CyVdRealTimeStatus(void) ;
 #define CLKDIST_CR_PTR                 ( (reg8 *) CYREG_CLKDIST_CR)
 #define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
 
+
+/*******************************************************************************
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
+*******************************************************************************/
+#define IMO_PM_ENABLE                   (0x10u)
+#define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
+#define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
+#define SLOWCLK_ILO_CR0_PTR            ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define SLOWCLK_ILO_CR0                (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
+#define ILO_CONTROL_PD_MODE             (0x10u)
+#define ILO_CONTROL_PD_POSITION         (4u)
+#define ILO_CONTROL_1KHZ_ON             (0x02u)
+#define ILO_CONTROL_100KHZ_ON           (0x04u)
+#define ILO_CONTROL_33KHZ_ON            (0x20u)
+#define PM_TW_CFG0_PTR                 ( (reg8 *) CYREG_PM_TW_CFG0)
+#define PM_TW_CFG0                     (*(reg8 *) CYREG_PM_TW_CFG0)
+#define PM_TW_CFG2_PTR                 ( (reg8 *) CYREG_PM_TW_CFG2)
+#define PM_TW_CFG2                     (*(reg8 *) CYREG_PM_TW_CFG2)
+#define RESET_CR2               ((reg8 *) CYREG_RESET_CR2)
+#define FASTCLK_IMO_USBCLK_ON_SET       (0x40u)
+#define CLOCK_IMO_3MHZ_VALUE            (0x03u)
+#define CLOCK_IMO_6MHZ_VALUE            (0x01u)
+#define CLOCK_IMO_12MHZ_VALUE           (0x00u)
+#define CLOCK_IMO_24MHZ_VALUE           (0x02u)
+#define CLOCK_IMO_48MHZ_VALUE           (0x04u)
+#define CLOCK_IMO_62MHZ_VALUE           (0x05u)
+#define CLOCK_IMO_74MHZ_VALUE           (0x06u)
+#define CLKDIST_DIV_POSITION            (4u)
+#define CLKDIST_MSTR1_DIV_CLEAR         (0x0Fu)
+#define SFR_USER_CPUCLK_DIV_MASK        (0x0Fu)
+#define CLOCK_USB_ENABLE                (0x02u)
+#define CLOCK_IMO_OUT_X2                (0x10u)
+#define CLOCK_IMO_OUT_X1                ((uint8)(~CLOCK_IMO_OUT_X2))
+#define CLOCK_IMO2X_ECO                 ((uint8)(~CLOCK_IMO2X_DSI))
+#define USB_CLKDIST_CONFIG_MASK         (0x03u)
+#define USB_CLK_IMO2X                   (0x00u)
+#define USB_CLK_IMO                     (0x01u)
+#define USB_CLK_PLL                     (0x02u)
+#define USB_CLK_DSI                     (0x03u)
+#define USB_CLK_DIV2_ON                 (0x04u)
+#define USB_CLK_STOP_FLAG               (0x00u)
+#define USB_CLK_START_FLAG              (0x01u)
+#define FTW_CLEAR_ALL_BITS              (0x00u)
+#define FTW_CLEAR_FTW_BITS              (0xFCu)
+#define FTW_ENABLE                      (0x01u)
+#define PM_STBY_CFG0_PTR               ( (reg8 *) CYREG_PM_STBY_CFG0)
+#define PM_STBY_CFG0                   (*(reg8 *) CYREG_PM_STBY_CFG0)
+#define PM_AVAIL_CR2_PTR               ( (reg8 *) CYREG_PM_AVAIL_CR2)
+#define PM_AVAIL_CR2                   (*(reg8 *) CYREG_PM_AVAIL_CR2)
+#define CLKDIST_UCFG_PTR               ( (reg8 *) CYREG_CLKDIST_UCFG)
+#define CLKDIST_UCFG                   (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CLKDIST_MSTR1_PTR              ( (reg8 *) CYREG_CLKDIST_MSTR1)
+#define CLKDIST_MSTR1                  (*(reg8 *) CYREG_CLKDIST_MSTR1)
+#define SFR_USER_CPUCLK_DIV_PTR        ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
+#define IMO_TR1_PTR                    ( (reg8 *) CYREG_IMO_TR1)
+#define IMO_TR1                        (*(reg8 *) CYREG_IMO_TR1)
+#define CLOCK_CONTROL                  ( (reg8 *) CYREG_CLKDIST_CR)
+#define CY_USB_CR1_PTR                 ( (reg8 *) CYREG_USB_CR1 )
+#define CY_USB_CR1                     (*(reg8 *) CYREG_USB_CR1 )
+#define USB_CLKDIST_CONFIG_PTR         ( (reg8 *) CYREG_CLKDIST_UCFG)
+#define USB_CLKDIST_CONFIG             (*(reg8 *) CYREG_CLKDIST_UCFG)
+#define CY_PM_ACT_CFG5_REG              (* (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_PM_ACT_CFG5_PTR              (  (reg8 *) CYREG_PM_ACT_CFG5 )
+#define CY_PM_STBY_CFG5_REG             (* (reg8 *) CYREG_PM_STBY_CFG5 )
+#define CY_PM_STBY_CFG5_PTR             (  (reg8 *) CYREG_PM_STBY_CFG5 )
+#if(CY_PSOC3)
+    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+ #else
+    #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
+    #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR         ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
+    #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
+    #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
+    #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
+    #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR        ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
+    #define FLSHID_CUST_TABLES_IMO_USB_PTR          ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
+    #define FLSHID_MFG_CFG_IMO_TR1_PTR              ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
+#endif  /* (CY_PSOC3) */
+
+
 #endif  /* (CY_BOOT_CYLIB_H) */
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Provides an API for the System Performance Component.
@@ -48,7 +48,7 @@
 uint8 SpcLockState = CY_SPC_UNLOCKED;
 
 
-#if(CY_PSOC5LP)
+#if(CY_PSOC5)
 
     /***************************************************************************
     * The wait-state pipeline must be enabled prior to accessing the SPC
@@ -57,9 +57,9 @@ uint8 SpcLockState = CY_SPC_UNLOCKED;
     * function, which must be called after SPC transaction, restores original
     * state.
     ***************************************************************************/
-    static uint8 spcWaitPipeBypass = 0u;
+    static uint32 spcWaitPipeBypass = 0u;
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 
 /*******************************************************************************
@@ -175,7 +175,8 @@ uint8 CySpcReadData(uint8 buffer[], uint8 size)
 *  CYRET_BAD_PARAM
 *
 *******************************************************************************/
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) 
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
+
 {
     cystatus status = CYRET_STARTED;
     uint8 i;
@@ -312,7 +313,8 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
 *  CYRET_LOCKED
 *
 *******************************************************************************/
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
+
 {
     cystatus status = CYRET_STARTED;
 
@@ -420,11 +422,7 @@ cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
 *  CYRET_LOCKED
 *
 *******************************************************************************/
-#if(CY_PSOC5A)
-cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect)
-#else
 cystatus CySpcGetTemp(uint8 numSamples)
-#endif  /* (CY_PSOC5A) */
 {
     cystatus status = CYRET_STARTED;
 
@@ -439,12 +437,6 @@ cystatus CySpcGetTemp(uint8 numSamples)
         if(CY_SPC_BUSY)
         {
             CY_SPC_CPU_DATA_REG = numSamples;
-
-            #if(CY_PSOC5A)
-                CY_SPC_CPU_DATA_REG = HI8(timerPeriod);
-                CY_SPC_CPU_DATA_REG = LO8(timerPeriod);
-                CY_SPC_CPU_DATA_REG = clkDivSelect;
-            #endif  /* (CY_PSOC5A) */
         }
         else
         {
@@ -488,7 +480,7 @@ cystatus CySpcLock(void)
         SpcLockState = CY_SPC_LOCKED;
         status = CYRET_SUCCESS;
 
-        #if(CY_PSOC5LP)
+        #if(CY_PSOC5)
 
             if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
             {
@@ -503,7 +495,7 @@ cystatus CySpcLock(void)
                 spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
             }
 
-        #endif  /* (CY_PSOC5LP) */
+        #endif  /* (CY_PSOC5) */
     }
 
     /* Exit critical section */
@@ -537,7 +529,7 @@ void CySpcUnlock(void)
     /* Release the SPC object */
     SpcLockState = CY_SPC_UNLOCKED;
 
-    #if(CY_PSOC5LP)
+    #if(CY_PSOC5)
 
         if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
         {
@@ -552,7 +544,7 @@ void CySpcUnlock(void)
             spcWaitPipeBypass = 0u;
         }
 
-    #endif  /* (CY_PSOC5LP) */
+    #endif  /* (CY_PSOC5) */
 
     /* Exit critical section */
     CyExitCriticalSection(interruptState);

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 3.40
+* Version 4.0
 *
 * Description:
 *  Provides definitions for the System Performance Component API.
@@ -34,18 +34,13 @@ extern uint8 SpcLockState;
 void     CySpcStart(void);
 void     CySpcStop(void);
 uint8    CySpcReadData(uint8 buffer[], uint8 size);
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
+;
 cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
+;
 cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
-
-#if(CY_PSOC5A)
-    cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);
-#else
-    cystatus CySpcGetTemp(uint8 numSamples);
-#endif  /* (CY_PSOC5A) */
-
-
+cystatus CySpcGetTemp(uint8 numSamples);
 cystatus CySpcLock(void);
 void     CySpcUnlock(void);
 
@@ -91,12 +86,12 @@ void     CySpcUnlock(void);
 #define CY_SPC_STATUS_TADC_INPUT            (0x0Du)   /* Invalid input value for Get Temp & Get ADC commands */
 #define CY_SPC_STATUS_BUSY                  (0xFFu)   /* SPC is busy */
 
-#if(CY_PSOC5LP)
+#if(CY_PSOC5)
 
     /* Wait-state pipeline */
     #define CY_SPC_CPU_WAITPIPE_BYPASS      ((uint32)0x01u)
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 
 /***************************************
@@ -119,13 +114,13 @@ void     CySpcUnlock(void);
 #define CY_SPC_PM_STBY_REG          (* (reg8 *) CYREG_PM_STBY_CFG0 )
 #define CY_SPC_PM_STBY_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0 )
 
-#if(CY_PSOC5LP)
+#if(CY_PSOC5)
 
     /* Wait State Pipeline */
     #define CY_SPC_CPU_WAITPIPE_REG     (* (reg32 *) CYREG_PANTHER_WAITPIPE )
     #define CY_SPC_CPU_WAITPIPE_PTR     (  (reg32 *) CYREG_PANTHER_WAITPIPE )
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 
 /***************************************

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c

@@ -0,0 +1,137 @@
+/*******************************************************************************
+* File Name: SCSI_ATN.c  
+* Version 1.90
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SCSI_ATN.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SCSI_ATN_Write(uint8 value) 
+{
+    uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK));
+    SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to this drive mode.
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SCSI_ATN_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SCSI_ATN_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SCSI_ATN_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SCSI_ATN_Read(void) 
+{
+    return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SCSI_ATN_ReadDataReg(void) 
+{
+    return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SCSI_ATN_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SCSI_ATN_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SCSI_ATN_ClearInterrupt(void) 
+    {
+        return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h

@@ -0,0 +1,130 @@
+/*******************************************************************************
+* File Name: SCSI_ATN.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */
+#define CY_PINS_SCSI_ATN_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SCSI_ATN_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SCSI_ATN_Write(uint8 value) ;
+void    SCSI_ATN_SetDriveMode(uint8 mode) ;
+uint8   SCSI_ATN_ReadDataReg(void) ;
+uint8   SCSI_ATN_Read(void) ;
+uint8   SCSI_ATN_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SCSI_ATN_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SCSI_ATN_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SCSI_ATN_DM_RES_UP          PIN_DM_RES_UP
+#define SCSI_ATN_DM_RES_DWN         PIN_DM_RES_DWN
+#define SCSI_ATN_DM_OD_LO           PIN_DM_OD_LO
+#define SCSI_ATN_DM_OD_HI           PIN_DM_OD_HI
+#define SCSI_ATN_DM_STRONG          PIN_DM_STRONG
+#define SCSI_ATN_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SCSI_ATN_MASK               SCSI_ATN__MASK
+#define SCSI_ATN_SHIFT              SCSI_ATN__SHIFT
+#define SCSI_ATN_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SCSI_ATN_PS                     (* (reg8 *) SCSI_ATN__PS)
+/* Data Register */
+#define SCSI_ATN_DR                     (* (reg8 *) SCSI_ATN__DR)
+/* Port Number */
+#define SCSI_ATN_PRT_NUM                (* (reg8 *) SCSI_ATN__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SCSI_ATN_AG                     (* (reg8 *) SCSI_ATN__AG)                       
+/* Analog MUX bux enable */
+#define SCSI_ATN_AMUX                   (* (reg8 *) SCSI_ATN__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SCSI_ATN_BIE                    (* (reg8 *) SCSI_ATN__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SCSI_ATN_BIT_MASK               (* (reg8 *) SCSI_ATN__BIT_MASK)
+/* Bypass Enable */
+#define SCSI_ATN_BYP                    (* (reg8 *) SCSI_ATN__BYP)
+/* Port wide control signals */                                                   
+#define SCSI_ATN_CTL                    (* (reg8 *) SCSI_ATN__CTL)
+/* Drive Modes */
+#define SCSI_ATN_DM0                    (* (reg8 *) SCSI_ATN__DM0) 
+#define SCSI_ATN_DM1                    (* (reg8 *) SCSI_ATN__DM1)
+#define SCSI_ATN_DM2                    (* (reg8 *) SCSI_ATN__DM2) 
+/* Input Buffer Disable Override */
+#define SCSI_ATN_INP_DIS                (* (reg8 *) SCSI_ATN__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SCSI_ATN_LCD_COM_SEG            (* (reg8 *) SCSI_ATN__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SCSI_ATN_LCD_EN                 (* (reg8 *) SCSI_ATN__LCD_EN)
+/* Slew Rate Control */
+#define SCSI_ATN_SLW                    (* (reg8 *) SCSI_ATN__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SCSI_ATN_PRTDSI__CAPS_SEL       (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SCSI_ATN_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SCSI_ATN_PRTDSI__OE_SEL0        (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0) 
+#define SCSI_ATN_PRTDSI__OE_SEL1        (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SCSI_ATN_PRTDSI__OUT_SEL0       (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0) 
+#define SCSI_ATN_PRTDSI__OUT_SEL1       (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SCSI_ATN_PRTDSI__SYNC_OUT       (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SCSI_ATN__INTSTAT)  /* Interrupt Registers */
+
+    #define SCSI_ATN_INTSTAT                (* (reg8 *) SCSI_ATN__INTSTAT)
+    #define SCSI_ATN_SNAP                   (* (reg8 *) SCSI_ATN__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SCSI_ATN_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_ISR.c

@@ -0,0 +1,356 @@
+/*******************************************************************************
+* File Name: SCSI_ATN_ISR.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_ATN_ISR.h>
+
+#if !defined(SCSI_ATN_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_ATN_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_ATN_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */
+    SCSI_ATN_ISR_SetVector(&SCSI_ATN_ISR_Interrupt);
+
+    /* Set the priority. */
+    SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_ATN_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_ATN_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */
+    SCSI_ATN_ISR_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_ATN_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_ATN_ISR_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_ATN_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_ATN_ISR.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_ATN_ISR_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_ATN_ISR_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_ATN_ISR_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_ATN_ISR_StartEx instead.
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_ATN_ISR_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. Note calling SCSI_ATN_ISR_Start
+*   or SCSI_ATN_ISR_StartEx will override any effect this method 
+*   would have had. This method should only be called after 
+*   SCSI_ATN_ISR_Start or SCSI_ATN_ISR_StartEx has been called. To set 
+*   the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_SetPriority(uint8 priority)
+{
+    *SCSI_ATN_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_ATN_ISR_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_ATN_ISR_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_ATN_ISR_INTC_SET_EN = SCSI_ATN_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_ATN_ISR_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_ATN_ISR_INTC_SET_EN & (uint32)SCSI_ATN_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_ATN_ISR_INTC_CLR_EN = SCSI_ATN_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_SetPending(void)
+{
+    *SCSI_ATN_ISR_INTC_SET_PD = SCSI_ATN_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_ATN_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_ATN_ISR_ClearPending(void)
+{
+    *SCSI_ATN_ISR_INTC_CLR_PD = SCSI_ATN_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_ISR.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+* File Name: SCSI_ATN_ISR.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_ATN_ISR_H)
+#define CY_ISR_SCSI_ATN_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_ATN_ISR_Start(void);
+void SCSI_ATN_ISR_StartEx(cyisraddress address);
+void SCSI_ATN_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_ATN_ISR_Interrupt);
+
+void SCSI_ATN_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_ATN_ISR_GetVector(void);
+
+void SCSI_ATN_ISR_SetPriority(uint8 priority);
+uint8 SCSI_ATN_ISR_GetPriority(void);
+
+void SCSI_ATN_ISR_Enable(void);
+uint8 SCSI_ATN_ISR_GetState(void);
+void SCSI_ATN_ISR_Disable(void);
+
+void SCSI_ATN_ISR_SetPending(void);
+void SCSI_ATN_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_ATN_ISR ISR. */
+#define SCSI_ATN_ISR_INTC_VECTOR            ((reg32 *) SCSI_ATN_ISR__INTC_VECT)
+
+/* Address of the SCSI_ATN_ISR ISR priority. */
+#define SCSI_ATN_ISR_INTC_PRIOR             ((reg8 *) SCSI_ATN_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_ATN_ISR interrupt. */
+#define SCSI_ATN_ISR_INTC_PRIOR_NUMBER      SCSI_ATN_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_ATN_ISR interrupt. */
+#define SCSI_ATN_ISR_INTC_SET_EN            ((reg32 *) SCSI_ATN_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_ATN_ISR interrupt. */
+#define SCSI_ATN_ISR_INTC_CLR_EN            ((reg32 *) SCSI_ATN_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_ATN_ISR interrupt state to pending. */
+#define SCSI_ATN_ISR_INTC_SET_PD            ((reg32 *) SCSI_ATN_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_ATN_ISR interrupt. */
+#define SCSI_ATN_ISR_INTC_CLR_PD            ((reg32 *) SCSI_ATN_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_ATN_ISR_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h

@@ -0,0 +1,34 @@
+/*******************************************************************************
+* File Name: SCSI_ATN.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */
+#define CY_PINS_SCSI_ATN_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_ATN_0		SCSI_ATN__0__PC
+
+#define SCSI_ATN_INT		SCSI_ATN__INT__PC
+
+#endif /* End Pins SCSI_ATN_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h

@@ -34,14 +34,14 @@
 #define SCSI_In_DBx_6		SCSI_In_DBx__6__PC
 #define SCSI_In_DBx_7		SCSI_In_DBx__7__PC
 
-#define SCSI_In_DBx_SCSI_Out_DB0		SCSI_In_DBx__SCSI_Out_DB0__PC
-#define SCSI_In_DBx_SCSI_Out_DB1		SCSI_In_DBx__SCSI_Out_DB1__PC
-#define SCSI_In_DBx_SCSI_Out_DB2		SCSI_In_DBx__SCSI_Out_DB2__PC
-#define SCSI_In_DBx_SCSI_Out_DB3		SCSI_In_DBx__SCSI_Out_DB3__PC
-#define SCSI_In_DBx_SCSI_Out_DB4		SCSI_In_DBx__SCSI_Out_DB4__PC
-#define SCSI_In_DBx_SCSI_Out_DB5		SCSI_In_DBx__SCSI_Out_DB5__PC
-#define SCSI_In_DBx_SCSI_Out_DB6		SCSI_In_DBx__SCSI_Out_DB6__PC
-#define SCSI_In_DBx_SCSI_Out_DB7		SCSI_In_DBx__SCSI_Out_DB7__PC
+#define SCSI_In_DBx_DB0		SCSI_In_DBx__DB0__PC
+#define SCSI_In_DBx_DB1		SCSI_In_DBx__DB1__PC
+#define SCSI_In_DBx_DB2		SCSI_In_DBx__DB2__PC
+#define SCSI_In_DBx_DB3		SCSI_In_DBx__DB3__PC
+#define SCSI_In_DBx_DB4		SCSI_In_DBx__DB4__PC
+#define SCSI_In_DBx_DB5		SCSI_In_DBx__DB5__PC
+#define SCSI_In_DBx_DB6		SCSI_In_DBx__DB6__PC
+#define SCSI_In_DBx_DB7		SCSI_In_DBx__DB7__PC
 
 #endif /* End Pins SCSI_In_DBx_ALIASES_H */
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h

@@ -33,14 +33,10 @@
 #define SCSI_In_5		SCSI_In__5__PC
 #define SCSI_In_6		SCSI_In__6__PC
 #define SCSI_In_7		SCSI_In__7__PC
-#define SCSI_In_8		SCSI_In__8__PC
-#define SCSI_In_9		SCSI_In__9__PC
 
 #define SCSI_In_DBP		SCSI_In__DBP__PC
-#define SCSI_In_ATN		SCSI_In__ATN__PC
 #define SCSI_In_BSY		SCSI_In__BSY__PC
 #define SCSI_In_ACK		SCSI_In__ACK__PC
-#define SCSI_In_RST		SCSI_In__RST__PC
 #define SCSI_In_MSG		SCSI_In__MSG__PC
 #define SCSI_In_SEL		SCSI_In__SEL__PC
 #define SCSI_In_CD		SCSI_In__CD__PC

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h

@@ -34,14 +34,14 @@
 #define SCSI_Out_DBx_6		SCSI_Out_DBx__6__PC
 #define SCSI_Out_DBx_7		SCSI_Out_DBx__7__PC
 
-#define SCSI_Out_DBx_SCSI_Out_DB0		SCSI_Out_DBx__SCSI_Out_DB0__PC
-#define SCSI_Out_DBx_SCSI_Out_DB1		SCSI_Out_DBx__SCSI_Out_DB1__PC
-#define SCSI_Out_DBx_SCSI_Out_DB2		SCSI_Out_DBx__SCSI_Out_DB2__PC
-#define SCSI_Out_DBx_SCSI_Out_DB3		SCSI_Out_DBx__SCSI_Out_DB3__PC
-#define SCSI_Out_DBx_SCSI_Out_DB4		SCSI_Out_DBx__SCSI_Out_DB4__PC
-#define SCSI_Out_DBx_SCSI_Out_DB5		SCSI_Out_DBx__SCSI_Out_DB5__PC
-#define SCSI_Out_DBx_SCSI_Out_DB6		SCSI_Out_DBx__SCSI_Out_DB6__PC
-#define SCSI_Out_DBx_SCSI_Out_DB7		SCSI_Out_DBx__SCSI_Out_DB7__PC
+#define SCSI_Out_DBx_DB0		SCSI_Out_DBx__DB0__PC
+#define SCSI_Out_DBx_DB1		SCSI_Out_DBx__DB1__PC
+#define SCSI_Out_DBx_DB2		SCSI_Out_DBx__DB2__PC
+#define SCSI_Out_DBx_DB3		SCSI_Out_DBx__DB3__PC
+#define SCSI_Out_DBx_DB4		SCSI_Out_DBx__DB4__PC
+#define SCSI_Out_DBx_DB5		SCSI_Out_DBx__DB5__PC
+#define SCSI_Out_DBx_DB6		SCSI_Out_DBx__DB6__PC
+#define SCSI_Out_DBx_DB7		SCSI_Out_DBx__DB7__PC
 
 #endif /* End Pins SCSI_Out_DBx_ALIASES_H */
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c

@@ -0,0 +1,137 @@
+/*******************************************************************************
+* File Name: SCSI_RST.c  
+* Version 1.90
+*
+* Description:
+*  This file contains API to enable firmware control of a Pins component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "cytypes.h"
+#include "SCSI_RST.h"
+
+/* APIs are not generated for P15[7:6] on PSoC 5 */
+#if !(CY_PSOC5A &&\
+	 SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_Write
+********************************************************************************
+*
+* Summary:
+*  Assign a new value to the digital port's data output register.  
+*
+* Parameters:  
+*  prtValue:  The value to be assigned to the Digital Port. 
+*
+* Return: 
+*  None
+*  
+*******************************************************************************/
+void SCSI_RST_Write(uint8 value) 
+{
+    uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK));
+    SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_SetDriveMode
+********************************************************************************
+*
+* Summary:
+*  Change the drive mode on the pins of the port.
+* 
+* Parameters:  
+*  mode:  Change the pins to this drive mode.
+*
+* Return: 
+*  None
+*
+*******************************************************************************/
+void SCSI_RST_SetDriveMode(uint8 mode) 
+{
+	CyPins_SetPinDriveMode(SCSI_RST_0, mode);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_Read
+********************************************************************************
+*
+* Summary:
+*  Read the current value on the pins of the Digital Port in right justified 
+*  form.
+*
+* Parameters:  
+*  None
+*
+* Return: 
+*  Returns the current value of the Digital Port as a right justified number
+*  
+* Note:
+*  Macro SCSI_RST_ReadPS calls this function. 
+*  
+*******************************************************************************/
+uint8 SCSI_RST_Read(void) 
+{
+    return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ReadDataReg
+********************************************************************************
+*
+* Summary:
+*  Read the current value assigned to a Digital Port's data output register
+*
+* Parameters:  
+*  None 
+*
+* Return: 
+*  Returns the current value assigned to the Digital Port's data output register
+*  
+*******************************************************************************/
+uint8 SCSI_RST_ReadDataReg(void) 
+{
+    return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
+}
+
+
+/* If Interrupts Are Enabled for this Pins component */ 
+#if defined(SCSI_RST_INTSTAT) 
+
+    /*******************************************************************************
+    * Function Name: SCSI_RST_ClearInterrupt
+    ********************************************************************************
+    * Summary:
+    *  Clears any active interrupts attached to port and returns the value of the 
+    *  interrupt status register.
+    *
+    * Parameters:  
+    *  None 
+    *
+    * Return: 
+    *  Returns the value of the interrupt status register
+    *  
+    *******************************************************************************/
+    uint8 SCSI_RST_ClearInterrupt(void) 
+    {
+        return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
+    }
+
+#endif /* If Interrupts Are Enabled for this Pins component */ 
+
+#endif /* CY_PSOC5A... */
+
+    
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h

@@ -0,0 +1,130 @@
+/*******************************************************************************
+* File Name: SCSI_RST.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */
+#define CY_PINS_SCSI_RST_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "cypins.h"
+#include "SCSI_RST_aliases.h"
+
+/* Check to see if required defines such as CY_PSOC5A are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5A)
+    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5A) */
+
+/* APIs are not generated for P15[7:6] */
+#if !(CY_PSOC5A &&\
+	 SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
+
+
+/***************************************
+*        Function Prototypes             
+***************************************/    
+
+void    SCSI_RST_Write(uint8 value) ;
+void    SCSI_RST_SetDriveMode(uint8 mode) ;
+uint8   SCSI_RST_ReadDataReg(void) ;
+uint8   SCSI_RST_Read(void) ;
+uint8   SCSI_RST_ClearInterrupt(void) ;
+
+
+/***************************************
+*           API Constants        
+***************************************/
+
+/* Drive Modes */
+#define SCSI_RST_DM_ALG_HIZ         PIN_DM_ALG_HIZ
+#define SCSI_RST_DM_DIG_HIZ         PIN_DM_DIG_HIZ
+#define SCSI_RST_DM_RES_UP          PIN_DM_RES_UP
+#define SCSI_RST_DM_RES_DWN         PIN_DM_RES_DWN
+#define SCSI_RST_DM_OD_LO           PIN_DM_OD_LO
+#define SCSI_RST_DM_OD_HI           PIN_DM_OD_HI
+#define SCSI_RST_DM_STRONG          PIN_DM_STRONG
+#define SCSI_RST_DM_RES_UPDWN       PIN_DM_RES_UPDWN
+
+/* Digital Port Constants */
+#define SCSI_RST_MASK               SCSI_RST__MASK
+#define SCSI_RST_SHIFT              SCSI_RST__SHIFT
+#define SCSI_RST_WIDTH              1u
+
+
+/***************************************
+*             Registers        
+***************************************/
+
+/* Main Port Registers */
+/* Pin State */
+#define SCSI_RST_PS                     (* (reg8 *) SCSI_RST__PS)
+/* Data Register */
+#define SCSI_RST_DR                     (* (reg8 *) SCSI_RST__DR)
+/* Port Number */
+#define SCSI_RST_PRT_NUM                (* (reg8 *) SCSI_RST__PRT) 
+/* Connect to Analog Globals */                                                  
+#define SCSI_RST_AG                     (* (reg8 *) SCSI_RST__AG)                       
+/* Analog MUX bux enable */
+#define SCSI_RST_AMUX                   (* (reg8 *) SCSI_RST__AMUX) 
+/* Bidirectional Enable */                                                        
+#define SCSI_RST_BIE                    (* (reg8 *) SCSI_RST__BIE)
+/* Bit-mask for Aliased Register Access */
+#define SCSI_RST_BIT_MASK               (* (reg8 *) SCSI_RST__BIT_MASK)
+/* Bypass Enable */
+#define SCSI_RST_BYP                    (* (reg8 *) SCSI_RST__BYP)
+/* Port wide control signals */                                                   
+#define SCSI_RST_CTL                    (* (reg8 *) SCSI_RST__CTL)
+/* Drive Modes */
+#define SCSI_RST_DM0                    (* (reg8 *) SCSI_RST__DM0) 
+#define SCSI_RST_DM1                    (* (reg8 *) SCSI_RST__DM1)
+#define SCSI_RST_DM2                    (* (reg8 *) SCSI_RST__DM2) 
+/* Input Buffer Disable Override */
+#define SCSI_RST_INP_DIS                (* (reg8 *) SCSI_RST__INP_DIS)
+/* LCD Common or Segment Drive */
+#define SCSI_RST_LCD_COM_SEG            (* (reg8 *) SCSI_RST__LCD_COM_SEG)
+/* Enable Segment LCD */
+#define SCSI_RST_LCD_EN                 (* (reg8 *) SCSI_RST__LCD_EN)
+/* Slew Rate Control */
+#define SCSI_RST_SLW                    (* (reg8 *) SCSI_RST__SLW)
+
+/* DSI Port Registers */
+/* Global DSI Select Register */
+#define SCSI_RST_PRTDSI__CAPS_SEL       (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL) 
+/* Double Sync Enable */
+#define SCSI_RST_PRTDSI__DBL_SYNC_IN    (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN) 
+/* Output Enable Select Drive Strength */
+#define SCSI_RST_PRTDSI__OE_SEL0        (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0) 
+#define SCSI_RST_PRTDSI__OE_SEL1        (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1) 
+/* Port Pin Output Select Registers */
+#define SCSI_RST_PRTDSI__OUT_SEL0       (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0) 
+#define SCSI_RST_PRTDSI__OUT_SEL1       (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1) 
+/* Sync Output Enable Registers */
+#define SCSI_RST_PRTDSI__SYNC_OUT       (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT) 
+
+
+#if defined(SCSI_RST__INTSTAT)  /* Interrupt Registers */
+
+    #define SCSI_RST_INTSTAT                (* (reg8 *) SCSI_RST__INTSTAT)
+    #define SCSI_RST_SNAP                   (* (reg8 *) SCSI_RST__SNAP)
+
+#endif /* Interrupt Registers */
+
+#endif /* CY_PSOC5A... */
+
+#endif /*  CY_PINS_SCSI_RST_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c

@@ -0,0 +1,356 @@
+/*******************************************************************************
+* File Name: SCSI_RST_ISR.c  
+* Version 1.70
+*
+*  Description:
+*   API for controlling the state of an interrupt.
+*
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_RST_ISR.h>
+
+#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+*  Place your includes, defines and code here 
+********************************************************************************/
+/* `#START SCSI_RST_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE      16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE    ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Start
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Start(void)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
+    SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);
+
+    /* Set the priority. */
+    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RST_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+*  Set up the interrupt and enable it.
+*
+* Parameters:  
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_StartEx(cyisraddress address)
+{
+    /* For all we know the interrupt is active. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
+    SCSI_RST_ISR_SetVector(address);
+
+    /* Set the priority. */
+    SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
+
+    /* Enable it. */
+    SCSI_RST_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Stop
+********************************************************************************
+*
+* Summary:
+*   Disables and removes the interrupt.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Stop(void)
+{
+    /* Disable this interrupt. */
+    SCSI_RST_ISR_Disable();
+
+    /* Set the ISR to point to the passive one. */
+    SCSI_RST_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+*   The default Interrupt Service Routine for SCSI_RST_ISR.
+*
+*   Add custom code between the coments to keep the next version of this file
+*   from over writting your code.
+*
+* Parameters:  
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+CY_ISR(SCSI_RST_ISR_Interrupt)
+{
+    /*  Place your Interrupt code here. */
+    /* `#START SCSI_RST_ISR_Interrupt` */
+
+    /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+*   Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
+*   will override any effect this method would have had. To set the vector 
+*   before the component has been started use SCSI_RST_ISR_StartEx instead.
+*
+* Parameters:
+*   address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetVector(cyisraddress address)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+*   Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_RST_ISR_GetVector(void)
+{
+    cyisraddress * ramVectorTable;
+
+    ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+    return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+*   Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start
+*   or SCSI_RST_ISR_StartEx will override any effect this method 
+*   would have had. This method should only be called after 
+*   SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set 
+*   the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+*   priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetPriority(uint8 priority)
+{
+    *SCSI_RST_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+*   Gets the Priority of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_RST_ISR_GetPriority(void)
+{
+    uint8 priority;
+
+
+    priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;
+
+    return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Enable
+********************************************************************************
+*
+* Summary:
+*   Enables the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Enable(void)
+{
+    /* Enable the general interrupt. */
+    *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_GetState
+********************************************************************************
+*
+* Summary:
+*   Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_RST_ISR_GetState(void)
+{
+    /* Get the state of the general interrupt. */
+    return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_Disable
+********************************************************************************
+*
+* Summary:
+*   Disables the Interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_Disable(void)
+{
+    /* Disable the general interrupt. */
+    *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+*   Causes the Interrupt to enter the pending state, a software method of
+*   generating the interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_SetPending(void)
+{
+    *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RST_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+*   Clears a pending interrupt.
+*
+* Parameters:
+*   None
+*
+* Return:
+*   None
+*
+*******************************************************************************/
+void SCSI_RST_ISR_ClearPending(void)
+{
+    *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+* File Name: SCSI_RST_ISR.h
+* Version 1.70
+*
+*  Description:
+*   Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_RST_ISR_H)
+#define CY_ISR_SCSI_RST_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_RST_ISR_Start(void);
+void SCSI_RST_ISR_StartEx(cyisraddress address);
+void SCSI_RST_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_RST_ISR_Interrupt);
+
+void SCSI_RST_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_RST_ISR_GetVector(void);
+
+void SCSI_RST_ISR_SetPriority(uint8 priority);
+uint8 SCSI_RST_ISR_GetPriority(void);
+
+void SCSI_RST_ISR_Enable(void);
+uint8 SCSI_RST_ISR_GetState(void);
+void SCSI_RST_ISR_Disable(void);
+
+void SCSI_RST_ISR_SetPending(void);
+void SCSI_RST_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */
+#define SCSI_RST_ISR_INTC_VECTOR            ((reg32 *) SCSI_RST_ISR__INTC_VECT)
+
+/* Address of the SCSI_RST_ISR ISR priority. */
+#define SCSI_RST_ISR_INTC_PRIOR             ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_PRIOR_NUMBER      SCSI_RST_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_SET_EN            ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_CLR_EN            ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */
+#define SCSI_RST_ISR_INTC_SET_PD            ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */
+#define SCSI_RST_ISR_INTC_CLR_PD            ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_RST_ISR_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h

@@ -0,0 +1,34 @@
+/*******************************************************************************
+* File Name: SCSI_RST.h  
+* Version 1.90
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_RST_ALIASES_H) /* Pins SCSI_RST_ALIASES_H */
+#define CY_PINS_SCSI_RST_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+*              Constants        
+***************************************/
+#define SCSI_RST_0		SCSI_RST__0__PC
+
+#define SCSI_RST_INT		SCSI_RST__INT__PC
+
+#endif /* End Pins SCSI_RST_ALIASES_H */
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h

@@ -48,8 +48,8 @@
 /* Internal interrupt handling */
 #define SDCard_TX_BUFFER_SIZE             (4u)
 #define SDCard_RX_BUFFER_SIZE             (4u)
-#define SDCard_INTERNAL_TX_INT_ENABLED    (1u)
-#define SDCard_INTERNAL_RX_INT_ENABLED    (1u)
+#define SDCard_INTERNAL_TX_INT_ENABLED    (0u)
+#define SDCard_INTERNAL_RX_INT_ENABLED    (0u)
 
 #define SDCard_SINGLE_REG_SIZE            (8u)
 #define SDCard_USE_SECOND_DATAPATH        (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.c
-* Version 2.0
+* Version 2.10
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.h
-* Version 2.0
+* Version 2.10
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_0 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -59,13 +59,13 @@ uint8 SD_Data_Clk_GetPhaseRegister(void) ;
 
 #define SD_Data_Clk_Enable()                       SD_Data_Clk_Start()
 #define SD_Data_Clk_Disable()                      SD_Data_Clk_Stop()
-#define SD_Data_Clk_SetDivider(clkDivider)         SD_Data_Clk_SetDividerRegister(clkDivider, 1)
-#define SD_Data_Clk_SetDividerValue(clkDivider)    SD_Data_Clk_SetDividerRegister((clkDivider) - 1, 1)
+#define SD_Data_Clk_SetDivider(clkDivider)         SD_Data_Clk_SetDividerRegister(clkDivider, 1u)
+#define SD_Data_Clk_SetDividerValue(clkDivider)    SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
 #define SD_Data_Clk_SetMode(clkMode)               SD_Data_Clk_SetModeRegister(clkMode)
 #define SD_Data_Clk_SetSource(clkSource)           SD_Data_Clk_SetSourceRegister(clkSource)
 #if defined(SD_Data_Clk__CFG3)
 #define SD_Data_Clk_SetPhase(clkPhase)             SD_Data_Clk_SetPhaseRegister(clkPhase)
-#define SD_Data_Clk_SetPhaseValue(clkPhase)        SD_Data_Clk_SetPhaseRegister((clkPhase) + 1)
+#define SD_Data_Clk_SetPhaseValue(clkPhase)        SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)
 #endif /* defined(SD_Data_Clk__CFG3) */
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Init_Clk.c
-* Version 2.0
+* Version 2.10
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Init_Clk.h
-* Version 2.0
+* Version 2.10
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_0 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -59,13 +59,13 @@ uint8 SD_Init_Clk_GetPhaseRegister(void) ;
 
 #define SD_Init_Clk_Enable()                       SD_Init_Clk_Start()
 #define SD_Init_Clk_Disable()                      SD_Init_Clk_Stop()
-#define SD_Init_Clk_SetDivider(clkDivider)         SD_Init_Clk_SetDividerRegister(clkDivider, 1)
-#define SD_Init_Clk_SetDividerValue(clkDivider)    SD_Init_Clk_SetDividerRegister((clkDivider) - 1, 1)
+#define SD_Init_Clk_SetDivider(clkDivider)         SD_Init_Clk_SetDividerRegister(clkDivider, 1u)
+#define SD_Init_Clk_SetDividerValue(clkDivider)    SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
 #define SD_Init_Clk_SetMode(clkMode)               SD_Init_Clk_SetModeRegister(clkMode)
 #define SD_Init_Clk_SetSource(clkSource)           SD_Init_Clk_SetSourceRegister(clkSource)
 #if defined(SD_Init_Clk__CFG3)
 #define SD_Init_Clk_SetPhase(clkPhase)             SD_Init_Clk_SetPhaseRegister(clkPhase)
-#define SD_Init_Clk_SetPhaseValue(clkPhase)        SD_Init_Clk_SetPhaseRegister((clkPhase) + 1)
+#define SD_Init_Clk_SetPhaseValue(clkPhase)        SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u)
 #endif /* defined(SD_Init_Clk__CFG3) */
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld

@@ -16,55 +16,84 @@
  * they apply.
  */
 OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-ENTRY(__cs3_reset)
+ENTRY(__cy_reset)
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+GROUP(-lgcc -lc -lnosys)
+
 
 MEMORY
 {
-  rom (rx) : ORIGIN = 0, LENGTH = (262144 - 0)
-  ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = (65536 - 0x4000 - 0x1000)
+  rom (rx) : ORIGIN = 0x0, LENGTH = 262144
+  ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = 65536
 }
 
+
+CY_APPL_ORIGIN      = 0; 
+CY_FLASH_ROW_SIZE   = 256;
+CY_ECC_ROW_SIZE     = 32;
+CY_EE_IN_BTLDR      = 0x0;
+CY_APPL_LOADABLE    = 0;
+CY_EE_SIZE          = 2048;
+CY_APPL_NUM         = 1;
+CY_APPL_MAX         = 1;
+CY_METADATA_SIZE    = 64;
+
+
 /* These force the linker to search for particular symbols from
  * the start of the link process and thus ensure the user's
  * overrides are picked up
  */
-EXTERN(__cs3_reset Reset)
-EXTERN(__cs3_start_asm __cs3_start_asm_generic_m)
+EXTERN(Reset)
+
 /* Bring in the interrupt routines & vector */
-INCLUDE micro-names.inc
-EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(main)
+
+/* Bring in the meta data */
+EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
+EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 
 /* Provide fall-back values */
-PROVIDE(__cs3_heap_start = _end);
-PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
-PROVIDE(__cs3_stack = 0x20000000 + (65536 / 2));
-PROVIDE(__cs3_heap_end = __cs3_stack - 0x4000);
+PROVIDE(__cy_heap_start = _end);
+PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
+PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
+PROVIDE(__cy_heap_end = __cy_stack - 0x4000);
 
 
 SECTIONS
 {
+  /* The bootloader location */
+  .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom
 
-  .text :
+  /* Calculate where the loadables should start */
+  appl1_start   = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);
+  appl2_start   = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);
+  appl_start    = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;
+  ecc_offset    = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
+  ee_offset     = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
+  ee_size       = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
+  PROVIDE(CY_ECC_OFFSET = ecc_offset);
+  
+  .text appl_start :
   {
     CREATE_OBJECT_SYMBOLS
-    PROVIDE(__cs3_interrupt_vector = RomVectors);
+    PROVIDE(__cy_interrupt_vector = RomVectors);
+
     *(.romvectors)
-    *(.cs3.interrupt_vector)
+
     /* Make sure we pulled in an interrupt vector.  */
-    ASSERT (. != __cs3_interrupt_vector, "No interrupt vector");
+    ASSERT (. != __cy_interrupt_vector, "No interrupt vector");
+
+    ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");
 
-    PROVIDE(__cs3_reset = Reset);
-    *(.cs3.reset)
+    PROVIDE(__cy_reset = Reset);
+    *(.text.Reset)
     /* Make sure we pulled in some reset code.  */
-    ASSERT (. != __cs3_reset, "No reset code");
+    ASSERT (. != __cy_reset, "No reset code");
 
 	/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
     *(.dma_init)
-    ASSERT(0 + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
+    ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
 		
-    *(.text.cs3.init)
     *(.text .text.* .gnu.linkonce.t.*)
     *(.plt)
     *(.gnu.warning)
@@ -130,13 +159,12 @@ SECTIONS
     KEEP (*crtend.o(.dtors))
 
     . = ALIGN(4);
-    __cs3_regions = .;
-    LONG (0)
-    LONG (__cs3_region_init_ram)
-    LONG (__cs3_region_start_data)
-    LONG (__cs3_region_init_size_ram)
-    LONG (__cs3_region_zero_size_ram)
-    __cs3_regions_end = .;
+    __cy_regions = .;
+    LONG (__cy_region_init_ram)
+    LONG (__cy_region_start_data)
+    LONG (__cy_region_init_size_ram)
+    LONG (__cy_region_zero_size_ram)
+    __cy_regions_end = .;
 
     . = ALIGN (8);
     _etext = .;
@@ -144,9 +172,7 @@ SECTIONS
 
   .ramvectors (NOLOAD) : ALIGN(8)
   {
-    __cs3_region_start_ram = .;
-    *(.cs3.region-head.ram)
-    ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");
+    __cy_region_start_ram = .;
     KEEP(*(.ramvectors))
   }
 
@@ -157,7 +183,7 @@ SECTIONS
 
   .data : ALIGN(8)
   {
-    __cs3_region_start_data = .;
+    __cy_region_start_data = .;
 
     KEEP(*(.jcr))
     *(.got.plt) *(.got)
@@ -169,6 +195,7 @@ SECTIONS
   } >ram AT>rom
   .bss : ALIGN(8)
   {
+    PROVIDE(__bss_start__ = .);
     *(.shbss)
     *(.bss .bss.* .gnu.linkonce.b.*)
     *(COMMON)
@@ -177,13 +204,58 @@ SECTIONS
     _end = .;
     __end = .;
   } >ram AT>rom
+  PROVIDE(end = .);
+  PROVIDE(__bss_end__ = .);
+  
+  __cy_region_init_ram = LOADADDR (.data);
+  __cy_region_init_size_ram = _edata - ADDR (.data);
+  __cy_region_zero_size_ram = _end - _edata;
+  
+  /* The .stack and .heap sections don't contain any symbols. 
+   * They are only used for linker to calculate RAM utilization.
+   */
+  .heap (NOLOAD) :
+  {
+    . = _end;
+    . += 0x1000;
+    __cy_heap_limit = .;
+  } >ram
+
+  .stack (__cy_stack - 0x4000) (NOLOAD) :
+  {
+    __cy_stack_limit = .;
+    . += 0x4000;
+  } >ram
   
-  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
-  __cs3_region_size_ram = LENGTH(ram);
-  __cs3_region_init_ram = LOADADDR (.data);
-  __cs3_region_init_size_ram = _edata - ADDR (.data);
-  __cs3_region_zero_size_ram = _end - _edata;
+  /* Check if data + heap + stack exceeds RAM limit */
+  ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")
+
+  .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :
+  {
+    KEEP(*(.cyloadermeta))
+  } :NONE
+
+  .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :
+  {
+    KEEP(*(.cyloadablemeta))
+  } >rom
+
+  .cyconfigecc (0x80000000 + ecc_offset) : 
+  {
+    KEEP(*(.cyconfigecc))
+  } :NONE 
+
+  .cycustnvl      0x90000000 : { KEEP(*(.cycustnvl)) } :NONE 
+  .cywolatch      0x90100000 : { KEEP(*(.cywolatch)) } :NONE 
+
+  .cyeeprom (0x90200000 + ee_offset) : 
+  {
+    KEEP(*(.cyeeprom))
+    ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");
+  } :NONE 
 
+  .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE 
+  .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE 
 
   .stab 0 (NOLOAD) : { *(.stab) }
   .stabstr 0 (NOLOAD) : { *(.stabstr) }

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex

@@ -1,30 +1,33 @@
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-:2000200003400140024101400242014002430140064801401049014004500140015101405C
-:2000400014FF18081CE12CFF34F06430870F5B045F018010818684418582870488818901B7
-:200060008A408BAE8C888D698E618F0690019186924094479698978698E299E79A089B0810
-:200080009C419D86A110A404A504A740A840A982AC41AD10B10FB3E0B4C0B510B63FB7087A
-:2000A000B880B922BA20BB0CBE40BF40D409D604D80BD90BDB0BDC99DD90DF010040012602
-:2000C0000A6910081220138019A02054226C2310281029A12A04300831403210330138500B
-:2000E0003905581059085A82628063406D407801C00FC20FC407CA0FCC0FCE0FD60FD809B0
-:20010000DE01023006040820095C0A0C0B200C100D380E0C0F421203140415401608173043
-:2001200019191A481B601C031D0722012307240328032C03303C3240337034013507360275
-:2001400037083B083E503F5054405604580B590B5B0B5C995D905F01820885018610870274
-:2001600089028B018D018E058F0494069A019D06AA03AC08AE10B018B107B407B902BE0108
-:20018000D808D908DC99DF010040010A02080448068008200A610E080F101028124013803D
-:2001A0001560190A1A021B901E88210822A027402902310832103340374038403B103C4019
-:2001C0003F1460806250632078017F018004848086808A028E2490409160926193169602FD
-:2001E00098219A509B80A028A208A508A6C2A780A821C0BFC26FC4CFCA01CC1ECE7CD80FA1
-:20020000DE11E250E42056085B045D90004401210A69102A190120102110221023042840C0
-:2002200029602A0430083210334138503904404041104380490A4A0A500352545E806108D9
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-:2002600099209C019D4B9E049F81A208A408A680AC40AE04AF40C00FC20FC407CA0FCC0F56
-:20028000CE0ED00DD20CD610D812DE0130103640CC309C10A6409C10A6409C10A640210887
-:2002A00025809C10AE40C860EE4009025004578081808410850889028C048F809C10A18852
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-:2002E0000021FF4E90DC40001FD0200C7F118022C0DC01000020008FC0080400C0040800B3
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-:200320002200F0080400000000000228040B0B0B909900010000C00040011011C001001132
-:20034000400140010000000000000000000000000000000000FFFF000000000008003000E5
-:2003600008000000000000000000000010000000FF000000000000010200F10E0E000C004A
-:200380000000000000FCFC0000000000F0000FF00000000000010000F00F0F000000000166
+:20000000014500400752004001640040020301403F0401402A05014003060140410701400F
+:20002000010D014009150140431601403A17014002400140014101400142014002430140D6
+:200040000244014002450140044801400E4901400450014001510140360214FF1804190CB8
+:200060001CE12CFF34F06410860F9840B04000011D012D013001310139023E01560858047F
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+:200180005980600266206C146EA16F3B744077027C0294289504960199109B089C029D4007
+:2001A0009E409F61A132A204A442A601A7AAAA40AD21C0F0C2F0C470CAF0CCD0CE70D0F068
+:2001C000D210D608D828DE80EA80848089409C80A140AA40AD01B085B210E620000402082A
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+:20024000A801A904AA04AC08AE10B007B107B207B618B80ABE40BF01D80BD904DB04DC092E
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+:200280001D841E4A1F102101254027082911320A351036023B203D883E20462047086405E1
+:2002A0006504680278027C028D409201980299109A129B739C809D809E20A080A124A21286
+:2002C000A580A601C0FBC2FAC4F3CA05CCA3CE74D870DE81E0403340CC109F409F40AB40E5
+:2002E000EE801440C404B040EA01201026808E80C86008025B205F4084028B209340A810AD
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+:20034000C000046C00480000000F00F00000FF1000080000000040403205100004FEDBCBA0
+:200360003FFFFFFF2200F0080400000000000224040B0B0B909900010000C000400110118C
+:20038000C0010011400140010000000000000000000000000000000000FFFF00000000000B
+:2003A0000800300008000000000000000000000010000000FF000000000000010200F10EEC
+:2003C0000E000C000000000000FCFC0000000000F0000FF00000000000010000F00F0F000D
+:2003E0000000000100000000000000000000000000000000000000000000000000000000FC
 :00000001FF

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: core_cm3_psoc5.h
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   Provides important type information for the PSoC5.  This includes types
@@ -38,6 +38,17 @@ typedef enum IRQn
   /* Not relevant.  All peripheral interrupts are defined by the user */
 } IRQn_Type;
 
+#include <cytypes.h>
+
+#define __CHECK_DEVICE_DEFINES
+
+#define __CM3_REV                 0x0201
+
+#define __MPU_PRESENT             0
+#define __NVIC_PRIO_BITS          3
+#define __Vendor_SysTickConfig    0
+
 #include <core_cm3.h>
 
+
 #endif /* __CORE_CM3_PSOC5_H__ */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h

@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.h
-* Version 3.40
+* Version 4.0
 *
 * Description:
 *  Provides the function definitions for the power management API.
@@ -91,37 +91,33 @@ void CyPmOppsSet(void) ;
 #endif  /* (CY_PSOC3) */
 
 
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-    /* Wake up sources for the Sleep mode */
-    #define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
-    #define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
-    #define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
-    #define PM_SLEEP_SRC_COMPARATOR3        (0x0008u)
-    #define PM_SLEEP_SRC_PICU               (0x0040u)
-    #define PM_SLEEP_SRC_I2C                (0x0080u)
-    #define PM_SLEEP_SRC_BOOSTCONVERTER     (0x0200u)
-    #define PM_SLEEP_SRC_VD                 (0x0400u)
-    #define PM_SLEEP_SRC_CTW                (0x0800u)
-    #define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
-    #define PM_SLEEP_SRC_LCD                (0x1000u)
-
-    /* Wake up sources for the Alternate Active mode */
-    #define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
-    #define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
-    #define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
-    #define PM_ALT_ACT_SRC_COMPARATOR3      (0x0008u)
-    #define PM_ALT_ACT_SRC_INTERRUPT        (0x0010u)
-    #define PM_ALT_ACT_SRC_PICU             (0x0040u)
-    #define PM_ALT_ACT_SRC_I2C              (0x0080u)
-    #define PM_ALT_ACT_SRC_BOOSTCONVERTER   (0x0200u)
-    #define PM_ALT_ACT_SRC_FTW              (0x0400u)
-    #define PM_ALT_ACT_SRC_VD               (0x0400u)
-    #define PM_ALT_ACT_SRC_CTW              (0x0800u)
-    #define PM_ALT_ACT_SRC_ONE_PPS          (0x0800u)
-    #define PM_ALT_ACT_SRC_LCD              (0x1000u)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+/* Wake up sources for the Sleep mode */
+#define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
+#define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
+#define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
+#define PM_SLEEP_SRC_COMPARATOR3        (0x0008u)
+#define PM_SLEEP_SRC_PICU               (0x0040u)
+#define PM_SLEEP_SRC_I2C                (0x0080u)
+#define PM_SLEEP_SRC_BOOSTCONVERTER     (0x0200u)
+#define PM_SLEEP_SRC_VD                 (0x0400u)
+#define PM_SLEEP_SRC_CTW                (0x0800u)
+#define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
+#define PM_SLEEP_SRC_LCD                (0x1000u)
+
+/* Wake up sources for the Alternate Active mode */
+#define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
+#define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
+#define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
+#define PM_ALT_ACT_SRC_COMPARATOR3      (0x0008u)
+#define PM_ALT_ACT_SRC_INTERRUPT        (0x0010u)
+#define PM_ALT_ACT_SRC_PICU             (0x0040u)
+#define PM_ALT_ACT_SRC_I2C              (0x0080u)
+#define PM_ALT_ACT_SRC_BOOSTCONVERTER   (0x0200u)
+#define PM_ALT_ACT_SRC_FTW              (0x0400u)
+#define PM_ALT_ACT_SRC_VD               (0x0400u)
+#define PM_ALT_ACT_SRC_CTW              (0x0800u)
+#define PM_ALT_ACT_SRC_ONE_PPS          (0x0800u)
+#define PM_ALT_ACT_SRC_LCD              (0x1000u)
 
 
 #define CY_PM_WAKEUP_PICU               (0x04u)
@@ -146,11 +142,7 @@ void CyPmOppsSet(void) ;
 #define CY_PM_FREQ_48MHZ                (48u)
 
 
-#if(CY_PSOC5A)
-    #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (650u)
-#else
-    #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
-#endif  /* (CY_PSOC5A) */
+#define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
 
 
 /* Delay line bandgap current settling time starting from a wakeup event */
@@ -165,13 +157,9 @@ void CyPmOppsSet(void) ;
     #define     CY_PM_MAX_FLASH_WAIT_CYCLES        (45u)
 #endif  /* (CY_PSOC3) */
 
-#if(CY_PSOC5A)
-    #define     CY_PM_MAX_FLASH_WAIT_CYCLES        (55u)
-#endif  /* (CY_PSOC5A) */
-
-#if(CY_PSOC5LP)
+#if(CY_PSOC5)
     #define     CY_PM_MAX_FLASH_WAIT_CYCLES        (55u)
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 
 /*******************************************************************************
@@ -182,8 +170,9 @@ void CyPmOppsSet(void) ;
 * bitfield.
 *******************************************************************************/
 #if(CY_PSOC3)
-    #define CY_PM_GET_CPU_FREQ_MHZ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \
-                                   ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))
+    #define CY_PM_GET_CPU_FREQ_MHZ \
+                            ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \
+                            ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))
 #endif  /* (CY_PSOC3) */
 
 #if(CY_PSOC5)
@@ -205,7 +194,7 @@ void CyPmOppsSet(void) ;
 
     #if defined(__ARMCC_VERSION)    /* Instristic for Keil compilers */
         #define CY_PM_WFI       __wfi()
-    #else   /* ASM for GCC */
+    #else   /* ASM for GCC & IAR */
         #define CY_PM_WFI       asm volatile ("WFI \n")
     #endif /* (__ARMCC_VERSION) */
 
@@ -273,75 +262,28 @@ typedef struct cyPmClockBackupStruct
 
 typedef struct cyPmBackupStruct
 {
-    #if(!CY_PSOC5A)
-
-        uint8 iloPowerMode;         /* ILO power mode           */
-        uint8 ilo1kEnable;          /* ILO 1K enable state      */
-        uint8 ilo100kEnable;        /* ILO 100K enable state    */
-
-        uint8 slpTrBypass;          /* Sleep Trim Bypass        */
-
-    #endif  /* (!CY_PSOC5A) */
-
-
-    #if(CY_PSOC5A)
-
-        /* State of the I2C regulator backup */
-        uint8 i2cRegBackup;
-
-    #endif /* (CY_PSOC5A) */
-
-
-    #if(CY_PSOC5A)
-        uint8 buzzSleepTrim;
-    #endif  /* (CY_PSOC5A) */
+    uint8 iloPowerMode;         /* ILO power mode           */
+    uint8 ilo1kEnable;          /* ILO 1K enable state      */
+    uint8 ilo100kEnable;        /* ILO 100K enable state    */
 
+    uint8 slpTrBypass;          /* Sleep Trim Bypass        */
 
     #if(CY_PSOC3)
 
         uint8 swvClkEnabled;    /* SWV clock enable state   */
         uint8 prt1Dm;           /* Ports drive mode configuration */
+        uint8 hardwareBuzz;
 
     #endif  /* (CY_PSOC3)  */
 
-    #if(CY_PSOC3 || CY_PSOC5LP)
-
-        uint8 wakeupCfg0;       /* Wake up configuration 0  */
-        uint8 wakeupCfg1;       /* Wake up configuration 1  */
-        uint8 wakeupCfg2;       /* Wake up configuration 2  */
-
-    #endif  /* (CY_PSOC3 || CY_PSOC5LP) */
-
+    uint8 wakeupCfg0;       /* Wake up configuration 0  */
+    uint8 wakeupCfg1;       /* Wake up configuration 1  */
+    uint8 wakeupCfg2;       /* Wake up configuration 2  */
 
-    #if(CY_PSOC3 || CY_PSOC5LP)
-
-        uint8 wakeupTrim0;
-        uint8 wakeupTrim1;
-
-    #endif  /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-    #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)
-
-        uint8 scctData[28u];   /* SC/CT routing registers  */
-
-    #endif  /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */
-
-    #if(CY_PSOC5A)
-
-        uint8 cmpData[20u];
-        uint8 dacData[16u];
-        uint8 dsmData[5u];
-        uint8 sarData[10u];
-
-        uint8 pmTwCfg2;
-        uint8 picuIntType[72u];
-
-        uint8 pres1;
-        uint8 pres2;
-
-    #endif  /* (CY_PSOC5A)  */
+    uint8 wakeupTrim0;
+    uint8 wakeupTrim1;
 
+    uint8 scctData[28u];   /* SC/CT routing registers  */
 
     /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */
     uint8 lvidEn;
@@ -425,26 +367,15 @@ typedef struct cyPmBackupStruct
 #endif /* (CY_PSOC3) */
 
 
-#if(!CY_PSOC5A)
+/* Sleep Regulator Trim Register */
+#define CY_PM_PWRSYS_SLP_TR_REG         (* (reg8 *) CYREG_PWRSYS_SLP_TR )
+#define CY_PM_PWRSYS_SLP_TR_PTR         (  (reg8 *) CYREG_PWRSYS_SLP_TR )
 
-    /* Sleep Regulator Trim Register */
-    #define CY_PM_PWRSYS_SLP_TR_REG         (* (reg8 *) CYREG_PWRSYS_SLP_TR )
-    #define CY_PM_PWRSYS_SLP_TR_PTR         (  (reg8 *) CYREG_PWRSYS_SLP_TR )
-
-#endif /* (CY_PSOC3) */
 
 /* Reset System Control Register */
 #define CY_PM_RESET_CR1_REG                 (* (reg8 *) CYREG_RESET_CR1 )
 #define CY_PM_RESET_CR1_PTR                 (  (reg8 *) CYREG_RESET_CR1 )
 
-#if(CY_PSOC5A)
-
-    /* LVD/POR Test Mode Control Register */
-    #define CY_PM_RESET_CR3_REG             (* (reg8 *) CYREG_RESET_CR3 )
-    #define CY_PM_RESET_CR3_PTR             (  (reg8 *) CYREG_RESET_CR3 )
-
-#endif  /* (CY_PSOC5A) */
-
 /* Power Mode Wakeup Trim Register 0 */
 #define CY_PM_PWRSYS_WAKE_TR0_REG           (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 )
 #define CY_PM_PWRSYS_WAKE_TR0_PTR           (  (reg8 *) CYREG_PWRSYS_WAKE_TR0 )
@@ -457,14 +388,6 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC3) */
 
-#if(CY_PSOC5A)
-
-    /* Power Mode Buzz Trim Register */
-    #define CY_PM_PWRSYS_BUZZ_TR_REG        (* (reg8 *) CYREG_PWRSYS_BUZZ_TR )
-    #define CY_PM_PWRSYS_BUZZ_TR_PTR        (  (reg8 *) CYREG_PWRSYS_BUZZ_TR )
-
-#endif  /* (CY_PSOC5A) */
-
 /* Power Manager Interrupt Status Register */
 #define CY_PM_INT_SR_REG                    (* (reg8 *) CYREG_PM_INT_SR )
 #define CY_PM_INT_SR_PTR                    (  (reg8 *) CYREG_PM_INT_SR )
@@ -533,31 +456,17 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-    /* Power Mode Wakeup Mask Configuration Register 0 */
-    #define CY_PM_WAKEUP_CFG0_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )
-    #define CY_PM_WAKEUP_CFG0_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG0 )
-
-    /* Power Mode Wakeup Mask Configuration Register 1 */
-    #define CY_PM_WAKEUP_CFG1_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )
-    #define CY_PM_WAKEUP_CFG1_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG1 )
-
-    /* Power Mode Wakeup Mask Configuration Register 2 */
-    #define CY_PM_WAKEUP_CFG2_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )
-    #define CY_PM_WAKEUP_CFG2_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG2 )
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
-
-
-#if(CY_PSOC5A)
-
-    /* Watchdog Timer Configuration Register */
-    #define CY_PM_WDT_CFG_REG               (* (reg8 *) CYREG_PM_WDT_CFG )
-    #define CY_PM_WDT_CFG_PTR               (  (reg8 *) CYREG_PM_WDT_CFG )
+/* Power Mode Wakeup Mask Configuration Register 0 */
+#define CY_PM_WAKEUP_CFG0_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )
+#define CY_PM_WAKEUP_CFG0_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG0 )
 
-#endif  /* (CY_PSOC5A) */
+/* Power Mode Wakeup Mask Configuration Register 1 */
+#define CY_PM_WAKEUP_CFG1_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )
+#define CY_PM_WAKEUP_CFG1_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG1 )
 
+/* Power Mode Wakeup Mask Configuration Register 2 */
+#define CY_PM_WAKEUP_CFG2_REG           (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )
+#define CY_PM_WAKEUP_CFG2_PTR           (  (reg8 *) CYREG_PM_WAKEUP_CFG2 )
 
 /* Boost Control 2 */
 #define CY_PM_BOOST_CR2_REG           (* (reg8 *) CYREG_BOOST_CR2 )
@@ -657,29 +566,14 @@ typedef struct cyPmBackupStruct
 /* The low-voltage-interrupt feature on the external digital supply */
 #define CY_PM_RESET_CR1_LVID_EN         (0x01u)
 
-#if(CY_PSOC5A)
-
-    /* Partly disables PRES-A and PRES-D circuits */
-    #define CY_PM_RESET_CR1_DIS_PRES1   (0x10u)
-
-    /* Partly disables PRES-A and PRES-D circuits */
-    #define CY_PM_RESET_CR3_DIS_PRES2   (0x08u)
-
-#endif  /* (CY_PSOC5A) */
-
 /* Allows the system to program delays on clk_sync_d */
 #define CY_PM_CLKDIST_DELAY_EN          (0x04u)
 
 
-#if(CY_PSOC3 || CY_PSOC5LP)
-
-    #define CY_PM_WAKEUP_SRC_CMPS_MASK                  (0x000Fu)
-
-    /* Holdoff mask sleep trim */
-    #define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK     (0x1Fu)
-
-#endif  /* (CY_PSOC3 || CY_PSOC5LP) */
+#define CY_PM_WAKEUP_SRC_CMPS_MASK      (0x000Fu)
 
+/* Holdoff mask sleep trim */
+#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK     (0x1Fu)
 
 #if(CY_PSOC3)
 
@@ -701,49 +595,12 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-#if(!CY_PSOC5A)
-
-    /* Disable the sleep regulator and shorts vccd to vpwrsleep */
-    #define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
-
-#endif /* (!CY_PSOC5A) */
-
-
-#if(CY_PSOC5A)
-
-    #define CY_PM_PWRSYS_BUZZ_TR_512_TICKS      (0x08u)
-    #define CY_PM_PWRSYS_BUZZ_TR_MASK           (0xF0u)
-
-#endif  /* (CY_PSOC5A) */
-
-
-#if(CY_PSOC5A)
-
-    /* Watchdog Timer Configuration Register */
-    #define CY_PM_WDT_CFG_CTW_RESET             (0x80u)
-
-    /***************************************************************************
-    * The PICU interrupt type registers are divided into three sections where
-    * the registers addresses are consecutive.
-    ***************************************************************************/
-    #define CY_PM_PICU_0_6_INT_BASE      (CYDEV_PICU_INTTYPE_PICU0_BASE )
-    #define CY_PM_PICU_12_INT_BASE       (CYDEV_PICU_INTTYPE_PICU12_BASE)
-    #define CY_PM_PICU_15_INT_BASE       (CYDEV_PICU_INTTYPE_PICU15_BASE)
-
-    #define CY_PM_PICU_0_6_INT_SIZE      (CYDEV_PICU_INTTYPE_PICU0_SIZE + CYDEV_PICU_INTTYPE_PICU1_SIZE + \
-                                          CYDEV_PICU_INTTYPE_PICU2_SIZE + CYDEV_PICU_INTTYPE_PICU3_SIZE + \
-                                          CYDEV_PICU_INTTYPE_PICU4_SIZE + CYDEV_PICU_INTTYPE_PICU5_SIZE + \
-                                          CYDEV_PICU_INTTYPE_PICU6_SIZE)
-    #define CY_PM_PICU_12_INT_SIZE       (CYDEV_PICU_INTTYPE_PICU12_SIZE)
-    #define CY_PM_PICU_15_INT_SIZE       (CYDEV_PICU_INTTYPE_PICU15_SIZE)
-
-#endif  /* (CY_PSOC5A) */
+/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+#define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
 
 /* Boost Control 2: Select external precision reference */
 #define CY_PM_BOOST_CR2_EREFSEL_EXT     (0x08u)
 
-
-
 #if(CY_PSOC3)
 
     #define CY_PM_PWRSYS_WAKE_TR0       (0xFFu)
@@ -751,13 +608,12 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC3) */
 
-
-#if(CY_PSOC5LP)
+#if(CY_PSOC5)
 
     #define CY_PM_PWRSYS_WAKE_TR0       (0xFFu)
     #define CY_PM_PWRSYS_WAKE_TR1       (0xB0u)
 
-#endif  /* (CY_PSOC5LP) */
+#endif  /* (CY_PSOC5) */
 
 
 /*******************************************************************************

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h

@@ -1,10 +1,11 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
+* This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
 * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h

@@ -1,10 +1,11 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
+* This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
 * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc

@@ -1,10 +1,11 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
+* This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
 * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc

@@ -1,10 +1,11 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
+* This file is automatically generated by PSoC Creator.
 *
 ********************************************************************************
 * Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc

@@ -0,0 +1,5356 @@
+;
+; FILENAME: cydeviceiar.inc
+; OBSOLETE: Do not use this file. Use the _trm version instead.
+; PSoC Creator 3.0
+;
+; DESCRIPTION:
+; This file provides all of the address values for the entire PSoC device.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions, 
+; disclaimers, and limitations in the end user license agreement accompanying 
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+#define CYDEV_FLASH_BASE 0x00000000
+#define CYDEV_FLASH_SIZE 0x00040000
+#define CYDEV_FLASH_DATA_MBASE 0x00000000
+#define CYDEV_FLASH_DATA_MSIZE 0x00040000
+#define CYDEV_SRAM_BASE 0x1fff8000
+#define CYDEV_SRAM_SIZE 0x00010000
+#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000
+#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000
+#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000
+#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000
+#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000
+#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000
+#define CYDEV_SRAM_CODE_MBASE 0x1fff8000
+#define CYDEV_SRAM_CODE_MSIZE 0x00008000
+#define CYDEV_SRAM_DATA_MBASE 0x20000000
+#define CYDEV_SRAM_DATA_MSIZE 0x00008000
+#define CYDEV_SRAM_DATA16K_MBASE 0x20001000
+#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000
+#define CYDEV_SRAM_DATA32K_MBASE 0x20002000
+#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000
+#define CYDEV_SRAM_DATA64K_MBASE 0x20004000
+#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000
+#define CYDEV_DMA_BASE 0x20008000
+#define CYDEV_DMA_SIZE 0x00008000
+#define CYDEV_DMA_SRAM64K_MBASE 0x20008000
+#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000
+#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000
+#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000
+#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000
+#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000
+#define CYDEV_DMA_SRAM_MBASE 0x2000f000
+#define CYDEV_DMA_SRAM_MSIZE 0x00001000
+#define CYDEV_CLKDIST_BASE 0x40004000
+#define CYDEV_CLKDIST_SIZE 0x00000110
+#define CYDEV_CLKDIST_CR 0x40004000
+#define CYDEV_CLKDIST_LD 0x40004001
+#define CYDEV_CLKDIST_WRK0 0x40004002
+#define CYDEV_CLKDIST_WRK1 0x40004003
+#define CYDEV_CLKDIST_MSTR0 0x40004004
+#define CYDEV_CLKDIST_MSTR1 0x40004005
+#define CYDEV_CLKDIST_BCFG0 0x40004006
+#define CYDEV_CLKDIST_BCFG1 0x40004007
+#define CYDEV_CLKDIST_BCFG2 0x40004008
+#define CYDEV_CLKDIST_UCFG 0x40004009
+#define CYDEV_CLKDIST_DLY0 0x4000400a
+#define CYDEV_CLKDIST_DLY1 0x4000400b
+#define CYDEV_CLKDIST_DMASK 0x40004010
+#define CYDEV_CLKDIST_AMASK 0x40004014
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080
+#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081
+#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084
+#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085
+#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088
+#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089
+#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c
+#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d
+#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090
+#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091
+#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094
+#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095
+#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098
+#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099
+#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003
+#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c
+#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d
+#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004
+#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100
+#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101
+#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102
+#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004
+#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104
+#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105
+#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106
+#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004
+#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108
+#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109
+#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a
+#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004
+#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c
+#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d
+#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e
+#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f
+#define CYDEV_FASTCLK_BASE 0x40004200
+#define CYDEV_FASTCLK_SIZE 0x00000026
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001
+#define CYDEV_FASTCLK_IMO_CR 0x40004200
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004
+#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210
+#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212
+#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006
+#define CYDEV_FASTCLK_PLL_CFG0 0x40004220
+#define CYDEV_FASTCLK_PLL_CFG1 0x40004221
+#define CYDEV_FASTCLK_PLL_P 0x40004222
+#define CYDEV_FASTCLK_PLL_Q 0x40004223
+#define CYDEV_FASTCLK_PLL_SR 0x40004225
+#define CYDEV_SLOWCLK_BASE 0x40004300
+#define CYDEV_SLOWCLK_SIZE 0x0000000b
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002
+#define CYDEV_SLOWCLK_ILO_CR0 0x40004300
+#define CYDEV_SLOWCLK_ILO_CR1 0x40004301
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003
+#define CYDEV_SLOWCLK_X32_CR 0x40004308
+#define CYDEV_SLOWCLK_X32_CFG 0x40004309
+#define CYDEV_SLOWCLK_X32_TST 0x4000430a
+#define CYDEV_BOOST_BASE 0x40004320
+#define CYDEV_BOOST_SIZE 0x00000007
+#define CYDEV_BOOST_CR0 0x40004320
+#define CYDEV_BOOST_CR1 0x40004321
+#define CYDEV_BOOST_CR2 0x40004322
+#define CYDEV_BOOST_CR3 0x40004323
+#define CYDEV_BOOST_SR 0x40004324
+#define CYDEV_BOOST_CR4 0x40004325
+#define CYDEV_BOOST_SR2 0x40004326
+#define CYDEV_PWRSYS_BASE 0x40004330
+#define CYDEV_PWRSYS_SIZE 0x00000002
+#define CYDEV_PWRSYS_CR0 0x40004330
+#define CYDEV_PWRSYS_CR1 0x40004331
+#define CYDEV_PM_BASE 0x40004380
+#define CYDEV_PM_SIZE 0x00000057
+#define CYDEV_PM_TW_CFG0 0x40004380
+#define CYDEV_PM_TW_CFG1 0x40004381
+#define CYDEV_PM_TW_CFG2 0x40004382
+#define CYDEV_PM_WDT_CFG 0x40004383
+#define CYDEV_PM_WDT_CR 0x40004384
+#define CYDEV_PM_INT_SR 0x40004390
+#define CYDEV_PM_MODE_CFG0 0x40004391
+#define CYDEV_PM_MODE_CFG1 0x40004392
+#define CYDEV_PM_MODE_CSR 0x40004393
+#define CYDEV_PM_USB_CR0 0x40004394
+#define CYDEV_PM_WAKEUP_CFG0 0x40004398
+#define CYDEV_PM_WAKEUP_CFG1 0x40004399
+#define CYDEV_PM_WAKEUP_CFG2 0x4000439a
+#define CYDEV_PM_ACT_BASE 0x400043a0
+#define CYDEV_PM_ACT_SIZE 0x0000000e
+#define CYDEV_PM_ACT_CFG0 0x400043a0
+#define CYDEV_PM_ACT_CFG1 0x400043a1
+#define CYDEV_PM_ACT_CFG2 0x400043a2
+#define CYDEV_PM_ACT_CFG3 0x400043a3
+#define CYDEV_PM_ACT_CFG4 0x400043a4
+#define CYDEV_PM_ACT_CFG5 0x400043a5
+#define CYDEV_PM_ACT_CFG6 0x400043a6
+#define CYDEV_PM_ACT_CFG7 0x400043a7
+#define CYDEV_PM_ACT_CFG8 0x400043a8
+#define CYDEV_PM_ACT_CFG9 0x400043a9
+#define CYDEV_PM_ACT_CFG10 0x400043aa
+#define CYDEV_PM_ACT_CFG11 0x400043ab
+#define CYDEV_PM_ACT_CFG12 0x400043ac
+#define CYDEV_PM_ACT_CFG13 0x400043ad
+#define CYDEV_PM_STBY_BASE 0x400043b0
+#define CYDEV_PM_STBY_SIZE 0x0000000e
+#define CYDEV_PM_STBY_CFG0 0x400043b0
+#define CYDEV_PM_STBY_CFG1 0x400043b1
+#define CYDEV_PM_STBY_CFG2 0x400043b2
+#define CYDEV_PM_STBY_CFG3 0x400043b3
+#define CYDEV_PM_STBY_CFG4 0x400043b4
+#define CYDEV_PM_STBY_CFG5 0x400043b5
+#define CYDEV_PM_STBY_CFG6 0x400043b6
+#define CYDEV_PM_STBY_CFG7 0x400043b7
+#define CYDEV_PM_STBY_CFG8 0x400043b8
+#define CYDEV_PM_STBY_CFG9 0x400043b9
+#define CYDEV_PM_STBY_CFG10 0x400043ba
+#define CYDEV_PM_STBY_CFG11 0x400043bb
+#define CYDEV_PM_STBY_CFG12 0x400043bc
+#define CYDEV_PM_STBY_CFG13 0x400043bd
+#define CYDEV_PM_AVAIL_BASE 0x400043c0
+#define CYDEV_PM_AVAIL_SIZE 0x00000017
+#define CYDEV_PM_AVAIL_CR0 0x400043c0
+#define CYDEV_PM_AVAIL_CR1 0x400043c1
+#define CYDEV_PM_AVAIL_CR2 0x400043c2
+#define CYDEV_PM_AVAIL_CR3 0x400043c3
+#define CYDEV_PM_AVAIL_CR4 0x400043c4
+#define CYDEV_PM_AVAIL_CR5 0x400043c5
+#define CYDEV_PM_AVAIL_CR6 0x400043c6
+#define CYDEV_PM_AVAIL_SR0 0x400043d0
+#define CYDEV_PM_AVAIL_SR1 0x400043d1
+#define CYDEV_PM_AVAIL_SR2 0x400043d2
+#define CYDEV_PM_AVAIL_SR3 0x400043d3
+#define CYDEV_PM_AVAIL_SR4 0x400043d4
+#define CYDEV_PM_AVAIL_SR5 0x400043d5
+#define CYDEV_PM_AVAIL_SR6 0x400043d6
+#define CYDEV_PICU_BASE 0x40004500
+#define CYDEV_PICU_SIZE 0x000000b0
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f
+#define CYDEV_PICU_STAT_BASE 0x40004580
+#define CYDEV_PICU_STAT_SIZE 0x00000010
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001
+#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f
+#define CYDEV_PICU_SNAP_BASE 0x40004590
+#define CYDEV_PICU_SNAP_SIZE 0x00000010
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001
+#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001
+#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af
+#define CYDEV_MFGCFG_BASE 0x40004600
+#define CYDEV_MFGCFG_SIZE 0x000000ed
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001
+#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681
+#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682
+#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683
+#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686
+#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687
+#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002
+#define CYDEV_MFGCFG_ILO_TR0 0x40004690
+#define CYDEV_MFGCFG_ILO_TR1 0x40004691
+#define CYDEV_MFGCFG_X32_BASE 0x40004698
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001
+#define CYDEV_MFGCFG_X32_TR 0x40004698
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005
+#define CYDEV_MFGCFG_IMO_TR0 0x400046a0
+#define CYDEV_MFGCFG_IMO_TR1 0x400046a1
+#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2
+#define CYDEV_MFGCFG_IMO_C36M 0x400046a3
+#define CYDEV_MFGCFG_IMO_TR2 0x400046a4
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001
+#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8
+#define CYDEV_MFGCFG_DLY 0x400046c0
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d
+#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002
+#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4
+#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5
+#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea
+#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec
+#define CYDEV_RESET_BASE 0x400046f0
+#define CYDEV_RESET_SIZE 0x0000000f
+#define CYDEV_RESET_IPOR_CR0 0x400046f0
+#define CYDEV_RESET_IPOR_CR1 0x400046f1
+#define CYDEV_RESET_IPOR_CR2 0x400046f2
+#define CYDEV_RESET_IPOR_CR3 0x400046f3
+#define CYDEV_RESET_CR0 0x400046f4
+#define CYDEV_RESET_CR1 0x400046f5
+#define CYDEV_RESET_CR2 0x400046f6
+#define CYDEV_RESET_CR3 0x400046f7
+#define CYDEV_RESET_CR4 0x400046f8
+#define CYDEV_RESET_CR5 0x400046f9
+#define CYDEV_RESET_SR0 0x400046fa
+#define CYDEV_RESET_SR1 0x400046fb
+#define CYDEV_RESET_SR2 0x400046fc
+#define CYDEV_RESET_SR3 0x400046fd
+#define CYDEV_RESET_TR 0x400046fe
+#define CYDEV_SPC_BASE 0x40004700
+#define CYDEV_SPC_SIZE 0x00000100
+#define CYDEV_SPC_FM_EE_CR 0x40004700
+#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701
+#define CYDEV_SPC_EE_SCR 0x40004702
+#define CYDEV_SPC_EE_ERR 0x40004703
+#define CYDEV_SPC_CPU_DATA 0x40004720
+#define CYDEV_SPC_DMA_DATA 0x40004721
+#define CYDEV_SPC_SR 0x40004722
+#define CYDEV_SPC_CR 0x40004723
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080
+#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780
+#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080
+#define CYDEV_CACHE_BASE 0x40004800
+#define CYDEV_CACHE_SIZE 0x0000009c
+#define CYDEV_CACHE_CC_CTL 0x40004800
+#define CYDEV_CACHE_ECC_CORR 0x40004880
+#define CYDEV_CACHE_ECC_ERR 0x40004888
+#define CYDEV_CACHE_FLASH_ERR 0x40004890
+#define CYDEV_CACHE_HITMISS 0x40004898
+#define CYDEV_I2C_BASE 0x40004900
+#define CYDEV_I2C_SIZE 0x000000e1
+#define CYDEV_I2C_XCFG 0x400049c8
+#define CYDEV_I2C_ADR 0x400049ca
+#define CYDEV_I2C_CFG 0x400049d6
+#define CYDEV_I2C_CSR 0x400049d7
+#define CYDEV_I2C_D 0x400049d8
+#define CYDEV_I2C_MCSR 0x400049d9
+#define CYDEV_I2C_CLK_DIV1 0x400049db
+#define CYDEV_I2C_CLK_DIV2 0x400049dc
+#define CYDEV_I2C_TMOUT_CSR 0x400049dd
+#define CYDEV_I2C_TMOUT_SR 0x400049de
+#define CYDEV_I2C_TMOUT_CFG0 0x400049df
+#define CYDEV_I2C_TMOUT_CFG1 0x400049e0
+#define CYDEV_DEC_BASE 0x40004e00
+#define CYDEV_DEC_SIZE 0x00000015
+#define CYDEV_DEC_CR 0x40004e00
+#define CYDEV_DEC_SR 0x40004e01
+#define CYDEV_DEC_SHIFT1 0x40004e02
+#define CYDEV_DEC_SHIFT2 0x40004e03
+#define CYDEV_DEC_DR2 0x40004e04
+#define CYDEV_DEC_DR2H 0x40004e05
+#define CYDEV_DEC_DR1 0x40004e06
+#define CYDEV_DEC_OCOR 0x40004e08
+#define CYDEV_DEC_OCORM 0x40004e09
+#define CYDEV_DEC_OCORH 0x40004e0a
+#define CYDEV_DEC_GCOR 0x40004e0c
+#define CYDEV_DEC_GCORH 0x40004e0d
+#define CYDEV_DEC_GVAL 0x40004e0e
+#define CYDEV_DEC_OUTSAMP 0x40004e10
+#define CYDEV_DEC_OUTSAMPM 0x40004e11
+#define CYDEV_DEC_OUTSAMPH 0x40004e12
+#define CYDEV_DEC_OUTSAMPS 0x40004e13
+#define CYDEV_DEC_COHER 0x40004e14
+#define CYDEV_TMR0_BASE 0x40004f00
+#define CYDEV_TMR0_SIZE 0x0000000c
+#define CYDEV_TMR0_CFG0 0x40004f00
+#define CYDEV_TMR0_CFG1 0x40004f01
+#define CYDEV_TMR0_CFG2 0x40004f02
+#define CYDEV_TMR0_SR0 0x40004f03
+#define CYDEV_TMR0_PER0 0x40004f04
+#define CYDEV_TMR0_PER1 0x40004f05
+#define CYDEV_TMR0_CNT_CMP0 0x40004f06
+#define CYDEV_TMR0_CNT_CMP1 0x40004f07
+#define CYDEV_TMR0_CAP0 0x40004f08
+#define CYDEV_TMR0_CAP1 0x40004f09
+#define CYDEV_TMR0_RT0 0x40004f0a
+#define CYDEV_TMR0_RT1 0x40004f0b
+#define CYDEV_TMR1_BASE 0x40004f0c
+#define CYDEV_TMR1_SIZE 0x0000000c
+#define CYDEV_TMR1_CFG0 0x40004f0c
+#define CYDEV_TMR1_CFG1 0x40004f0d
+#define CYDEV_TMR1_CFG2 0x40004f0e
+#define CYDEV_TMR1_SR0 0x40004f0f
+#define CYDEV_TMR1_PER0 0x40004f10
+#define CYDEV_TMR1_PER1 0x40004f11
+#define CYDEV_TMR1_CNT_CMP0 0x40004f12
+#define CYDEV_TMR1_CNT_CMP1 0x40004f13
+#define CYDEV_TMR1_CAP0 0x40004f14
+#define CYDEV_TMR1_CAP1 0x40004f15
+#define CYDEV_TMR1_RT0 0x40004f16
+#define CYDEV_TMR1_RT1 0x40004f17
+#define CYDEV_TMR2_BASE 0x40004f18
+#define CYDEV_TMR2_SIZE 0x0000000c
+#define CYDEV_TMR2_CFG0 0x40004f18
+#define CYDEV_TMR2_CFG1 0x40004f19
+#define CYDEV_TMR2_CFG2 0x40004f1a
+#define CYDEV_TMR2_SR0 0x40004f1b
+#define CYDEV_TMR2_PER0 0x40004f1c
+#define CYDEV_TMR2_PER1 0x40004f1d
+#define CYDEV_TMR2_CNT_CMP0 0x40004f1e
+#define CYDEV_TMR2_CNT_CMP1 0x40004f1f
+#define CYDEV_TMR2_CAP0 0x40004f20
+#define CYDEV_TMR2_CAP1 0x40004f21
+#define CYDEV_TMR2_RT0 0x40004f22
+#define CYDEV_TMR2_RT1 0x40004f23
+#define CYDEV_TMR3_BASE 0x40004f24
+#define CYDEV_TMR3_SIZE 0x0000000c
+#define CYDEV_TMR3_CFG0 0x40004f24
+#define CYDEV_TMR3_CFG1 0x40004f25
+#define CYDEV_TMR3_CFG2 0x40004f26
+#define CYDEV_TMR3_SR0 0x40004f27
+#define CYDEV_TMR3_PER0 0x40004f28
+#define CYDEV_TMR3_PER1 0x40004f29
+#define CYDEV_TMR3_CNT_CMP0 0x40004f2a
+#define CYDEV_TMR3_CNT_CMP1 0x40004f2b
+#define CYDEV_TMR3_CAP0 0x40004f2c
+#define CYDEV_TMR3_CAP1 0x40004f2d
+#define CYDEV_TMR3_RT0 0x40004f2e
+#define CYDEV_TMR3_RT1 0x40004f2f
+#define CYDEV_IO_BASE 0x40005000
+#define CYDEV_IO_SIZE 0x00000200
+#define CYDEV_IO_PC_BASE 0x40005000
+#define CYDEV_IO_PC_SIZE 0x00000080
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT0_PC0 0x40005000
+#define CYDEV_IO_PC_PRT0_PC1 0x40005001
+#define CYDEV_IO_PC_PRT0_PC2 0x40005002
+#define CYDEV_IO_PC_PRT0_PC3 0x40005003
+#define CYDEV_IO_PC_PRT0_PC4 0x40005004
+#define CYDEV_IO_PC_PRT0_PC5 0x40005005
+#define CYDEV_IO_PC_PRT0_PC6 0x40005006
+#define CYDEV_IO_PC_PRT0_PC7 0x40005007
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT1_PC0 0x40005008
+#define CYDEV_IO_PC_PRT1_PC1 0x40005009
+#define CYDEV_IO_PC_PRT1_PC2 0x4000500a
+#define CYDEV_IO_PC_PRT1_PC3 0x4000500b
+#define CYDEV_IO_PC_PRT1_PC4 0x4000500c
+#define CYDEV_IO_PC_PRT1_PC5 0x4000500d
+#define CYDEV_IO_PC_PRT1_PC6 0x4000500e
+#define CYDEV_IO_PC_PRT1_PC7 0x4000500f
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT2_PC0 0x40005010
+#define CYDEV_IO_PC_PRT2_PC1 0x40005011
+#define CYDEV_IO_PC_PRT2_PC2 0x40005012
+#define CYDEV_IO_PC_PRT2_PC3 0x40005013
+#define CYDEV_IO_PC_PRT2_PC4 0x40005014
+#define CYDEV_IO_PC_PRT2_PC5 0x40005015
+#define CYDEV_IO_PC_PRT2_PC6 0x40005016
+#define CYDEV_IO_PC_PRT2_PC7 0x40005017
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT3_PC0 0x40005018
+#define CYDEV_IO_PC_PRT3_PC1 0x40005019
+#define CYDEV_IO_PC_PRT3_PC2 0x4000501a
+#define CYDEV_IO_PC_PRT3_PC3 0x4000501b
+#define CYDEV_IO_PC_PRT3_PC4 0x4000501c
+#define CYDEV_IO_PC_PRT3_PC5 0x4000501d
+#define CYDEV_IO_PC_PRT3_PC6 0x4000501e
+#define CYDEV_IO_PC_PRT3_PC7 0x4000501f
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT4_PC0 0x40005020
+#define CYDEV_IO_PC_PRT4_PC1 0x40005021
+#define CYDEV_IO_PC_PRT4_PC2 0x40005022
+#define CYDEV_IO_PC_PRT4_PC3 0x40005023
+#define CYDEV_IO_PC_PRT4_PC4 0x40005024
+#define CYDEV_IO_PC_PRT4_PC5 0x40005025
+#define CYDEV_IO_PC_PRT4_PC6 0x40005026
+#define CYDEV_IO_PC_PRT4_PC7 0x40005027
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT5_PC0 0x40005028
+#define CYDEV_IO_PC_PRT5_PC1 0x40005029
+#define CYDEV_IO_PC_PRT5_PC2 0x4000502a
+#define CYDEV_IO_PC_PRT5_PC3 0x4000502b
+#define CYDEV_IO_PC_PRT5_PC4 0x4000502c
+#define CYDEV_IO_PC_PRT5_PC5 0x4000502d
+#define CYDEV_IO_PC_PRT5_PC6 0x4000502e
+#define CYDEV_IO_PC_PRT5_PC7 0x4000502f
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT6_PC0 0x40005030
+#define CYDEV_IO_PC_PRT6_PC1 0x40005031
+#define CYDEV_IO_PC_PRT6_PC2 0x40005032
+#define CYDEV_IO_PC_PRT6_PC3 0x40005033
+#define CYDEV_IO_PC_PRT6_PC4 0x40005034
+#define CYDEV_IO_PC_PRT6_PC5 0x40005035
+#define CYDEV_IO_PC_PRT6_PC6 0x40005036
+#define CYDEV_IO_PC_PRT6_PC7 0x40005037
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008
+#define CYDEV_IO_PC_PRT12_PC0 0x40005060
+#define CYDEV_IO_PC_PRT12_PC1 0x40005061
+#define CYDEV_IO_PC_PRT12_PC2 0x40005062
+#define CYDEV_IO_PC_PRT12_PC3 0x40005063
+#define CYDEV_IO_PC_PRT12_PC4 0x40005064
+#define CYDEV_IO_PC_PRT12_PC5 0x40005065
+#define CYDEV_IO_PC_PRT12_PC6 0x40005066
+#define CYDEV_IO_PC_PRT12_PC7 0x40005067
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006
+#define CYDEV_IO_PC_PRT15_PC0 0x40005078
+#define CYDEV_IO_PC_PRT15_PC1 0x40005079
+#define CYDEV_IO_PC_PRT15_PC2 0x4000507a
+#define CYDEV_IO_PC_PRT15_PC3 0x4000507b
+#define CYDEV_IO_PC_PRT15_PC4 0x4000507c
+#define CYDEV_IO_PC_PRT15_PC5 0x4000507d
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002
+#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e
+#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f
+#define CYDEV_IO_DR_BASE 0x40005080
+#define CYDEV_IO_DR_SIZE 0x00000010
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508c
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508f
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001
+#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f
+#define CYDEV_IO_PS_BASE 0x40005090
+#define CYDEV_IO_PS_SIZE 0x00000010
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509c
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509f
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001
+#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f
+#define CYDEV_IO_PRT_BASE 0x40005100
+#define CYDEV_IO_PRT_SIZE 0x00000100
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT0_DR 0x40005100
+#define CYDEV_IO_PRT_PRT0_PS 0x40005101
+#define CYDEV_IO_PRT_PRT0_DM0 0x40005102
+#define CYDEV_IO_PRT_PRT0_DM1 0x40005103
+#define CYDEV_IO_PRT_PRT0_DM2 0x40005104
+#define CYDEV_IO_PRT_PRT0_SLW 0x40005105
+#define CYDEV_IO_PRT_PRT0_BYP 0x40005106
+#define CYDEV_IO_PRT_PRT0_BIE 0x40005107
+#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108
+#define CYDEV_IO_PRT_PRT0_CTL 0x40005109
+#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a
+#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b
+#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c
+#define CYDEV_IO_PRT_PRT0_AG 0x4000510d
+#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e
+#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT1_DR 0x40005110
+#define CYDEV_IO_PRT_PRT1_PS 0x40005111
+#define CYDEV_IO_PRT_PRT1_DM0 0x40005112
+#define CYDEV_IO_PRT_PRT1_DM1 0x40005113
+#define CYDEV_IO_PRT_PRT1_DM2 0x40005114
+#define CYDEV_IO_PRT_PRT1_SLW 0x40005115
+#define CYDEV_IO_PRT_PRT1_BYP 0x40005116
+#define CYDEV_IO_PRT_PRT1_BIE 0x40005117
+#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118
+#define CYDEV_IO_PRT_PRT1_CTL 0x40005119
+#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a
+#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b
+#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c
+#define CYDEV_IO_PRT_PRT1_AG 0x4000511d
+#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e
+#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT2_DR 0x40005120
+#define CYDEV_IO_PRT_PRT2_PS 0x40005121
+#define CYDEV_IO_PRT_PRT2_DM0 0x40005122
+#define CYDEV_IO_PRT_PRT2_DM1 0x40005123
+#define CYDEV_IO_PRT_PRT2_DM2 0x40005124
+#define CYDEV_IO_PRT_PRT2_SLW 0x40005125
+#define CYDEV_IO_PRT_PRT2_BYP 0x40005126
+#define CYDEV_IO_PRT_PRT2_BIE 0x40005127
+#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128
+#define CYDEV_IO_PRT_PRT2_CTL 0x40005129
+#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a
+#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b
+#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c
+#define CYDEV_IO_PRT_PRT2_AG 0x4000512d
+#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e
+#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT3_DR 0x40005130
+#define CYDEV_IO_PRT_PRT3_PS 0x40005131
+#define CYDEV_IO_PRT_PRT3_DM0 0x40005132
+#define CYDEV_IO_PRT_PRT3_DM1 0x40005133
+#define CYDEV_IO_PRT_PRT3_DM2 0x40005134
+#define CYDEV_IO_PRT_PRT3_SLW 0x40005135
+#define CYDEV_IO_PRT_PRT3_BYP 0x40005136
+#define CYDEV_IO_PRT_PRT3_BIE 0x40005137
+#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138
+#define CYDEV_IO_PRT_PRT3_CTL 0x40005139
+#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a
+#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b
+#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c
+#define CYDEV_IO_PRT_PRT3_AG 0x4000513d
+#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e
+#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT4_DR 0x40005140
+#define CYDEV_IO_PRT_PRT4_PS 0x40005141
+#define CYDEV_IO_PRT_PRT4_DM0 0x40005142
+#define CYDEV_IO_PRT_PRT4_DM1 0x40005143
+#define CYDEV_IO_PRT_PRT4_DM2 0x40005144
+#define CYDEV_IO_PRT_PRT4_SLW 0x40005145
+#define CYDEV_IO_PRT_PRT4_BYP 0x40005146
+#define CYDEV_IO_PRT_PRT4_BIE 0x40005147
+#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148
+#define CYDEV_IO_PRT_PRT4_CTL 0x40005149
+#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a
+#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b
+#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c
+#define CYDEV_IO_PRT_PRT4_AG 0x4000514d
+#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e
+#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT5_DR 0x40005150
+#define CYDEV_IO_PRT_PRT5_PS 0x40005151
+#define CYDEV_IO_PRT_PRT5_DM0 0x40005152
+#define CYDEV_IO_PRT_PRT5_DM1 0x40005153
+#define CYDEV_IO_PRT_PRT5_DM2 0x40005154
+#define CYDEV_IO_PRT_PRT5_SLW 0x40005155
+#define CYDEV_IO_PRT_PRT5_BYP 0x40005156
+#define CYDEV_IO_PRT_PRT5_BIE 0x40005157
+#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158
+#define CYDEV_IO_PRT_PRT5_CTL 0x40005159
+#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a
+#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b
+#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c
+#define CYDEV_IO_PRT_PRT5_AG 0x4000515d
+#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e
+#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT6_DR 0x40005160
+#define CYDEV_IO_PRT_PRT6_PS 0x40005161
+#define CYDEV_IO_PRT_PRT6_DM0 0x40005162
+#define CYDEV_IO_PRT_PRT6_DM1 0x40005163
+#define CYDEV_IO_PRT_PRT6_DM2 0x40005164
+#define CYDEV_IO_PRT_PRT6_SLW 0x40005165
+#define CYDEV_IO_PRT_PRT6_BYP 0x40005166
+#define CYDEV_IO_PRT_PRT6_BIE 0x40005167
+#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168
+#define CYDEV_IO_PRT_PRT6_CTL 0x40005169
+#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a
+#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b
+#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c
+#define CYDEV_IO_PRT_PRT6_AG 0x4000516d
+#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e
+#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT12_DR 0x400051c0
+#define CYDEV_IO_PRT_PRT12_PS 0x400051c1
+#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2
+#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3
+#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4
+#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5
+#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6
+#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7
+#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8
+#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9
+#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca
+#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb
+#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc
+#define CYDEV_IO_PRT_PRT12_AG 0x400051cd
+#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce
+#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010
+#define CYDEV_IO_PRT_PRT15_DR 0x400051f0
+#define CYDEV_IO_PRT_PRT15_PS 0x400051f1
+#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2
+#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3
+#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4
+#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5
+#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6
+#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7
+#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8
+#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9
+#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa
+#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb
+#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc
+#define CYDEV_IO_PRT_PRT15_AG 0x400051fd
+#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe
+#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff
+#define CYDEV_PRTDSI_BASE 0x40005200
+#define CYDEV_PRTDSI_SIZE 0x0000007f
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200
+#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201
+#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202
+#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203
+#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204
+#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205
+#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208
+#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209
+#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a
+#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b
+#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c
+#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d
+#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210
+#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211
+#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212
+#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213
+#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214
+#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215
+#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218
+#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219
+#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a
+#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b
+#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c
+#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d
+#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220
+#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221
+#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222
+#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223
+#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224
+#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225
+#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228
+#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229
+#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a
+#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b
+#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c
+#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d
+#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230
+#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231
+#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232
+#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233
+#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234
+#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235
+#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006
+#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260
+#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261
+#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262
+#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263
+#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264
+#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007
+#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278
+#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279
+#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a
+#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b
+#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c
+#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d
+#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e
+#define CYDEV_EMIF_BASE 0x40005400
+#define CYDEV_EMIF_SIZE 0x00000007
+#define CYDEV_EMIF_NO_UDB 0x40005400
+#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401
+#define CYDEV_EMIF_MEM_DWN 0x40005402
+#define CYDEV_EMIF_MEMCLK_DIV 0x40005403
+#define CYDEV_EMIF_CLOCK_EN 0x40005404
+#define CYDEV_EMIF_EM_TYPE 0x40005405
+#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406
+#define CYDEV_ANAIF_BASE 0x40005800
+#define CYDEV_ANAIF_SIZE 0x000003a9
+#define CYDEV_ANAIF_CFG_BASE 0x40005800
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010f
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800
+#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801
+#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804
+#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805
+#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808
+#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809
+#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c
+#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d
+#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820
+#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821
+#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824
+#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825
+#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828
+#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829
+#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003
+#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c
+#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d
+#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848
+#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a
+#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c
+#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e
+#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858
+#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a
+#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c
+#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e
+#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868
+#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004
+#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c
+#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d
+#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e
+#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870
+#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872
+#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876
+#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878
+#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002
+#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a
+#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001
+#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020
+#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880
+#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881
+#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882
+#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883
+#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884
+#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885
+#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886
+#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887
+#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888
+#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889
+#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a
+#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b
+#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c
+#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d
+#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e
+#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f
+#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890
+#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891
+#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892
+#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893
+#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894
+#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895
+#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896
+#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897
+#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898
+#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899
+#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a
+#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b
+#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c
+#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d
+#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e
+#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007
+#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900
+#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901
+#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902
+#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903
+#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904
+#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905
+#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007
+#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908
+#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909
+#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a
+#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b
+#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c
+#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d
+#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e
+#define CYDEV_ANAIF_RT_BASE 0x40005a00
+#define CYDEV_ANAIF_RT_SIZE 0x00000162
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d
+#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00
+#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02
+#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03
+#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04
+#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06
+#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07
+#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08
+#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a
+#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b
+#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d
+#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10
+#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12
+#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13
+#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14
+#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16
+#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17
+#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18
+#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a
+#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b
+#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d
+#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20
+#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22
+#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23
+#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24
+#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26
+#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27
+#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28
+#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a
+#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b
+#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d
+#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30
+#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32
+#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33
+#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34
+#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36
+#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37
+#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38
+#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a
+#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b
+#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80
+#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82
+#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83
+#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84
+#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88
+#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a
+#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b
+#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c
+#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90
+#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92
+#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93
+#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94
+#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98
+#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a
+#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b
+#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c
+#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0
+#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2
+#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3
+#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4
+#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6
+#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8
+#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca
+#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb
+#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc
+#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace
+#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0
+#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2
+#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3
+#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4
+#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6
+#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8
+#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada
+#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb
+#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc
+#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade
+#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00
+#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02
+#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03
+#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04
+#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06
+#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20
+#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22
+#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23
+#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24
+#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26
+#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008
+#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28
+#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a
+#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b
+#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c
+#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e
+#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002
+#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40
+#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002
+#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42
+#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002
+#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44
+#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002
+#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46
+#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005
+#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50
+#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51
+#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52
+#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53
+#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001
+#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004
+#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58
+#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a
+#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006
+#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c
+#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d
+#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e
+#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f
+#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60
+#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001
+#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001
+#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001
+#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001
+#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002
+#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88
+#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005
+#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90
+#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91
+#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92
+#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93
+#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002
+#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96
+#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005
+#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98
+#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99
+#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a
+#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b
+#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002
+#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0
+#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002
+#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2
+#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001
+#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8
+#define CYDEV_USB_BASE 0x40006000
+#define CYDEV_USB_SIZE 0x00000300
+#define CYDEV_USB_EP0_DR0 0x40006000
+#define CYDEV_USB_EP0_DR1 0x40006001
+#define CYDEV_USB_EP0_DR2 0x40006002
+#define CYDEV_USB_EP0_DR3 0x40006003
+#define CYDEV_USB_EP0_DR4 0x40006004
+#define CYDEV_USB_EP0_DR5 0x40006005
+#define CYDEV_USB_EP0_DR6 0x40006006
+#define CYDEV_USB_EP0_DR7 0x40006007
+#define CYDEV_USB_CR0 0x40006008
+#define CYDEV_USB_CR1 0x40006009
+#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a
+#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600c
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c
+#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d
+#define CYDEV_USB_SIE_EP1_CR0 0x4000600e
+#define CYDEV_USB_USBIO_CR0 0x40006010
+#define CYDEV_USB_USBIO_CR1 0x40006012
+#define CYDEV_USB_DYN_RECONFIG 0x40006014
+#define CYDEV_USB_SOF0 0x40006018
+#define CYDEV_USB_SOF1 0x40006019
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601c
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c
+#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d
+#define CYDEV_USB_SIE_EP2_CR0 0x4000601e
+#define CYDEV_USB_EP0_CR 0x40006028
+#define CYDEV_USB_EP0_CNT 0x40006029
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602c
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c
+#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d
+#define CYDEV_USB_SIE_EP3_CR0 0x4000602e
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603c
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c
+#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d
+#define CYDEV_USB_SIE_EP4_CR0 0x4000603e
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604c
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c
+#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d
+#define CYDEV_USB_SIE_EP5_CR0 0x4000604e
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605c
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c
+#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d
+#define CYDEV_USB_SIE_EP6_CR0 0x4000605e
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606c
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c
+#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d
+#define CYDEV_USB_SIE_EP7_CR0 0x4000606e
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607c
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003
+#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c
+#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d
+#define CYDEV_USB_SIE_EP8_CR0 0x4000607e
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP1_CFG 0x40006080
+#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081
+#define CYDEV_USB_ARB_EP1_SR 0x40006082
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW1_WA 0x40006084
+#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085
+#define CYDEV_USB_ARB_RW1_RA 0x40006086
+#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087
+#define CYDEV_USB_ARB_RW1_DR 0x40006088
+#define CYDEV_USB_BUF_SIZE 0x4000608c
+#define CYDEV_USB_EP_ACTIVE 0x4000608e
+#define CYDEV_USB_EP_TYPE 0x4000608f
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP2_CFG 0x40006090
+#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091
+#define CYDEV_USB_ARB_EP2_SR 0x40006092
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW2_WA 0x40006094
+#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095
+#define CYDEV_USB_ARB_RW2_RA 0x40006096
+#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097
+#define CYDEV_USB_ARB_RW2_DR 0x40006098
+#define CYDEV_USB_ARB_CFG 0x4000609c
+#define CYDEV_USB_USB_CLK_EN 0x4000609d
+#define CYDEV_USB_ARB_INT_EN 0x4000609e
+#define CYDEV_USB_ARB_INT_SR 0x4000609f
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP3_CFG 0x400060a0
+#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1
+#define CYDEV_USB_ARB_EP3_SR 0x400060a2
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW3_WA 0x400060a4
+#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5
+#define CYDEV_USB_ARB_RW3_RA 0x400060a6
+#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7
+#define CYDEV_USB_ARB_RW3_DR 0x400060a8
+#define CYDEV_USB_CWA 0x400060ac
+#define CYDEV_USB_CWA_MSB 0x400060ad
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP4_CFG 0x400060b0
+#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1
+#define CYDEV_USB_ARB_EP4_SR 0x400060b2
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW4_WA 0x400060b4
+#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5
+#define CYDEV_USB_ARB_RW4_RA 0x400060b6
+#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7
+#define CYDEV_USB_ARB_RW4_DR 0x400060b8
+#define CYDEV_USB_DMA_THRES 0x400060bc
+#define CYDEV_USB_DMA_THRES_MSB 0x400060bd
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP5_CFG 0x400060c0
+#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1
+#define CYDEV_USB_ARB_EP5_SR 0x400060c2
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW5_WA 0x400060c4
+#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5
+#define CYDEV_USB_ARB_RW5_RA 0x400060c6
+#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7
+#define CYDEV_USB_ARB_RW5_DR 0x400060c8
+#define CYDEV_USB_BUS_RST_CNT 0x400060cc
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP6_CFG 0x400060d0
+#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1
+#define CYDEV_USB_ARB_EP6_SR 0x400060d2
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW6_WA 0x400060d4
+#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5
+#define CYDEV_USB_ARB_RW6_RA 0x400060d6
+#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7
+#define CYDEV_USB_ARB_RW6_DR 0x400060d8
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP7_CFG 0x400060e0
+#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1
+#define CYDEV_USB_ARB_EP7_SR 0x400060e2
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW7_WA 0x400060e4
+#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5
+#define CYDEV_USB_ARB_RW7_RA 0x400060e6
+#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7
+#define CYDEV_USB_ARB_RW7_DR 0x400060e8
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003
+#define CYDEV_USB_ARB_EP8_CFG 0x400060f0
+#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1
+#define CYDEV_USB_ARB_EP8_SR 0x400060f2
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005
+#define CYDEV_USB_ARB_RW8_WA 0x400060f4
+#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5
+#define CYDEV_USB_ARB_RW8_RA 0x400060f6
+#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7
+#define CYDEV_USB_ARB_RW8_DR 0x400060f8
+#define CYDEV_USB_MEM_BASE 0x40006100
+#define CYDEV_USB_MEM_SIZE 0x00000200
+#define CYDEV_USB_MEM_DATA_MBASE 0x40006100
+#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200
+#define CYDEV_UWRK_BASE 0x40006400
+#define CYDEV_UWRK_SIZE 0x00000b60
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470
+#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471
+#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472
+#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473
+#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474
+#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475
+#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476
+#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477
+#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478
+#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479
+#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574
+#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575
+#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576
+#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577
+#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578
+#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579
+#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56
+#define CYDEV_PHUB_BASE 0x40007000
+#define CYDEV_PHUB_SIZE 0x00000c00
+#define CYDEV_PHUB_CFG 0x40007000
+#define CYDEV_PHUB_ERR 0x40007004
+#define CYDEV_PHUB_ERR_ADR 0x40007008
+#define CYDEV_PHUB_CH0_BASE 0x40007010
+#define CYDEV_PHUB_CH0_SIZE 0x0000000c
+#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010
+#define CYDEV_PHUB_CH0_ACTION 0x40007014
+#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018
+#define CYDEV_PHUB_CH1_BASE 0x40007020
+#define CYDEV_PHUB_CH1_SIZE 0x0000000c
+#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020
+#define CYDEV_PHUB_CH1_ACTION 0x40007024
+#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028
+#define CYDEV_PHUB_CH2_BASE 0x40007030
+#define CYDEV_PHUB_CH2_SIZE 0x0000000c
+#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030
+#define CYDEV_PHUB_CH2_ACTION 0x40007034
+#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038
+#define CYDEV_PHUB_CH3_BASE 0x40007040
+#define CYDEV_PHUB_CH3_SIZE 0x0000000c
+#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040
+#define CYDEV_PHUB_CH3_ACTION 0x40007044
+#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048
+#define CYDEV_PHUB_CH4_BASE 0x40007050
+#define CYDEV_PHUB_CH4_SIZE 0x0000000c
+#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050
+#define CYDEV_PHUB_CH4_ACTION 0x40007054
+#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058
+#define CYDEV_PHUB_CH5_BASE 0x40007060
+#define CYDEV_PHUB_CH5_SIZE 0x0000000c
+#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060
+#define CYDEV_PHUB_CH5_ACTION 0x40007064
+#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068
+#define CYDEV_PHUB_CH6_BASE 0x40007070
+#define CYDEV_PHUB_CH6_SIZE 0x0000000c
+#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070
+#define CYDEV_PHUB_CH6_ACTION 0x40007074
+#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078
+#define CYDEV_PHUB_CH7_BASE 0x40007080
+#define CYDEV_PHUB_CH7_SIZE 0x0000000c
+#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080
+#define CYDEV_PHUB_CH7_ACTION 0x40007084
+#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088
+#define CYDEV_PHUB_CH8_BASE 0x40007090
+#define CYDEV_PHUB_CH8_SIZE 0x0000000c
+#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090
+#define CYDEV_PHUB_CH8_ACTION 0x40007094
+#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098
+#define CYDEV_PHUB_CH9_BASE 0x400070a0
+#define CYDEV_PHUB_CH9_SIZE 0x0000000c
+#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0
+#define CYDEV_PHUB_CH9_ACTION 0x400070a4
+#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8
+#define CYDEV_PHUB_CH10_BASE 0x400070b0
+#define CYDEV_PHUB_CH10_SIZE 0x0000000c
+#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0
+#define CYDEV_PHUB_CH10_ACTION 0x400070b4
+#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8
+#define CYDEV_PHUB_CH11_BASE 0x400070c0
+#define CYDEV_PHUB_CH11_SIZE 0x0000000c
+#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0
+#define CYDEV_PHUB_CH11_ACTION 0x400070c4
+#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8
+#define CYDEV_PHUB_CH12_BASE 0x400070d0
+#define CYDEV_PHUB_CH12_SIZE 0x0000000c
+#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0
+#define CYDEV_PHUB_CH12_ACTION 0x400070d4
+#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8
+#define CYDEV_PHUB_CH13_BASE 0x400070e0
+#define CYDEV_PHUB_CH13_SIZE 0x0000000c
+#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0
+#define CYDEV_PHUB_CH13_ACTION 0x400070e4
+#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8
+#define CYDEV_PHUB_CH14_BASE 0x400070f0
+#define CYDEV_PHUB_CH14_SIZE 0x0000000c
+#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0
+#define CYDEV_PHUB_CH14_ACTION 0x400070f4
+#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8
+#define CYDEV_PHUB_CH15_BASE 0x40007100
+#define CYDEV_PHUB_CH15_SIZE 0x0000000c
+#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100
+#define CYDEV_PHUB_CH15_ACTION 0x40007104
+#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108
+#define CYDEV_PHUB_CH16_BASE 0x40007110
+#define CYDEV_PHUB_CH16_SIZE 0x0000000c
+#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110
+#define CYDEV_PHUB_CH16_ACTION 0x40007114
+#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118
+#define CYDEV_PHUB_CH17_BASE 0x40007120
+#define CYDEV_PHUB_CH17_SIZE 0x0000000c
+#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120
+#define CYDEV_PHUB_CH17_ACTION 0x40007124
+#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128
+#define CYDEV_PHUB_CH18_BASE 0x40007130
+#define CYDEV_PHUB_CH18_SIZE 0x0000000c
+#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130
+#define CYDEV_PHUB_CH18_ACTION 0x40007134
+#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138
+#define CYDEV_PHUB_CH19_BASE 0x40007140
+#define CYDEV_PHUB_CH19_SIZE 0x0000000c
+#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140
+#define CYDEV_PHUB_CH19_ACTION 0x40007144
+#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148
+#define CYDEV_PHUB_CH20_BASE 0x40007150
+#define CYDEV_PHUB_CH20_SIZE 0x0000000c
+#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150
+#define CYDEV_PHUB_CH20_ACTION 0x40007154
+#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158
+#define CYDEV_PHUB_CH21_BASE 0x40007160
+#define CYDEV_PHUB_CH21_SIZE 0x0000000c
+#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160
+#define CYDEV_PHUB_CH21_ACTION 0x40007164
+#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168
+#define CYDEV_PHUB_CH22_BASE 0x40007170
+#define CYDEV_PHUB_CH22_SIZE 0x0000000c
+#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170
+#define CYDEV_PHUB_CH22_ACTION 0x40007174
+#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178
+#define CYDEV_PHUB_CH23_BASE 0x40007180
+#define CYDEV_PHUB_CH23_SIZE 0x0000000c
+#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180
+#define CYDEV_PHUB_CH23_ACTION 0x40007184
+#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600
+#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608
+#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610
+#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618
+#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620
+#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628
+#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630
+#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638
+#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640
+#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648
+#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650
+#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658
+#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660
+#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668
+#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670
+#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678
+#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680
+#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688
+#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690
+#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698
+#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0
+#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8
+#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0
+#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008
+#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8
+#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800
+#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808
+#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810
+#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818
+#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820
+#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828
+#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830
+#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838
+#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840
+#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848
+#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850
+#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858
+#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860
+#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868
+#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870
+#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878
+#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880
+#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888
+#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890
+#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898
+#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0
+#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8
+#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0
+#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8
+#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0
+#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8
+#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0
+#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8
+#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0
+#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8
+#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0
+#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8
+#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900
+#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908
+#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910
+#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918
+#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920
+#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928
+#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930
+#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938
+#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940
+#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948
+#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950
+#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958
+#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960
+#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968
+#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970
+#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978
+#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980
+#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988
+#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990
+#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998
+#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0
+#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8
+#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0
+#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8
+#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0
+#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8
+#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0
+#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8
+#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0
+#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8
+#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0
+#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8
+#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00
+#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08
+#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10
+#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18
+#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20
+#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28
+#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30
+#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38
+#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40
+#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48
+#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50
+#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58
+#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60
+#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68
+#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70
+#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78
+#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80
+#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88
+#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90
+#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98
+#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0
+#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8
+#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0
+#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8
+#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0
+#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8
+#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0
+#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8
+#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0
+#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8
+#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0
+#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8
+#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00
+#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08
+#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10
+#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18
+#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20
+#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28
+#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30
+#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38
+#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40
+#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48
+#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50
+#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58
+#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60
+#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68
+#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70
+#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78
+#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80
+#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88
+#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90
+#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98
+#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0
+#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8
+#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0
+#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8
+#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0
+#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8
+#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0
+#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8
+#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0
+#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8
+#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0
+#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008
+#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8
+#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc
+#define CYDEV_EE_BASE 0x40008000
+#define CYDEV_EE_SIZE 0x00000800
+#define CYDEV_EE_DATA_MBASE 0x40008000
+#define CYDEV_EE_DATA_MSIZE 0x00000800
+#define CYDEV_CAN0_BASE 0x4000a000
+#define CYDEV_CAN0_SIZE 0x000002a0
+#define CYDEV_CAN0_CSR_BASE 0x4000a000
+#define CYDEV_CAN0_CSR_SIZE 0x00000018
+#define CYDEV_CAN0_CSR_INT_SR 0x4000a000
+#define CYDEV_CAN0_CSR_INT_EN 0x4000a004
+#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008
+#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c
+#define CYDEV_CAN0_CSR_CMD 0x4000a010
+#define CYDEV_CAN0_CSR_CFG 0x4000a014
+#define CYDEV_CAN0_TX0_BASE 0x4000a020
+#define CYDEV_CAN0_TX0_SIZE 0x00000010
+#define CYDEV_CAN0_TX0_CMD 0x4000a020
+#define CYDEV_CAN0_TX0_ID 0x4000a024
+#define CYDEV_CAN0_TX0_DH 0x4000a028
+#define CYDEV_CAN0_TX0_DL 0x4000a02c
+#define CYDEV_CAN0_TX1_BASE 0x4000a030
+#define CYDEV_CAN0_TX1_SIZE 0x00000010
+#define CYDEV_CAN0_TX1_CMD 0x4000a030
+#define CYDEV_CAN0_TX1_ID 0x4000a034
+#define CYDEV_CAN0_TX1_DH 0x4000a038
+#define CYDEV_CAN0_TX1_DL 0x4000a03c
+#define CYDEV_CAN0_TX2_BASE 0x4000a040
+#define CYDEV_CAN0_TX2_SIZE 0x00000010
+#define CYDEV_CAN0_TX2_CMD 0x4000a040
+#define CYDEV_CAN0_TX2_ID 0x4000a044
+#define CYDEV_CAN0_TX2_DH 0x4000a048
+#define CYDEV_CAN0_TX2_DL 0x4000a04c
+#define CYDEV_CAN0_TX3_BASE 0x4000a050
+#define CYDEV_CAN0_TX3_SIZE 0x00000010
+#define CYDEV_CAN0_TX3_CMD 0x4000a050
+#define CYDEV_CAN0_TX3_ID 0x4000a054
+#define CYDEV_CAN0_TX3_DH 0x4000a058
+#define CYDEV_CAN0_TX3_DL 0x4000a05c
+#define CYDEV_CAN0_TX4_BASE 0x4000a060
+#define CYDEV_CAN0_TX4_SIZE 0x00000010
+#define CYDEV_CAN0_TX4_CMD 0x4000a060
+#define CYDEV_CAN0_TX4_ID 0x4000a064
+#define CYDEV_CAN0_TX4_DH 0x4000a068
+#define CYDEV_CAN0_TX4_DL 0x4000a06c
+#define CYDEV_CAN0_TX5_BASE 0x4000a070
+#define CYDEV_CAN0_TX5_SIZE 0x00000010
+#define CYDEV_CAN0_TX5_CMD 0x4000a070
+#define CYDEV_CAN0_TX5_ID 0x4000a074
+#define CYDEV_CAN0_TX5_DH 0x4000a078
+#define CYDEV_CAN0_TX5_DL 0x4000a07c
+#define CYDEV_CAN0_TX6_BASE 0x4000a080
+#define CYDEV_CAN0_TX6_SIZE 0x00000010
+#define CYDEV_CAN0_TX6_CMD 0x4000a080
+#define CYDEV_CAN0_TX6_ID 0x4000a084
+#define CYDEV_CAN0_TX6_DH 0x4000a088
+#define CYDEV_CAN0_TX6_DL 0x4000a08c
+#define CYDEV_CAN0_TX7_BASE 0x4000a090
+#define CYDEV_CAN0_TX7_SIZE 0x00000010
+#define CYDEV_CAN0_TX7_CMD 0x4000a090
+#define CYDEV_CAN0_TX7_ID 0x4000a094
+#define CYDEV_CAN0_TX7_DH 0x4000a098
+#define CYDEV_CAN0_TX7_DL 0x4000a09c
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0
+#define CYDEV_CAN0_RX0_SIZE 0x00000020
+#define CYDEV_CAN0_RX0_CMD 0x4000a0a0
+#define CYDEV_CAN0_RX0_ID 0x4000a0a4
+#define CYDEV_CAN0_RX0_DH 0x4000a0a8
+#define CYDEV_CAN0_RX0_DL 0x4000a0ac
+#define CYDEV_CAN0_RX0_AMR 0x4000a0b0
+#define CYDEV_CAN0_RX0_ACR 0x4000a0b4
+#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8
+#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0
+#define CYDEV_CAN0_RX1_SIZE 0x00000020
+#define CYDEV_CAN0_RX1_CMD 0x4000a0c0
+#define CYDEV_CAN0_RX1_ID 0x4000a0c4
+#define CYDEV_CAN0_RX1_DH 0x4000a0c8
+#define CYDEV_CAN0_RX1_DL 0x4000a0cc
+#define CYDEV_CAN0_RX1_AMR 0x4000a0d0
+#define CYDEV_CAN0_RX1_ACR 0x4000a0d4
+#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8
+#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0
+#define CYDEV_CAN0_RX2_SIZE 0x00000020
+#define CYDEV_CAN0_RX2_CMD 0x4000a0e0
+#define CYDEV_CAN0_RX2_ID 0x4000a0e4
+#define CYDEV_CAN0_RX2_DH 0x4000a0e8
+#define CYDEV_CAN0_RX2_DL 0x4000a0ec
+#define CYDEV_CAN0_RX2_AMR 0x4000a0f0
+#define CYDEV_CAN0_RX2_ACR 0x4000a0f4
+#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8
+#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc
+#define CYDEV_CAN0_RX3_BASE 0x4000a100
+#define CYDEV_CAN0_RX3_SIZE 0x00000020
+#define CYDEV_CAN0_RX3_CMD 0x4000a100
+#define CYDEV_CAN0_RX3_ID 0x4000a104
+#define CYDEV_CAN0_RX3_DH 0x4000a108
+#define CYDEV_CAN0_RX3_DL 0x4000a10c
+#define CYDEV_CAN0_RX3_AMR 0x4000a110
+#define CYDEV_CAN0_RX3_ACR 0x4000a114
+#define CYDEV_CAN0_RX3_AMRD 0x4000a118
+#define CYDEV_CAN0_RX3_ACRD 0x4000a11c
+#define CYDEV_CAN0_RX4_BASE 0x4000a120
+#define CYDEV_CAN0_RX4_SIZE 0x00000020
+#define CYDEV_CAN0_RX4_CMD 0x4000a120
+#define CYDEV_CAN0_RX4_ID 0x4000a124
+#define CYDEV_CAN0_RX4_DH 0x4000a128
+#define CYDEV_CAN0_RX4_DL 0x4000a12c
+#define CYDEV_CAN0_RX4_AMR 0x4000a130
+#define CYDEV_CAN0_RX4_ACR 0x4000a134
+#define CYDEV_CAN0_RX4_AMRD 0x4000a138
+#define CYDEV_CAN0_RX4_ACRD 0x4000a13c
+#define CYDEV_CAN0_RX5_BASE 0x4000a140
+#define CYDEV_CAN0_RX5_SIZE 0x00000020
+#define CYDEV_CAN0_RX5_CMD 0x4000a140
+#define CYDEV_CAN0_RX5_ID 0x4000a144
+#define CYDEV_CAN0_RX5_DH 0x4000a148
+#define CYDEV_CAN0_RX5_DL 0x4000a14c
+#define CYDEV_CAN0_RX5_AMR 0x4000a150
+#define CYDEV_CAN0_RX5_ACR 0x4000a154
+#define CYDEV_CAN0_RX5_AMRD 0x4000a158
+#define CYDEV_CAN0_RX5_ACRD 0x4000a15c
+#define CYDEV_CAN0_RX6_BASE 0x4000a160
+#define CYDEV_CAN0_RX6_SIZE 0x00000020
+#define CYDEV_CAN0_RX6_CMD 0x4000a160
+#define CYDEV_CAN0_RX6_ID 0x4000a164
+#define CYDEV_CAN0_RX6_DH 0x4000a168
+#define CYDEV_CAN0_RX6_DL 0x4000a16c
+#define CYDEV_CAN0_RX6_AMR 0x4000a170
+#define CYDEV_CAN0_RX6_ACR 0x4000a174
+#define CYDEV_CAN0_RX6_AMRD 0x4000a178
+#define CYDEV_CAN0_RX6_ACRD 0x4000a17c
+#define CYDEV_CAN0_RX7_BASE 0x4000a180
+#define CYDEV_CAN0_RX7_SIZE 0x00000020
+#define CYDEV_CAN0_RX7_CMD 0x4000a180
+#define CYDEV_CAN0_RX7_ID 0x4000a184
+#define CYDEV_CAN0_RX7_DH 0x4000a188
+#define CYDEV_CAN0_RX7_DL 0x4000a18c
+#define CYDEV_CAN0_RX7_AMR 0x4000a190
+#define CYDEV_CAN0_RX7_ACR 0x4000a194
+#define CYDEV_CAN0_RX7_AMRD 0x4000a198
+#define CYDEV_CAN0_RX7_ACRD 0x4000a19c
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0
+#define CYDEV_CAN0_RX8_SIZE 0x00000020
+#define CYDEV_CAN0_RX8_CMD 0x4000a1a0
+#define CYDEV_CAN0_RX8_ID 0x4000a1a4
+#define CYDEV_CAN0_RX8_DH 0x4000a1a8
+#define CYDEV_CAN0_RX8_DL 0x4000a1ac
+#define CYDEV_CAN0_RX8_AMR 0x4000a1b0
+#define CYDEV_CAN0_RX8_ACR 0x4000a1b4
+#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8
+#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0
+#define CYDEV_CAN0_RX9_SIZE 0x00000020
+#define CYDEV_CAN0_RX9_CMD 0x4000a1c0
+#define CYDEV_CAN0_RX9_ID 0x4000a1c4
+#define CYDEV_CAN0_RX9_DH 0x4000a1c8
+#define CYDEV_CAN0_RX9_DL 0x4000a1cc
+#define CYDEV_CAN0_RX9_AMR 0x4000a1d0
+#define CYDEV_CAN0_RX9_ACR 0x4000a1d4
+#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8
+#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0
+#define CYDEV_CAN0_RX10_SIZE 0x00000020
+#define CYDEV_CAN0_RX10_CMD 0x4000a1e0
+#define CYDEV_CAN0_RX10_ID 0x4000a1e4
+#define CYDEV_CAN0_RX10_DH 0x4000a1e8
+#define CYDEV_CAN0_RX10_DL 0x4000a1ec
+#define CYDEV_CAN0_RX10_AMR 0x4000a1f0
+#define CYDEV_CAN0_RX10_ACR 0x4000a1f4
+#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8
+#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc
+#define CYDEV_CAN0_RX11_BASE 0x4000a200
+#define CYDEV_CAN0_RX11_SIZE 0x00000020
+#define CYDEV_CAN0_RX11_CMD 0x4000a200
+#define CYDEV_CAN0_RX11_ID 0x4000a204
+#define CYDEV_CAN0_RX11_DH 0x4000a208
+#define CYDEV_CAN0_RX11_DL 0x4000a20c
+#define CYDEV_CAN0_RX11_AMR 0x4000a210
+#define CYDEV_CAN0_RX11_ACR 0x4000a214
+#define CYDEV_CAN0_RX11_AMRD 0x4000a218
+#define CYDEV_CAN0_RX11_ACRD 0x4000a21c
+#define CYDEV_CAN0_RX12_BASE 0x4000a220
+#define CYDEV_CAN0_RX12_SIZE 0x00000020
+#define CYDEV_CAN0_RX12_CMD 0x4000a220
+#define CYDEV_CAN0_RX12_ID 0x4000a224
+#define CYDEV_CAN0_RX12_DH 0x4000a228
+#define CYDEV_CAN0_RX12_DL 0x4000a22c
+#define CYDEV_CAN0_RX12_AMR 0x4000a230
+#define CYDEV_CAN0_RX12_ACR 0x4000a234
+#define CYDEV_CAN0_RX12_AMRD 0x4000a238
+#define CYDEV_CAN0_RX12_ACRD 0x4000a23c
+#define CYDEV_CAN0_RX13_BASE 0x4000a240
+#define CYDEV_CAN0_RX13_SIZE 0x00000020
+#define CYDEV_CAN0_RX13_CMD 0x4000a240
+#define CYDEV_CAN0_RX13_ID 0x4000a244
+#define CYDEV_CAN0_RX13_DH 0x4000a248
+#define CYDEV_CAN0_RX13_DL 0x4000a24c
+#define CYDEV_CAN0_RX13_AMR 0x4000a250
+#define CYDEV_CAN0_RX13_ACR 0x4000a254
+#define CYDEV_CAN0_RX13_AMRD 0x4000a258
+#define CYDEV_CAN0_RX13_ACRD 0x4000a25c
+#define CYDEV_CAN0_RX14_BASE 0x4000a260
+#define CYDEV_CAN0_RX14_SIZE 0x00000020
+#define CYDEV_CAN0_RX14_CMD 0x4000a260
+#define CYDEV_CAN0_RX14_ID 0x4000a264
+#define CYDEV_CAN0_RX14_DH 0x4000a268
+#define CYDEV_CAN0_RX14_DL 0x4000a26c
+#define CYDEV_CAN0_RX14_AMR 0x4000a270
+#define CYDEV_CAN0_RX14_ACR 0x4000a274
+#define CYDEV_CAN0_RX14_AMRD 0x4000a278
+#define CYDEV_CAN0_RX14_ACRD 0x4000a27c
+#define CYDEV_CAN0_RX15_BASE 0x4000a280
+#define CYDEV_CAN0_RX15_SIZE 0x00000020
+#define CYDEV_CAN0_RX15_CMD 0x4000a280
+#define CYDEV_CAN0_RX15_ID 0x4000a284
+#define CYDEV_CAN0_RX15_DH 0x4000a288
+#define CYDEV_CAN0_RX15_DL 0x4000a28c
+#define CYDEV_CAN0_RX15_AMR 0x4000a290
+#define CYDEV_CAN0_RX15_ACR 0x4000a294
+#define CYDEV_CAN0_RX15_AMRD 0x4000a298
+#define CYDEV_CAN0_RX15_ACRD 0x4000a29c
+#define CYDEV_DFB0_BASE 0x4000c000
+#define CYDEV_DFB0_SIZE 0x000007b5
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200
+#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000
+#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200
+#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200
+#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100
+#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400
+#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100
+#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500
+#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100
+#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600
+#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040
+#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700
+#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040
+#define CYDEV_DFB0_CR 0x4000c780
+#define CYDEV_DFB0_SR 0x4000c784
+#define CYDEV_DFB0_RAM_EN 0x4000c788
+#define CYDEV_DFB0_RAM_DIR 0x4000c78c
+#define CYDEV_DFB0_SEMA 0x4000c790
+#define CYDEV_DFB0_DSI_CTRL 0x4000c794
+#define CYDEV_DFB0_INT_CTRL 0x4000c798
+#define CYDEV_DFB0_DMA_CTRL 0x4000c79c
+#define CYDEV_DFB0_STAGEA 0x4000c7a0
+#define CYDEV_DFB0_STAGEAM 0x4000c7a1
+#define CYDEV_DFB0_STAGEAH 0x4000c7a2
+#define CYDEV_DFB0_STAGEB 0x4000c7a4
+#define CYDEV_DFB0_STAGEBM 0x4000c7a5
+#define CYDEV_DFB0_STAGEBH 0x4000c7a6
+#define CYDEV_DFB0_HOLDA 0x4000c7a8
+#define CYDEV_DFB0_HOLDAM 0x4000c7a9
+#define CYDEV_DFB0_HOLDAH 0x4000c7aa
+#define CYDEV_DFB0_HOLDAS 0x4000c7ab
+#define CYDEV_DFB0_HOLDB 0x4000c7ac
+#define CYDEV_DFB0_HOLDBM 0x4000c7ad
+#define CYDEV_DFB0_HOLDBH 0x4000c7ae
+#define CYDEV_DFB0_HOLDBS 0x4000c7af
+#define CYDEV_DFB0_COHER 0x4000c7b0
+#define CYDEV_DFB0_DALIGN 0x4000c7b4
+#define CYDEV_UCFG_BASE 0x40010000
+#define CYDEV_UCFG_SIZE 0x00005040
+#define CYDEV_UCFG_B0_BASE 0x40010000
+#define CYDEV_UCFG_B0_SIZE 0x00000fef
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e
+#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040
+#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041
+#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042
+#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043
+#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044
+#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045
+#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046
+#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047
+#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048
+#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049
+#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a
+#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b
+#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c
+#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d
+#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e
+#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f
+#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050
+#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051
+#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052
+#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053
+#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054
+#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055
+#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056
+#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057
+#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058
+#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059
+#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a
+#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b
+#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c
+#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d
+#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e
+#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f
+#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060
+#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062
+#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064
+#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066
+#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068
+#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a
+#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c
+#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be
+#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0
+#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1
+#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2
+#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3
+#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4
+#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5
+#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6
+#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7
+#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8
+#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9
+#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca
+#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb
+#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc
+#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd
+#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce
+#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf
+#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0
+#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1
+#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2
+#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3
+#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4
+#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5
+#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6
+#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7
+#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8
+#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9
+#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da
+#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db
+#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc
+#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd
+#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de
+#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df
+#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0
+#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2
+#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4
+#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6
+#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8
+#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea
+#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec
+#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e
+#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240
+#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241
+#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242
+#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243
+#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244
+#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245
+#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246
+#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247
+#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248
+#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249
+#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a
+#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b
+#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c
+#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d
+#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e
+#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f
+#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250
+#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251
+#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252
+#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253
+#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254
+#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255
+#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256
+#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257
+#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258
+#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259
+#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a
+#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b
+#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c
+#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d
+#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e
+#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f
+#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260
+#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262
+#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264
+#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266
+#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268
+#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a
+#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c
+#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be
+#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0
+#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1
+#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2
+#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3
+#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4
+#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5
+#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6
+#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7
+#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8
+#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9
+#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca
+#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb
+#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc
+#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd
+#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce
+#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf
+#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0
+#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1
+#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2
+#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3
+#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4
+#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5
+#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6
+#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7
+#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8
+#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9
+#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da
+#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db
+#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc
+#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd
+#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de
+#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df
+#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0
+#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2
+#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4
+#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6
+#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8
+#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea
+#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec
+#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e
+#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440
+#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441
+#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442
+#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443
+#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444
+#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445
+#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446
+#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447
+#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448
+#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449
+#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a
+#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b
+#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c
+#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d
+#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e
+#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f
+#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450
+#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451
+#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452
+#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453
+#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454
+#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455
+#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456
+#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457
+#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458
+#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459
+#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a
+#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b
+#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c
+#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d
+#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e
+#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f
+#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460
+#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462
+#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464
+#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466
+#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468
+#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a
+#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c
+#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be
+#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0
+#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1
+#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2
+#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3
+#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4
+#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5
+#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6
+#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7
+#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8
+#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9
+#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca
+#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb
+#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc
+#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd
+#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce
+#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf
+#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0
+#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1
+#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2
+#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3
+#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4
+#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5
+#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6
+#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7
+#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8
+#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9
+#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da
+#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db
+#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc
+#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd
+#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de
+#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df
+#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0
+#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2
+#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4
+#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6
+#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8
+#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea
+#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec
+#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e
+#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640
+#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641
+#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642
+#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643
+#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644
+#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645
+#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646
+#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647
+#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648
+#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649
+#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a
+#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b
+#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c
+#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d
+#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e
+#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f
+#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650
+#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651
+#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652
+#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653
+#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654
+#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655
+#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656
+#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657
+#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658
+#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659
+#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a
+#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b
+#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c
+#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d
+#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e
+#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f
+#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660
+#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662
+#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664
+#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666
+#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668
+#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a
+#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c
+#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be
+#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0
+#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1
+#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2
+#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3
+#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4
+#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5
+#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6
+#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7
+#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8
+#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9
+#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca
+#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb
+#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc
+#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd
+#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce
+#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf
+#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0
+#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1
+#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2
+#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3
+#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4
+#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5
+#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6
+#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7
+#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8
+#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9
+#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da
+#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db
+#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc
+#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd
+#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de
+#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df
+#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0
+#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2
+#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4
+#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6
+#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8
+#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea
+#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec
+#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e
+#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840
+#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841
+#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842
+#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843
+#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844
+#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845
+#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846
+#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847
+#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848
+#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849
+#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a
+#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b
+#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c
+#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d
+#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e
+#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f
+#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850
+#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851
+#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852
+#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853
+#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854
+#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855
+#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856
+#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857
+#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858
+#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859
+#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a
+#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b
+#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c
+#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d
+#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e
+#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f
+#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860
+#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862
+#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864
+#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866
+#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868
+#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a
+#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c
+#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be
+#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0
+#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1
+#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2
+#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3
+#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4
+#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5
+#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6
+#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7
+#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8
+#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9
+#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca
+#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb
+#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc
+#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd
+#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce
+#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf
+#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0
+#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1
+#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2
+#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3
+#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4
+#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5
+#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6
+#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7
+#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8
+#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9
+#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da
+#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db
+#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc
+#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd
+#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de
+#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df
+#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0
+#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2
+#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4
+#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6
+#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8
+#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea
+#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec
+#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e
+#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40
+#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41
+#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42
+#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43
+#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44
+#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45
+#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46
+#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47
+#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48
+#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49
+#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a
+#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b
+#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c
+#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d
+#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e
+#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f
+#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50
+#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51
+#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52
+#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53
+#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54
+#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55
+#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56
+#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57
+#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58
+#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59
+#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a
+#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b
+#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c
+#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d
+#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e
+#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f
+#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60
+#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62
+#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64
+#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66
+#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68
+#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a
+#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c
+#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe
+#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0
+#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1
+#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2
+#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3
+#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4
+#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5
+#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6
+#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7
+#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8
+#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9
+#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca
+#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb
+#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc
+#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd
+#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace
+#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf
+#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0
+#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1
+#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2
+#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3
+#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4
+#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5
+#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6
+#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7
+#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8
+#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9
+#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada
+#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb
+#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc
+#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add
+#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade
+#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf
+#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0
+#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2
+#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4
+#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6
+#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8
+#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea
+#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec
+#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e
+#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40
+#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41
+#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42
+#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43
+#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44
+#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45
+#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46
+#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47
+#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48
+#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49
+#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a
+#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b
+#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c
+#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d
+#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e
+#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f
+#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50
+#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51
+#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52
+#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53
+#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54
+#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55
+#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56
+#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57
+#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58
+#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59
+#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a
+#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b
+#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c
+#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d
+#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e
+#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f
+#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60
+#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62
+#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64
+#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66
+#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68
+#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a
+#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c
+#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe
+#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0
+#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1
+#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2
+#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3
+#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4
+#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5
+#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6
+#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7
+#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8
+#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9
+#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca
+#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb
+#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc
+#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd
+#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce
+#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf
+#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0
+#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1
+#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2
+#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3
+#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4
+#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5
+#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6
+#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7
+#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8
+#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9
+#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda
+#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb
+#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc
+#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd
+#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde
+#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf
+#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0
+#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2
+#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4
+#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6
+#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8
+#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea
+#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec
+#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e
+#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40
+#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41
+#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42
+#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43
+#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44
+#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45
+#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46
+#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47
+#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48
+#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49
+#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a
+#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b
+#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c
+#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d
+#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e
+#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f
+#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50
+#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51
+#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52
+#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53
+#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54
+#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55
+#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56
+#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57
+#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58
+#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59
+#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a
+#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b
+#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c
+#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d
+#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e
+#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f
+#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60
+#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62
+#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64
+#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66
+#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68
+#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a
+#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c
+#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe
+#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0
+#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1
+#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2
+#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3
+#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4
+#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5
+#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6
+#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7
+#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8
+#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9
+#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca
+#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb
+#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc
+#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd
+#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece
+#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf
+#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0
+#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1
+#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2
+#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3
+#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4
+#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5
+#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6
+#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7
+#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8
+#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9
+#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda
+#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb
+#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc
+#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd
+#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede
+#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf
+#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0
+#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2
+#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4
+#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6
+#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8
+#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea
+#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec
+#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_BASE 0x40011000
+#define CYDEV_UCFG_B1_SIZE 0x00000fef
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e
+#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440
+#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441
+#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442
+#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443
+#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444
+#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445
+#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446
+#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447
+#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448
+#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449
+#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a
+#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b
+#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c
+#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d
+#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e
+#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f
+#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450
+#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451
+#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452
+#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453
+#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454
+#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455
+#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456
+#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457
+#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458
+#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459
+#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a
+#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b
+#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c
+#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d
+#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e
+#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f
+#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460
+#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462
+#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464
+#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466
+#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468
+#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a
+#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c
+#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be
+#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0
+#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1
+#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2
+#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3
+#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4
+#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5
+#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6
+#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7
+#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8
+#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9
+#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca
+#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb
+#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc
+#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd
+#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce
+#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf
+#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0
+#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1
+#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2
+#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3
+#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4
+#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5
+#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6
+#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7
+#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8
+#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9
+#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da
+#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db
+#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc
+#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd
+#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de
+#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df
+#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0
+#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2
+#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4
+#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6
+#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8
+#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea
+#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec
+#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e
+#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640
+#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641
+#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642
+#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643
+#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644
+#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645
+#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646
+#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647
+#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648
+#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649
+#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a
+#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b
+#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c
+#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d
+#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e
+#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f
+#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650
+#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651
+#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652
+#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653
+#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654
+#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655
+#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656
+#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657
+#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658
+#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659
+#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a
+#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b
+#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c
+#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d
+#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e
+#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f
+#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660
+#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662
+#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664
+#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666
+#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668
+#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a
+#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c
+#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be
+#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0
+#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1
+#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2
+#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3
+#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4
+#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5
+#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6
+#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7
+#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8
+#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9
+#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca
+#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb
+#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc
+#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd
+#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce
+#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf
+#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0
+#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1
+#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2
+#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3
+#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4
+#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5
+#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6
+#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7
+#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8
+#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9
+#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da
+#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db
+#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc
+#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd
+#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de
+#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df
+#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0
+#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2
+#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4
+#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6
+#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8
+#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea
+#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec
+#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e
+#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840
+#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841
+#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842
+#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843
+#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844
+#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845
+#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846
+#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847
+#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848
+#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849
+#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a
+#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b
+#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c
+#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d
+#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e
+#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f
+#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850
+#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851
+#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852
+#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853
+#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854
+#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855
+#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856
+#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857
+#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858
+#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859
+#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a
+#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b
+#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c
+#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d
+#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e
+#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f
+#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860
+#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862
+#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864
+#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866
+#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868
+#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a
+#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c
+#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be
+#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0
+#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1
+#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2
+#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3
+#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4
+#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5
+#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6
+#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7
+#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8
+#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9
+#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca
+#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb
+#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc
+#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd
+#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce
+#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf
+#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0
+#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1
+#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2
+#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3
+#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4
+#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5
+#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6
+#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7
+#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8
+#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9
+#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da
+#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db
+#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc
+#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd
+#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de
+#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df
+#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0
+#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2
+#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4
+#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6
+#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8
+#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea
+#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec
+#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e
+#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40
+#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41
+#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42
+#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43
+#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44
+#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45
+#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46
+#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47
+#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48
+#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49
+#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a
+#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b
+#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c
+#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d
+#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e
+#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f
+#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50
+#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51
+#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52
+#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53
+#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54
+#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55
+#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56
+#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57
+#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58
+#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59
+#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a
+#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b
+#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c
+#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d
+#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e
+#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f
+#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60
+#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62
+#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64
+#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66
+#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68
+#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a
+#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c
+#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe
+#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0
+#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1
+#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2
+#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3
+#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4
+#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5
+#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6
+#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7
+#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8
+#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9
+#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca
+#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb
+#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc
+#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd
+#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace
+#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf
+#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0
+#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1
+#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2
+#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3
+#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4
+#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5
+#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6
+#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7
+#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8
+#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9
+#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada
+#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb
+#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc
+#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add
+#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade
+#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf
+#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0
+#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2
+#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4
+#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6
+#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8
+#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea
+#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec
+#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI0_BASE 0x40014000
+#define CYDEV_UCFG_DSI0_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI1_BASE 0x40014100
+#define CYDEV_UCFG_DSI1_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI2_BASE 0x40014200
+#define CYDEV_UCFG_DSI2_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI3_BASE 0x40014300
+#define CYDEV_UCFG_DSI3_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI4_BASE 0x40014400
+#define CYDEV_UCFG_DSI4_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI5_BASE 0x40014500
+#define CYDEV_UCFG_DSI5_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI6_BASE 0x40014600
+#define CYDEV_UCFG_DSI6_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI7_BASE 0x40014700
+#define CYDEV_UCFG_DSI7_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI8_BASE 0x40014800
+#define CYDEV_UCFG_DSI8_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI9_BASE 0x40014900
+#define CYDEV_UCFG_DSI9_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00
+#define CYDEV_UCFG_DSI12_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00
+#define CYDEV_UCFG_DSI13_SIZE 0x000000ef
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010
+#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000
+#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001
+#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002
+#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003
+#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007
+#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008
+#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009
+#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a
+#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b
+#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c
+#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d
+#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e
+#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010
+#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010
+#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011
+#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012
+#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013
+#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017
+#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018
+#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019
+#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a
+#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b
+#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c
+#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d
+#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e
+#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f
+#define CYDEV_IDMUX_BASE 0x40015100
+#define CYDEV_IDMUX_SIZE 0x00000016
+#define CYDEV_IDMUX_IRQ_CTL0 0x40015100
+#define CYDEV_IDMUX_IRQ_CTL1 0x40015101
+#define CYDEV_IDMUX_IRQ_CTL2 0x40015102
+#define CYDEV_IDMUX_IRQ_CTL3 0x40015103
+#define CYDEV_IDMUX_IRQ_CTL4 0x40015104
+#define CYDEV_IDMUX_IRQ_CTL5 0x40015105
+#define CYDEV_IDMUX_IRQ_CTL6 0x40015106
+#define CYDEV_IDMUX_IRQ_CTL7 0x40015107
+#define CYDEV_IDMUX_DRQ_CTL0 0x40015110
+#define CYDEV_IDMUX_DRQ_CTL1 0x40015111
+#define CYDEV_IDMUX_DRQ_CTL2 0x40015112
+#define CYDEV_IDMUX_DRQ_CTL3 0x40015113
+#define CYDEV_IDMUX_DRQ_CTL4 0x40015114
+#define CYDEV_IDMUX_DRQ_CTL5 0x40015115
+#define CYDEV_CACHERAM_BASE 0x40030000
+#define CYDEV_CACHERAM_SIZE 0x00000400
+#define CYDEV_CACHERAM_DATA_MBASE 0x40030000
+#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400
+#define CYDEV_SFR_BASE 0x40050100
+#define CYDEV_SFR_SIZE 0x000000fb
+#define CYDEV_SFR_GPIO0 0x40050180
+#define CYDEV_SFR_GPIRD0 0x40050189
+#define CYDEV_SFR_GPIO0_SEL 0x4005018a
+#define CYDEV_SFR_GPIO1 0x40050190
+#define CYDEV_SFR_GPIRD1 0x40050191
+#define CYDEV_SFR_GPIO2 0x40050198
+#define CYDEV_SFR_GPIRD2 0x40050199
+#define CYDEV_SFR_GPIO2_SEL 0x4005019a
+#define CYDEV_SFR_GPIO1_SEL 0x400501a2
+#define CYDEV_SFR_GPIO3 0x400501b0
+#define CYDEV_SFR_GPIRD3 0x400501b1
+#define CYDEV_SFR_GPIO3_SEL 0x400501b2
+#define CYDEV_SFR_GPIO4 0x400501c0
+#define CYDEV_SFR_GPIRD4 0x400501c1
+#define CYDEV_SFR_GPIO4_SEL 0x400501c2
+#define CYDEV_SFR_GPIO5 0x400501c8
+#define CYDEV_SFR_GPIRD5 0x400501c9
+#define CYDEV_SFR_GPIO5_SEL 0x400501ca
+#define CYDEV_SFR_GPIO6 0x400501d8
+#define CYDEV_SFR_GPIRD6 0x400501d9
+#define CYDEV_SFR_GPIO6_SEL 0x400501da
+#define CYDEV_SFR_GPIO12 0x400501e8
+#define CYDEV_SFR_GPIRD12 0x400501e9
+#define CYDEV_SFR_GPIO12_SEL 0x400501f2
+#define CYDEV_SFR_GPIO15 0x400501f8
+#define CYDEV_SFR_GPIRD15 0x400501f9
+#define CYDEV_SFR_GPIO15_SEL 0x400501fa
+#define CYDEV_P3BA_BASE 0x40050300
+#define CYDEV_P3BA_SIZE 0x0000002b
+#define CYDEV_P3BA_Y_START 0x40050300
+#define CYDEV_P3BA_YROLL 0x40050301
+#define CYDEV_P3BA_YCFG 0x40050302
+#define CYDEV_P3BA_X_START1 0x40050303
+#define CYDEV_P3BA_X_START2 0x40050304
+#define CYDEV_P3BA_XROLL1 0x40050305
+#define CYDEV_P3BA_XROLL2 0x40050306
+#define CYDEV_P3BA_XINC 0x40050307
+#define CYDEV_P3BA_XCFG 0x40050308
+#define CYDEV_P3BA_OFFSETADDR1 0x40050309
+#define CYDEV_P3BA_OFFSETADDR2 0x4005030a
+#define CYDEV_P3BA_OFFSETADDR3 0x4005030b
+#define CYDEV_P3BA_ABSADDR1 0x4005030c
+#define CYDEV_P3BA_ABSADDR2 0x4005030d
+#define CYDEV_P3BA_ABSADDR3 0x4005030e
+#define CYDEV_P3BA_ABSADDR4 0x4005030f
+#define CYDEV_P3BA_DATCFG1 0x40050310
+#define CYDEV_P3BA_DATCFG2 0x40050311
+#define CYDEV_P3BA_CMP_RSLT1 0x40050314
+#define CYDEV_P3BA_CMP_RSLT2 0x40050315
+#define CYDEV_P3BA_CMP_RSLT3 0x40050316
+#define CYDEV_P3BA_CMP_RSLT4 0x40050317
+#define CYDEV_P3BA_DATA_REG1 0x40050318
+#define CYDEV_P3BA_DATA_REG2 0x40050319
+#define CYDEV_P3BA_DATA_REG3 0x4005031a
+#define CYDEV_P3BA_DATA_REG4 0x4005031b
+#define CYDEV_P3BA_EXP_DATA1 0x4005031c
+#define CYDEV_P3BA_EXP_DATA2 0x4005031d
+#define CYDEV_P3BA_EXP_DATA3 0x4005031e
+#define CYDEV_P3BA_EXP_DATA4 0x4005031f
+#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320
+#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321
+#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322
+#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323
+#define CYDEV_P3BA_BIST_EN 0x40050324
+#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325
+#define CYDEV_P3BA_SEQCFG1 0x40050326
+#define CYDEV_P3BA_SEQCFG2 0x40050327
+#define CYDEV_P3BA_Y_CURR 0x40050328
+#define CYDEV_P3BA_X_CURR1 0x40050329
+#define CYDEV_P3BA_X_CURR2 0x4005032a
+#define CYDEV_PANTHER_BASE 0x40080000
+#define CYDEV_PANTHER_SIZE 0x00000020
+#define CYDEV_PANTHER_STCALIB_CFG 0x40080000
+#define CYDEV_PANTHER_WAITPIPE 0x40080004
+#define CYDEV_PANTHER_TRACE_CFG 0x40080008
+#define CYDEV_PANTHER_DBG_CFG 0x4008000c
+#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018
+#define CYDEV_PANTHER_DEVICE_ID 0x4008001c
+#define CYDEV_FLSECC_BASE 0x48000000
+#define CYDEV_FLSECC_SIZE 0x00008000
+#define CYDEV_FLSECC_DATA_MBASE 0x48000000
+#define CYDEV_FLSECC_DATA_MSIZE 0x00008000
+#define CYDEV_FLSHID_BASE 0x49000000
+#define CYDEV_FLSHID_SIZE 0x00000200
+#define CYDEV_FLSHID_RSVD_MBASE 0x49000000
+#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080
+#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080
+#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040
+#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100
+#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101
+#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102
+#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103
+#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104
+#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105
+#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106
+#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107
+#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108
+#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109
+#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a
+#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b
+#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c
+#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d
+#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e
+#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080
+#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba
+#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce
+#define CYDEV_EXTMEM_BASE 0x60000000
+#define CYDEV_EXTMEM_SIZE 0x00800000
+#define CYDEV_EXTMEM_DATA_MBASE 0x60000000
+#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000
+#define CYDEV_ITM_BASE 0xe0000000
+#define CYDEV_ITM_SIZE 0x00001000
+#define CYDEV_ITM_TRACE_EN 0xe0000e00
+#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40
+#define CYDEV_ITM_TRACE_CTRL 0xe0000e80
+#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0
+#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4
+#define CYDEV_ITM_PID4 0xe0000fd0
+#define CYDEV_ITM_PID5 0xe0000fd4
+#define CYDEV_ITM_PID6 0xe0000fd8
+#define CYDEV_ITM_PID7 0xe0000fdc
+#define CYDEV_ITM_PID0 0xe0000fe0
+#define CYDEV_ITM_PID1 0xe0000fe4
+#define CYDEV_ITM_PID2 0xe0000fe8
+#define CYDEV_ITM_PID3 0xe0000fec
+#define CYDEV_ITM_CID0 0xe0000ff0
+#define CYDEV_ITM_CID1 0xe0000ff4
+#define CYDEV_ITM_CID2 0xe0000ff8
+#define CYDEV_ITM_CID3 0xe0000ffc
+#define CYDEV_DWT_BASE 0xe0001000
+#define CYDEV_DWT_SIZE 0x0000005c
+#define CYDEV_DWT_CTRL 0xe0001000
+#define CYDEV_DWT_CYCLE_COUNT 0xe0001004
+#define CYDEV_DWT_CPI_COUNT 0xe0001008
+#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c
+#define CYDEV_DWT_SLEEP_COUNT 0xe0001010
+#define CYDEV_DWT_LSU_COUNT 0xe0001014
+#define CYDEV_DWT_FOLD_COUNT 0xe0001018
+#define CYDEV_DWT_PC_SAMPLE 0xe000101c
+#define CYDEV_DWT_COMP_0 0xe0001020
+#define CYDEV_DWT_MASK_0 0xe0001024
+#define CYDEV_DWT_FUNCTION_0 0xe0001028
+#define CYDEV_DWT_COMP_1 0xe0001030
+#define CYDEV_DWT_MASK_1 0xe0001034
+#define CYDEV_DWT_FUNCTION_1 0xe0001038
+#define CYDEV_DWT_COMP_2 0xe0001040
+#define CYDEV_DWT_MASK_2 0xe0001044
+#define CYDEV_DWT_FUNCTION_2 0xe0001048
+#define CYDEV_DWT_COMP_3 0xe0001050
+#define CYDEV_DWT_MASK_3 0xe0001054
+#define CYDEV_DWT_FUNCTION_3 0xe0001058
+#define CYDEV_FPB_BASE 0xe0002000
+#define CYDEV_FPB_SIZE 0x00001000
+#define CYDEV_FPB_CTRL 0xe0002000
+#define CYDEV_FPB_REMAP 0xe0002004
+#define CYDEV_FPB_FP_COMP_0 0xe0002008
+#define CYDEV_FPB_FP_COMP_1 0xe000200c
+#define CYDEV_FPB_FP_COMP_2 0xe0002010
+#define CYDEV_FPB_FP_COMP_3 0xe0002014
+#define CYDEV_FPB_FP_COMP_4 0xe0002018
+#define CYDEV_FPB_FP_COMP_5 0xe000201c
+#define CYDEV_FPB_FP_COMP_6 0xe0002020
+#define CYDEV_FPB_FP_COMP_7 0xe0002024
+#define CYDEV_FPB_PID4 0xe0002fd0
+#define CYDEV_FPB_PID5 0xe0002fd4
+#define CYDEV_FPB_PID6 0xe0002fd8
+#define CYDEV_FPB_PID7 0xe0002fdc
+#define CYDEV_FPB_PID0 0xe0002fe0
+#define CYDEV_FPB_PID1 0xe0002fe4
+#define CYDEV_FPB_PID2 0xe0002fe8
+#define CYDEV_FPB_PID3 0xe0002fec
+#define CYDEV_FPB_CID0 0xe0002ff0
+#define CYDEV_FPB_CID1 0xe0002ff4
+#define CYDEV_FPB_CID2 0xe0002ff8
+#define CYDEV_FPB_CID3 0xe0002ffc
+#define CYDEV_NVIC_BASE 0xe000e000
+#define CYDEV_NVIC_SIZE 0x00000d3c
+#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004
+#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010
+#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014
+#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018
+#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c
+#define CYDEV_NVIC_SETENA0 0xe000e100
+#define CYDEV_NVIC_CLRENA0 0xe000e180
+#define CYDEV_NVIC_SETPEND0 0xe000e200
+#define CYDEV_NVIC_CLRPEND0 0xe000e280
+#define CYDEV_NVIC_ACTIVE0 0xe000e300
+#define CYDEV_NVIC_PRI_0 0xe000e400
+#define CYDEV_NVIC_PRI_1 0xe000e401
+#define CYDEV_NVIC_PRI_2 0xe000e402
+#define CYDEV_NVIC_PRI_3 0xe000e403
+#define CYDEV_NVIC_PRI_4 0xe000e404
+#define CYDEV_NVIC_PRI_5 0xe000e405
+#define CYDEV_NVIC_PRI_6 0xe000e406
+#define CYDEV_NVIC_PRI_7 0xe000e407
+#define CYDEV_NVIC_PRI_8 0xe000e408
+#define CYDEV_NVIC_PRI_9 0xe000e409
+#define CYDEV_NVIC_PRI_10 0xe000e40a
+#define CYDEV_NVIC_PRI_11 0xe000e40b
+#define CYDEV_NVIC_PRI_12 0xe000e40c
+#define CYDEV_NVIC_PRI_13 0xe000e40d
+#define CYDEV_NVIC_PRI_14 0xe000e40e
+#define CYDEV_NVIC_PRI_15 0xe000e40f
+#define CYDEV_NVIC_PRI_16 0xe000e410
+#define CYDEV_NVIC_PRI_17 0xe000e411
+#define CYDEV_NVIC_PRI_18 0xe000e412
+#define CYDEV_NVIC_PRI_19 0xe000e413
+#define CYDEV_NVIC_PRI_20 0xe000e414
+#define CYDEV_NVIC_PRI_21 0xe000e415
+#define CYDEV_NVIC_PRI_22 0xe000e416
+#define CYDEV_NVIC_PRI_23 0xe000e417
+#define CYDEV_NVIC_PRI_24 0xe000e418
+#define CYDEV_NVIC_PRI_25 0xe000e419
+#define CYDEV_NVIC_PRI_26 0xe000e41a
+#define CYDEV_NVIC_PRI_27 0xe000e41b
+#define CYDEV_NVIC_PRI_28 0xe000e41c
+#define CYDEV_NVIC_PRI_29 0xe000e41d
+#define CYDEV_NVIC_PRI_30 0xe000e41e
+#define CYDEV_NVIC_PRI_31 0xe000e41f
+#define CYDEV_NVIC_CPUID_BASE 0xe000ed00
+#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04
+#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08
+#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c
+#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10
+#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20
+#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24
+#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28
+#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29
+#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a
+#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c
+#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30
+#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34
+#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38
+#define CYDEV_CORE_DBG_BASE 0xe000edf0
+#define CYDEV_CORE_DBG_SIZE 0x00000010
+#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0
+#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4
+#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8
+#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc
+#define CYDEV_TPIU_BASE 0xe0040000
+#define CYDEV_TPIU_SIZE 0x00001000
+#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000
+#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004
+#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010
+#define CYDEV_TPIU_PROTOCOL 0xe00400f0
+#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300
+#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304
+#define CYDEV_TPIU_TRIGGER 0xe0040ee8
+#define CYDEV_TPIU_ITETMDATA 0xe0040eec
+#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0
+#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8
+#define CYDEV_TPIU_ITITMDATA 0xe0040efc
+#define CYDEV_TPIU_ITCTRL 0xe0040f00
+#define CYDEV_TPIU_DEVID 0xe0040fc8
+#define CYDEV_TPIU_DEVTYPE 0xe0040fcc
+#define CYDEV_TPIU_PID4 0xe0040fd0
+#define CYDEV_TPIU_PID5 0xe0040fd4
+#define CYDEV_TPIU_PID6 0xe0040fd8
+#define CYDEV_TPIU_PID7 0xe0040fdc
+#define CYDEV_TPIU_PID0 0xe0040fe0
+#define CYDEV_TPIU_PID1 0xe0040fe4
+#define CYDEV_TPIU_PID2 0xe0040fe8
+#define CYDEV_TPIU_PID3 0xe0040fec
+#define CYDEV_TPIU_CID0 0xe0040ff0
+#define CYDEV_TPIU_CID1 0xe0040ff4
+#define CYDEV_TPIU_CID2 0xe0040ff8
+#define CYDEV_TPIU_CID3 0xe0040ffc
+#define CYDEV_ETM_BASE 0xe0041000
+#define CYDEV_ETM_SIZE 0x00001000
+#define CYDEV_ETM_CTL 0xe0041000
+#define CYDEV_ETM_CFG_CODE 0xe0041004
+#define CYDEV_ETM_TRIG_EVENT 0xe0041008
+#define CYDEV_ETM_STATUS 0xe0041010
+#define CYDEV_ETM_SYS_CFG 0xe0041014
+#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020
+#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024
+#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c
+#define CYDEV_ETM_SYNC_FREQ 0xe00411e0
+#define CYDEV_ETM_ETM_ID 0xe00411e4
+#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8
+#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0
+#define CYDEV_ETM_CS_TRACE_ID 0xe0041200
+#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300
+#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304
+#define CYDEV_ETM_PDSR 0xe0041314
+#define CYDEV_ETM_ITMISCIN 0xe0041ee0
+#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8
+#define CYDEV_ETM_ITATBCTR2 0xe0041ef0
+#define CYDEV_ETM_ITATBCTR0 0xe0041ef8
+#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00
+#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0
+#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4
+#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0
+#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4
+#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8
+#define CYDEV_ETM_DEV_TYPE 0xe0041fcc
+#define CYDEV_ETM_PID4 0xe0041fd0
+#define CYDEV_ETM_PID5 0xe0041fd4
+#define CYDEV_ETM_PID6 0xe0041fd8
+#define CYDEV_ETM_PID7 0xe0041fdc
+#define CYDEV_ETM_PID0 0xe0041fe0
+#define CYDEV_ETM_PID1 0xe0041fe4
+#define CYDEV_ETM_PID2 0xe0041fe8
+#define CYDEV_ETM_PID3 0xe0041fec
+#define CYDEV_ETM_CID0 0xe0041ff0
+#define CYDEV_ETM_CID1 0xe0041ff4
+#define CYDEV_ETM_CID2 0xe0041ff8
+#define CYDEV_ETM_CID3 0xe0041ffc
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000
+#define CYDEV_ROM_TABLE_SIZE 0x00001000
+#define CYDEV_ROM_TABLE_NVIC 0xe00ff000
+#define CYDEV_ROM_TABLE_DWT 0xe00ff004
+#define CYDEV_ROM_TABLE_FPB 0xe00ff008
+#define CYDEV_ROM_TABLE_ITM 0xe00ff00c
+#define CYDEV_ROM_TABLE_TPIU 0xe00ff010
+#define CYDEV_ROM_TABLE_ETM 0xe00ff014
+#define CYDEV_ROM_TABLE_END 0xe00ff018
+#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc
+#define CYDEV_ROM_TABLE_PID4 0xe00fffd0
+#define CYDEV_ROM_TABLE_PID5 0xe00fffd4
+#define CYDEV_ROM_TABLE_PID6 0xe00fffd8
+#define CYDEV_ROM_TABLE_PID7 0xe00fffdc
+#define CYDEV_ROM_TABLE_PID0 0xe00fffe0
+#define CYDEV_ROM_TABLE_PID1 0xe00fffe4
+#define CYDEV_ROM_TABLE_PID2 0xe00fffe8
+#define CYDEV_ROM_TABLE_PID3 0xe00fffec
+#define CYDEV_ROM_TABLE_CID0 0xe00ffff0
+#define CYDEV_ROM_TABLE_CID1 0xe00ffff4
+#define CYDEV_ROM_TABLE_CID2 0xe00ffff8
+#define CYDEV_ROM_TABLE_CID3 0xe00ffffc
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000
+#define CYDEV_FLS_ROW_SIZE 0x00000100
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000
+#define CYDEV_ECC_ROW_SIZE 0x00000020
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE
+#define CYCLK_LD_DISABLE 0x00000004
+#define CYCLK_LD_SYNC_EN 0x00000002
+#define CYCLK_LD_LOAD 0x00000001
+#define CYCLK_PIPE 0x00000080
+#define CYCLK_SSS 0x00000040
+#define CYCLK_EARLY 0x00000020
+#define CYCLK_DUTY 0x00000010
+#define CYCLK_SYNC 0x00000008
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0
+#define CYCLK_SRC_SEL_SYNC_DIG 0
+#define CYCLK_SRC_SEL_IMO 1
+#define CYCLK_SRC_SEL_XTAL_MHZ 2
+#define CYCLK_SRC_SEL_XTALM 2
+#define CYCLK_SRC_SEL_ILO 3
+#define CYCLK_SRC_SEL_PLL 4
+#define CYCLK_SRC_SEL_XTAL_KHZ 5
+#define CYCLK_SRC_SEL_XTALK 5
+#define CYCLK_SRC_SEL_DSI_G 6
+#define CYCLK_SRC_SEL_DSI_D 7
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0
+#define CYCLK_SRC_SEL_DSI_A 7

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc

@@ -0,0 +1,5356 @@
+;
+; FILENAME: cydeviceiar_trm.inc
+; 
+; PSoC Creator 3.0
+;
+; DESCRIPTION:
+; This file provides all of the address values for the entire PSoC device.
+;
+;-------------------------------------------------------------------------------
+; Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; You may use this file only in accordance with the license, terms, conditions, 
+; disclaimers, and limitations in the end user license agreement accompanying 
+; the software package with which this file was provided.
+;-------------------------------------------------------------------------------
+
+#define CYDEV_FLASH_BASE 0x00000000
+#define CYDEV_FLASH_SIZE 0x00040000
+#define CYREG_FLASH_DATA_MBASE 0x00000000
+#define CYREG_FLASH_DATA_MSIZE 0x00040000
+#define CYDEV_SRAM_BASE 0x1fff8000
+#define CYDEV_SRAM_SIZE 0x00010000
+#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000
+#define CYREG_SRAM_CODE64K_MSIZE 0x00004000
+#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000
+#define CYREG_SRAM_CODE32K_MSIZE 0x00002000
+#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000
+#define CYREG_SRAM_CODE16K_MSIZE 0x00001000
+#define CYREG_SRAM_CODE_MBASE 0x1fff8000
+#define CYREG_SRAM_CODE_MSIZE 0x00008000
+#define CYREG_SRAM_DATA_MBASE 0x20000000
+#define CYREG_SRAM_DATA_MSIZE 0x00008000
+#define CYREG_SRAM_DATA16K_MBASE 0x20001000
+#define CYREG_SRAM_DATA16K_MSIZE 0x00001000
+#define CYREG_SRAM_DATA32K_MBASE 0x20002000
+#define CYREG_SRAM_DATA32K_MSIZE 0x00002000
+#define CYREG_SRAM_DATA64K_MBASE 0x20004000
+#define CYREG_SRAM_DATA64K_MSIZE 0x00004000
+#define CYDEV_DMA_BASE 0x20008000
+#define CYDEV_DMA_SIZE 0x00008000
+#define CYREG_DMA_SRAM64K_MBASE 0x20008000
+#define CYREG_DMA_SRAM64K_MSIZE 0x00004000
+#define CYREG_DMA_SRAM32K_MBASE 0x2000c000
+#define CYREG_DMA_SRAM32K_MSIZE 0x00002000
+#define CYREG_DMA_SRAM16K_MBASE 0x2000e000
+#define CYREG_DMA_SRAM16K_MSIZE 0x00001000
+#define CYREG_DMA_SRAM_MBASE 0x2000f000
+#define CYREG_DMA_SRAM_MSIZE 0x00001000
+#define CYDEV_CLKDIST_BASE 0x40004000
+#define CYDEV_CLKDIST_SIZE 0x00000110
+#define CYREG_CLKDIST_CR 0x40004000
+#define CYREG_CLKDIST_LD 0x40004001
+#define CYREG_CLKDIST_WRK0 0x40004002
+#define CYREG_CLKDIST_WRK1 0x40004003
+#define CYREG_CLKDIST_MSTR0 0x40004004
+#define CYREG_CLKDIST_MSTR1 0x40004005
+#define CYREG_CLKDIST_BCFG0 0x40004006
+#define CYREG_CLKDIST_BCFG1 0x40004007
+#define CYREG_CLKDIST_BCFG2 0x40004008
+#define CYREG_CLKDIST_UCFG 0x40004009
+#define CYREG_CLKDIST_DLY0 0x4000400a
+#define CYREG_CLKDIST_DLY1 0x4000400b
+#define CYREG_CLKDIST_DMASK 0x40004010
+#define CYREG_CLKDIST_AMASK 0x40004014
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080
+#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081
+#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084
+#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085
+#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088
+#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089
+#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c
+#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d
+#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090
+#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091
+#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094
+#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095
+#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098
+#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099
+#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003
+#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c
+#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d
+#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004
+#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100
+#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101
+#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102
+#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004
+#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104
+#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105
+#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106
+#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004
+#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108
+#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109
+#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a
+#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004
+#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c
+#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d
+#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e
+#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f
+#define CYDEV_FASTCLK_BASE 0x40004200
+#define CYDEV_FASTCLK_SIZE 0x00000026
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001
+#define CYREG_FASTCLK_IMO_CR 0x40004200
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004
+#define CYREG_FASTCLK_XMHZ_CSR 0x40004210
+#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212
+#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006
+#define CYREG_FASTCLK_PLL_CFG0 0x40004220
+#define CYREG_FASTCLK_PLL_CFG1 0x40004221
+#define CYREG_FASTCLK_PLL_P 0x40004222
+#define CYREG_FASTCLK_PLL_Q 0x40004223
+#define CYREG_FASTCLK_PLL_SR 0x40004225
+#define CYDEV_SLOWCLK_BASE 0x40004300
+#define CYDEV_SLOWCLK_SIZE 0x0000000b
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002
+#define CYREG_SLOWCLK_ILO_CR0 0x40004300
+#define CYREG_SLOWCLK_ILO_CR1 0x40004301
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003
+#define CYREG_SLOWCLK_X32_CR 0x40004308
+#define CYREG_SLOWCLK_X32_CFG 0x40004309
+#define CYREG_SLOWCLK_X32_TST 0x4000430a
+#define CYDEV_BOOST_BASE 0x40004320
+#define CYDEV_BOOST_SIZE 0x00000007
+#define CYREG_BOOST_CR0 0x40004320
+#define CYREG_BOOST_CR1 0x40004321
+#define CYREG_BOOST_CR2 0x40004322
+#define CYREG_BOOST_CR3 0x40004323
+#define CYREG_BOOST_SR 0x40004324
+#define CYREG_BOOST_CR4 0x40004325
+#define CYREG_BOOST_SR2 0x40004326
+#define CYDEV_PWRSYS_BASE 0x40004330
+#define CYDEV_PWRSYS_SIZE 0x00000002
+#define CYREG_PWRSYS_CR0 0x40004330
+#define CYREG_PWRSYS_CR1 0x40004331
+#define CYDEV_PM_BASE 0x40004380
+#define CYDEV_PM_SIZE 0x00000057
+#define CYREG_PM_TW_CFG0 0x40004380
+#define CYREG_PM_TW_CFG1 0x40004381
+#define CYREG_PM_TW_CFG2 0x40004382
+#define CYREG_PM_WDT_CFG 0x40004383
+#define CYREG_PM_WDT_CR 0x40004384
+#define CYREG_PM_INT_SR 0x40004390
+#define CYREG_PM_MODE_CFG0 0x40004391
+#define CYREG_PM_MODE_CFG1 0x40004392
+#define CYREG_PM_MODE_CSR 0x40004393
+#define CYREG_PM_USB_CR0 0x40004394
+#define CYREG_PM_WAKEUP_CFG0 0x40004398
+#define CYREG_PM_WAKEUP_CFG1 0x40004399
+#define CYREG_PM_WAKEUP_CFG2 0x4000439a
+#define CYDEV_PM_ACT_BASE 0x400043a0
+#define CYDEV_PM_ACT_SIZE 0x0000000e
+#define CYREG_PM_ACT_CFG0 0x400043a0
+#define CYREG_PM_ACT_CFG1 0x400043a1
+#define CYREG_PM_ACT_CFG2 0x400043a2
+#define CYREG_PM_ACT_CFG3 0x400043a3
+#define CYREG_PM_ACT_CFG4 0x400043a4
+#define CYREG_PM_ACT_CFG5 0x400043a5
+#define CYREG_PM_ACT_CFG6 0x400043a6
+#define CYREG_PM_ACT_CFG7 0x400043a7
+#define CYREG_PM_ACT_CFG8 0x400043a8
+#define CYREG_PM_ACT_CFG9 0x400043a9
+#define CYREG_PM_ACT_CFG10 0x400043aa
+#define CYREG_PM_ACT_CFG11 0x400043ab
+#define CYREG_PM_ACT_CFG12 0x400043ac
+#define CYREG_PM_ACT_CFG13 0x400043ad
+#define CYDEV_PM_STBY_BASE 0x400043b0
+#define CYDEV_PM_STBY_SIZE 0x0000000e
+#define CYREG_PM_STBY_CFG0 0x400043b0
+#define CYREG_PM_STBY_CFG1 0x400043b1
+#define CYREG_PM_STBY_CFG2 0x400043b2
+#define CYREG_PM_STBY_CFG3 0x400043b3
+#define CYREG_PM_STBY_CFG4 0x400043b4
+#define CYREG_PM_STBY_CFG5 0x400043b5
+#define CYREG_PM_STBY_CFG6 0x400043b6
+#define CYREG_PM_STBY_CFG7 0x400043b7
+#define CYREG_PM_STBY_CFG8 0x400043b8
+#define CYREG_PM_STBY_CFG9 0x400043b9
+#define CYREG_PM_STBY_CFG10 0x400043ba
+#define CYREG_PM_STBY_CFG11 0x400043bb
+#define CYREG_PM_STBY_CFG12 0x400043bc
+#define CYREG_PM_STBY_CFG13 0x400043bd
+#define CYDEV_PM_AVAIL_BASE 0x400043c0
+#define CYDEV_PM_AVAIL_SIZE 0x00000017
+#define CYREG_PM_AVAIL_CR0 0x400043c0
+#define CYREG_PM_AVAIL_CR1 0x400043c1
+#define CYREG_PM_AVAIL_CR2 0x400043c2
+#define CYREG_PM_AVAIL_CR3 0x400043c3
+#define CYREG_PM_AVAIL_CR4 0x400043c4
+#define CYREG_PM_AVAIL_CR5 0x400043c5
+#define CYREG_PM_AVAIL_CR6 0x400043c6
+#define CYREG_PM_AVAIL_SR0 0x400043d0
+#define CYREG_PM_AVAIL_SR1 0x400043d1
+#define CYREG_PM_AVAIL_SR2 0x400043d2
+#define CYREG_PM_AVAIL_SR3 0x400043d3
+#define CYREG_PM_AVAIL_SR4 0x400043d4
+#define CYREG_PM_AVAIL_SR5 0x400043d5
+#define CYREG_PM_AVAIL_SR6 0x400043d6
+#define CYDEV_PICU_BASE 0x40004500
+#define CYDEV_PICU_SIZE 0x000000b0
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008
+#define CYREG_PICU0_INTTYPE0 0x40004500
+#define CYREG_PICU0_INTTYPE1 0x40004501
+#define CYREG_PICU0_INTTYPE2 0x40004502
+#define CYREG_PICU0_INTTYPE3 0x40004503
+#define CYREG_PICU0_INTTYPE4 0x40004504
+#define CYREG_PICU0_INTTYPE5 0x40004505
+#define CYREG_PICU0_INTTYPE6 0x40004506
+#define CYREG_PICU0_INTTYPE7 0x40004507
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008
+#define CYREG_PICU1_INTTYPE0 0x40004508
+#define CYREG_PICU1_INTTYPE1 0x40004509
+#define CYREG_PICU1_INTTYPE2 0x4000450a
+#define CYREG_PICU1_INTTYPE3 0x4000450b
+#define CYREG_PICU1_INTTYPE4 0x4000450c
+#define CYREG_PICU1_INTTYPE5 0x4000450d
+#define CYREG_PICU1_INTTYPE6 0x4000450e
+#define CYREG_PICU1_INTTYPE7 0x4000450f
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008
+#define CYREG_PICU2_INTTYPE0 0x40004510
+#define CYREG_PICU2_INTTYPE1 0x40004511
+#define CYREG_PICU2_INTTYPE2 0x40004512
+#define CYREG_PICU2_INTTYPE3 0x40004513
+#define CYREG_PICU2_INTTYPE4 0x40004514
+#define CYREG_PICU2_INTTYPE5 0x40004515
+#define CYREG_PICU2_INTTYPE6 0x40004516
+#define CYREG_PICU2_INTTYPE7 0x40004517
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008
+#define CYREG_PICU3_INTTYPE0 0x40004518
+#define CYREG_PICU3_INTTYPE1 0x40004519
+#define CYREG_PICU3_INTTYPE2 0x4000451a
+#define CYREG_PICU3_INTTYPE3 0x4000451b
+#define CYREG_PICU3_INTTYPE4 0x4000451c
+#define CYREG_PICU3_INTTYPE5 0x4000451d
+#define CYREG_PICU3_INTTYPE6 0x4000451e
+#define CYREG_PICU3_INTTYPE7 0x4000451f
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008
+#define CYREG_PICU4_INTTYPE0 0x40004520
+#define CYREG_PICU4_INTTYPE1 0x40004521
+#define CYREG_PICU4_INTTYPE2 0x40004522
+#define CYREG_PICU4_INTTYPE3 0x40004523
+#define CYREG_PICU4_INTTYPE4 0x40004524
+#define CYREG_PICU4_INTTYPE5 0x40004525
+#define CYREG_PICU4_INTTYPE6 0x40004526
+#define CYREG_PICU4_INTTYPE7 0x40004527
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008
+#define CYREG_PICU5_INTTYPE0 0x40004528
+#define CYREG_PICU5_INTTYPE1 0x40004529
+#define CYREG_PICU5_INTTYPE2 0x4000452a
+#define CYREG_PICU5_INTTYPE3 0x4000452b
+#define CYREG_PICU5_INTTYPE4 0x4000452c
+#define CYREG_PICU5_INTTYPE5 0x4000452d
+#define CYREG_PICU5_INTTYPE6 0x4000452e
+#define CYREG_PICU5_INTTYPE7 0x4000452f
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008
+#define CYREG_PICU6_INTTYPE0 0x40004530
+#define CYREG_PICU6_INTTYPE1 0x40004531
+#define CYREG_PICU6_INTTYPE2 0x40004532
+#define CYREG_PICU6_INTTYPE3 0x40004533
+#define CYREG_PICU6_INTTYPE4 0x40004534
+#define CYREG_PICU6_INTTYPE5 0x40004535
+#define CYREG_PICU6_INTTYPE6 0x40004536
+#define CYREG_PICU6_INTTYPE7 0x40004537
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008
+#define CYREG_PICU12_INTTYPE0 0x40004560
+#define CYREG_PICU12_INTTYPE1 0x40004561
+#define CYREG_PICU12_INTTYPE2 0x40004562
+#define CYREG_PICU12_INTTYPE3 0x40004563
+#define CYREG_PICU12_INTTYPE4 0x40004564
+#define CYREG_PICU12_INTTYPE5 0x40004565
+#define CYREG_PICU12_INTTYPE6 0x40004566
+#define CYREG_PICU12_INTTYPE7 0x40004567
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008
+#define CYREG_PICU15_INTTYPE0 0x40004578
+#define CYREG_PICU15_INTTYPE1 0x40004579
+#define CYREG_PICU15_INTTYPE2 0x4000457a
+#define CYREG_PICU15_INTTYPE3 0x4000457b
+#define CYREG_PICU15_INTTYPE4 0x4000457c
+#define CYREG_PICU15_INTTYPE5 0x4000457d
+#define CYREG_PICU15_INTTYPE6 0x4000457e
+#define CYREG_PICU15_INTTYPE7 0x4000457f
+#define CYDEV_PICU_STAT_BASE 0x40004580
+#define CYDEV_PICU_STAT_SIZE 0x00000010
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001
+#define CYREG_PICU0_INTSTAT 0x40004580
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001
+#define CYREG_PICU1_INTSTAT 0x40004581
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001
+#define CYREG_PICU2_INTSTAT 0x40004582
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001
+#define CYREG_PICU3_INTSTAT 0x40004583
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001
+#define CYREG_PICU4_INTSTAT 0x40004584
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001
+#define CYREG_PICU5_INTSTAT 0x40004585
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001
+#define CYREG_PICU6_INTSTAT 0x40004586
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001
+#define CYREG_PICU12_INTSTAT 0x4000458c
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001
+#define CYREG_PICU15_INTSTAT 0x4000458f
+#define CYDEV_PICU_SNAP_BASE 0x40004590
+#define CYDEV_PICU_SNAP_SIZE 0x00000010
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001
+#define CYREG_PICU0_SNAP 0x40004590
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001
+#define CYREG_PICU1_SNAP 0x40004591
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001
+#define CYREG_PICU2_SNAP 0x40004592
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001
+#define CYREG_PICU3_SNAP 0x40004593
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001
+#define CYREG_PICU4_SNAP 0x40004594
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001
+#define CYREG_PICU5_SNAP 0x40004595
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001
+#define CYREG_PICU6_SNAP 0x40004596
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001
+#define CYREG_PICU12_SNAP 0x4000459c
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001
+#define CYREG_PICU_15_SNAP_15 0x4000459f
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001
+#define CYREG_PICU0_DISABLE_COR 0x400045a0
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001
+#define CYREG_PICU1_DISABLE_COR 0x400045a1
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001
+#define CYREG_PICU2_DISABLE_COR 0x400045a2
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001
+#define CYREG_PICU3_DISABLE_COR 0x400045a3
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001
+#define CYREG_PICU4_DISABLE_COR 0x400045a4
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001
+#define CYREG_PICU5_DISABLE_COR 0x400045a5
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001
+#define CYREG_PICU6_DISABLE_COR 0x400045a6
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001
+#define CYREG_PICU12_DISABLE_COR 0x400045ac
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001
+#define CYREG_PICU15_DISABLE_COR 0x400045af
+#define CYDEV_MFGCFG_BASE 0x40004600
+#define CYDEV_MFGCFG_SIZE 0x000000ed
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001
+#define CYREG_DAC0_TR 0x40004608
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001
+#define CYREG_DAC1_TR 0x40004609
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001
+#define CYREG_DAC2_TR 0x4000460a
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001
+#define CYREG_DAC3_TR 0x4000460b
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001
+#define CYREG_NPUMP_DSM_TR0 0x40004610
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001
+#define CYREG_NPUMP_SC_TR0 0x40004611
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001
+#define CYREG_NPUMP_OPAMP_TR0 0x40004612
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001
+#define CYREG_SAR0_TR0 0x40004614
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001
+#define CYREG_SAR1_TR0 0x40004616
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002
+#define CYREG_OPAMP0_TR0 0x40004620
+#define CYREG_OPAMP0_TR1 0x40004621
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002
+#define CYREG_OPAMP1_TR0 0x40004622
+#define CYREG_OPAMP1_TR1 0x40004623
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002
+#define CYREG_OPAMP2_TR0 0x40004624
+#define CYREG_OPAMP2_TR1 0x40004625
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002
+#define CYREG_OPAMP3_TR0 0x40004626
+#define CYREG_OPAMP3_TR1 0x40004627
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002
+#define CYREG_CMP0_TR0 0x40004630
+#define CYREG_CMP0_TR1 0x40004631
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002
+#define CYREG_CMP1_TR0 0x40004632
+#define CYREG_CMP1_TR1 0x40004633
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002
+#define CYREG_CMP2_TR0 0x40004634
+#define CYREG_CMP2_TR1 0x40004635
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002
+#define CYREG_CMP3_TR0 0x40004636
+#define CYREG_CMP3_TR1 0x40004637
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b
+#define CYREG_PWRSYS_HIB_TR0 0x40004680
+#define CYREG_PWRSYS_HIB_TR1 0x40004681
+#define CYREG_PWRSYS_I2C_TR 0x40004682
+#define CYREG_PWRSYS_SLP_TR 0x40004683
+#define CYREG_PWRSYS_BUZZ_TR 0x40004684
+#define CYREG_PWRSYS_WAKE_TR0 0x40004685
+#define CYREG_PWRSYS_WAKE_TR1 0x40004686
+#define CYREG_PWRSYS_BREF_TR 0x40004687
+#define CYREG_PWRSYS_BG_TR 0x40004688
+#define CYREG_PWRSYS_WAKE_TR2 0x40004689
+#define CYREG_PWRSYS_WAKE_TR3 0x4000468a
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002
+#define CYREG_ILO_TR0 0x40004690
+#define CYREG_ILO_TR1 0x40004691
+#define CYDEV_MFGCFG_X32_BASE 0x40004698
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001
+#define CYREG_X32_TR 0x40004698
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005
+#define CYREG_IMO_TR0 0x400046a0
+#define CYREG_IMO_TR1 0x400046a1
+#define CYREG_IMO_GAIN 0x400046a2
+#define CYREG_IMO_C36M 0x400046a3
+#define CYREG_IMO_TR2 0x400046a4
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001
+#define CYREG_XMHZ_TR 0x400046a8
+#define CYREG_MFGCFG_DLY 0x400046c0
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d
+#define CYREG_MLOGIC_DMPSTR 0x400046e2
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002
+#define CYREG_MLOGIC_SEG_CR 0x400046e4
+#define CYREG_MLOGIC_SEG_CFG0 0x400046e5
+#define CYREG_MLOGIC_DEBUG 0x400046e8
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001
+#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea
+#define CYREG_MLOGIC_REV_ID 0x400046ec
+#define CYDEV_RESET_BASE 0x400046f0
+#define CYDEV_RESET_SIZE 0x0000000f
+#define CYREG_RESET_IPOR_CR0 0x400046f0
+#define CYREG_RESET_IPOR_CR1 0x400046f1
+#define CYREG_RESET_IPOR_CR2 0x400046f2
+#define CYREG_RESET_IPOR_CR3 0x400046f3
+#define CYREG_RESET_CR0 0x400046f4
+#define CYREG_RESET_CR1 0x400046f5
+#define CYREG_RESET_CR2 0x400046f6
+#define CYREG_RESET_CR3 0x400046f7
+#define CYREG_RESET_CR4 0x400046f8
+#define CYREG_RESET_CR5 0x400046f9
+#define CYREG_RESET_SR0 0x400046fa
+#define CYREG_RESET_SR1 0x400046fb
+#define CYREG_RESET_SR2 0x400046fc
+#define CYREG_RESET_SR3 0x400046fd
+#define CYREG_RESET_TR 0x400046fe
+#define CYDEV_SPC_BASE 0x40004700
+#define CYDEV_SPC_SIZE 0x00000100
+#define CYREG_SPC_FM_EE_CR 0x40004700
+#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701
+#define CYREG_SPC_EE_SCR 0x40004702
+#define CYREG_SPC_EE_ERR 0x40004703
+#define CYREG_SPC_CPU_DATA 0x40004720
+#define CYREG_SPC_DMA_DATA 0x40004721
+#define CYREG_SPC_SR 0x40004722
+#define CYREG_SPC_CR 0x40004723
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080
+#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780
+#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080
+#define CYDEV_CACHE_BASE 0x40004800
+#define CYDEV_CACHE_SIZE 0x0000009c
+#define CYREG_CACHE_CC_CTL 0x40004800
+#define CYREG_CACHE_ECC_CORR 0x40004880
+#define CYREG_CACHE_ECC_ERR 0x40004888
+#define CYREG_CACHE_FLASH_ERR 0x40004890
+#define CYREG_CACHE_HITMISS 0x40004898
+#define CYDEV_I2C_BASE 0x40004900
+#define CYDEV_I2C_SIZE 0x000000e1
+#define CYREG_I2C_XCFG 0x400049c8
+#define CYREG_I2C_ADR 0x400049ca
+#define CYREG_I2C_CFG 0x400049d6
+#define CYREG_I2C_CSR 0x400049d7
+#define CYREG_I2C_D 0x400049d8
+#define CYREG_I2C_MCSR 0x400049d9
+#define CYREG_I2C_CLK_DIV1 0x400049db
+#define CYREG_I2C_CLK_DIV2 0x400049dc
+#define CYREG_I2C_TMOUT_CSR 0x400049dd
+#define CYREG_I2C_TMOUT_SR 0x400049de
+#define CYREG_I2C_TMOUT_CFG0 0x400049df
+#define CYREG_I2C_TMOUT_CFG1 0x400049e0
+#define CYDEV_DEC_BASE 0x40004e00
+#define CYDEV_DEC_SIZE 0x00000015
+#define CYREG_DEC_CR 0x40004e00
+#define CYREG_DEC_SR 0x40004e01
+#define CYREG_DEC_SHIFT1 0x40004e02
+#define CYREG_DEC_SHIFT2 0x40004e03
+#define CYREG_DEC_DR2 0x40004e04
+#define CYREG_DEC_DR2H 0x40004e05
+#define CYREG_DEC_DR1 0x40004e06
+#define CYREG_DEC_OCOR 0x40004e08
+#define CYREG_DEC_OCORM 0x40004e09
+#define CYREG_DEC_OCORH 0x40004e0a
+#define CYREG_DEC_GCOR 0x40004e0c
+#define CYREG_DEC_GCORH 0x40004e0d
+#define CYREG_DEC_GVAL 0x40004e0e
+#define CYREG_DEC_OUTSAMP 0x40004e10
+#define CYREG_DEC_OUTSAMPM 0x40004e11
+#define CYREG_DEC_OUTSAMPH 0x40004e12
+#define CYREG_DEC_OUTSAMPS 0x40004e13
+#define CYREG_DEC_COHER 0x40004e14
+#define CYDEV_TMR0_BASE 0x40004f00
+#define CYDEV_TMR0_SIZE 0x0000000c
+#define CYREG_TMR0_CFG0 0x40004f00
+#define CYREG_TMR0_CFG1 0x40004f01
+#define CYREG_TMR0_CFG2 0x40004f02
+#define CYREG_TMR0_SR0 0x40004f03
+#define CYREG_TMR0_PER0 0x40004f04
+#define CYREG_TMR0_PER1 0x40004f05
+#define CYREG_TMR0_CNT_CMP0 0x40004f06
+#define CYREG_TMR0_CNT_CMP1 0x40004f07
+#define CYREG_TMR0_CAP0 0x40004f08
+#define CYREG_TMR0_CAP1 0x40004f09
+#define CYREG_TMR0_RT0 0x40004f0a
+#define CYREG_TMR0_RT1 0x40004f0b
+#define CYDEV_TMR1_BASE 0x40004f0c
+#define CYDEV_TMR1_SIZE 0x0000000c
+#define CYREG_TMR1_CFG0 0x40004f0c
+#define CYREG_TMR1_CFG1 0x40004f0d
+#define CYREG_TMR1_CFG2 0x40004f0e
+#define CYREG_TMR1_SR0 0x40004f0f
+#define CYREG_TMR1_PER0 0x40004f10
+#define CYREG_TMR1_PER1 0x40004f11
+#define CYREG_TMR1_CNT_CMP0 0x40004f12
+#define CYREG_TMR1_CNT_CMP1 0x40004f13
+#define CYREG_TMR1_CAP0 0x40004f14
+#define CYREG_TMR1_CAP1 0x40004f15
+#define CYREG_TMR1_RT0 0x40004f16
+#define CYREG_TMR1_RT1 0x40004f17
+#define CYDEV_TMR2_BASE 0x40004f18
+#define CYDEV_TMR2_SIZE 0x0000000c
+#define CYREG_TMR2_CFG0 0x40004f18
+#define CYREG_TMR2_CFG1 0x40004f19
+#define CYREG_TMR2_CFG2 0x40004f1a
+#define CYREG_TMR2_SR0 0x40004f1b
+#define CYREG_TMR2_PER0 0x40004f1c
+#define CYREG_TMR2_PER1 0x40004f1d
+#define CYREG_TMR2_CNT_CMP0 0x40004f1e
+#define CYREG_TMR2_CNT_CMP1 0x40004f1f
+#define CYREG_TMR2_CAP0 0x40004f20
+#define CYREG_TMR2_CAP1 0x40004f21
+#define CYREG_TMR2_RT0 0x40004f22
+#define CYREG_TMR2_RT1 0x40004f23
+#define CYDEV_TMR3_BASE 0x40004f24
+#define CYDEV_TMR3_SIZE 0x0000000c
+#define CYREG_TMR3_CFG0 0x40004f24
+#define CYREG_TMR3_CFG1 0x40004f25
+#define CYREG_TMR3_CFG2 0x40004f26
+#define CYREG_TMR3_SR0 0x40004f27
+#define CYREG_TMR3_PER0 0x40004f28
+#define CYREG_TMR3_PER1 0x40004f29
+#define CYREG_TMR3_CNT_CMP0 0x40004f2a
+#define CYREG_TMR3_CNT_CMP1 0x40004f2b
+#define CYREG_TMR3_CAP0 0x40004f2c
+#define CYREG_TMR3_CAP1 0x40004f2d
+#define CYREG_TMR3_RT0 0x40004f2e
+#define CYREG_TMR3_RT1 0x40004f2f
+#define CYDEV_IO_BASE 0x40005000
+#define CYDEV_IO_SIZE 0x00000200
+#define CYDEV_IO_PC_BASE 0x40005000
+#define CYDEV_IO_PC_SIZE 0x00000080
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008
+#define CYREG_PRT0_PC0 0x40005000
+#define CYREG_PRT0_PC1 0x40005001
+#define CYREG_PRT0_PC2 0x40005002
+#define CYREG_PRT0_PC3 0x40005003
+#define CYREG_PRT0_PC4 0x40005004
+#define CYREG_PRT0_PC5 0x40005005
+#define CYREG_PRT0_PC6 0x40005006
+#define CYREG_PRT0_PC7 0x40005007
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008
+#define CYREG_PRT1_PC0 0x40005008
+#define CYREG_PRT1_PC1 0x40005009
+#define CYREG_PRT1_PC2 0x4000500a
+#define CYREG_PRT1_PC3 0x4000500b
+#define CYREG_PRT1_PC4 0x4000500c
+#define CYREG_PRT1_PC5 0x4000500d
+#define CYREG_PRT1_PC6 0x4000500e
+#define CYREG_PRT1_PC7 0x4000500f
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008
+#define CYREG_PRT2_PC0 0x40005010
+#define CYREG_PRT2_PC1 0x40005011
+#define CYREG_PRT2_PC2 0x40005012
+#define CYREG_PRT2_PC3 0x40005013
+#define CYREG_PRT2_PC4 0x40005014
+#define CYREG_PRT2_PC5 0x40005015
+#define CYREG_PRT2_PC6 0x40005016
+#define CYREG_PRT2_PC7 0x40005017
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008
+#define CYREG_PRT3_PC0 0x40005018
+#define CYREG_PRT3_PC1 0x40005019
+#define CYREG_PRT3_PC2 0x4000501a
+#define CYREG_PRT3_PC3 0x4000501b
+#define CYREG_PRT3_PC4 0x4000501c
+#define CYREG_PRT3_PC5 0x4000501d
+#define CYREG_PRT3_PC6 0x4000501e
+#define CYREG_PRT3_PC7 0x4000501f
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008
+#define CYREG_PRT4_PC0 0x40005020
+#define CYREG_PRT4_PC1 0x40005021
+#define CYREG_PRT4_PC2 0x40005022
+#define CYREG_PRT4_PC3 0x40005023
+#define CYREG_PRT4_PC4 0x40005024
+#define CYREG_PRT4_PC5 0x40005025
+#define CYREG_PRT4_PC6 0x40005026
+#define CYREG_PRT4_PC7 0x40005027
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008
+#define CYREG_PRT5_PC0 0x40005028
+#define CYREG_PRT5_PC1 0x40005029
+#define CYREG_PRT5_PC2 0x4000502a
+#define CYREG_PRT5_PC3 0x4000502b
+#define CYREG_PRT5_PC4 0x4000502c
+#define CYREG_PRT5_PC5 0x4000502d
+#define CYREG_PRT5_PC6 0x4000502e
+#define CYREG_PRT5_PC7 0x4000502f
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008
+#define CYREG_PRT6_PC0 0x40005030
+#define CYREG_PRT6_PC1 0x40005031
+#define CYREG_PRT6_PC2 0x40005032
+#define CYREG_PRT6_PC3 0x40005033
+#define CYREG_PRT6_PC4 0x40005034
+#define CYREG_PRT6_PC5 0x40005035
+#define CYREG_PRT6_PC6 0x40005036
+#define CYREG_PRT6_PC7 0x40005037
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008
+#define CYREG_PRT12_PC0 0x40005060
+#define CYREG_PRT12_PC1 0x40005061
+#define CYREG_PRT12_PC2 0x40005062
+#define CYREG_PRT12_PC3 0x40005063
+#define CYREG_PRT12_PC4 0x40005064
+#define CYREG_PRT12_PC5 0x40005065
+#define CYREG_PRT12_PC6 0x40005066
+#define CYREG_PRT12_PC7 0x40005067
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006
+#define CYREG_IO_PC_PRT15_PC0 0x40005078
+#define CYREG_IO_PC_PRT15_PC1 0x40005079
+#define CYREG_IO_PC_PRT15_PC2 0x4000507a
+#define CYREG_IO_PC_PRT15_PC3 0x4000507b
+#define CYREG_IO_PC_PRT15_PC4 0x4000507c
+#define CYREG_IO_PC_PRT15_PC5 0x4000507d
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002
+#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e
+#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f
+#define CYDEV_IO_DR_BASE 0x40005080
+#define CYDEV_IO_DR_SIZE 0x00000010
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001
+#define CYREG_PRT0_DR_ALIAS 0x40005080
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001
+#define CYREG_PRT1_DR_ALIAS 0x40005081
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001
+#define CYREG_PRT2_DR_ALIAS 0x40005082
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001
+#define CYREG_PRT3_DR_ALIAS 0x40005083
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001
+#define CYREG_PRT4_DR_ALIAS 0x40005084
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001
+#define CYREG_PRT5_DR_ALIAS 0x40005085
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001
+#define CYREG_PRT6_DR_ALIAS 0x40005086
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508c
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001
+#define CYREG_PRT12_DR_ALIAS 0x4000508c
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508f
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001
+#define CYREG_PRT15_DR_15_ALIAS 0x4000508f
+#define CYDEV_IO_PS_BASE 0x40005090
+#define CYDEV_IO_PS_SIZE 0x00000010
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001
+#define CYREG_PRT0_PS_ALIAS 0x40005090
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001
+#define CYREG_PRT1_PS_ALIAS 0x40005091
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001
+#define CYREG_PRT2_PS_ALIAS 0x40005092
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001
+#define CYREG_PRT3_PS_ALIAS 0x40005093
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001
+#define CYREG_PRT4_PS_ALIAS 0x40005094
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001
+#define CYREG_PRT5_PS_ALIAS 0x40005095
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001
+#define CYREG_PRT6_PS_ALIAS 0x40005096
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509c
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001
+#define CYREG_PRT12_PS_ALIAS 0x4000509c
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509f
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001
+#define CYREG_PRT15_PS15_ALIAS 0x4000509f
+#define CYDEV_IO_PRT_BASE 0x40005100
+#define CYDEV_IO_PRT_SIZE 0x00000100
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010
+#define CYREG_PRT0_DR 0x40005100
+#define CYREG_PRT0_PS 0x40005101
+#define CYREG_PRT0_DM0 0x40005102
+#define CYREG_PRT0_DM1 0x40005103
+#define CYREG_PRT0_DM2 0x40005104
+#define CYREG_PRT0_SLW 0x40005105
+#define CYREG_PRT0_BYP 0x40005106
+#define CYREG_PRT0_BIE 0x40005107
+#define CYREG_PRT0_INP_DIS 0x40005108
+#define CYREG_PRT0_CTL 0x40005109
+#define CYREG_PRT0_PRT 0x4000510a
+#define CYREG_PRT0_BIT_MASK 0x4000510b
+#define CYREG_PRT0_AMUX 0x4000510c
+#define CYREG_PRT0_AG 0x4000510d
+#define CYREG_PRT0_LCD_COM_SEG 0x4000510e
+#define CYREG_PRT0_LCD_EN 0x4000510f
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010
+#define CYREG_PRT1_DR 0x40005110
+#define CYREG_PRT1_PS 0x40005111
+#define CYREG_PRT1_DM0 0x40005112
+#define CYREG_PRT1_DM1 0x40005113
+#define CYREG_PRT1_DM2 0x40005114
+#define CYREG_PRT1_SLW 0x40005115
+#define CYREG_PRT1_BYP 0x40005116
+#define CYREG_PRT1_BIE 0x40005117
+#define CYREG_PRT1_INP_DIS 0x40005118
+#define CYREG_PRT1_CTL 0x40005119
+#define CYREG_PRT1_PRT 0x4000511a
+#define CYREG_PRT1_BIT_MASK 0x4000511b
+#define CYREG_PRT1_AMUX 0x4000511c
+#define CYREG_PRT1_AG 0x4000511d
+#define CYREG_PRT1_LCD_COM_SEG 0x4000511e
+#define CYREG_PRT1_LCD_EN 0x4000511f
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010
+#define CYREG_PRT2_DR 0x40005120
+#define CYREG_PRT2_PS 0x40005121
+#define CYREG_PRT2_DM0 0x40005122
+#define CYREG_PRT2_DM1 0x40005123
+#define CYREG_PRT2_DM2 0x40005124
+#define CYREG_PRT2_SLW 0x40005125
+#define CYREG_PRT2_BYP 0x40005126
+#define CYREG_PRT2_BIE 0x40005127
+#define CYREG_PRT2_INP_DIS 0x40005128
+#define CYREG_PRT2_CTL 0x40005129
+#define CYREG_PRT2_PRT 0x4000512a
+#define CYREG_PRT2_BIT_MASK 0x4000512b
+#define CYREG_PRT2_AMUX 0x4000512c
+#define CYREG_PRT2_AG 0x4000512d
+#define CYREG_PRT2_LCD_COM_SEG 0x4000512e
+#define CYREG_PRT2_LCD_EN 0x4000512f
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010
+#define CYREG_PRT3_DR 0x40005130
+#define CYREG_PRT3_PS 0x40005131
+#define CYREG_PRT3_DM0 0x40005132
+#define CYREG_PRT3_DM1 0x40005133
+#define CYREG_PRT3_DM2 0x40005134
+#define CYREG_PRT3_SLW 0x40005135
+#define CYREG_PRT3_BYP 0x40005136
+#define CYREG_PRT3_BIE 0x40005137
+#define CYREG_PRT3_INP_DIS 0x40005138
+#define CYREG_PRT3_CTL 0x40005139
+#define CYREG_PRT3_PRT 0x4000513a
+#define CYREG_PRT3_BIT_MASK 0x4000513b
+#define CYREG_PRT3_AMUX 0x4000513c
+#define CYREG_PRT3_AG 0x4000513d
+#define CYREG_PRT3_LCD_COM_SEG 0x4000513e
+#define CYREG_PRT3_LCD_EN 0x4000513f
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010
+#define CYREG_PRT4_DR 0x40005140
+#define CYREG_PRT4_PS 0x40005141
+#define CYREG_PRT4_DM0 0x40005142
+#define CYREG_PRT4_DM1 0x40005143
+#define CYREG_PRT4_DM2 0x40005144
+#define CYREG_PRT4_SLW 0x40005145
+#define CYREG_PRT4_BYP 0x40005146
+#define CYREG_PRT4_BIE 0x40005147
+#define CYREG_PRT4_INP_DIS 0x40005148
+#define CYREG_PRT4_CTL 0x40005149
+#define CYREG_PRT4_PRT 0x4000514a
+#define CYREG_PRT4_BIT_MASK 0x4000514b
+#define CYREG_PRT4_AMUX 0x4000514c
+#define CYREG_PRT4_AG 0x4000514d
+#define CYREG_PRT4_LCD_COM_SEG 0x4000514e
+#define CYREG_PRT4_LCD_EN 0x4000514f
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010
+#define CYREG_PRT5_DR 0x40005150
+#define CYREG_PRT5_PS 0x40005151
+#define CYREG_PRT5_DM0 0x40005152
+#define CYREG_PRT5_DM1 0x40005153
+#define CYREG_PRT5_DM2 0x40005154
+#define CYREG_PRT5_SLW 0x40005155
+#define CYREG_PRT5_BYP 0x40005156
+#define CYREG_PRT5_BIE 0x40005157
+#define CYREG_PRT5_INP_DIS 0x40005158
+#define CYREG_PRT5_CTL 0x40005159
+#define CYREG_PRT5_PRT 0x4000515a
+#define CYREG_PRT5_BIT_MASK 0x4000515b
+#define CYREG_PRT5_AMUX 0x4000515c
+#define CYREG_PRT5_AG 0x4000515d
+#define CYREG_PRT5_LCD_COM_SEG 0x4000515e
+#define CYREG_PRT5_LCD_EN 0x4000515f
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010
+#define CYREG_PRT6_DR 0x40005160
+#define CYREG_PRT6_PS 0x40005161
+#define CYREG_PRT6_DM0 0x40005162
+#define CYREG_PRT6_DM1 0x40005163
+#define CYREG_PRT6_DM2 0x40005164
+#define CYREG_PRT6_SLW 0x40005165
+#define CYREG_PRT6_BYP 0x40005166
+#define CYREG_PRT6_BIE 0x40005167
+#define CYREG_PRT6_INP_DIS 0x40005168
+#define CYREG_PRT6_CTL 0x40005169
+#define CYREG_PRT6_PRT 0x4000516a
+#define CYREG_PRT6_BIT_MASK 0x4000516b
+#define CYREG_PRT6_AMUX 0x4000516c
+#define CYREG_PRT6_AG 0x4000516d
+#define CYREG_PRT6_LCD_COM_SEG 0x4000516e
+#define CYREG_PRT6_LCD_EN 0x4000516f
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010
+#define CYREG_PRT12_DR 0x400051c0
+#define CYREG_PRT12_PS 0x400051c1
+#define CYREG_PRT12_DM0 0x400051c2
+#define CYREG_PRT12_DM1 0x400051c3
+#define CYREG_PRT12_DM2 0x400051c4
+#define CYREG_PRT12_SLW 0x400051c5
+#define CYREG_PRT12_BYP 0x400051c6
+#define CYREG_PRT12_BIE 0x400051c7
+#define CYREG_PRT12_INP_DIS 0x400051c8
+#define CYREG_PRT12_SIO_HYST_EN 0x400051c9
+#define CYREG_PRT12_PRT 0x400051ca
+#define CYREG_PRT12_BIT_MASK 0x400051cb
+#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc
+#define CYREG_PRT12_AG 0x400051cd
+#define CYREG_PRT12_SIO_CFG 0x400051ce
+#define CYREG_PRT12_SIO_DIFF 0x400051cf
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010
+#define CYREG_PRT15_DR 0x400051f0
+#define CYREG_PRT15_PS 0x400051f1
+#define CYREG_PRT15_DM0 0x400051f2
+#define CYREG_PRT15_DM1 0x400051f3
+#define CYREG_PRT15_DM2 0x400051f4
+#define CYREG_PRT15_SLW 0x400051f5
+#define CYREG_PRT15_BYP 0x400051f6
+#define CYREG_PRT15_BIE 0x400051f7
+#define CYREG_PRT15_INP_DIS 0x400051f8
+#define CYREG_PRT15_CTL 0x400051f9
+#define CYREG_PRT15_PRT 0x400051fa
+#define CYREG_PRT15_BIT_MASK 0x400051fb
+#define CYREG_PRT15_AMUX 0x400051fc
+#define CYREG_PRT15_AG 0x400051fd
+#define CYREG_PRT15_LCD_COM_SEG 0x400051fe
+#define CYREG_PRT15_LCD_EN 0x400051ff
+#define CYDEV_PRTDSI_BASE 0x40005200
+#define CYDEV_PRTDSI_SIZE 0x0000007f
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007
+#define CYREG_PRT0_OUT_SEL0 0x40005200
+#define CYREG_PRT0_OUT_SEL1 0x40005201
+#define CYREG_PRT0_OE_SEL0 0x40005202
+#define CYREG_PRT0_OE_SEL1 0x40005203
+#define CYREG_PRT0_DBL_SYNC_IN 0x40005204
+#define CYREG_PRT0_SYNC_OUT 0x40005205
+#define CYREG_PRT0_CAPS_SEL 0x40005206
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007
+#define CYREG_PRT1_OUT_SEL0 0x40005208
+#define CYREG_PRT1_OUT_SEL1 0x40005209
+#define CYREG_PRT1_OE_SEL0 0x4000520a
+#define CYREG_PRT1_OE_SEL1 0x4000520b
+#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c
+#define CYREG_PRT1_SYNC_OUT 0x4000520d
+#define CYREG_PRT1_CAPS_SEL 0x4000520e
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007
+#define CYREG_PRT2_OUT_SEL0 0x40005210
+#define CYREG_PRT2_OUT_SEL1 0x40005211
+#define CYREG_PRT2_OE_SEL0 0x40005212
+#define CYREG_PRT2_OE_SEL1 0x40005213
+#define CYREG_PRT2_DBL_SYNC_IN 0x40005214
+#define CYREG_PRT2_SYNC_OUT 0x40005215
+#define CYREG_PRT2_CAPS_SEL 0x40005216
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007
+#define CYREG_PRT3_OUT_SEL0 0x40005218
+#define CYREG_PRT3_OUT_SEL1 0x40005219
+#define CYREG_PRT3_OE_SEL0 0x4000521a
+#define CYREG_PRT3_OE_SEL1 0x4000521b
+#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c
+#define CYREG_PRT3_SYNC_OUT 0x4000521d
+#define CYREG_PRT3_CAPS_SEL 0x4000521e
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007
+#define CYREG_PRT4_OUT_SEL0 0x40005220
+#define CYREG_PRT4_OUT_SEL1 0x40005221
+#define CYREG_PRT4_OE_SEL0 0x40005222
+#define CYREG_PRT4_OE_SEL1 0x40005223
+#define CYREG_PRT4_DBL_SYNC_IN 0x40005224
+#define CYREG_PRT4_SYNC_OUT 0x40005225
+#define CYREG_PRT4_CAPS_SEL 0x40005226
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007
+#define CYREG_PRT5_OUT_SEL0 0x40005228
+#define CYREG_PRT5_OUT_SEL1 0x40005229
+#define CYREG_PRT5_OE_SEL0 0x4000522a
+#define CYREG_PRT5_OE_SEL1 0x4000522b
+#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c
+#define CYREG_PRT5_SYNC_OUT 0x4000522d
+#define CYREG_PRT5_CAPS_SEL 0x4000522e
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007
+#define CYREG_PRT6_OUT_SEL0 0x40005230
+#define CYREG_PRT6_OUT_SEL1 0x40005231
+#define CYREG_PRT6_OE_SEL0 0x40005232
+#define CYREG_PRT6_OE_SEL1 0x40005233
+#define CYREG_PRT6_DBL_SYNC_IN 0x40005234
+#define CYREG_PRT6_SYNC_OUT 0x40005235
+#define CYREG_PRT6_CAPS_SEL 0x40005236
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006
+#define CYREG_PRT12_OUT_SEL0 0x40005260
+#define CYREG_PRT12_OUT_SEL1 0x40005261
+#define CYREG_PRT12_OE_SEL0 0x40005262
+#define CYREG_PRT12_OE_SEL1 0x40005263
+#define CYREG_PRT12_DBL_SYNC_IN 0x40005264
+#define CYREG_PRT12_SYNC_OUT 0x40005265
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007
+#define CYREG_PRT15_OUT_SEL0 0x40005278
+#define CYREG_PRT15_OUT_SEL1 0x40005279
+#define CYREG_PRT15_OE_SEL0 0x4000527a
+#define CYREG_PRT15_OE_SEL1 0x4000527b
+#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c
+#define CYREG_PRT15_SYNC_OUT 0x4000527d
+#define CYREG_PRT15_CAPS_SEL 0x4000527e
+#define CYDEV_EMIF_BASE 0x40005400
+#define CYDEV_EMIF_SIZE 0x00000007
+#define CYREG_EMIF_NO_UDB 0x40005400
+#define CYREG_EMIF_RP_WAIT_STATES 0x40005401
+#define CYREG_EMIF_MEM_DWN 0x40005402
+#define CYREG_EMIF_MEMCLK_DIV 0x40005403
+#define CYREG_EMIF_CLOCK_EN 0x40005404
+#define CYREG_EMIF_EM_TYPE 0x40005405
+#define CYREG_EMIF_WP_WAIT_STATES 0x40005406
+#define CYDEV_ANAIF_BASE 0x40005800
+#define CYDEV_ANAIF_SIZE 0x000003a9
+#define CYDEV_ANAIF_CFG_BASE 0x40005800
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010f
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003
+#define CYREG_SC0_CR0 0x40005800
+#define CYREG_SC0_CR1 0x40005801
+#define CYREG_SC0_CR2 0x40005802
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003
+#define CYREG_SC1_CR0 0x40005804
+#define CYREG_SC1_CR1 0x40005805
+#define CYREG_SC1_CR2 0x40005806
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003
+#define CYREG_SC2_CR0 0x40005808
+#define CYREG_SC2_CR1 0x40005809
+#define CYREG_SC2_CR2 0x4000580a
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003
+#define CYREG_SC3_CR0 0x4000580c
+#define CYREG_SC3_CR1 0x4000580d
+#define CYREG_SC3_CR2 0x4000580e
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003
+#define CYREG_DAC0_CR0 0x40005820
+#define CYREG_DAC0_CR1 0x40005821
+#define CYREG_DAC0_TST 0x40005822
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003
+#define CYREG_DAC1_CR0 0x40005824
+#define CYREG_DAC1_CR1 0x40005825
+#define CYREG_DAC1_TST 0x40005826
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003
+#define CYREG_DAC2_CR0 0x40005828
+#define CYREG_DAC2_CR1 0x40005829
+#define CYREG_DAC2_TST 0x4000582a
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003
+#define CYREG_DAC3_CR0 0x4000582c
+#define CYREG_DAC3_CR1 0x4000582d
+#define CYREG_DAC3_TST 0x4000582e
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001
+#define CYREG_CMP0_CR 0x40005840
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001
+#define CYREG_CMP1_CR 0x40005841
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001
+#define CYREG_CMP2_CR 0x40005842
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001
+#define CYREG_CMP3_CR 0x40005843
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002
+#define CYREG_LUT0_CR 0x40005848
+#define CYREG_LUT0_MX 0x40005849
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002
+#define CYREG_LUT1_CR 0x4000584a
+#define CYREG_LUT1_MX 0x4000584b
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002
+#define CYREG_LUT2_CR 0x4000584c
+#define CYREG_LUT2_MX 0x4000584d
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002
+#define CYREG_LUT3_CR 0x4000584e
+#define CYREG_LUT3_MX 0x4000584f
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002
+#define CYREG_OPAMP0_CR 0x40005858
+#define CYREG_OPAMP0_RSVD 0x40005859
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002
+#define CYREG_OPAMP1_CR 0x4000585a
+#define CYREG_OPAMP1_RSVD 0x4000585b
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002
+#define CYREG_OPAMP2_CR 0x4000585c
+#define CYREG_OPAMP2_RSVD 0x4000585d
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002
+#define CYREG_OPAMP3_CR 0x4000585e
+#define CYREG_OPAMP3_RSVD 0x4000585f
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002
+#define CYREG_LCDDAC_CR0 0x40005868
+#define CYREG_LCDDAC_CR1 0x40005869
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001
+#define CYREG_LCDDRV_CR 0x4000586a
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001
+#define CYREG_LCDTMR_CFG 0x4000586b
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004
+#define CYREG_BG_CR0 0x4000586c
+#define CYREG_BG_RSVD 0x4000586d
+#define CYREG_BG_DFT0 0x4000586e
+#define CYREG_BG_DFT1 0x4000586f
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002
+#define CYREG_CAPSL_CFG0 0x40005870
+#define CYREG_CAPSL_CFG1 0x40005871
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002
+#define CYREG_CAPSR_CFG0 0x40005872
+#define CYREG_CAPSR_CFG1 0x40005873
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002
+#define CYREG_PUMP_CR0 0x40005876
+#define CYREG_PUMP_CR1 0x40005877
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002
+#define CYREG_LPF0_CR0 0x40005878
+#define CYREG_LPF0_RSVD 0x40005879
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002
+#define CYREG_LPF1_CR0 0x4000587a
+#define CYREG_LPF1_RSVD 0x4000587b
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001
+#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020
+#define CYREG_DSM0_CR0 0x40005880
+#define CYREG_DSM0_CR1 0x40005881
+#define CYREG_DSM0_CR2 0x40005882
+#define CYREG_DSM0_CR3 0x40005883
+#define CYREG_DSM0_CR4 0x40005884
+#define CYREG_DSM0_CR5 0x40005885
+#define CYREG_DSM0_CR6 0x40005886
+#define CYREG_DSM0_CR7 0x40005887
+#define CYREG_DSM0_CR8 0x40005888
+#define CYREG_DSM0_CR9 0x40005889
+#define CYREG_DSM0_CR10 0x4000588a
+#define CYREG_DSM0_CR11 0x4000588b
+#define CYREG_DSM0_CR12 0x4000588c
+#define CYREG_DSM0_CR13 0x4000588d
+#define CYREG_DSM0_CR14 0x4000588e
+#define CYREG_DSM0_CR15 0x4000588f
+#define CYREG_DSM0_CR16 0x40005890
+#define CYREG_DSM0_CR17 0x40005891
+#define CYREG_DSM0_REF0 0x40005892
+#define CYREG_DSM0_REF1 0x40005893
+#define CYREG_DSM0_REF2 0x40005894
+#define CYREG_DSM0_REF3 0x40005895
+#define CYREG_DSM0_DEM0 0x40005896
+#define CYREG_DSM0_DEM1 0x40005897
+#define CYREG_DSM0_TST0 0x40005898
+#define CYREG_DSM0_TST1 0x40005899
+#define CYREG_DSM0_BUF0 0x4000589a
+#define CYREG_DSM0_BUF1 0x4000589b
+#define CYREG_DSM0_BUF2 0x4000589c
+#define CYREG_DSM0_BUF3 0x4000589d
+#define CYREG_DSM0_MISC 0x4000589e
+#define CYREG_DSM0_RSVD1 0x4000589f
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007
+#define CYREG_SAR0_CSR0 0x40005900
+#define CYREG_SAR0_CSR1 0x40005901
+#define CYREG_SAR0_CSR2 0x40005902
+#define CYREG_SAR0_CSR3 0x40005903
+#define CYREG_SAR0_CSR4 0x40005904
+#define CYREG_SAR0_CSR5 0x40005905
+#define CYREG_SAR0_CSR6 0x40005906
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007
+#define CYREG_SAR1_CSR0 0x40005908
+#define CYREG_SAR1_CSR1 0x40005909
+#define CYREG_SAR1_CSR2 0x4000590a
+#define CYREG_SAR1_CSR3 0x4000590b
+#define CYREG_SAR1_CSR4 0x4000590c
+#define CYREG_SAR1_CSR5 0x4000590d
+#define CYREG_SAR1_CSR6 0x4000590e
+#define CYDEV_ANAIF_RT_BASE 0x40005a00
+#define CYDEV_ANAIF_RT_SIZE 0x00000162
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d
+#define CYREG_SC0_SW0 0x40005a00
+#define CYREG_SC0_SW2 0x40005a02
+#define CYREG_SC0_SW3 0x40005a03
+#define CYREG_SC0_SW4 0x40005a04
+#define CYREG_SC0_SW6 0x40005a06
+#define CYREG_SC0_SW7 0x40005a07
+#define CYREG_SC0_SW8 0x40005a08
+#define CYREG_SC0_SW10 0x40005a0a
+#define CYREG_SC0_CLK 0x40005a0b
+#define CYREG_SC0_BST 0x40005a0c
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d
+#define CYREG_SC1_SW0 0x40005a10
+#define CYREG_SC1_SW2 0x40005a12
+#define CYREG_SC1_SW3 0x40005a13
+#define CYREG_SC1_SW4 0x40005a14
+#define CYREG_SC1_SW6 0x40005a16
+#define CYREG_SC1_SW7 0x40005a17
+#define CYREG_SC1_SW8 0x40005a18
+#define CYREG_SC1_SW10 0x40005a1a
+#define CYREG_SC1_CLK 0x40005a1b
+#define CYREG_SC1_BST 0x40005a1c
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d
+#define CYREG_SC2_SW0 0x40005a20
+#define CYREG_SC2_SW2 0x40005a22
+#define CYREG_SC2_SW3 0x40005a23
+#define CYREG_SC2_SW4 0x40005a24
+#define CYREG_SC2_SW6 0x40005a26
+#define CYREG_SC2_SW7 0x40005a27
+#define CYREG_SC2_SW8 0x40005a28
+#define CYREG_SC2_SW10 0x40005a2a
+#define CYREG_SC2_CLK 0x40005a2b
+#define CYREG_SC2_BST 0x40005a2c
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d
+#define CYREG_SC3_SW0 0x40005a30
+#define CYREG_SC3_SW2 0x40005a32
+#define CYREG_SC3_SW3 0x40005a33
+#define CYREG_SC3_SW4 0x40005a34
+#define CYREG_SC3_SW6 0x40005a36
+#define CYREG_SC3_SW7 0x40005a37
+#define CYREG_SC3_SW8 0x40005a38
+#define CYREG_SC3_SW10 0x40005a3a
+#define CYREG_SC3_CLK 0x40005a3b
+#define CYREG_SC3_BST 0x40005a3c
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008
+#define CYREG_DAC0_SW0 0x40005a80
+#define CYREG_DAC0_SW2 0x40005a82
+#define CYREG_DAC0_SW3 0x40005a83
+#define CYREG_DAC0_SW4 0x40005a84
+#define CYREG_DAC0_STROBE 0x40005a87
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008
+#define CYREG_DAC1_SW0 0x40005a88
+#define CYREG_DAC1_SW2 0x40005a8a
+#define CYREG_DAC1_SW3 0x40005a8b
+#define CYREG_DAC1_SW4 0x40005a8c
+#define CYREG_DAC1_STROBE 0x40005a8f
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008
+#define CYREG_DAC2_SW0 0x40005a90
+#define CYREG_DAC2_SW2 0x40005a92
+#define CYREG_DAC2_SW3 0x40005a93
+#define CYREG_DAC2_SW4 0x40005a94
+#define CYREG_DAC2_STROBE 0x40005a97
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008
+#define CYREG_DAC3_SW0 0x40005a98
+#define CYREG_DAC3_SW2 0x40005a9a
+#define CYREG_DAC3_SW3 0x40005a9b
+#define CYREG_DAC3_SW4 0x40005a9c
+#define CYREG_DAC3_STROBE 0x40005a9f
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008
+#define CYREG_CMP0_SW0 0x40005ac0
+#define CYREG_CMP0_SW2 0x40005ac2
+#define CYREG_CMP0_SW3 0x40005ac3
+#define CYREG_CMP0_SW4 0x40005ac4
+#define CYREG_CMP0_SW6 0x40005ac6
+#define CYREG_CMP0_CLK 0x40005ac7
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008
+#define CYREG_CMP1_SW0 0x40005ac8
+#define CYREG_CMP1_SW2 0x40005aca
+#define CYREG_CMP1_SW3 0x40005acb
+#define CYREG_CMP1_SW4 0x40005acc
+#define CYREG_CMP1_SW6 0x40005ace
+#define CYREG_CMP1_CLK 0x40005acf
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008
+#define CYREG_CMP2_SW0 0x40005ad0
+#define CYREG_CMP2_SW2 0x40005ad2
+#define CYREG_CMP2_SW3 0x40005ad3
+#define CYREG_CMP2_SW4 0x40005ad4
+#define CYREG_CMP2_SW6 0x40005ad6
+#define CYREG_CMP2_CLK 0x40005ad7
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008
+#define CYREG_CMP3_SW0 0x40005ad8
+#define CYREG_CMP3_SW2 0x40005ada
+#define CYREG_CMP3_SW3 0x40005adb
+#define CYREG_CMP3_SW4 0x40005adc
+#define CYREG_CMP3_SW6 0x40005ade
+#define CYREG_CMP3_CLK 0x40005adf
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008
+#define CYREG_DSM0_SW0 0x40005b00
+#define CYREG_DSM0_SW2 0x40005b02
+#define CYREG_DSM0_SW3 0x40005b03
+#define CYREG_DSM0_SW4 0x40005b04
+#define CYREG_DSM0_SW6 0x40005b06
+#define CYREG_DSM0_CLK 0x40005b07
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008
+#define CYREG_SAR0_SW0 0x40005b20
+#define CYREG_SAR0_SW2 0x40005b22
+#define CYREG_SAR0_SW3 0x40005b23
+#define CYREG_SAR0_SW4 0x40005b24
+#define CYREG_SAR0_SW6 0x40005b26
+#define CYREG_SAR0_CLK 0x40005b27
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008
+#define CYREG_SAR1_SW0 0x40005b28
+#define CYREG_SAR1_SW2 0x40005b2a
+#define CYREG_SAR1_SW3 0x40005b2b
+#define CYREG_SAR1_SW4 0x40005b2c
+#define CYREG_SAR1_SW6 0x40005b2e
+#define CYREG_SAR1_CLK 0x40005b2f
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002
+#define CYREG_OPAMP0_MX 0x40005b40
+#define CYREG_OPAMP0_SW 0x40005b41
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002
+#define CYREG_OPAMP1_MX 0x40005b42
+#define CYREG_OPAMP1_SW 0x40005b43
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002
+#define CYREG_OPAMP2_MX 0x40005b44
+#define CYREG_OPAMP2_SW 0x40005b45
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002
+#define CYREG_OPAMP3_MX 0x40005b46
+#define CYREG_OPAMP3_SW 0x40005b47
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005
+#define CYREG_LCDDAC_SW0 0x40005b50
+#define CYREG_LCDDAC_SW1 0x40005b51
+#define CYREG_LCDDAC_SW2 0x40005b52
+#define CYREG_LCDDAC_SW3 0x40005b53
+#define CYREG_LCDDAC_SW4 0x40005b54
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001
+#define CYREG_SC_MISC 0x40005b56
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004
+#define CYREG_BUS_SW0 0x40005b58
+#define CYREG_BUS_SW2 0x40005b5a
+#define CYREG_BUS_SW3 0x40005b5b
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006
+#define CYREG_DFT_CR0 0x40005b5c
+#define CYREG_DFT_CR1 0x40005b5d
+#define CYREG_DFT_CR2 0x40005b5e
+#define CYREG_DFT_CR3 0x40005b5f
+#define CYREG_DFT_CR4 0x40005b60
+#define CYREG_DFT_CR5 0x40005b61
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001
+#define CYREG_DAC0_D 0x40005b80
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001
+#define CYREG_DAC1_D 0x40005b81
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001
+#define CYREG_DAC2_D 0x40005b82
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001
+#define CYREG_DAC3_D 0x40005b83
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002
+#define CYREG_DSM0_OUT0 0x40005b88
+#define CYREG_DSM0_OUT1 0x40005b89
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005
+#define CYREG_LUT_SR 0x40005b90
+#define CYREG_LUT_WRK1 0x40005b91
+#define CYREG_LUT_MSK 0x40005b92
+#define CYREG_LUT_CLK 0x40005b93
+#define CYREG_LUT_CPTR 0x40005b94
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002
+#define CYREG_CMP_WRK 0x40005b96
+#define CYREG_CMP_TST 0x40005b97
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005
+#define CYREG_SC_SR 0x40005b98
+#define CYREG_SC_WRK1 0x40005b99
+#define CYREG_SC_MSK 0x40005b9a
+#define CYREG_SC_CMPINV 0x40005b9b
+#define CYREG_SC_CPTR 0x40005b9c
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002
+#define CYREG_SAR0_WRK0 0x40005ba0
+#define CYREG_SAR0_WRK1 0x40005ba1
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002
+#define CYREG_SAR1_WRK0 0x40005ba2
+#define CYREG_SAR1_WRK1 0x40005ba3
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001
+#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8
+#define CYDEV_USB_BASE 0x40006000
+#define CYDEV_USB_SIZE 0x00000300
+#define CYREG_USB_EP0_DR0 0x40006000
+#define CYREG_USB_EP0_DR1 0x40006001
+#define CYREG_USB_EP0_DR2 0x40006002
+#define CYREG_USB_EP0_DR3 0x40006003
+#define CYREG_USB_EP0_DR4 0x40006004
+#define CYREG_USB_EP0_DR5 0x40006005
+#define CYREG_USB_EP0_DR6 0x40006006
+#define CYREG_USB_EP0_DR7 0x40006007
+#define CYREG_USB_CR0 0x40006008
+#define CYREG_USB_CR1 0x40006009
+#define CYREG_USB_SIE_EP_INT_EN 0x4000600a
+#define CYREG_USB_SIE_EP_INT_SR 0x4000600b
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600c
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003
+#define CYREG_USB_SIE_EP1_CNT0 0x4000600c
+#define CYREG_USB_SIE_EP1_CNT1 0x4000600d
+#define CYREG_USB_SIE_EP1_CR0 0x4000600e
+#define CYREG_USB_USBIO_CR0 0x40006010
+#define CYREG_USB_USBIO_CR1 0x40006012
+#define CYREG_USB_DYN_RECONFIG 0x40006014
+#define CYREG_USB_SOF0 0x40006018
+#define CYREG_USB_SOF1 0x40006019
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601c
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003
+#define CYREG_USB_SIE_EP2_CNT0 0x4000601c
+#define CYREG_USB_SIE_EP2_CNT1 0x4000601d
+#define CYREG_USB_SIE_EP2_CR0 0x4000601e
+#define CYREG_USB_EP0_CR 0x40006028
+#define CYREG_USB_EP0_CNT 0x40006029
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602c
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003
+#define CYREG_USB_SIE_EP3_CNT0 0x4000602c
+#define CYREG_USB_SIE_EP3_CNT1 0x4000602d
+#define CYREG_USB_SIE_EP3_CR0 0x4000602e
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603c
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003
+#define CYREG_USB_SIE_EP4_CNT0 0x4000603c
+#define CYREG_USB_SIE_EP4_CNT1 0x4000603d
+#define CYREG_USB_SIE_EP4_CR0 0x4000603e
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604c
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003
+#define CYREG_USB_SIE_EP5_CNT0 0x4000604c
+#define CYREG_USB_SIE_EP5_CNT1 0x4000604d
+#define CYREG_USB_SIE_EP5_CR0 0x4000604e
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605c
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003
+#define CYREG_USB_SIE_EP6_CNT0 0x4000605c
+#define CYREG_USB_SIE_EP6_CNT1 0x4000605d
+#define CYREG_USB_SIE_EP6_CR0 0x4000605e
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606c
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003
+#define CYREG_USB_SIE_EP7_CNT0 0x4000606c
+#define CYREG_USB_SIE_EP7_CNT1 0x4000606d
+#define CYREG_USB_SIE_EP7_CR0 0x4000606e
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607c
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003
+#define CYREG_USB_SIE_EP8_CNT0 0x4000607c
+#define CYREG_USB_SIE_EP8_CNT1 0x4000607d
+#define CYREG_USB_SIE_EP8_CR0 0x4000607e
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003
+#define CYREG_USB_ARB_EP1_CFG 0x40006080
+#define CYREG_USB_ARB_EP1_INT_EN 0x40006081
+#define CYREG_USB_ARB_EP1_SR 0x40006082
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005
+#define CYREG_USB_ARB_RW1_WA 0x40006084
+#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085
+#define CYREG_USB_ARB_RW1_RA 0x40006086
+#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087
+#define CYREG_USB_ARB_RW1_DR 0x40006088
+#define CYREG_USB_BUF_SIZE 0x4000608c
+#define CYREG_USB_EP_ACTIVE 0x4000608e
+#define CYREG_USB_EP_TYPE 0x4000608f
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003
+#define CYREG_USB_ARB_EP2_CFG 0x40006090
+#define CYREG_USB_ARB_EP2_INT_EN 0x40006091
+#define CYREG_USB_ARB_EP2_SR 0x40006092
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005
+#define CYREG_USB_ARB_RW2_WA 0x40006094
+#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095
+#define CYREG_USB_ARB_RW2_RA 0x40006096
+#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097
+#define CYREG_USB_ARB_RW2_DR 0x40006098
+#define CYREG_USB_ARB_CFG 0x4000609c
+#define CYREG_USB_USB_CLK_EN 0x4000609d
+#define CYREG_USB_ARB_INT_EN 0x4000609e
+#define CYREG_USB_ARB_INT_SR 0x4000609f
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003
+#define CYREG_USB_ARB_EP3_CFG 0x400060a0
+#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1
+#define CYREG_USB_ARB_EP3_SR 0x400060a2
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005
+#define CYREG_USB_ARB_RW3_WA 0x400060a4
+#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5
+#define CYREG_USB_ARB_RW3_RA 0x400060a6
+#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7
+#define CYREG_USB_ARB_RW3_DR 0x400060a8
+#define CYREG_USB_CWA 0x400060ac
+#define CYREG_USB_CWA_MSB 0x400060ad
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003
+#define CYREG_USB_ARB_EP4_CFG 0x400060b0
+#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1
+#define CYREG_USB_ARB_EP4_SR 0x400060b2
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005
+#define CYREG_USB_ARB_RW4_WA 0x400060b4
+#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5
+#define CYREG_USB_ARB_RW4_RA 0x400060b6
+#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7
+#define CYREG_USB_ARB_RW4_DR 0x400060b8
+#define CYREG_USB_DMA_THRES 0x400060bc
+#define CYREG_USB_DMA_THRES_MSB 0x400060bd
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003
+#define CYREG_USB_ARB_EP5_CFG 0x400060c0
+#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1
+#define CYREG_USB_ARB_EP5_SR 0x400060c2
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005
+#define CYREG_USB_ARB_RW5_WA 0x400060c4
+#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5
+#define CYREG_USB_ARB_RW5_RA 0x400060c6
+#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7
+#define CYREG_USB_ARB_RW5_DR 0x400060c8
+#define CYREG_USB_BUS_RST_CNT 0x400060cc
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003
+#define CYREG_USB_ARB_EP6_CFG 0x400060d0
+#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1
+#define CYREG_USB_ARB_EP6_SR 0x400060d2
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005
+#define CYREG_USB_ARB_RW6_WA 0x400060d4
+#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5
+#define CYREG_USB_ARB_RW6_RA 0x400060d6
+#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7
+#define CYREG_USB_ARB_RW6_DR 0x400060d8
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003
+#define CYREG_USB_ARB_EP7_CFG 0x400060e0
+#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1
+#define CYREG_USB_ARB_EP7_SR 0x400060e2
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005
+#define CYREG_USB_ARB_RW7_WA 0x400060e4
+#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5
+#define CYREG_USB_ARB_RW7_RA 0x400060e6
+#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7
+#define CYREG_USB_ARB_RW7_DR 0x400060e8
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003
+#define CYREG_USB_ARB_EP8_CFG 0x400060f0
+#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1
+#define CYREG_USB_ARB_EP8_SR 0x400060f2
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005
+#define CYREG_USB_ARB_RW8_WA 0x400060f4
+#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5
+#define CYREG_USB_ARB_RW8_RA 0x400060f6
+#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7
+#define CYREG_USB_ARB_RW8_DR 0x400060f8
+#define CYDEV_USB_MEM_BASE 0x40006100
+#define CYDEV_USB_MEM_SIZE 0x00000200
+#define CYREG_USB_MEM_DATA_MBASE 0x40006100
+#define CYREG_USB_MEM_DATA_MSIZE 0x00000200
+#define CYDEV_UWRK_BASE 0x40006400
+#define CYDEV_UWRK_SIZE 0x00000b60
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0
+#define CYREG_B0_UDB00_A0 0x40006400
+#define CYREG_B0_UDB01_A0 0x40006401
+#define CYREG_B0_UDB02_A0 0x40006402
+#define CYREG_B0_UDB03_A0 0x40006403
+#define CYREG_B0_UDB04_A0 0x40006404
+#define CYREG_B0_UDB05_A0 0x40006405
+#define CYREG_B0_UDB06_A0 0x40006406
+#define CYREG_B0_UDB07_A0 0x40006407
+#define CYREG_B0_UDB08_A0 0x40006408
+#define CYREG_B0_UDB09_A0 0x40006409
+#define CYREG_B0_UDB10_A0 0x4000640a
+#define CYREG_B0_UDB11_A0 0x4000640b
+#define CYREG_B0_UDB12_A0 0x4000640c
+#define CYREG_B0_UDB13_A0 0x4000640d
+#define CYREG_B0_UDB14_A0 0x4000640e
+#define CYREG_B0_UDB15_A0 0x4000640f
+#define CYREG_B0_UDB00_A1 0x40006410
+#define CYREG_B0_UDB01_A1 0x40006411
+#define CYREG_B0_UDB02_A1 0x40006412
+#define CYREG_B0_UDB03_A1 0x40006413
+#define CYREG_B0_UDB04_A1 0x40006414
+#define CYREG_B0_UDB05_A1 0x40006415
+#define CYREG_B0_UDB06_A1 0x40006416
+#define CYREG_B0_UDB07_A1 0x40006417
+#define CYREG_B0_UDB08_A1 0x40006418
+#define CYREG_B0_UDB09_A1 0x40006419
+#define CYREG_B0_UDB10_A1 0x4000641a
+#define CYREG_B0_UDB11_A1 0x4000641b
+#define CYREG_B0_UDB12_A1 0x4000641c
+#define CYREG_B0_UDB13_A1 0x4000641d
+#define CYREG_B0_UDB14_A1 0x4000641e
+#define CYREG_B0_UDB15_A1 0x4000641f
+#define CYREG_B0_UDB00_D0 0x40006420
+#define CYREG_B0_UDB01_D0 0x40006421
+#define CYREG_B0_UDB02_D0 0x40006422
+#define CYREG_B0_UDB03_D0 0x40006423
+#define CYREG_B0_UDB04_D0 0x40006424
+#define CYREG_B0_UDB05_D0 0x40006425
+#define CYREG_B0_UDB06_D0 0x40006426
+#define CYREG_B0_UDB07_D0 0x40006427
+#define CYREG_B0_UDB08_D0 0x40006428
+#define CYREG_B0_UDB09_D0 0x40006429
+#define CYREG_B0_UDB10_D0 0x4000642a
+#define CYREG_B0_UDB11_D0 0x4000642b
+#define CYREG_B0_UDB12_D0 0x4000642c
+#define CYREG_B0_UDB13_D0 0x4000642d
+#define CYREG_B0_UDB14_D0 0x4000642e
+#define CYREG_B0_UDB15_D0 0x4000642f
+#define CYREG_B0_UDB00_D1 0x40006430
+#define CYREG_B0_UDB01_D1 0x40006431
+#define CYREG_B0_UDB02_D1 0x40006432
+#define CYREG_B0_UDB03_D1 0x40006433
+#define CYREG_B0_UDB04_D1 0x40006434
+#define CYREG_B0_UDB05_D1 0x40006435
+#define CYREG_B0_UDB06_D1 0x40006436
+#define CYREG_B0_UDB07_D1 0x40006437
+#define CYREG_B0_UDB08_D1 0x40006438
+#define CYREG_B0_UDB09_D1 0x40006439
+#define CYREG_B0_UDB10_D1 0x4000643a
+#define CYREG_B0_UDB11_D1 0x4000643b
+#define CYREG_B0_UDB12_D1 0x4000643c
+#define CYREG_B0_UDB13_D1 0x4000643d
+#define CYREG_B0_UDB14_D1 0x4000643e
+#define CYREG_B0_UDB15_D1 0x4000643f
+#define CYREG_B0_UDB00_F0 0x40006440
+#define CYREG_B0_UDB01_F0 0x40006441
+#define CYREG_B0_UDB02_F0 0x40006442
+#define CYREG_B0_UDB03_F0 0x40006443
+#define CYREG_B0_UDB04_F0 0x40006444
+#define CYREG_B0_UDB05_F0 0x40006445
+#define CYREG_B0_UDB06_F0 0x40006446
+#define CYREG_B0_UDB07_F0 0x40006447
+#define CYREG_B0_UDB08_F0 0x40006448
+#define CYREG_B0_UDB09_F0 0x40006449
+#define CYREG_B0_UDB10_F0 0x4000644a
+#define CYREG_B0_UDB11_F0 0x4000644b
+#define CYREG_B0_UDB12_F0 0x4000644c
+#define CYREG_B0_UDB13_F0 0x4000644d
+#define CYREG_B0_UDB14_F0 0x4000644e
+#define CYREG_B0_UDB15_F0 0x4000644f
+#define CYREG_B0_UDB00_F1 0x40006450
+#define CYREG_B0_UDB01_F1 0x40006451
+#define CYREG_B0_UDB02_F1 0x40006452
+#define CYREG_B0_UDB03_F1 0x40006453
+#define CYREG_B0_UDB04_F1 0x40006454
+#define CYREG_B0_UDB05_F1 0x40006455
+#define CYREG_B0_UDB06_F1 0x40006456
+#define CYREG_B0_UDB07_F1 0x40006457
+#define CYREG_B0_UDB08_F1 0x40006458
+#define CYREG_B0_UDB09_F1 0x40006459
+#define CYREG_B0_UDB10_F1 0x4000645a
+#define CYREG_B0_UDB11_F1 0x4000645b
+#define CYREG_B0_UDB12_F1 0x4000645c
+#define CYREG_B0_UDB13_F1 0x4000645d
+#define CYREG_B0_UDB14_F1 0x4000645e
+#define CYREG_B0_UDB15_F1 0x4000645f
+#define CYREG_B0_UDB00_ST 0x40006460
+#define CYREG_B0_UDB01_ST 0x40006461
+#define CYREG_B0_UDB02_ST 0x40006462
+#define CYREG_B0_UDB03_ST 0x40006463
+#define CYREG_B0_UDB04_ST 0x40006464
+#define CYREG_B0_UDB05_ST 0x40006465
+#define CYREG_B0_UDB06_ST 0x40006466
+#define CYREG_B0_UDB07_ST 0x40006467
+#define CYREG_B0_UDB08_ST 0x40006468
+#define CYREG_B0_UDB09_ST 0x40006469
+#define CYREG_B0_UDB10_ST 0x4000646a
+#define CYREG_B0_UDB11_ST 0x4000646b
+#define CYREG_B0_UDB12_ST 0x4000646c
+#define CYREG_B0_UDB13_ST 0x4000646d
+#define CYREG_B0_UDB14_ST 0x4000646e
+#define CYREG_B0_UDB15_ST 0x4000646f
+#define CYREG_B0_UDB00_CTL 0x40006470
+#define CYREG_B0_UDB01_CTL 0x40006471
+#define CYREG_B0_UDB02_CTL 0x40006472
+#define CYREG_B0_UDB03_CTL 0x40006473
+#define CYREG_B0_UDB04_CTL 0x40006474
+#define CYREG_B0_UDB05_CTL 0x40006475
+#define CYREG_B0_UDB06_CTL 0x40006476
+#define CYREG_B0_UDB07_CTL 0x40006477
+#define CYREG_B0_UDB08_CTL 0x40006478
+#define CYREG_B0_UDB09_CTL 0x40006479
+#define CYREG_B0_UDB10_CTL 0x4000647a
+#define CYREG_B0_UDB11_CTL 0x4000647b
+#define CYREG_B0_UDB12_CTL 0x4000647c
+#define CYREG_B0_UDB13_CTL 0x4000647d
+#define CYREG_B0_UDB14_CTL 0x4000647e
+#define CYREG_B0_UDB15_CTL 0x4000647f
+#define CYREG_B0_UDB00_MSK 0x40006480
+#define CYREG_B0_UDB01_MSK 0x40006481
+#define CYREG_B0_UDB02_MSK 0x40006482
+#define CYREG_B0_UDB03_MSK 0x40006483
+#define CYREG_B0_UDB04_MSK 0x40006484
+#define CYREG_B0_UDB05_MSK 0x40006485
+#define CYREG_B0_UDB06_MSK 0x40006486
+#define CYREG_B0_UDB07_MSK 0x40006487
+#define CYREG_B0_UDB08_MSK 0x40006488
+#define CYREG_B0_UDB09_MSK 0x40006489
+#define CYREG_B0_UDB10_MSK 0x4000648a
+#define CYREG_B0_UDB11_MSK 0x4000648b
+#define CYREG_B0_UDB12_MSK 0x4000648c
+#define CYREG_B0_UDB13_MSK 0x4000648d
+#define CYREG_B0_UDB14_MSK 0x4000648e
+#define CYREG_B0_UDB15_MSK 0x4000648f
+#define CYREG_B0_UDB00_ACTL 0x40006490
+#define CYREG_B0_UDB01_ACTL 0x40006491
+#define CYREG_B0_UDB02_ACTL 0x40006492
+#define CYREG_B0_UDB03_ACTL 0x40006493
+#define CYREG_B0_UDB04_ACTL 0x40006494
+#define CYREG_B0_UDB05_ACTL 0x40006495
+#define CYREG_B0_UDB06_ACTL 0x40006496
+#define CYREG_B0_UDB07_ACTL 0x40006497
+#define CYREG_B0_UDB08_ACTL 0x40006498
+#define CYREG_B0_UDB09_ACTL 0x40006499
+#define CYREG_B0_UDB10_ACTL 0x4000649a
+#define CYREG_B0_UDB11_ACTL 0x4000649b
+#define CYREG_B0_UDB12_ACTL 0x4000649c
+#define CYREG_B0_UDB13_ACTL 0x4000649d
+#define CYREG_B0_UDB14_ACTL 0x4000649e
+#define CYREG_B0_UDB15_ACTL 0x4000649f
+#define CYREG_B0_UDB00_MC 0x400064a0
+#define CYREG_B0_UDB01_MC 0x400064a1
+#define CYREG_B0_UDB02_MC 0x400064a2
+#define CYREG_B0_UDB03_MC 0x400064a3
+#define CYREG_B0_UDB04_MC 0x400064a4
+#define CYREG_B0_UDB05_MC 0x400064a5
+#define CYREG_B0_UDB06_MC 0x400064a6
+#define CYREG_B0_UDB07_MC 0x400064a7
+#define CYREG_B0_UDB08_MC 0x400064a8
+#define CYREG_B0_UDB09_MC 0x400064a9
+#define CYREG_B0_UDB10_MC 0x400064aa
+#define CYREG_B0_UDB11_MC 0x400064ab
+#define CYREG_B0_UDB12_MC 0x400064ac
+#define CYREG_B0_UDB13_MC 0x400064ad
+#define CYREG_B0_UDB14_MC 0x400064ae
+#define CYREG_B0_UDB15_MC 0x400064af
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0
+#define CYREG_B1_UDB04_A0 0x40006504
+#define CYREG_B1_UDB05_A0 0x40006505
+#define CYREG_B1_UDB06_A0 0x40006506
+#define CYREG_B1_UDB07_A0 0x40006507
+#define CYREG_B1_UDB08_A0 0x40006508
+#define CYREG_B1_UDB09_A0 0x40006509
+#define CYREG_B1_UDB10_A0 0x4000650a
+#define CYREG_B1_UDB11_A0 0x4000650b
+#define CYREG_B1_UDB04_A1 0x40006514
+#define CYREG_B1_UDB05_A1 0x40006515
+#define CYREG_B1_UDB06_A1 0x40006516
+#define CYREG_B1_UDB07_A1 0x40006517
+#define CYREG_B1_UDB08_A1 0x40006518
+#define CYREG_B1_UDB09_A1 0x40006519
+#define CYREG_B1_UDB10_A1 0x4000651a
+#define CYREG_B1_UDB11_A1 0x4000651b
+#define CYREG_B1_UDB04_D0 0x40006524
+#define CYREG_B1_UDB05_D0 0x40006525
+#define CYREG_B1_UDB06_D0 0x40006526
+#define CYREG_B1_UDB07_D0 0x40006527
+#define CYREG_B1_UDB08_D0 0x40006528
+#define CYREG_B1_UDB09_D0 0x40006529
+#define CYREG_B1_UDB10_D0 0x4000652a
+#define CYREG_B1_UDB11_D0 0x4000652b
+#define CYREG_B1_UDB04_D1 0x40006534
+#define CYREG_B1_UDB05_D1 0x40006535
+#define CYREG_B1_UDB06_D1 0x40006536
+#define CYREG_B1_UDB07_D1 0x40006537
+#define CYREG_B1_UDB08_D1 0x40006538
+#define CYREG_B1_UDB09_D1 0x40006539
+#define CYREG_B1_UDB10_D1 0x4000653a
+#define CYREG_B1_UDB11_D1 0x4000653b
+#define CYREG_B1_UDB04_F0 0x40006544
+#define CYREG_B1_UDB05_F0 0x40006545
+#define CYREG_B1_UDB06_F0 0x40006546
+#define CYREG_B1_UDB07_F0 0x40006547
+#define CYREG_B1_UDB08_F0 0x40006548
+#define CYREG_B1_UDB09_F0 0x40006549
+#define CYREG_B1_UDB10_F0 0x4000654a
+#define CYREG_B1_UDB11_F0 0x4000654b
+#define CYREG_B1_UDB04_F1 0x40006554
+#define CYREG_B1_UDB05_F1 0x40006555
+#define CYREG_B1_UDB06_F1 0x40006556
+#define CYREG_B1_UDB07_F1 0x40006557
+#define CYREG_B1_UDB08_F1 0x40006558
+#define CYREG_B1_UDB09_F1 0x40006559
+#define CYREG_B1_UDB10_F1 0x4000655a
+#define CYREG_B1_UDB11_F1 0x4000655b
+#define CYREG_B1_UDB04_ST 0x40006564
+#define CYREG_B1_UDB05_ST 0x40006565
+#define CYREG_B1_UDB06_ST 0x40006566
+#define CYREG_B1_UDB07_ST 0x40006567
+#define CYREG_B1_UDB08_ST 0x40006568
+#define CYREG_B1_UDB09_ST 0x40006569
+#define CYREG_B1_UDB10_ST 0x4000656a
+#define CYREG_B1_UDB11_ST 0x4000656b
+#define CYREG_B1_UDB04_CTL 0x40006574
+#define CYREG_B1_UDB05_CTL 0x40006575
+#define CYREG_B1_UDB06_CTL 0x40006576
+#define CYREG_B1_UDB07_CTL 0x40006577
+#define CYREG_B1_UDB08_CTL 0x40006578
+#define CYREG_B1_UDB09_CTL 0x40006579
+#define CYREG_B1_UDB10_CTL 0x4000657a
+#define CYREG_B1_UDB11_CTL 0x4000657b
+#define CYREG_B1_UDB04_MSK 0x40006584
+#define CYREG_B1_UDB05_MSK 0x40006585
+#define CYREG_B1_UDB06_MSK 0x40006586
+#define CYREG_B1_UDB07_MSK 0x40006587
+#define CYREG_B1_UDB08_MSK 0x40006588
+#define CYREG_B1_UDB09_MSK 0x40006589
+#define CYREG_B1_UDB10_MSK 0x4000658a
+#define CYREG_B1_UDB11_MSK 0x4000658b
+#define CYREG_B1_UDB04_ACTL 0x40006594
+#define CYREG_B1_UDB05_ACTL 0x40006595
+#define CYREG_B1_UDB06_ACTL 0x40006596
+#define CYREG_B1_UDB07_ACTL 0x40006597
+#define CYREG_B1_UDB08_ACTL 0x40006598
+#define CYREG_B1_UDB09_ACTL 0x40006599
+#define CYREG_B1_UDB10_ACTL 0x4000659a
+#define CYREG_B1_UDB11_ACTL 0x4000659b
+#define CYREG_B1_UDB04_MC 0x400065a4
+#define CYREG_B1_UDB05_MC 0x400065a5
+#define CYREG_B1_UDB06_MC 0x400065a6
+#define CYREG_B1_UDB07_MC 0x400065a7
+#define CYREG_B1_UDB08_MC 0x400065a8
+#define CYREG_B1_UDB09_MC 0x400065a9
+#define CYREG_B1_UDB10_MC 0x400065aa
+#define CYREG_B1_UDB11_MC 0x400065ab
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160
+#define CYREG_B0_UDB00_A0_A1 0x40006800
+#define CYREG_B0_UDB01_A0_A1 0x40006802
+#define CYREG_B0_UDB02_A0_A1 0x40006804
+#define CYREG_B0_UDB03_A0_A1 0x40006806
+#define CYREG_B0_UDB04_A0_A1 0x40006808
+#define CYREG_B0_UDB05_A0_A1 0x4000680a
+#define CYREG_B0_UDB06_A0_A1 0x4000680c
+#define CYREG_B0_UDB07_A0_A1 0x4000680e
+#define CYREG_B0_UDB08_A0_A1 0x40006810
+#define CYREG_B0_UDB09_A0_A1 0x40006812
+#define CYREG_B0_UDB10_A0_A1 0x40006814
+#define CYREG_B0_UDB11_A0_A1 0x40006816
+#define CYREG_B0_UDB12_A0_A1 0x40006818
+#define CYREG_B0_UDB13_A0_A1 0x4000681a
+#define CYREG_B0_UDB14_A0_A1 0x4000681c
+#define CYREG_B0_UDB15_A0_A1 0x4000681e
+#define CYREG_B0_UDB00_D0_D1 0x40006840
+#define CYREG_B0_UDB01_D0_D1 0x40006842
+#define CYREG_B0_UDB02_D0_D1 0x40006844
+#define CYREG_B0_UDB03_D0_D1 0x40006846
+#define CYREG_B0_UDB04_D0_D1 0x40006848
+#define CYREG_B0_UDB05_D0_D1 0x4000684a
+#define CYREG_B0_UDB06_D0_D1 0x4000684c
+#define CYREG_B0_UDB07_D0_D1 0x4000684e
+#define CYREG_B0_UDB08_D0_D1 0x40006850
+#define CYREG_B0_UDB09_D0_D1 0x40006852
+#define CYREG_B0_UDB10_D0_D1 0x40006854
+#define CYREG_B0_UDB11_D0_D1 0x40006856
+#define CYREG_B0_UDB12_D0_D1 0x40006858
+#define CYREG_B0_UDB13_D0_D1 0x4000685a
+#define CYREG_B0_UDB14_D0_D1 0x4000685c
+#define CYREG_B0_UDB15_D0_D1 0x4000685e
+#define CYREG_B0_UDB00_F0_F1 0x40006880
+#define CYREG_B0_UDB01_F0_F1 0x40006882
+#define CYREG_B0_UDB02_F0_F1 0x40006884
+#define CYREG_B0_UDB03_F0_F1 0x40006886
+#define CYREG_B0_UDB04_F0_F1 0x40006888
+#define CYREG_B0_UDB05_F0_F1 0x4000688a
+#define CYREG_B0_UDB06_F0_F1 0x4000688c
+#define CYREG_B0_UDB07_F0_F1 0x4000688e
+#define CYREG_B0_UDB08_F0_F1 0x40006890
+#define CYREG_B0_UDB09_F0_F1 0x40006892
+#define CYREG_B0_UDB10_F0_F1 0x40006894
+#define CYREG_B0_UDB11_F0_F1 0x40006896
+#define CYREG_B0_UDB12_F0_F1 0x40006898
+#define CYREG_B0_UDB13_F0_F1 0x4000689a
+#define CYREG_B0_UDB14_F0_F1 0x4000689c
+#define CYREG_B0_UDB15_F0_F1 0x4000689e
+#define CYREG_B0_UDB00_ST_CTL 0x400068c0
+#define CYREG_B0_UDB01_ST_CTL 0x400068c2
+#define CYREG_B0_UDB02_ST_CTL 0x400068c4
+#define CYREG_B0_UDB03_ST_CTL 0x400068c6
+#define CYREG_B0_UDB04_ST_CTL 0x400068c8
+#define CYREG_B0_UDB05_ST_CTL 0x400068ca
+#define CYREG_B0_UDB06_ST_CTL 0x400068cc
+#define CYREG_B0_UDB07_ST_CTL 0x400068ce
+#define CYREG_B0_UDB08_ST_CTL 0x400068d0
+#define CYREG_B0_UDB09_ST_CTL 0x400068d2
+#define CYREG_B0_UDB10_ST_CTL 0x400068d4
+#define CYREG_B0_UDB11_ST_CTL 0x400068d6
+#define CYREG_B0_UDB12_ST_CTL 0x400068d8
+#define CYREG_B0_UDB13_ST_CTL 0x400068da
+#define CYREG_B0_UDB14_ST_CTL 0x400068dc
+#define CYREG_B0_UDB15_ST_CTL 0x400068de
+#define CYREG_B0_UDB00_MSK_ACTL 0x40006900
+#define CYREG_B0_UDB01_MSK_ACTL 0x40006902
+#define CYREG_B0_UDB02_MSK_ACTL 0x40006904
+#define CYREG_B0_UDB03_MSK_ACTL 0x40006906
+#define CYREG_B0_UDB04_MSK_ACTL 0x40006908
+#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a
+#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c
+#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e
+#define CYREG_B0_UDB08_MSK_ACTL 0x40006910
+#define CYREG_B0_UDB09_MSK_ACTL 0x40006912
+#define CYREG_B0_UDB10_MSK_ACTL 0x40006914
+#define CYREG_B0_UDB11_MSK_ACTL 0x40006916
+#define CYREG_B0_UDB12_MSK_ACTL 0x40006918
+#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a
+#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c
+#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e
+#define CYREG_B0_UDB00_MC_00 0x40006940
+#define CYREG_B0_UDB01_MC_00 0x40006942
+#define CYREG_B0_UDB02_MC_00 0x40006944
+#define CYREG_B0_UDB03_MC_00 0x40006946
+#define CYREG_B0_UDB04_MC_00 0x40006948
+#define CYREG_B0_UDB05_MC_00 0x4000694a
+#define CYREG_B0_UDB06_MC_00 0x4000694c
+#define CYREG_B0_UDB07_MC_00 0x4000694e
+#define CYREG_B0_UDB08_MC_00 0x40006950
+#define CYREG_B0_UDB09_MC_00 0x40006952
+#define CYREG_B0_UDB10_MC_00 0x40006954
+#define CYREG_B0_UDB11_MC_00 0x40006956
+#define CYREG_B0_UDB12_MC_00 0x40006958
+#define CYREG_B0_UDB13_MC_00 0x4000695a
+#define CYREG_B0_UDB14_MC_00 0x4000695c
+#define CYREG_B0_UDB15_MC_00 0x4000695e
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160
+#define CYREG_B1_UDB04_A0_A1 0x40006a08
+#define CYREG_B1_UDB05_A0_A1 0x40006a0a
+#define CYREG_B1_UDB06_A0_A1 0x40006a0c
+#define CYREG_B1_UDB07_A0_A1 0x40006a0e
+#define CYREG_B1_UDB08_A0_A1 0x40006a10
+#define CYREG_B1_UDB09_A0_A1 0x40006a12
+#define CYREG_B1_UDB10_A0_A1 0x40006a14
+#define CYREG_B1_UDB11_A0_A1 0x40006a16
+#define CYREG_B1_UDB04_D0_D1 0x40006a48
+#define CYREG_B1_UDB05_D0_D1 0x40006a4a
+#define CYREG_B1_UDB06_D0_D1 0x40006a4c
+#define CYREG_B1_UDB07_D0_D1 0x40006a4e
+#define CYREG_B1_UDB08_D0_D1 0x40006a50
+#define CYREG_B1_UDB09_D0_D1 0x40006a52
+#define CYREG_B1_UDB10_D0_D1 0x40006a54
+#define CYREG_B1_UDB11_D0_D1 0x40006a56
+#define CYREG_B1_UDB04_F0_F1 0x40006a88
+#define CYREG_B1_UDB05_F0_F1 0x40006a8a
+#define CYREG_B1_UDB06_F0_F1 0x40006a8c
+#define CYREG_B1_UDB07_F0_F1 0x40006a8e
+#define CYREG_B1_UDB08_F0_F1 0x40006a90
+#define CYREG_B1_UDB09_F0_F1 0x40006a92
+#define CYREG_B1_UDB10_F0_F1 0x40006a94
+#define CYREG_B1_UDB11_F0_F1 0x40006a96
+#define CYREG_B1_UDB04_ST_CTL 0x40006ac8
+#define CYREG_B1_UDB05_ST_CTL 0x40006aca
+#define CYREG_B1_UDB06_ST_CTL 0x40006acc
+#define CYREG_B1_UDB07_ST_CTL 0x40006ace
+#define CYREG_B1_UDB08_ST_CTL 0x40006ad0
+#define CYREG_B1_UDB09_ST_CTL 0x40006ad2
+#define CYREG_B1_UDB10_ST_CTL 0x40006ad4
+#define CYREG_B1_UDB11_ST_CTL 0x40006ad6
+#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08
+#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a
+#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c
+#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e
+#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10
+#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12
+#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14
+#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16
+#define CYREG_B1_UDB04_MC_00 0x40006b48
+#define CYREG_B1_UDB05_MC_00 0x40006b4a
+#define CYREG_B1_UDB06_MC_00 0x40006b4c
+#define CYREG_B1_UDB07_MC_00 0x40006b4e
+#define CYREG_B1_UDB08_MC_00 0x40006b50
+#define CYREG_B1_UDB09_MC_00 0x40006b52
+#define CYREG_B1_UDB10_MC_00 0x40006b54
+#define CYREG_B1_UDB11_MC_00 0x40006b56
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e
+#define CYREG_B0_UDB00_01_A0 0x40006800
+#define CYREG_B0_UDB01_02_A0 0x40006802
+#define CYREG_B0_UDB02_03_A0 0x40006804
+#define CYREG_B0_UDB03_04_A0 0x40006806
+#define CYREG_B0_UDB04_05_A0 0x40006808
+#define CYREG_B0_UDB05_06_A0 0x4000680a
+#define CYREG_B0_UDB06_07_A0 0x4000680c
+#define CYREG_B0_UDB07_08_A0 0x4000680e
+#define CYREG_B0_UDB08_09_A0 0x40006810
+#define CYREG_B0_UDB09_10_A0 0x40006812
+#define CYREG_B0_UDB10_11_A0 0x40006814
+#define CYREG_B0_UDB11_12_A0 0x40006816
+#define CYREG_B0_UDB12_13_A0 0x40006818
+#define CYREG_B0_UDB13_14_A0 0x4000681a
+#define CYREG_B0_UDB14_15_A0 0x4000681c
+#define CYREG_B0_UDB00_01_A1 0x40006820
+#define CYREG_B0_UDB01_02_A1 0x40006822
+#define CYREG_B0_UDB02_03_A1 0x40006824
+#define CYREG_B0_UDB03_04_A1 0x40006826
+#define CYREG_B0_UDB04_05_A1 0x40006828
+#define CYREG_B0_UDB05_06_A1 0x4000682a
+#define CYREG_B0_UDB06_07_A1 0x4000682c
+#define CYREG_B0_UDB07_08_A1 0x4000682e
+#define CYREG_B0_UDB08_09_A1 0x40006830
+#define CYREG_B0_UDB09_10_A1 0x40006832
+#define CYREG_B0_UDB10_11_A1 0x40006834
+#define CYREG_B0_UDB11_12_A1 0x40006836
+#define CYREG_B0_UDB12_13_A1 0x40006838
+#define CYREG_B0_UDB13_14_A1 0x4000683a
+#define CYREG_B0_UDB14_15_A1 0x4000683c
+#define CYREG_B0_UDB00_01_D0 0x40006840
+#define CYREG_B0_UDB01_02_D0 0x40006842
+#define CYREG_B0_UDB02_03_D0 0x40006844
+#define CYREG_B0_UDB03_04_D0 0x40006846
+#define CYREG_B0_UDB04_05_D0 0x40006848
+#define CYREG_B0_UDB05_06_D0 0x4000684a
+#define CYREG_B0_UDB06_07_D0 0x4000684c
+#define CYREG_B0_UDB07_08_D0 0x4000684e
+#define CYREG_B0_UDB08_09_D0 0x40006850
+#define CYREG_B0_UDB09_10_D0 0x40006852
+#define CYREG_B0_UDB10_11_D0 0x40006854
+#define CYREG_B0_UDB11_12_D0 0x40006856
+#define CYREG_B0_UDB12_13_D0 0x40006858
+#define CYREG_B0_UDB13_14_D0 0x4000685a
+#define CYREG_B0_UDB14_15_D0 0x4000685c
+#define CYREG_B0_UDB00_01_D1 0x40006860
+#define CYREG_B0_UDB01_02_D1 0x40006862
+#define CYREG_B0_UDB02_03_D1 0x40006864
+#define CYREG_B0_UDB03_04_D1 0x40006866
+#define CYREG_B0_UDB04_05_D1 0x40006868
+#define CYREG_B0_UDB05_06_D1 0x4000686a
+#define CYREG_B0_UDB06_07_D1 0x4000686c
+#define CYREG_B0_UDB07_08_D1 0x4000686e
+#define CYREG_B0_UDB08_09_D1 0x40006870
+#define CYREG_B0_UDB09_10_D1 0x40006872
+#define CYREG_B0_UDB10_11_D1 0x40006874
+#define CYREG_B0_UDB11_12_D1 0x40006876
+#define CYREG_B0_UDB12_13_D1 0x40006878
+#define CYREG_B0_UDB13_14_D1 0x4000687a
+#define CYREG_B0_UDB14_15_D1 0x4000687c
+#define CYREG_B0_UDB00_01_F0 0x40006880
+#define CYREG_B0_UDB01_02_F0 0x40006882
+#define CYREG_B0_UDB02_03_F0 0x40006884
+#define CYREG_B0_UDB03_04_F0 0x40006886
+#define CYREG_B0_UDB04_05_F0 0x40006888
+#define CYREG_B0_UDB05_06_F0 0x4000688a
+#define CYREG_B0_UDB06_07_F0 0x4000688c
+#define CYREG_B0_UDB07_08_F0 0x4000688e
+#define CYREG_B0_UDB08_09_F0 0x40006890
+#define CYREG_B0_UDB09_10_F0 0x40006892
+#define CYREG_B0_UDB10_11_F0 0x40006894
+#define CYREG_B0_UDB11_12_F0 0x40006896
+#define CYREG_B0_UDB12_13_F0 0x40006898
+#define CYREG_B0_UDB13_14_F0 0x4000689a
+#define CYREG_B0_UDB14_15_F0 0x4000689c
+#define CYREG_B0_UDB00_01_F1 0x400068a0
+#define CYREG_B0_UDB01_02_F1 0x400068a2
+#define CYREG_B0_UDB02_03_F1 0x400068a4
+#define CYREG_B0_UDB03_04_F1 0x400068a6
+#define CYREG_B0_UDB04_05_F1 0x400068a8
+#define CYREG_B0_UDB05_06_F1 0x400068aa
+#define CYREG_B0_UDB06_07_F1 0x400068ac
+#define CYREG_B0_UDB07_08_F1 0x400068ae
+#define CYREG_B0_UDB08_09_F1 0x400068b0
+#define CYREG_B0_UDB09_10_F1 0x400068b2
+#define CYREG_B0_UDB10_11_F1 0x400068b4
+#define CYREG_B0_UDB11_12_F1 0x400068b6
+#define CYREG_B0_UDB12_13_F1 0x400068b8
+#define CYREG_B0_UDB13_14_F1 0x400068ba
+#define CYREG_B0_UDB14_15_F1 0x400068bc
+#define CYREG_B0_UDB00_01_ST 0x400068c0
+#define CYREG_B0_UDB01_02_ST 0x400068c2
+#define CYREG_B0_UDB02_03_ST 0x400068c4
+#define CYREG_B0_UDB03_04_ST 0x400068c6
+#define CYREG_B0_UDB04_05_ST 0x400068c8
+#define CYREG_B0_UDB05_06_ST 0x400068ca
+#define CYREG_B0_UDB06_07_ST 0x400068cc
+#define CYREG_B0_UDB07_08_ST 0x400068ce
+#define CYREG_B0_UDB08_09_ST 0x400068d0
+#define CYREG_B0_UDB09_10_ST 0x400068d2
+#define CYREG_B0_UDB10_11_ST 0x400068d4
+#define CYREG_B0_UDB11_12_ST 0x400068d6
+#define CYREG_B0_UDB12_13_ST 0x400068d8
+#define CYREG_B0_UDB13_14_ST 0x400068da
+#define CYREG_B0_UDB14_15_ST 0x400068dc
+#define CYREG_B0_UDB00_01_CTL 0x400068e0
+#define CYREG_B0_UDB01_02_CTL 0x400068e2
+#define CYREG_B0_UDB02_03_CTL 0x400068e4
+#define CYREG_B0_UDB03_04_CTL 0x400068e6
+#define CYREG_B0_UDB04_05_CTL 0x400068e8
+#define CYREG_B0_UDB05_06_CTL 0x400068ea
+#define CYREG_B0_UDB06_07_CTL 0x400068ec
+#define CYREG_B0_UDB07_08_CTL 0x400068ee
+#define CYREG_B0_UDB08_09_CTL 0x400068f0
+#define CYREG_B0_UDB09_10_CTL 0x400068f2
+#define CYREG_B0_UDB10_11_CTL 0x400068f4
+#define CYREG_B0_UDB11_12_CTL 0x400068f6
+#define CYREG_B0_UDB12_13_CTL 0x400068f8
+#define CYREG_B0_UDB13_14_CTL 0x400068fa
+#define CYREG_B0_UDB14_15_CTL 0x400068fc
+#define CYREG_B0_UDB00_01_MSK 0x40006900
+#define CYREG_B0_UDB01_02_MSK 0x40006902
+#define CYREG_B0_UDB02_03_MSK 0x40006904
+#define CYREG_B0_UDB03_04_MSK 0x40006906
+#define CYREG_B0_UDB04_05_MSK 0x40006908
+#define CYREG_B0_UDB05_06_MSK 0x4000690a
+#define CYREG_B0_UDB06_07_MSK 0x4000690c
+#define CYREG_B0_UDB07_08_MSK 0x4000690e
+#define CYREG_B0_UDB08_09_MSK 0x40006910
+#define CYREG_B0_UDB09_10_MSK 0x40006912
+#define CYREG_B0_UDB10_11_MSK 0x40006914
+#define CYREG_B0_UDB11_12_MSK 0x40006916
+#define CYREG_B0_UDB12_13_MSK 0x40006918
+#define CYREG_B0_UDB13_14_MSK 0x4000691a
+#define CYREG_B0_UDB14_15_MSK 0x4000691c
+#define CYREG_B0_UDB00_01_ACTL 0x40006920
+#define CYREG_B0_UDB01_02_ACTL 0x40006922
+#define CYREG_B0_UDB02_03_ACTL 0x40006924
+#define CYREG_B0_UDB03_04_ACTL 0x40006926
+#define CYREG_B0_UDB04_05_ACTL 0x40006928
+#define CYREG_B0_UDB05_06_ACTL 0x4000692a
+#define CYREG_B0_UDB06_07_ACTL 0x4000692c
+#define CYREG_B0_UDB07_08_ACTL 0x4000692e
+#define CYREG_B0_UDB08_09_ACTL 0x40006930
+#define CYREG_B0_UDB09_10_ACTL 0x40006932
+#define CYREG_B0_UDB10_11_ACTL 0x40006934
+#define CYREG_B0_UDB11_12_ACTL 0x40006936
+#define CYREG_B0_UDB12_13_ACTL 0x40006938
+#define CYREG_B0_UDB13_14_ACTL 0x4000693a
+#define CYREG_B0_UDB14_15_ACTL 0x4000693c
+#define CYREG_B0_UDB00_01_MC 0x40006940
+#define CYREG_B0_UDB01_02_MC 0x40006942
+#define CYREG_B0_UDB02_03_MC 0x40006944
+#define CYREG_B0_UDB03_04_MC 0x40006946
+#define CYREG_B0_UDB04_05_MC 0x40006948
+#define CYREG_B0_UDB05_06_MC 0x4000694a
+#define CYREG_B0_UDB06_07_MC 0x4000694c
+#define CYREG_B0_UDB07_08_MC 0x4000694e
+#define CYREG_B0_UDB08_09_MC 0x40006950
+#define CYREG_B0_UDB09_10_MC 0x40006952
+#define CYREG_B0_UDB10_11_MC 0x40006954
+#define CYREG_B0_UDB11_12_MC 0x40006956
+#define CYREG_B0_UDB12_13_MC 0x40006958
+#define CYREG_B0_UDB13_14_MC 0x4000695a
+#define CYREG_B0_UDB14_15_MC 0x4000695c
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e
+#define CYREG_B1_UDB04_05_A0 0x40006a08
+#define CYREG_B1_UDB05_06_A0 0x40006a0a
+#define CYREG_B1_UDB06_07_A0 0x40006a0c
+#define CYREG_B1_UDB07_08_A0 0x40006a0e
+#define CYREG_B1_UDB08_09_A0 0x40006a10
+#define CYREG_B1_UDB09_10_A0 0x40006a12
+#define CYREG_B1_UDB10_11_A0 0x40006a14
+#define CYREG_B1_UDB11_12_A0 0x40006a16
+#define CYREG_B1_UDB04_05_A1 0x40006a28
+#define CYREG_B1_UDB05_06_A1 0x40006a2a
+#define CYREG_B1_UDB06_07_A1 0x40006a2c
+#define CYREG_B1_UDB07_08_A1 0x40006a2e
+#define CYREG_B1_UDB08_09_A1 0x40006a30
+#define CYREG_B1_UDB09_10_A1 0x40006a32
+#define CYREG_B1_UDB10_11_A1 0x40006a34
+#define CYREG_B1_UDB11_12_A1 0x40006a36
+#define CYREG_B1_UDB04_05_D0 0x40006a48
+#define CYREG_B1_UDB05_06_D0 0x40006a4a
+#define CYREG_B1_UDB06_07_D0 0x40006a4c
+#define CYREG_B1_UDB07_08_D0 0x40006a4e
+#define CYREG_B1_UDB08_09_D0 0x40006a50
+#define CYREG_B1_UDB09_10_D0 0x40006a52
+#define CYREG_B1_UDB10_11_D0 0x40006a54
+#define CYREG_B1_UDB11_12_D0 0x40006a56
+#define CYREG_B1_UDB04_05_D1 0x40006a68
+#define CYREG_B1_UDB05_06_D1 0x40006a6a
+#define CYREG_B1_UDB06_07_D1 0x40006a6c
+#define CYREG_B1_UDB07_08_D1 0x40006a6e
+#define CYREG_B1_UDB08_09_D1 0x40006a70
+#define CYREG_B1_UDB09_10_D1 0x40006a72
+#define CYREG_B1_UDB10_11_D1 0x40006a74
+#define CYREG_B1_UDB11_12_D1 0x40006a76
+#define CYREG_B1_UDB04_05_F0 0x40006a88
+#define CYREG_B1_UDB05_06_F0 0x40006a8a
+#define CYREG_B1_UDB06_07_F0 0x40006a8c
+#define CYREG_B1_UDB07_08_F0 0x40006a8e
+#define CYREG_B1_UDB08_09_F0 0x40006a90
+#define CYREG_B1_UDB09_10_F0 0x40006a92
+#define CYREG_B1_UDB10_11_F0 0x40006a94
+#define CYREG_B1_UDB11_12_F0 0x40006a96
+#define CYREG_B1_UDB04_05_F1 0x40006aa8
+#define CYREG_B1_UDB05_06_F1 0x40006aaa
+#define CYREG_B1_UDB06_07_F1 0x40006aac
+#define CYREG_B1_UDB07_08_F1 0x40006aae
+#define CYREG_B1_UDB08_09_F1 0x40006ab0
+#define CYREG_B1_UDB09_10_F1 0x40006ab2
+#define CYREG_B1_UDB10_11_F1 0x40006ab4
+#define CYREG_B1_UDB11_12_F1 0x40006ab6
+#define CYREG_B1_UDB04_05_ST 0x40006ac8
+#define CYREG_B1_UDB05_06_ST 0x40006aca
+#define CYREG_B1_UDB06_07_ST 0x40006acc
+#define CYREG_B1_UDB07_08_ST 0x40006ace
+#define CYREG_B1_UDB08_09_ST 0x40006ad0
+#define CYREG_B1_UDB09_10_ST 0x40006ad2
+#define CYREG_B1_UDB10_11_ST 0x40006ad4
+#define CYREG_B1_UDB11_12_ST 0x40006ad6
+#define CYREG_B1_UDB04_05_CTL 0x40006ae8
+#define CYREG_B1_UDB05_06_CTL 0x40006aea
+#define CYREG_B1_UDB06_07_CTL 0x40006aec
+#define CYREG_B1_UDB07_08_CTL 0x40006aee
+#define CYREG_B1_UDB08_09_CTL 0x40006af0
+#define CYREG_B1_UDB09_10_CTL 0x40006af2
+#define CYREG_B1_UDB10_11_CTL 0x40006af4
+#define CYREG_B1_UDB11_12_CTL 0x40006af6
+#define CYREG_B1_UDB04_05_MSK 0x40006b08
+#define CYREG_B1_UDB05_06_MSK 0x40006b0a
+#define CYREG_B1_UDB06_07_MSK 0x40006b0c
+#define CYREG_B1_UDB07_08_MSK 0x40006b0e
+#define CYREG_B1_UDB08_09_MSK 0x40006b10
+#define CYREG_B1_UDB09_10_MSK 0x40006b12
+#define CYREG_B1_UDB10_11_MSK 0x40006b14
+#define CYREG_B1_UDB11_12_MSK 0x40006b16
+#define CYREG_B1_UDB04_05_ACTL 0x40006b28
+#define CYREG_B1_UDB05_06_ACTL 0x40006b2a
+#define CYREG_B1_UDB06_07_ACTL 0x40006b2c
+#define CYREG_B1_UDB07_08_ACTL 0x40006b2e
+#define CYREG_B1_UDB08_09_ACTL 0x40006b30
+#define CYREG_B1_UDB09_10_ACTL 0x40006b32
+#define CYREG_B1_UDB10_11_ACTL 0x40006b34
+#define CYREG_B1_UDB11_12_ACTL 0x40006b36
+#define CYREG_B1_UDB04_05_MC 0x40006b48
+#define CYREG_B1_UDB05_06_MC 0x40006b4a
+#define CYREG_B1_UDB06_07_MC 0x40006b4c
+#define CYREG_B1_UDB07_08_MC 0x40006b4e
+#define CYREG_B1_UDB08_09_MC 0x40006b50
+#define CYREG_B1_UDB09_10_MC 0x40006b52
+#define CYREG_B1_UDB10_11_MC 0x40006b54
+#define CYREG_B1_UDB11_12_MC 0x40006b56
+#define CYDEV_PHUB_BASE 0x40007000
+#define CYDEV_PHUB_SIZE 0x00000c00
+#define CYREG_PHUB_CFG 0x40007000
+#define CYREG_PHUB_ERR 0x40007004
+#define CYREG_PHUB_ERR_ADR 0x40007008
+#define CYDEV_PHUB_CH0_BASE 0x40007010
+#define CYDEV_PHUB_CH0_SIZE 0x0000000c
+#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010
+#define CYREG_PHUB_CH0_ACTION 0x40007014
+#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018
+#define CYDEV_PHUB_CH1_BASE 0x40007020
+#define CYDEV_PHUB_CH1_SIZE 0x0000000c
+#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020
+#define CYREG_PHUB_CH1_ACTION 0x40007024
+#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028
+#define CYDEV_PHUB_CH2_BASE 0x40007030
+#define CYDEV_PHUB_CH2_SIZE 0x0000000c
+#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030
+#define CYREG_PHUB_CH2_ACTION 0x40007034
+#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038
+#define CYDEV_PHUB_CH3_BASE 0x40007040
+#define CYDEV_PHUB_CH3_SIZE 0x0000000c
+#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040
+#define CYREG_PHUB_CH3_ACTION 0x40007044
+#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048
+#define CYDEV_PHUB_CH4_BASE 0x40007050
+#define CYDEV_PHUB_CH4_SIZE 0x0000000c
+#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050
+#define CYREG_PHUB_CH4_ACTION 0x40007054
+#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058
+#define CYDEV_PHUB_CH5_BASE 0x40007060
+#define CYDEV_PHUB_CH5_SIZE 0x0000000c
+#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060
+#define CYREG_PHUB_CH5_ACTION 0x40007064
+#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068
+#define CYDEV_PHUB_CH6_BASE 0x40007070
+#define CYDEV_PHUB_CH6_SIZE 0x0000000c
+#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070
+#define CYREG_PHUB_CH6_ACTION 0x40007074
+#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078
+#define CYDEV_PHUB_CH7_BASE 0x40007080
+#define CYDEV_PHUB_CH7_SIZE 0x0000000c
+#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080
+#define CYREG_PHUB_CH7_ACTION 0x40007084
+#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088
+#define CYDEV_PHUB_CH8_BASE 0x40007090
+#define CYDEV_PHUB_CH8_SIZE 0x0000000c
+#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090
+#define CYREG_PHUB_CH8_ACTION 0x40007094
+#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098
+#define CYDEV_PHUB_CH9_BASE 0x400070a0
+#define CYDEV_PHUB_CH9_SIZE 0x0000000c
+#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0
+#define CYREG_PHUB_CH9_ACTION 0x400070a4
+#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8
+#define CYDEV_PHUB_CH10_BASE 0x400070b0
+#define CYDEV_PHUB_CH10_SIZE 0x0000000c
+#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0
+#define CYREG_PHUB_CH10_ACTION 0x400070b4
+#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8
+#define CYDEV_PHUB_CH11_BASE 0x400070c0
+#define CYDEV_PHUB_CH11_SIZE 0x0000000c
+#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0
+#define CYREG_PHUB_CH11_ACTION 0x400070c4
+#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8
+#define CYDEV_PHUB_CH12_BASE 0x400070d0
+#define CYDEV_PHUB_CH12_SIZE 0x0000000c
+#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0
+#define CYREG_PHUB_CH12_ACTION 0x400070d4
+#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8
+#define CYDEV_PHUB_CH13_BASE 0x400070e0
+#define CYDEV_PHUB_CH13_SIZE 0x0000000c
+#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0
+#define CYREG_PHUB_CH13_ACTION 0x400070e4
+#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8
+#define CYDEV_PHUB_CH14_BASE 0x400070f0
+#define CYDEV_PHUB_CH14_SIZE 0x0000000c
+#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0
+#define CYREG_PHUB_CH14_ACTION 0x400070f4
+#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8
+#define CYDEV_PHUB_CH15_BASE 0x40007100
+#define CYDEV_PHUB_CH15_SIZE 0x0000000c
+#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100
+#define CYREG_PHUB_CH15_ACTION 0x40007104
+#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108
+#define CYDEV_PHUB_CH16_BASE 0x40007110
+#define CYDEV_PHUB_CH16_SIZE 0x0000000c
+#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110
+#define CYREG_PHUB_CH16_ACTION 0x40007114
+#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118
+#define CYDEV_PHUB_CH17_BASE 0x40007120
+#define CYDEV_PHUB_CH17_SIZE 0x0000000c
+#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120
+#define CYREG_PHUB_CH17_ACTION 0x40007124
+#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128
+#define CYDEV_PHUB_CH18_BASE 0x40007130
+#define CYDEV_PHUB_CH18_SIZE 0x0000000c
+#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130
+#define CYREG_PHUB_CH18_ACTION 0x40007134
+#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138
+#define CYDEV_PHUB_CH19_BASE 0x40007140
+#define CYDEV_PHUB_CH19_SIZE 0x0000000c
+#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140
+#define CYREG_PHUB_CH19_ACTION 0x40007144
+#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148
+#define CYDEV_PHUB_CH20_BASE 0x40007150
+#define CYDEV_PHUB_CH20_SIZE 0x0000000c
+#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150
+#define CYREG_PHUB_CH20_ACTION 0x40007154
+#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158
+#define CYDEV_PHUB_CH21_BASE 0x40007160
+#define CYDEV_PHUB_CH21_SIZE 0x0000000c
+#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160
+#define CYREG_PHUB_CH21_ACTION 0x40007164
+#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168
+#define CYDEV_PHUB_CH22_BASE 0x40007170
+#define CYDEV_PHUB_CH22_SIZE 0x0000000c
+#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170
+#define CYREG_PHUB_CH22_ACTION 0x40007174
+#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178
+#define CYDEV_PHUB_CH23_BASE 0x40007180
+#define CYDEV_PHUB_CH23_SIZE 0x0000000c
+#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180
+#define CYREG_PHUB_CH23_ACTION 0x40007184
+#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600
+#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608
+#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610
+#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618
+#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620
+#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628
+#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630
+#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638
+#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640
+#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648
+#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650
+#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658
+#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660
+#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668
+#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670
+#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678
+#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680
+#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688
+#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690
+#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698
+#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0
+#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8
+#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0
+#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008
+#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8
+#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800
+#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808
+#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810
+#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818
+#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820
+#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828
+#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830
+#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838
+#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840
+#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848
+#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850
+#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858
+#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860
+#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868
+#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870
+#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878
+#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880
+#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888
+#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890
+#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898
+#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0
+#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8
+#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0
+#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8
+#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0
+#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8
+#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0
+#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8
+#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0
+#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8
+#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0
+#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8
+#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900
+#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908
+#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910
+#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918
+#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920
+#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928
+#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930
+#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938
+#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940
+#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948
+#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950
+#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958
+#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960
+#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968
+#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970
+#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978
+#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980
+#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988
+#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990
+#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998
+#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0
+#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8
+#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0
+#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8
+#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0
+#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8
+#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0
+#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8
+#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0
+#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8
+#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0
+#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8
+#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00
+#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08
+#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10
+#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18
+#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20
+#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28
+#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30
+#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38
+#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40
+#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48
+#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50
+#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58
+#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60
+#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68
+#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70
+#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78
+#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80
+#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88
+#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90
+#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98
+#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0
+#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8
+#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0
+#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8
+#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0
+#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8
+#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0
+#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8
+#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0
+#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8
+#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0
+#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8
+#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00
+#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08
+#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10
+#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18
+#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20
+#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28
+#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30
+#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38
+#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40
+#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48
+#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50
+#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58
+#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60
+#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68
+#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70
+#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78
+#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80
+#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88
+#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90
+#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98
+#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0
+#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8
+#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0
+#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8
+#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0
+#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8
+#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0
+#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8
+#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0
+#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8
+#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0
+#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008
+#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8
+#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc
+#define CYDEV_EE_BASE 0x40008000
+#define CYDEV_EE_SIZE 0x00000800
+#define CYREG_EE_DATA_MBASE 0x40008000
+#define CYREG_EE_DATA_MSIZE 0x00000800
+#define CYDEV_CAN0_BASE 0x4000a000
+#define CYDEV_CAN0_SIZE 0x000002a0
+#define CYDEV_CAN0_CSR_BASE 0x4000a000
+#define CYDEV_CAN0_CSR_SIZE 0x00000018
+#define CYREG_CAN0_CSR_INT_SR 0x4000a000
+#define CYREG_CAN0_CSR_INT_EN 0x4000a004
+#define CYREG_CAN0_CSR_BUF_SR 0x4000a008
+#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c
+#define CYREG_CAN0_CSR_CMD 0x4000a010
+#define CYREG_CAN0_CSR_CFG 0x4000a014
+#define CYDEV_CAN0_TX0_BASE 0x4000a020
+#define CYDEV_CAN0_TX0_SIZE 0x00000010
+#define CYREG_CAN0_TX0_CMD 0x4000a020
+#define CYREG_CAN0_TX0_ID 0x4000a024
+#define CYREG_CAN0_TX0_DH 0x4000a028
+#define CYREG_CAN0_TX0_DL 0x4000a02c
+#define CYDEV_CAN0_TX1_BASE 0x4000a030
+#define CYDEV_CAN0_TX1_SIZE 0x00000010
+#define CYREG_CAN0_TX1_CMD 0x4000a030
+#define CYREG_CAN0_TX1_ID 0x4000a034
+#define CYREG_CAN0_TX1_DH 0x4000a038
+#define CYREG_CAN0_TX1_DL 0x4000a03c
+#define CYDEV_CAN0_TX2_BASE 0x4000a040
+#define CYDEV_CAN0_TX2_SIZE 0x00000010
+#define CYREG_CAN0_TX2_CMD 0x4000a040
+#define CYREG_CAN0_TX2_ID 0x4000a044
+#define CYREG_CAN0_TX2_DH 0x4000a048
+#define CYREG_CAN0_TX2_DL 0x4000a04c
+#define CYDEV_CAN0_TX3_BASE 0x4000a050
+#define CYDEV_CAN0_TX3_SIZE 0x00000010
+#define CYREG_CAN0_TX3_CMD 0x4000a050
+#define CYREG_CAN0_TX3_ID 0x4000a054
+#define CYREG_CAN0_TX3_DH 0x4000a058
+#define CYREG_CAN0_TX3_DL 0x4000a05c
+#define CYDEV_CAN0_TX4_BASE 0x4000a060
+#define CYDEV_CAN0_TX4_SIZE 0x00000010
+#define CYREG_CAN0_TX4_CMD 0x4000a060
+#define CYREG_CAN0_TX4_ID 0x4000a064
+#define CYREG_CAN0_TX4_DH 0x4000a068
+#define CYREG_CAN0_TX4_DL 0x4000a06c
+#define CYDEV_CAN0_TX5_BASE 0x4000a070
+#define CYDEV_CAN0_TX5_SIZE 0x00000010
+#define CYREG_CAN0_TX5_CMD 0x4000a070
+#define CYREG_CAN0_TX5_ID 0x4000a074
+#define CYREG_CAN0_TX5_DH 0x4000a078
+#define CYREG_CAN0_TX5_DL 0x4000a07c
+#define CYDEV_CAN0_TX6_BASE 0x4000a080
+#define CYDEV_CAN0_TX6_SIZE 0x00000010
+#define CYREG_CAN0_TX6_CMD 0x4000a080
+#define CYREG_CAN0_TX6_ID 0x4000a084
+#define CYREG_CAN0_TX6_DH 0x4000a088
+#define CYREG_CAN0_TX6_DL 0x4000a08c
+#define CYDEV_CAN0_TX7_BASE 0x4000a090
+#define CYDEV_CAN0_TX7_SIZE 0x00000010
+#define CYREG_CAN0_TX7_CMD 0x4000a090
+#define CYREG_CAN0_TX7_ID 0x4000a094
+#define CYREG_CAN0_TX7_DH 0x4000a098
+#define CYREG_CAN0_TX7_DL 0x4000a09c
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0
+#define CYDEV_CAN0_RX0_SIZE 0x00000020
+#define CYREG_CAN0_RX0_CMD 0x4000a0a0
+#define CYREG_CAN0_RX0_ID 0x4000a0a4
+#define CYREG_CAN0_RX0_DH 0x4000a0a8
+#define CYREG_CAN0_RX0_DL 0x4000a0ac
+#define CYREG_CAN0_RX0_AMR 0x4000a0b0
+#define CYREG_CAN0_RX0_ACR 0x4000a0b4
+#define CYREG_CAN0_RX0_AMRD 0x4000a0b8
+#define CYREG_CAN0_RX0_ACRD 0x4000a0bc
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0
+#define CYDEV_CAN0_RX1_SIZE 0x00000020
+#define CYREG_CAN0_RX1_CMD 0x4000a0c0
+#define CYREG_CAN0_RX1_ID 0x4000a0c4
+#define CYREG_CAN0_RX1_DH 0x4000a0c8
+#define CYREG_CAN0_RX1_DL 0x4000a0cc
+#define CYREG_CAN0_RX1_AMR 0x4000a0d0
+#define CYREG_CAN0_RX1_ACR 0x4000a0d4
+#define CYREG_CAN0_RX1_AMRD 0x4000a0d8
+#define CYREG_CAN0_RX1_ACRD 0x4000a0dc
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0
+#define CYDEV_CAN0_RX2_SIZE 0x00000020
+#define CYREG_CAN0_RX2_CMD 0x4000a0e0
+#define CYREG_CAN0_RX2_ID 0x4000a0e4
+#define CYREG_CAN0_RX2_DH 0x4000a0e8
+#define CYREG_CAN0_RX2_DL 0x4000a0ec
+#define CYREG_CAN0_RX2_AMR 0x4000a0f0
+#define CYREG_CAN0_RX2_ACR 0x4000a0f4
+#define CYREG_CAN0_RX2_AMRD 0x4000a0f8
+#define CYREG_CAN0_RX2_ACRD 0x4000a0fc
+#define CYDEV_CAN0_RX3_BASE 0x4000a100
+#define CYDEV_CAN0_RX3_SIZE 0x00000020
+#define CYREG_CAN0_RX3_CMD 0x4000a100
+#define CYREG_CAN0_RX3_ID 0x4000a104
+#define CYREG_CAN0_RX3_DH 0x4000a108
+#define CYREG_CAN0_RX3_DL 0x4000a10c
+#define CYREG_CAN0_RX3_AMR 0x4000a110
+#define CYREG_CAN0_RX3_ACR 0x4000a114
+#define CYREG_CAN0_RX3_AMRD 0x4000a118
+#define CYREG_CAN0_RX3_ACRD 0x4000a11c
+#define CYDEV_CAN0_RX4_BASE 0x4000a120
+#define CYDEV_CAN0_RX4_SIZE 0x00000020
+#define CYREG_CAN0_RX4_CMD 0x4000a120
+#define CYREG_CAN0_RX4_ID 0x4000a124
+#define CYREG_CAN0_RX4_DH 0x4000a128
+#define CYREG_CAN0_RX4_DL 0x4000a12c
+#define CYREG_CAN0_RX4_AMR 0x4000a130
+#define CYREG_CAN0_RX4_ACR 0x4000a134
+#define CYREG_CAN0_RX4_AMRD 0x4000a138
+#define CYREG_CAN0_RX4_ACRD 0x4000a13c
+#define CYDEV_CAN0_RX5_BASE 0x4000a140
+#define CYDEV_CAN0_RX5_SIZE 0x00000020
+#define CYREG_CAN0_RX5_CMD 0x4000a140
+#define CYREG_CAN0_RX5_ID 0x4000a144
+#define CYREG_CAN0_RX5_DH 0x4000a148
+#define CYREG_CAN0_RX5_DL 0x4000a14c
+#define CYREG_CAN0_RX5_AMR 0x4000a150
+#define CYREG_CAN0_RX5_ACR 0x4000a154
+#define CYREG_CAN0_RX5_AMRD 0x4000a158
+#define CYREG_CAN0_RX5_ACRD 0x4000a15c
+#define CYDEV_CAN0_RX6_BASE 0x4000a160
+#define CYDEV_CAN0_RX6_SIZE 0x00000020
+#define CYREG_CAN0_RX6_CMD 0x4000a160
+#define CYREG_CAN0_RX6_ID 0x4000a164
+#define CYREG_CAN0_RX6_DH 0x4000a168
+#define CYREG_CAN0_RX6_DL 0x4000a16c
+#define CYREG_CAN0_RX6_AMR 0x4000a170
+#define CYREG_CAN0_RX6_ACR 0x4000a174
+#define CYREG_CAN0_RX6_AMRD 0x4000a178
+#define CYREG_CAN0_RX6_ACRD 0x4000a17c
+#define CYDEV_CAN0_RX7_BASE 0x4000a180
+#define CYDEV_CAN0_RX7_SIZE 0x00000020
+#define CYREG_CAN0_RX7_CMD 0x4000a180
+#define CYREG_CAN0_RX7_ID 0x4000a184
+#define CYREG_CAN0_RX7_DH 0x4000a188
+#define CYREG_CAN0_RX7_DL 0x4000a18c
+#define CYREG_CAN0_RX7_AMR 0x4000a190
+#define CYREG_CAN0_RX7_ACR 0x4000a194
+#define CYREG_CAN0_RX7_AMRD 0x4000a198
+#define CYREG_CAN0_RX7_ACRD 0x4000a19c
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0
+#define CYDEV_CAN0_RX8_SIZE 0x00000020
+#define CYREG_CAN0_RX8_CMD 0x4000a1a0
+#define CYREG_CAN0_RX8_ID 0x4000a1a4
+#define CYREG_CAN0_RX8_DH 0x4000a1a8
+#define CYREG_CAN0_RX8_DL 0x4000a1ac
+#define CYREG_CAN0_RX8_AMR 0x4000a1b0
+#define CYREG_CAN0_RX8_ACR 0x4000a1b4
+#define CYREG_CAN0_RX8_AMRD 0x4000a1b8
+#define CYREG_CAN0_RX8_ACRD 0x4000a1bc
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0
+#define CYDEV_CAN0_RX9_SIZE 0x00000020
+#define CYREG_CAN0_RX9_CMD 0x4000a1c0
+#define CYREG_CAN0_RX9_ID 0x4000a1c4
+#define CYREG_CAN0_RX9_DH 0x4000a1c8
+#define CYREG_CAN0_RX9_DL 0x4000a1cc
+#define CYREG_CAN0_RX9_AMR 0x4000a1d0
+#define CYREG_CAN0_RX9_ACR 0x4000a1d4
+#define CYREG_CAN0_RX9_AMRD 0x4000a1d8
+#define CYREG_CAN0_RX9_ACRD 0x4000a1dc
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0
+#define CYDEV_CAN0_RX10_SIZE 0x00000020
+#define CYREG_CAN0_RX10_CMD 0x4000a1e0
+#define CYREG_CAN0_RX10_ID 0x4000a1e4
+#define CYREG_CAN0_RX10_DH 0x4000a1e8
+#define CYREG_CAN0_RX10_DL 0x4000a1ec
+#define CYREG_CAN0_RX10_AMR 0x4000a1f0
+#define CYREG_CAN0_RX10_ACR 0x4000a1f4
+#define CYREG_CAN0_RX10_AMRD 0x4000a1f8
+#define CYREG_CAN0_RX10_ACRD 0x4000a1fc
+#define CYDEV_CAN0_RX11_BASE 0x4000a200
+#define CYDEV_CAN0_RX11_SIZE 0x00000020
+#define CYREG_CAN0_RX11_CMD 0x4000a200
+#define CYREG_CAN0_RX11_ID 0x4000a204
+#define CYREG_CAN0_RX11_DH 0x4000a208
+#define CYREG_CAN0_RX11_DL 0x4000a20c
+#define CYREG_CAN0_RX11_AMR 0x4000a210
+#define CYREG_CAN0_RX11_ACR 0x4000a214
+#define CYREG_CAN0_RX11_AMRD 0x4000a218
+#define CYREG_CAN0_RX11_ACRD 0x4000a21c
+#define CYDEV_CAN0_RX12_BASE 0x4000a220
+#define CYDEV_CAN0_RX12_SIZE 0x00000020
+#define CYREG_CAN0_RX12_CMD 0x4000a220
+#define CYREG_CAN0_RX12_ID 0x4000a224
+#define CYREG_CAN0_RX12_DH 0x4000a228
+#define CYREG_CAN0_RX12_DL 0x4000a22c
+#define CYREG_CAN0_RX12_AMR 0x4000a230
+#define CYREG_CAN0_RX12_ACR 0x4000a234
+#define CYREG_CAN0_RX12_AMRD 0x4000a238
+#define CYREG_CAN0_RX12_ACRD 0x4000a23c
+#define CYDEV_CAN0_RX13_BASE 0x4000a240
+#define CYDEV_CAN0_RX13_SIZE 0x00000020
+#define CYREG_CAN0_RX13_CMD 0x4000a240
+#define CYREG_CAN0_RX13_ID 0x4000a244
+#define CYREG_CAN0_RX13_DH 0x4000a248
+#define CYREG_CAN0_RX13_DL 0x4000a24c
+#define CYREG_CAN0_RX13_AMR 0x4000a250
+#define CYREG_CAN0_RX13_ACR 0x4000a254
+#define CYREG_CAN0_RX13_AMRD 0x4000a258
+#define CYREG_CAN0_RX13_ACRD 0x4000a25c
+#define CYDEV_CAN0_RX14_BASE 0x4000a260
+#define CYDEV_CAN0_RX14_SIZE 0x00000020
+#define CYREG_CAN0_RX14_CMD 0x4000a260
+#define CYREG_CAN0_RX14_ID 0x4000a264
+#define CYREG_CAN0_RX14_DH 0x4000a268
+#define CYREG_CAN0_RX14_DL 0x4000a26c
+#define CYREG_CAN0_RX14_AMR 0x4000a270
+#define CYREG_CAN0_RX14_ACR 0x4000a274
+#define CYREG_CAN0_RX14_AMRD 0x4000a278
+#define CYREG_CAN0_RX14_ACRD 0x4000a27c
+#define CYDEV_CAN0_RX15_BASE 0x4000a280
+#define CYDEV_CAN0_RX15_SIZE 0x00000020
+#define CYREG_CAN0_RX15_CMD 0x4000a280
+#define CYREG_CAN0_RX15_ID 0x4000a284
+#define CYREG_CAN0_RX15_DH 0x4000a288
+#define CYREG_CAN0_RX15_DL 0x4000a28c
+#define CYREG_CAN0_RX15_AMR 0x4000a290
+#define CYREG_CAN0_RX15_ACR 0x4000a294
+#define CYREG_CAN0_RX15_AMRD 0x4000a298
+#define CYREG_CAN0_RX15_ACRD 0x4000a29c
+#define CYDEV_DFB0_BASE 0x4000c000
+#define CYDEV_DFB0_SIZE 0x000007b5
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200
+#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000
+#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200
+#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200
+#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100
+#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400
+#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100
+#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500
+#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100
+#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600
+#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040
+#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700
+#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040
+#define CYREG_DFB0_CR 0x4000c780
+#define CYREG_DFB0_SR 0x4000c784
+#define CYREG_DFB0_RAM_EN 0x4000c788
+#define CYREG_DFB0_RAM_DIR 0x4000c78c
+#define CYREG_DFB0_SEMA 0x4000c790
+#define CYREG_DFB0_DSI_CTRL 0x4000c794
+#define CYREG_DFB0_INT_CTRL 0x4000c798
+#define CYREG_DFB0_DMA_CTRL 0x4000c79c
+#define CYREG_DFB0_STAGEA 0x4000c7a0
+#define CYREG_DFB0_STAGEAM 0x4000c7a1
+#define CYREG_DFB0_STAGEAH 0x4000c7a2
+#define CYREG_DFB0_STAGEB 0x4000c7a4
+#define CYREG_DFB0_STAGEBM 0x4000c7a5
+#define CYREG_DFB0_STAGEBH 0x4000c7a6
+#define CYREG_DFB0_HOLDA 0x4000c7a8
+#define CYREG_DFB0_HOLDAM 0x4000c7a9
+#define CYREG_DFB0_HOLDAH 0x4000c7aa
+#define CYREG_DFB0_HOLDAS 0x4000c7ab
+#define CYREG_DFB0_HOLDB 0x4000c7ac
+#define CYREG_DFB0_HOLDBM 0x4000c7ad
+#define CYREG_DFB0_HOLDBH 0x4000c7ae
+#define CYREG_DFB0_HOLDBS 0x4000c7af
+#define CYREG_DFB0_COHER 0x4000c7b0
+#define CYREG_DFB0_DALIGN 0x4000c7b4
+#define CYDEV_UCFG_BASE 0x40010000
+#define CYDEV_UCFG_SIZE 0x00005040
+#define CYDEV_UCFG_B0_BASE 0x40010000
+#define CYDEV_UCFG_B0_SIZE 0x00000fef
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070
+#define CYREG_B0_P0_U0_PLD_IT0 0x40010000
+#define CYREG_B0_P0_U0_PLD_IT1 0x40010004
+#define CYREG_B0_P0_U0_PLD_IT2 0x40010008
+#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c
+#define CYREG_B0_P0_U0_PLD_IT4 0x40010010
+#define CYREG_B0_P0_U0_PLD_IT5 0x40010014
+#define CYREG_B0_P0_U0_PLD_IT6 0x40010018
+#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c
+#define CYREG_B0_P0_U0_PLD_IT8 0x40010020
+#define CYREG_B0_P0_U0_PLD_IT9 0x40010024
+#define CYREG_B0_P0_U0_PLD_IT10 0x40010028
+#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c
+#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030
+#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032
+#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034
+#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036
+#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038
+#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a
+#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c
+#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e
+#define CYREG_B0_P0_U0_CFG0 0x40010040
+#define CYREG_B0_P0_U0_CFG1 0x40010041
+#define CYREG_B0_P0_U0_CFG2 0x40010042
+#define CYREG_B0_P0_U0_CFG3 0x40010043
+#define CYREG_B0_P0_U0_CFG4 0x40010044
+#define CYREG_B0_P0_U0_CFG5 0x40010045
+#define CYREG_B0_P0_U0_CFG6 0x40010046
+#define CYREG_B0_P0_U0_CFG7 0x40010047
+#define CYREG_B0_P0_U0_CFG8 0x40010048
+#define CYREG_B0_P0_U0_CFG9 0x40010049
+#define CYREG_B0_P0_U0_CFG10 0x4001004a
+#define CYREG_B0_P0_U0_CFG11 0x4001004b
+#define CYREG_B0_P0_U0_CFG12 0x4001004c
+#define CYREG_B0_P0_U0_CFG13 0x4001004d
+#define CYREG_B0_P0_U0_CFG14 0x4001004e
+#define CYREG_B0_P0_U0_CFG15 0x4001004f
+#define CYREG_B0_P0_U0_CFG16 0x40010050
+#define CYREG_B0_P0_U0_CFG17 0x40010051
+#define CYREG_B0_P0_U0_CFG18 0x40010052
+#define CYREG_B0_P0_U0_CFG19 0x40010053
+#define CYREG_B0_P0_U0_CFG20 0x40010054
+#define CYREG_B0_P0_U0_CFG21 0x40010055
+#define CYREG_B0_P0_U0_CFG22 0x40010056
+#define CYREG_B0_P0_U0_CFG23 0x40010057
+#define CYREG_B0_P0_U0_CFG24 0x40010058
+#define CYREG_B0_P0_U0_CFG25 0x40010059
+#define CYREG_B0_P0_U0_CFG26 0x4001005a
+#define CYREG_B0_P0_U0_CFG27 0x4001005b
+#define CYREG_B0_P0_U0_CFG28 0x4001005c
+#define CYREG_B0_P0_U0_CFG29 0x4001005d
+#define CYREG_B0_P0_U0_CFG30 0x4001005e
+#define CYREG_B0_P0_U0_CFG31 0x4001005f
+#define CYREG_B0_P0_U0_DCFG0 0x40010060
+#define CYREG_B0_P0_U0_DCFG1 0x40010062
+#define CYREG_B0_P0_U0_DCFG2 0x40010064
+#define CYREG_B0_P0_U0_DCFG3 0x40010066
+#define CYREG_B0_P0_U0_DCFG4 0x40010068
+#define CYREG_B0_P0_U0_DCFG5 0x4001006a
+#define CYREG_B0_P0_U0_DCFG6 0x4001006c
+#define CYREG_B0_P0_U0_DCFG7 0x4001006e
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070
+#define CYREG_B0_P0_U1_PLD_IT0 0x40010080
+#define CYREG_B0_P0_U1_PLD_IT1 0x40010084
+#define CYREG_B0_P0_U1_PLD_IT2 0x40010088
+#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c
+#define CYREG_B0_P0_U1_PLD_IT4 0x40010090
+#define CYREG_B0_P0_U1_PLD_IT5 0x40010094
+#define CYREG_B0_P0_U1_PLD_IT6 0x40010098
+#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c
+#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0
+#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4
+#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8
+#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac
+#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0
+#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2
+#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4
+#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6
+#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8
+#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba
+#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc
+#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be
+#define CYREG_B0_P0_U1_CFG0 0x400100c0
+#define CYREG_B0_P0_U1_CFG1 0x400100c1
+#define CYREG_B0_P0_U1_CFG2 0x400100c2
+#define CYREG_B0_P0_U1_CFG3 0x400100c3
+#define CYREG_B0_P0_U1_CFG4 0x400100c4
+#define CYREG_B0_P0_U1_CFG5 0x400100c5
+#define CYREG_B0_P0_U1_CFG6 0x400100c6
+#define CYREG_B0_P0_U1_CFG7 0x400100c7
+#define CYREG_B0_P0_U1_CFG8 0x400100c8
+#define CYREG_B0_P0_U1_CFG9 0x400100c9
+#define CYREG_B0_P0_U1_CFG10 0x400100ca
+#define CYREG_B0_P0_U1_CFG11 0x400100cb
+#define CYREG_B0_P0_U1_CFG12 0x400100cc
+#define CYREG_B0_P0_U1_CFG13 0x400100cd
+#define CYREG_B0_P0_U1_CFG14 0x400100ce
+#define CYREG_B0_P0_U1_CFG15 0x400100cf
+#define CYREG_B0_P0_U1_CFG16 0x400100d0
+#define CYREG_B0_P0_U1_CFG17 0x400100d1
+#define CYREG_B0_P0_U1_CFG18 0x400100d2
+#define CYREG_B0_P0_U1_CFG19 0x400100d3
+#define CYREG_B0_P0_U1_CFG20 0x400100d4
+#define CYREG_B0_P0_U1_CFG21 0x400100d5
+#define CYREG_B0_P0_U1_CFG22 0x400100d6
+#define CYREG_B0_P0_U1_CFG23 0x400100d7
+#define CYREG_B0_P0_U1_CFG24 0x400100d8
+#define CYREG_B0_P0_U1_CFG25 0x400100d9
+#define CYREG_B0_P0_U1_CFG26 0x400100da
+#define CYREG_B0_P0_U1_CFG27 0x400100db
+#define CYREG_B0_P0_U1_CFG28 0x400100dc
+#define CYREG_B0_P0_U1_CFG29 0x400100dd
+#define CYREG_B0_P0_U1_CFG30 0x400100de
+#define CYREG_B0_P0_U1_CFG31 0x400100df
+#define CYREG_B0_P0_U1_DCFG0 0x400100e0
+#define CYREG_B0_P0_U1_DCFG1 0x400100e2
+#define CYREG_B0_P0_U1_DCFG2 0x400100e4
+#define CYREG_B0_P0_U1_DCFG3 0x400100e6
+#define CYREG_B0_P0_U1_DCFG4 0x400100e8
+#define CYREG_B0_P0_U1_DCFG5 0x400100ea
+#define CYREG_B0_P0_U1_DCFG6 0x400100ec
+#define CYREG_B0_P0_U1_DCFG7 0x400100ee
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070
+#define CYREG_B0_P1_U0_PLD_IT0 0x40010200
+#define CYREG_B0_P1_U0_PLD_IT1 0x40010204
+#define CYREG_B0_P1_U0_PLD_IT2 0x40010208
+#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c
+#define CYREG_B0_P1_U0_PLD_IT4 0x40010210
+#define CYREG_B0_P1_U0_PLD_IT5 0x40010214
+#define CYREG_B0_P1_U0_PLD_IT6 0x40010218
+#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c
+#define CYREG_B0_P1_U0_PLD_IT8 0x40010220
+#define CYREG_B0_P1_U0_PLD_IT9 0x40010224
+#define CYREG_B0_P1_U0_PLD_IT10 0x40010228
+#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c
+#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230
+#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232
+#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234
+#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236
+#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238
+#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a
+#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c
+#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e
+#define CYREG_B0_P1_U0_CFG0 0x40010240
+#define CYREG_B0_P1_U0_CFG1 0x40010241
+#define CYREG_B0_P1_U0_CFG2 0x40010242
+#define CYREG_B0_P1_U0_CFG3 0x40010243
+#define CYREG_B0_P1_U0_CFG4 0x40010244
+#define CYREG_B0_P1_U0_CFG5 0x40010245
+#define CYREG_B0_P1_U0_CFG6 0x40010246
+#define CYREG_B0_P1_U0_CFG7 0x40010247
+#define CYREG_B0_P1_U0_CFG8 0x40010248
+#define CYREG_B0_P1_U0_CFG9 0x40010249
+#define CYREG_B0_P1_U0_CFG10 0x4001024a
+#define CYREG_B0_P1_U0_CFG11 0x4001024b
+#define CYREG_B0_P1_U0_CFG12 0x4001024c
+#define CYREG_B0_P1_U0_CFG13 0x4001024d
+#define CYREG_B0_P1_U0_CFG14 0x4001024e
+#define CYREG_B0_P1_U0_CFG15 0x4001024f
+#define CYREG_B0_P1_U0_CFG16 0x40010250
+#define CYREG_B0_P1_U0_CFG17 0x40010251
+#define CYREG_B0_P1_U0_CFG18 0x40010252
+#define CYREG_B0_P1_U0_CFG19 0x40010253
+#define CYREG_B0_P1_U0_CFG20 0x40010254
+#define CYREG_B0_P1_U0_CFG21 0x40010255
+#define CYREG_B0_P1_U0_CFG22 0x40010256
+#define CYREG_B0_P1_U0_CFG23 0x40010257
+#define CYREG_B0_P1_U0_CFG24 0x40010258
+#define CYREG_B0_P1_U0_CFG25 0x40010259
+#define CYREG_B0_P1_U0_CFG26 0x4001025a
+#define CYREG_B0_P1_U0_CFG27 0x4001025b
+#define CYREG_B0_P1_U0_CFG28 0x4001025c
+#define CYREG_B0_P1_U0_CFG29 0x4001025d
+#define CYREG_B0_P1_U0_CFG30 0x4001025e
+#define CYREG_B0_P1_U0_CFG31 0x4001025f
+#define CYREG_B0_P1_U0_DCFG0 0x40010260
+#define CYREG_B0_P1_U0_DCFG1 0x40010262
+#define CYREG_B0_P1_U0_DCFG2 0x40010264
+#define CYREG_B0_P1_U0_DCFG3 0x40010266
+#define CYREG_B0_P1_U0_DCFG4 0x40010268
+#define CYREG_B0_P1_U0_DCFG5 0x4001026a
+#define CYREG_B0_P1_U0_DCFG6 0x4001026c
+#define CYREG_B0_P1_U0_DCFG7 0x4001026e
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070
+#define CYREG_B0_P1_U1_PLD_IT0 0x40010280
+#define CYREG_B0_P1_U1_PLD_IT1 0x40010284
+#define CYREG_B0_P1_U1_PLD_IT2 0x40010288
+#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c
+#define CYREG_B0_P1_U1_PLD_IT4 0x40010290
+#define CYREG_B0_P1_U1_PLD_IT5 0x40010294
+#define CYREG_B0_P1_U1_PLD_IT6 0x40010298
+#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c
+#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0
+#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4
+#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8
+#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac
+#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0
+#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2
+#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4
+#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6
+#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8
+#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba
+#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc
+#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be
+#define CYREG_B0_P1_U1_CFG0 0x400102c0
+#define CYREG_B0_P1_U1_CFG1 0x400102c1
+#define CYREG_B0_P1_U1_CFG2 0x400102c2
+#define CYREG_B0_P1_U1_CFG3 0x400102c3
+#define CYREG_B0_P1_U1_CFG4 0x400102c4
+#define CYREG_B0_P1_U1_CFG5 0x400102c5
+#define CYREG_B0_P1_U1_CFG6 0x400102c6
+#define CYREG_B0_P1_U1_CFG7 0x400102c7
+#define CYREG_B0_P1_U1_CFG8 0x400102c8
+#define CYREG_B0_P1_U1_CFG9 0x400102c9
+#define CYREG_B0_P1_U1_CFG10 0x400102ca
+#define CYREG_B0_P1_U1_CFG11 0x400102cb
+#define CYREG_B0_P1_U1_CFG12 0x400102cc
+#define CYREG_B0_P1_U1_CFG13 0x400102cd
+#define CYREG_B0_P1_U1_CFG14 0x400102ce
+#define CYREG_B0_P1_U1_CFG15 0x400102cf
+#define CYREG_B0_P1_U1_CFG16 0x400102d0
+#define CYREG_B0_P1_U1_CFG17 0x400102d1
+#define CYREG_B0_P1_U1_CFG18 0x400102d2
+#define CYREG_B0_P1_U1_CFG19 0x400102d3
+#define CYREG_B0_P1_U1_CFG20 0x400102d4
+#define CYREG_B0_P1_U1_CFG21 0x400102d5
+#define CYREG_B0_P1_U1_CFG22 0x400102d6
+#define CYREG_B0_P1_U1_CFG23 0x400102d7
+#define CYREG_B0_P1_U1_CFG24 0x400102d8
+#define CYREG_B0_P1_U1_CFG25 0x400102d9
+#define CYREG_B0_P1_U1_CFG26 0x400102da
+#define CYREG_B0_P1_U1_CFG27 0x400102db
+#define CYREG_B0_P1_U1_CFG28 0x400102dc
+#define CYREG_B0_P1_U1_CFG29 0x400102dd
+#define CYREG_B0_P1_U1_CFG30 0x400102de
+#define CYREG_B0_P1_U1_CFG31 0x400102df
+#define CYREG_B0_P1_U1_DCFG0 0x400102e0
+#define CYREG_B0_P1_U1_DCFG1 0x400102e2
+#define CYREG_B0_P1_U1_DCFG2 0x400102e4
+#define CYREG_B0_P1_U1_DCFG3 0x400102e6
+#define CYREG_B0_P1_U1_DCFG4 0x400102e8
+#define CYREG_B0_P1_U1_DCFG5 0x400102ea
+#define CYREG_B0_P1_U1_DCFG6 0x400102ec
+#define CYREG_B0_P1_U1_DCFG7 0x400102ee
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070
+#define CYREG_B0_P2_U0_PLD_IT0 0x40010400
+#define CYREG_B0_P2_U0_PLD_IT1 0x40010404
+#define CYREG_B0_P2_U0_PLD_IT2 0x40010408
+#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c
+#define CYREG_B0_P2_U0_PLD_IT4 0x40010410
+#define CYREG_B0_P2_U0_PLD_IT5 0x40010414
+#define CYREG_B0_P2_U0_PLD_IT6 0x40010418
+#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c
+#define CYREG_B0_P2_U0_PLD_IT8 0x40010420
+#define CYREG_B0_P2_U0_PLD_IT9 0x40010424
+#define CYREG_B0_P2_U0_PLD_IT10 0x40010428
+#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c
+#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430
+#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432
+#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434
+#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436
+#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438
+#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a
+#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c
+#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e
+#define CYREG_B0_P2_U0_CFG0 0x40010440
+#define CYREG_B0_P2_U0_CFG1 0x40010441
+#define CYREG_B0_P2_U0_CFG2 0x40010442
+#define CYREG_B0_P2_U0_CFG3 0x40010443
+#define CYREG_B0_P2_U0_CFG4 0x40010444
+#define CYREG_B0_P2_U0_CFG5 0x40010445
+#define CYREG_B0_P2_U0_CFG6 0x40010446
+#define CYREG_B0_P2_U0_CFG7 0x40010447
+#define CYREG_B0_P2_U0_CFG8 0x40010448
+#define CYREG_B0_P2_U0_CFG9 0x40010449
+#define CYREG_B0_P2_U0_CFG10 0x4001044a
+#define CYREG_B0_P2_U0_CFG11 0x4001044b
+#define CYREG_B0_P2_U0_CFG12 0x4001044c
+#define CYREG_B0_P2_U0_CFG13 0x4001044d
+#define CYREG_B0_P2_U0_CFG14 0x4001044e
+#define CYREG_B0_P2_U0_CFG15 0x4001044f
+#define CYREG_B0_P2_U0_CFG16 0x40010450
+#define CYREG_B0_P2_U0_CFG17 0x40010451
+#define CYREG_B0_P2_U0_CFG18 0x40010452
+#define CYREG_B0_P2_U0_CFG19 0x40010453
+#define CYREG_B0_P2_U0_CFG20 0x40010454
+#define CYREG_B0_P2_U0_CFG21 0x40010455
+#define CYREG_B0_P2_U0_CFG22 0x40010456
+#define CYREG_B0_P2_U0_CFG23 0x40010457
+#define CYREG_B0_P2_U0_CFG24 0x40010458
+#define CYREG_B0_P2_U0_CFG25 0x40010459
+#define CYREG_B0_P2_U0_CFG26 0x4001045a
+#define CYREG_B0_P2_U0_CFG27 0x4001045b
+#define CYREG_B0_P2_U0_CFG28 0x4001045c
+#define CYREG_B0_P2_U0_CFG29 0x4001045d
+#define CYREG_B0_P2_U0_CFG30 0x4001045e
+#define CYREG_B0_P2_U0_CFG31 0x4001045f
+#define CYREG_B0_P2_U0_DCFG0 0x40010460
+#define CYREG_B0_P2_U0_DCFG1 0x40010462
+#define CYREG_B0_P2_U0_DCFG2 0x40010464
+#define CYREG_B0_P2_U0_DCFG3 0x40010466
+#define CYREG_B0_P2_U0_DCFG4 0x40010468
+#define CYREG_B0_P2_U0_DCFG5 0x4001046a
+#define CYREG_B0_P2_U0_DCFG6 0x4001046c
+#define CYREG_B0_P2_U0_DCFG7 0x4001046e
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070
+#define CYREG_B0_P2_U1_PLD_IT0 0x40010480
+#define CYREG_B0_P2_U1_PLD_IT1 0x40010484
+#define CYREG_B0_P2_U1_PLD_IT2 0x40010488
+#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c
+#define CYREG_B0_P2_U1_PLD_IT4 0x40010490
+#define CYREG_B0_P2_U1_PLD_IT5 0x40010494
+#define CYREG_B0_P2_U1_PLD_IT6 0x40010498
+#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c
+#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0
+#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4
+#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8
+#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac
+#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0
+#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2
+#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4
+#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6
+#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8
+#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba
+#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc
+#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be
+#define CYREG_B0_P2_U1_CFG0 0x400104c0
+#define CYREG_B0_P2_U1_CFG1 0x400104c1
+#define CYREG_B0_P2_U1_CFG2 0x400104c2
+#define CYREG_B0_P2_U1_CFG3 0x400104c3
+#define CYREG_B0_P2_U1_CFG4 0x400104c4
+#define CYREG_B0_P2_U1_CFG5 0x400104c5
+#define CYREG_B0_P2_U1_CFG6 0x400104c6
+#define CYREG_B0_P2_U1_CFG7 0x400104c7
+#define CYREG_B0_P2_U1_CFG8 0x400104c8
+#define CYREG_B0_P2_U1_CFG9 0x400104c9
+#define CYREG_B0_P2_U1_CFG10 0x400104ca
+#define CYREG_B0_P2_U1_CFG11 0x400104cb
+#define CYREG_B0_P2_U1_CFG12 0x400104cc
+#define CYREG_B0_P2_U1_CFG13 0x400104cd
+#define CYREG_B0_P2_U1_CFG14 0x400104ce
+#define CYREG_B0_P2_U1_CFG15 0x400104cf
+#define CYREG_B0_P2_U1_CFG16 0x400104d0
+#define CYREG_B0_P2_U1_CFG17 0x400104d1
+#define CYREG_B0_P2_U1_CFG18 0x400104d2
+#define CYREG_B0_P2_U1_CFG19 0x400104d3
+#define CYREG_B0_P2_U1_CFG20 0x400104d4
+#define CYREG_B0_P2_U1_CFG21 0x400104d5
+#define CYREG_B0_P2_U1_CFG22 0x400104d6
+#define CYREG_B0_P2_U1_CFG23 0x400104d7
+#define CYREG_B0_P2_U1_CFG24 0x400104d8
+#define CYREG_B0_P2_U1_CFG25 0x400104d9
+#define CYREG_B0_P2_U1_CFG26 0x400104da
+#define CYREG_B0_P2_U1_CFG27 0x400104db
+#define CYREG_B0_P2_U1_CFG28 0x400104dc
+#define CYREG_B0_P2_U1_CFG29 0x400104dd
+#define CYREG_B0_P2_U1_CFG30 0x400104de
+#define CYREG_B0_P2_U1_CFG31 0x400104df
+#define CYREG_B0_P2_U1_DCFG0 0x400104e0
+#define CYREG_B0_P2_U1_DCFG1 0x400104e2
+#define CYREG_B0_P2_U1_DCFG2 0x400104e4
+#define CYREG_B0_P2_U1_DCFG3 0x400104e6
+#define CYREG_B0_P2_U1_DCFG4 0x400104e8
+#define CYREG_B0_P2_U1_DCFG5 0x400104ea
+#define CYREG_B0_P2_U1_DCFG6 0x400104ec
+#define CYREG_B0_P2_U1_DCFG7 0x400104ee
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070
+#define CYREG_B0_P3_U0_PLD_IT0 0x40010600
+#define CYREG_B0_P3_U0_PLD_IT1 0x40010604
+#define CYREG_B0_P3_U0_PLD_IT2 0x40010608
+#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c
+#define CYREG_B0_P3_U0_PLD_IT4 0x40010610
+#define CYREG_B0_P3_U0_PLD_IT5 0x40010614
+#define CYREG_B0_P3_U0_PLD_IT6 0x40010618
+#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c
+#define CYREG_B0_P3_U0_PLD_IT8 0x40010620
+#define CYREG_B0_P3_U0_PLD_IT9 0x40010624
+#define CYREG_B0_P3_U0_PLD_IT10 0x40010628
+#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c
+#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630
+#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632
+#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634
+#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636
+#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638
+#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a
+#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c
+#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e
+#define CYREG_B0_P3_U0_CFG0 0x40010640
+#define CYREG_B0_P3_U0_CFG1 0x40010641
+#define CYREG_B0_P3_U0_CFG2 0x40010642
+#define CYREG_B0_P3_U0_CFG3 0x40010643
+#define CYREG_B0_P3_U0_CFG4 0x40010644
+#define CYREG_B0_P3_U0_CFG5 0x40010645
+#define CYREG_B0_P3_U0_CFG6 0x40010646
+#define CYREG_B0_P3_U0_CFG7 0x40010647
+#define CYREG_B0_P3_U0_CFG8 0x40010648
+#define CYREG_B0_P3_U0_CFG9 0x40010649
+#define CYREG_B0_P3_U0_CFG10 0x4001064a
+#define CYREG_B0_P3_U0_CFG11 0x4001064b
+#define CYREG_B0_P3_U0_CFG12 0x4001064c
+#define CYREG_B0_P3_U0_CFG13 0x4001064d
+#define CYREG_B0_P3_U0_CFG14 0x4001064e
+#define CYREG_B0_P3_U0_CFG15 0x4001064f
+#define CYREG_B0_P3_U0_CFG16 0x40010650
+#define CYREG_B0_P3_U0_CFG17 0x40010651
+#define CYREG_B0_P3_U0_CFG18 0x40010652
+#define CYREG_B0_P3_U0_CFG19 0x40010653
+#define CYREG_B0_P3_U0_CFG20 0x40010654
+#define CYREG_B0_P3_U0_CFG21 0x40010655
+#define CYREG_B0_P3_U0_CFG22 0x40010656
+#define CYREG_B0_P3_U0_CFG23 0x40010657
+#define CYREG_B0_P3_U0_CFG24 0x40010658
+#define CYREG_B0_P3_U0_CFG25 0x40010659
+#define CYREG_B0_P3_U0_CFG26 0x4001065a
+#define CYREG_B0_P3_U0_CFG27 0x4001065b
+#define CYREG_B0_P3_U0_CFG28 0x4001065c
+#define CYREG_B0_P3_U0_CFG29 0x4001065d
+#define CYREG_B0_P3_U0_CFG30 0x4001065e
+#define CYREG_B0_P3_U0_CFG31 0x4001065f
+#define CYREG_B0_P3_U0_DCFG0 0x40010660
+#define CYREG_B0_P3_U0_DCFG1 0x40010662
+#define CYREG_B0_P3_U0_DCFG2 0x40010664
+#define CYREG_B0_P3_U0_DCFG3 0x40010666
+#define CYREG_B0_P3_U0_DCFG4 0x40010668
+#define CYREG_B0_P3_U0_DCFG5 0x4001066a
+#define CYREG_B0_P3_U0_DCFG6 0x4001066c
+#define CYREG_B0_P3_U0_DCFG7 0x4001066e
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070
+#define CYREG_B0_P3_U1_PLD_IT0 0x40010680
+#define CYREG_B0_P3_U1_PLD_IT1 0x40010684
+#define CYREG_B0_P3_U1_PLD_IT2 0x40010688
+#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c
+#define CYREG_B0_P3_U1_PLD_IT4 0x40010690
+#define CYREG_B0_P3_U1_PLD_IT5 0x40010694
+#define CYREG_B0_P3_U1_PLD_IT6 0x40010698
+#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c
+#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0
+#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4
+#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8
+#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac
+#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0
+#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2
+#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4
+#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6
+#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8
+#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba
+#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc
+#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be
+#define CYREG_B0_P3_U1_CFG0 0x400106c0
+#define CYREG_B0_P3_U1_CFG1 0x400106c1
+#define CYREG_B0_P3_U1_CFG2 0x400106c2
+#define CYREG_B0_P3_U1_CFG3 0x400106c3
+#define CYREG_B0_P3_U1_CFG4 0x400106c4
+#define CYREG_B0_P3_U1_CFG5 0x400106c5
+#define CYREG_B0_P3_U1_CFG6 0x400106c6
+#define CYREG_B0_P3_U1_CFG7 0x400106c7
+#define CYREG_B0_P3_U1_CFG8 0x400106c8
+#define CYREG_B0_P3_U1_CFG9 0x400106c9
+#define CYREG_B0_P3_U1_CFG10 0x400106ca
+#define CYREG_B0_P3_U1_CFG11 0x400106cb
+#define CYREG_B0_P3_U1_CFG12 0x400106cc
+#define CYREG_B0_P3_U1_CFG13 0x400106cd
+#define CYREG_B0_P3_U1_CFG14 0x400106ce
+#define CYREG_B0_P3_U1_CFG15 0x400106cf
+#define CYREG_B0_P3_U1_CFG16 0x400106d0
+#define CYREG_B0_P3_U1_CFG17 0x400106d1
+#define CYREG_B0_P3_U1_CFG18 0x400106d2
+#define CYREG_B0_P3_U1_CFG19 0x400106d3
+#define CYREG_B0_P3_U1_CFG20 0x400106d4
+#define CYREG_B0_P3_U1_CFG21 0x400106d5
+#define CYREG_B0_P3_U1_CFG22 0x400106d6
+#define CYREG_B0_P3_U1_CFG23 0x400106d7
+#define CYREG_B0_P3_U1_CFG24 0x400106d8
+#define CYREG_B0_P3_U1_CFG25 0x400106d9
+#define CYREG_B0_P3_U1_CFG26 0x400106da
+#define CYREG_B0_P3_U1_CFG27 0x400106db
+#define CYREG_B0_P3_U1_CFG28 0x400106dc
+#define CYREG_B0_P3_U1_CFG29 0x400106dd
+#define CYREG_B0_P3_U1_CFG30 0x400106de
+#define CYREG_B0_P3_U1_CFG31 0x400106df
+#define CYREG_B0_P3_U1_DCFG0 0x400106e0
+#define CYREG_B0_P3_U1_DCFG1 0x400106e2
+#define CYREG_B0_P3_U1_DCFG2 0x400106e4
+#define CYREG_B0_P3_U1_DCFG3 0x400106e6
+#define CYREG_B0_P3_U1_DCFG4 0x400106e8
+#define CYREG_B0_P3_U1_DCFG5 0x400106ea
+#define CYREG_B0_P3_U1_DCFG6 0x400106ec
+#define CYREG_B0_P3_U1_DCFG7 0x400106ee
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070
+#define CYREG_B0_P4_U0_PLD_IT0 0x40010800
+#define CYREG_B0_P4_U0_PLD_IT1 0x40010804
+#define CYREG_B0_P4_U0_PLD_IT2 0x40010808
+#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c
+#define CYREG_B0_P4_U0_PLD_IT4 0x40010810
+#define CYREG_B0_P4_U0_PLD_IT5 0x40010814
+#define CYREG_B0_P4_U0_PLD_IT6 0x40010818
+#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c
+#define CYREG_B0_P4_U0_PLD_IT8 0x40010820
+#define CYREG_B0_P4_U0_PLD_IT9 0x40010824
+#define CYREG_B0_P4_U0_PLD_IT10 0x40010828
+#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c
+#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830
+#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832
+#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834
+#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836
+#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838
+#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a
+#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c
+#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e
+#define CYREG_B0_P4_U0_CFG0 0x40010840
+#define CYREG_B0_P4_U0_CFG1 0x40010841
+#define CYREG_B0_P4_U0_CFG2 0x40010842
+#define CYREG_B0_P4_U0_CFG3 0x40010843
+#define CYREG_B0_P4_U0_CFG4 0x40010844
+#define CYREG_B0_P4_U0_CFG5 0x40010845
+#define CYREG_B0_P4_U0_CFG6 0x40010846
+#define CYREG_B0_P4_U0_CFG7 0x40010847
+#define CYREG_B0_P4_U0_CFG8 0x40010848
+#define CYREG_B0_P4_U0_CFG9 0x40010849
+#define CYREG_B0_P4_U0_CFG10 0x4001084a
+#define CYREG_B0_P4_U0_CFG11 0x4001084b
+#define CYREG_B0_P4_U0_CFG12 0x4001084c
+#define CYREG_B0_P4_U0_CFG13 0x4001084d
+#define CYREG_B0_P4_U0_CFG14 0x4001084e
+#define CYREG_B0_P4_U0_CFG15 0x4001084f
+#define CYREG_B0_P4_U0_CFG16 0x40010850
+#define CYREG_B0_P4_U0_CFG17 0x40010851
+#define CYREG_B0_P4_U0_CFG18 0x40010852
+#define CYREG_B0_P4_U0_CFG19 0x40010853
+#define CYREG_B0_P4_U0_CFG20 0x40010854
+#define CYREG_B0_P4_U0_CFG21 0x40010855
+#define CYREG_B0_P4_U0_CFG22 0x40010856
+#define CYREG_B0_P4_U0_CFG23 0x40010857
+#define CYREG_B0_P4_U0_CFG24 0x40010858
+#define CYREG_B0_P4_U0_CFG25 0x40010859
+#define CYREG_B0_P4_U0_CFG26 0x4001085a
+#define CYREG_B0_P4_U0_CFG27 0x4001085b
+#define CYREG_B0_P4_U0_CFG28 0x4001085c
+#define CYREG_B0_P4_U0_CFG29 0x4001085d
+#define CYREG_B0_P4_U0_CFG30 0x4001085e
+#define CYREG_B0_P4_U0_CFG31 0x4001085f
+#define CYREG_B0_P4_U0_DCFG0 0x40010860
+#define CYREG_B0_P4_U0_DCFG1 0x40010862
+#define CYREG_B0_P4_U0_DCFG2 0x40010864
+#define CYREG_B0_P4_U0_DCFG3 0x40010866
+#define CYREG_B0_P4_U0_DCFG4 0x40010868
+#define CYREG_B0_P4_U0_DCFG5 0x4001086a
+#define CYREG_B0_P4_U0_DCFG6 0x4001086c
+#define CYREG_B0_P4_U0_DCFG7 0x4001086e
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070
+#define CYREG_B0_P4_U1_PLD_IT0 0x40010880
+#define CYREG_B0_P4_U1_PLD_IT1 0x40010884
+#define CYREG_B0_P4_U1_PLD_IT2 0x40010888
+#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c
+#define CYREG_B0_P4_U1_PLD_IT4 0x40010890
+#define CYREG_B0_P4_U1_PLD_IT5 0x40010894
+#define CYREG_B0_P4_U1_PLD_IT6 0x40010898
+#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c
+#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0
+#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4
+#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8
+#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac
+#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0
+#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2
+#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4
+#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6
+#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8
+#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba
+#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc
+#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be
+#define CYREG_B0_P4_U1_CFG0 0x400108c0
+#define CYREG_B0_P4_U1_CFG1 0x400108c1
+#define CYREG_B0_P4_U1_CFG2 0x400108c2
+#define CYREG_B0_P4_U1_CFG3 0x400108c3
+#define CYREG_B0_P4_U1_CFG4 0x400108c4
+#define CYREG_B0_P4_U1_CFG5 0x400108c5
+#define CYREG_B0_P4_U1_CFG6 0x400108c6
+#define CYREG_B0_P4_U1_CFG7 0x400108c7
+#define CYREG_B0_P4_U1_CFG8 0x400108c8
+#define CYREG_B0_P4_U1_CFG9 0x400108c9
+#define CYREG_B0_P4_U1_CFG10 0x400108ca
+#define CYREG_B0_P4_U1_CFG11 0x400108cb
+#define CYREG_B0_P4_U1_CFG12 0x400108cc
+#define CYREG_B0_P4_U1_CFG13 0x400108cd
+#define CYREG_B0_P4_U1_CFG14 0x400108ce
+#define CYREG_B0_P4_U1_CFG15 0x400108cf
+#define CYREG_B0_P4_U1_CFG16 0x400108d0
+#define CYREG_B0_P4_U1_CFG17 0x400108d1
+#define CYREG_B0_P4_U1_CFG18 0x400108d2
+#define CYREG_B0_P4_U1_CFG19 0x400108d3
+#define CYREG_B0_P4_U1_CFG20 0x400108d4
+#define CYREG_B0_P4_U1_CFG21 0x400108d5
+#define CYREG_B0_P4_U1_CFG22 0x400108d6
+#define CYREG_B0_P4_U1_CFG23 0x400108d7
+#define CYREG_B0_P4_U1_CFG24 0x400108d8
+#define CYREG_B0_P4_U1_CFG25 0x400108d9
+#define CYREG_B0_P4_U1_CFG26 0x400108da
+#define CYREG_B0_P4_U1_CFG27 0x400108db
+#define CYREG_B0_P4_U1_CFG28 0x400108dc
+#define CYREG_B0_P4_U1_CFG29 0x400108dd
+#define CYREG_B0_P4_U1_CFG30 0x400108de
+#define CYREG_B0_P4_U1_CFG31 0x400108df
+#define CYREG_B0_P4_U1_DCFG0 0x400108e0
+#define CYREG_B0_P4_U1_DCFG1 0x400108e2
+#define CYREG_B0_P4_U1_DCFG2 0x400108e4
+#define CYREG_B0_P4_U1_DCFG3 0x400108e6
+#define CYREG_B0_P4_U1_DCFG4 0x400108e8
+#define CYREG_B0_P4_U1_DCFG5 0x400108ea
+#define CYREG_B0_P4_U1_DCFG6 0x400108ec
+#define CYREG_B0_P4_U1_DCFG7 0x400108ee
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070
+#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00
+#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04
+#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08
+#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c
+#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10
+#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14
+#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18
+#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c
+#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20
+#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24
+#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28
+#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c
+#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30
+#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32
+#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34
+#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36
+#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38
+#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a
+#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c
+#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e
+#define CYREG_B0_P5_U0_CFG0 0x40010a40
+#define CYREG_B0_P5_U0_CFG1 0x40010a41
+#define CYREG_B0_P5_U0_CFG2 0x40010a42
+#define CYREG_B0_P5_U0_CFG3 0x40010a43
+#define CYREG_B0_P5_U0_CFG4 0x40010a44
+#define CYREG_B0_P5_U0_CFG5 0x40010a45
+#define CYREG_B0_P5_U0_CFG6 0x40010a46
+#define CYREG_B0_P5_U0_CFG7 0x40010a47
+#define CYREG_B0_P5_U0_CFG8 0x40010a48
+#define CYREG_B0_P5_U0_CFG9 0x40010a49
+#define CYREG_B0_P5_U0_CFG10 0x40010a4a
+#define CYREG_B0_P5_U0_CFG11 0x40010a4b
+#define CYREG_B0_P5_U0_CFG12 0x40010a4c
+#define CYREG_B0_P5_U0_CFG13 0x40010a4d
+#define CYREG_B0_P5_U0_CFG14 0x40010a4e
+#define CYREG_B0_P5_U0_CFG15 0x40010a4f
+#define CYREG_B0_P5_U0_CFG16 0x40010a50
+#define CYREG_B0_P5_U0_CFG17 0x40010a51
+#define CYREG_B0_P5_U0_CFG18 0x40010a52
+#define CYREG_B0_P5_U0_CFG19 0x40010a53
+#define CYREG_B0_P5_U0_CFG20 0x40010a54
+#define CYREG_B0_P5_U0_CFG21 0x40010a55
+#define CYREG_B0_P5_U0_CFG22 0x40010a56
+#define CYREG_B0_P5_U0_CFG23 0x40010a57
+#define CYREG_B0_P5_U0_CFG24 0x40010a58
+#define CYREG_B0_P5_U0_CFG25 0x40010a59
+#define CYREG_B0_P5_U0_CFG26 0x40010a5a
+#define CYREG_B0_P5_U0_CFG27 0x40010a5b
+#define CYREG_B0_P5_U0_CFG28 0x40010a5c
+#define CYREG_B0_P5_U0_CFG29 0x40010a5d
+#define CYREG_B0_P5_U0_CFG30 0x40010a5e
+#define CYREG_B0_P5_U0_CFG31 0x40010a5f
+#define CYREG_B0_P5_U0_DCFG0 0x40010a60
+#define CYREG_B0_P5_U0_DCFG1 0x40010a62
+#define CYREG_B0_P5_U0_DCFG2 0x40010a64
+#define CYREG_B0_P5_U0_DCFG3 0x40010a66
+#define CYREG_B0_P5_U0_DCFG4 0x40010a68
+#define CYREG_B0_P5_U0_DCFG5 0x40010a6a
+#define CYREG_B0_P5_U0_DCFG6 0x40010a6c
+#define CYREG_B0_P5_U0_DCFG7 0x40010a6e
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070
+#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80
+#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84
+#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88
+#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c
+#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90
+#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94
+#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98
+#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c
+#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0
+#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4
+#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8
+#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac
+#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0
+#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2
+#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4
+#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6
+#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8
+#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba
+#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc
+#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe
+#define CYREG_B0_P5_U1_CFG0 0x40010ac0
+#define CYREG_B0_P5_U1_CFG1 0x40010ac1
+#define CYREG_B0_P5_U1_CFG2 0x40010ac2
+#define CYREG_B0_P5_U1_CFG3 0x40010ac3
+#define CYREG_B0_P5_U1_CFG4 0x40010ac4
+#define CYREG_B0_P5_U1_CFG5 0x40010ac5
+#define CYREG_B0_P5_U1_CFG6 0x40010ac6
+#define CYREG_B0_P5_U1_CFG7 0x40010ac7
+#define CYREG_B0_P5_U1_CFG8 0x40010ac8
+#define CYREG_B0_P5_U1_CFG9 0x40010ac9
+#define CYREG_B0_P5_U1_CFG10 0x40010aca
+#define CYREG_B0_P5_U1_CFG11 0x40010acb
+#define CYREG_B0_P5_U1_CFG12 0x40010acc
+#define CYREG_B0_P5_U1_CFG13 0x40010acd
+#define CYREG_B0_P5_U1_CFG14 0x40010ace
+#define CYREG_B0_P5_U1_CFG15 0x40010acf
+#define CYREG_B0_P5_U1_CFG16 0x40010ad0
+#define CYREG_B0_P5_U1_CFG17 0x40010ad1
+#define CYREG_B0_P5_U1_CFG18 0x40010ad2
+#define CYREG_B0_P5_U1_CFG19 0x40010ad3
+#define CYREG_B0_P5_U1_CFG20 0x40010ad4
+#define CYREG_B0_P5_U1_CFG21 0x40010ad5
+#define CYREG_B0_P5_U1_CFG22 0x40010ad6
+#define CYREG_B0_P5_U1_CFG23 0x40010ad7
+#define CYREG_B0_P5_U1_CFG24 0x40010ad8
+#define CYREG_B0_P5_U1_CFG25 0x40010ad9
+#define CYREG_B0_P5_U1_CFG26 0x40010ada
+#define CYREG_B0_P5_U1_CFG27 0x40010adb
+#define CYREG_B0_P5_U1_CFG28 0x40010adc
+#define CYREG_B0_P5_U1_CFG29 0x40010add
+#define CYREG_B0_P5_U1_CFG30 0x40010ade
+#define CYREG_B0_P5_U1_CFG31 0x40010adf
+#define CYREG_B0_P5_U1_DCFG0 0x40010ae0
+#define CYREG_B0_P5_U1_DCFG1 0x40010ae2
+#define CYREG_B0_P5_U1_DCFG2 0x40010ae4
+#define CYREG_B0_P5_U1_DCFG3 0x40010ae6
+#define CYREG_B0_P5_U1_DCFG4 0x40010ae8
+#define CYREG_B0_P5_U1_DCFG5 0x40010aea
+#define CYREG_B0_P5_U1_DCFG6 0x40010aec
+#define CYREG_B0_P5_U1_DCFG7 0x40010aee
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070
+#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00
+#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04
+#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08
+#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c
+#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10
+#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14
+#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18
+#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c
+#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20
+#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24
+#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28
+#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c
+#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30
+#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32
+#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34
+#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36
+#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38
+#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a
+#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c
+#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e
+#define CYREG_B0_P6_U0_CFG0 0x40010c40
+#define CYREG_B0_P6_U0_CFG1 0x40010c41
+#define CYREG_B0_P6_U0_CFG2 0x40010c42
+#define CYREG_B0_P6_U0_CFG3 0x40010c43
+#define CYREG_B0_P6_U0_CFG4 0x40010c44
+#define CYREG_B0_P6_U0_CFG5 0x40010c45
+#define CYREG_B0_P6_U0_CFG6 0x40010c46
+#define CYREG_B0_P6_U0_CFG7 0x40010c47
+#define CYREG_B0_P6_U0_CFG8 0x40010c48
+#define CYREG_B0_P6_U0_CFG9 0x40010c49
+#define CYREG_B0_P6_U0_CFG10 0x40010c4a
+#define CYREG_B0_P6_U0_CFG11 0x40010c4b
+#define CYREG_B0_P6_U0_CFG12 0x40010c4c
+#define CYREG_B0_P6_U0_CFG13 0x40010c4d
+#define CYREG_B0_P6_U0_CFG14 0x40010c4e
+#define CYREG_B0_P6_U0_CFG15 0x40010c4f
+#define CYREG_B0_P6_U0_CFG16 0x40010c50
+#define CYREG_B0_P6_U0_CFG17 0x40010c51
+#define CYREG_B0_P6_U0_CFG18 0x40010c52
+#define CYREG_B0_P6_U0_CFG19 0x40010c53
+#define CYREG_B0_P6_U0_CFG20 0x40010c54
+#define CYREG_B0_P6_U0_CFG21 0x40010c55
+#define CYREG_B0_P6_U0_CFG22 0x40010c56
+#define CYREG_B0_P6_U0_CFG23 0x40010c57
+#define CYREG_B0_P6_U0_CFG24 0x40010c58
+#define CYREG_B0_P6_U0_CFG25 0x40010c59
+#define CYREG_B0_P6_U0_CFG26 0x40010c5a
+#define CYREG_B0_P6_U0_CFG27 0x40010c5b
+#define CYREG_B0_P6_U0_CFG28 0x40010c5c
+#define CYREG_B0_P6_U0_CFG29 0x40010c5d
+#define CYREG_B0_P6_U0_CFG30 0x40010c5e
+#define CYREG_B0_P6_U0_CFG31 0x40010c5f
+#define CYREG_B0_P6_U0_DCFG0 0x40010c60
+#define CYREG_B0_P6_U0_DCFG1 0x40010c62
+#define CYREG_B0_P6_U0_DCFG2 0x40010c64
+#define CYREG_B0_P6_U0_DCFG3 0x40010c66
+#define CYREG_B0_P6_U0_DCFG4 0x40010c68
+#define CYREG_B0_P6_U0_DCFG5 0x40010c6a
+#define CYREG_B0_P6_U0_DCFG6 0x40010c6c
+#define CYREG_B0_P6_U0_DCFG7 0x40010c6e
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070
+#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80
+#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84
+#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88
+#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c
+#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90
+#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94
+#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98
+#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c
+#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0
+#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4
+#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8
+#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac
+#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0
+#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2
+#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4
+#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6
+#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8
+#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba
+#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc
+#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe
+#define CYREG_B0_P6_U1_CFG0 0x40010cc0
+#define CYREG_B0_P6_U1_CFG1 0x40010cc1
+#define CYREG_B0_P6_U1_CFG2 0x40010cc2
+#define CYREG_B0_P6_U1_CFG3 0x40010cc3
+#define CYREG_B0_P6_U1_CFG4 0x40010cc4
+#define CYREG_B0_P6_U1_CFG5 0x40010cc5
+#define CYREG_B0_P6_U1_CFG6 0x40010cc6
+#define CYREG_B0_P6_U1_CFG7 0x40010cc7
+#define CYREG_B0_P6_U1_CFG8 0x40010cc8
+#define CYREG_B0_P6_U1_CFG9 0x40010cc9
+#define CYREG_B0_P6_U1_CFG10 0x40010cca
+#define CYREG_B0_P6_U1_CFG11 0x40010ccb
+#define CYREG_B0_P6_U1_CFG12 0x40010ccc
+#define CYREG_B0_P6_U1_CFG13 0x40010ccd
+#define CYREG_B0_P6_U1_CFG14 0x40010cce
+#define CYREG_B0_P6_U1_CFG15 0x40010ccf
+#define CYREG_B0_P6_U1_CFG16 0x40010cd0
+#define CYREG_B0_P6_U1_CFG17 0x40010cd1
+#define CYREG_B0_P6_U1_CFG18 0x40010cd2
+#define CYREG_B0_P6_U1_CFG19 0x40010cd3
+#define CYREG_B0_P6_U1_CFG20 0x40010cd4
+#define CYREG_B0_P6_U1_CFG21 0x40010cd5
+#define CYREG_B0_P6_U1_CFG22 0x40010cd6
+#define CYREG_B0_P6_U1_CFG23 0x40010cd7
+#define CYREG_B0_P6_U1_CFG24 0x40010cd8
+#define CYREG_B0_P6_U1_CFG25 0x40010cd9
+#define CYREG_B0_P6_U1_CFG26 0x40010cda
+#define CYREG_B0_P6_U1_CFG27 0x40010cdb
+#define CYREG_B0_P6_U1_CFG28 0x40010cdc
+#define CYREG_B0_P6_U1_CFG29 0x40010cdd
+#define CYREG_B0_P6_U1_CFG30 0x40010cde
+#define CYREG_B0_P6_U1_CFG31 0x40010cdf
+#define CYREG_B0_P6_U1_DCFG0 0x40010ce0
+#define CYREG_B0_P6_U1_DCFG1 0x40010ce2
+#define CYREG_B0_P6_U1_DCFG2 0x40010ce4
+#define CYREG_B0_P6_U1_DCFG3 0x40010ce6
+#define CYREG_B0_P6_U1_DCFG4 0x40010ce8
+#define CYREG_B0_P6_U1_DCFG5 0x40010cea
+#define CYREG_B0_P6_U1_DCFG6 0x40010cec
+#define CYREG_B0_P6_U1_DCFG7 0x40010cee
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070
+#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00
+#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04
+#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08
+#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c
+#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10
+#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14
+#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18
+#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c
+#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20
+#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24
+#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28
+#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c
+#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30
+#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32
+#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34
+#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36
+#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38
+#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a
+#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c
+#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e
+#define CYREG_B0_P7_U0_CFG0 0x40010e40
+#define CYREG_B0_P7_U0_CFG1 0x40010e41
+#define CYREG_B0_P7_U0_CFG2 0x40010e42
+#define CYREG_B0_P7_U0_CFG3 0x40010e43
+#define CYREG_B0_P7_U0_CFG4 0x40010e44
+#define CYREG_B0_P7_U0_CFG5 0x40010e45
+#define CYREG_B0_P7_U0_CFG6 0x40010e46
+#define CYREG_B0_P7_U0_CFG7 0x40010e47
+#define CYREG_B0_P7_U0_CFG8 0x40010e48
+#define CYREG_B0_P7_U0_CFG9 0x40010e49
+#define CYREG_B0_P7_U0_CFG10 0x40010e4a
+#define CYREG_B0_P7_U0_CFG11 0x40010e4b
+#define CYREG_B0_P7_U0_CFG12 0x40010e4c
+#define CYREG_B0_P7_U0_CFG13 0x40010e4d
+#define CYREG_B0_P7_U0_CFG14 0x40010e4e
+#define CYREG_B0_P7_U0_CFG15 0x40010e4f
+#define CYREG_B0_P7_U0_CFG16 0x40010e50
+#define CYREG_B0_P7_U0_CFG17 0x40010e51
+#define CYREG_B0_P7_U0_CFG18 0x40010e52
+#define CYREG_B0_P7_U0_CFG19 0x40010e53
+#define CYREG_B0_P7_U0_CFG20 0x40010e54
+#define CYREG_B0_P7_U0_CFG21 0x40010e55
+#define CYREG_B0_P7_U0_CFG22 0x40010e56
+#define CYREG_B0_P7_U0_CFG23 0x40010e57
+#define CYREG_B0_P7_U0_CFG24 0x40010e58
+#define CYREG_B0_P7_U0_CFG25 0x40010e59
+#define CYREG_B0_P7_U0_CFG26 0x40010e5a
+#define CYREG_B0_P7_U0_CFG27 0x40010e5b
+#define CYREG_B0_P7_U0_CFG28 0x40010e5c
+#define CYREG_B0_P7_U0_CFG29 0x40010e5d
+#define CYREG_B0_P7_U0_CFG30 0x40010e5e
+#define CYREG_B0_P7_U0_CFG31 0x40010e5f
+#define CYREG_B0_P7_U0_DCFG0 0x40010e60
+#define CYREG_B0_P7_U0_DCFG1 0x40010e62
+#define CYREG_B0_P7_U0_DCFG2 0x40010e64
+#define CYREG_B0_P7_U0_DCFG3 0x40010e66
+#define CYREG_B0_P7_U0_DCFG4 0x40010e68
+#define CYREG_B0_P7_U0_DCFG5 0x40010e6a
+#define CYREG_B0_P7_U0_DCFG6 0x40010e6c
+#define CYREG_B0_P7_U0_DCFG7 0x40010e6e
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070
+#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80
+#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84
+#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88
+#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c
+#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90
+#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94
+#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98
+#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c
+#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0
+#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4
+#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8
+#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac
+#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0
+#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2
+#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4
+#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6
+#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8
+#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba
+#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc
+#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe
+#define CYREG_B0_P7_U1_CFG0 0x40010ec0
+#define CYREG_B0_P7_U1_CFG1 0x40010ec1
+#define CYREG_B0_P7_U1_CFG2 0x40010ec2
+#define CYREG_B0_P7_U1_CFG3 0x40010ec3
+#define CYREG_B0_P7_U1_CFG4 0x40010ec4
+#define CYREG_B0_P7_U1_CFG5 0x40010ec5
+#define CYREG_B0_P7_U1_CFG6 0x40010ec6
+#define CYREG_B0_P7_U1_CFG7 0x40010ec7
+#define CYREG_B0_P7_U1_CFG8 0x40010ec8
+#define CYREG_B0_P7_U1_CFG9 0x40010ec9
+#define CYREG_B0_P7_U1_CFG10 0x40010eca
+#define CYREG_B0_P7_U1_CFG11 0x40010ecb
+#define CYREG_B0_P7_U1_CFG12 0x40010ecc
+#define CYREG_B0_P7_U1_CFG13 0x40010ecd
+#define CYREG_B0_P7_U1_CFG14 0x40010ece
+#define CYREG_B0_P7_U1_CFG15 0x40010ecf
+#define CYREG_B0_P7_U1_CFG16 0x40010ed0
+#define CYREG_B0_P7_U1_CFG17 0x40010ed1
+#define CYREG_B0_P7_U1_CFG18 0x40010ed2
+#define CYREG_B0_P7_U1_CFG19 0x40010ed3
+#define CYREG_B0_P7_U1_CFG20 0x40010ed4
+#define CYREG_B0_P7_U1_CFG21 0x40010ed5
+#define CYREG_B0_P7_U1_CFG22 0x40010ed6
+#define CYREG_B0_P7_U1_CFG23 0x40010ed7
+#define CYREG_B0_P7_U1_CFG24 0x40010ed8
+#define CYREG_B0_P7_U1_CFG25 0x40010ed9
+#define CYREG_B0_P7_U1_CFG26 0x40010eda
+#define CYREG_B0_P7_U1_CFG27 0x40010edb
+#define CYREG_B0_P7_U1_CFG28 0x40010edc
+#define CYREG_B0_P7_U1_CFG29 0x40010edd
+#define CYREG_B0_P7_U1_CFG30 0x40010ede
+#define CYREG_B0_P7_U1_CFG31 0x40010edf
+#define CYREG_B0_P7_U1_DCFG0 0x40010ee0
+#define CYREG_B0_P7_U1_DCFG1 0x40010ee2
+#define CYREG_B0_P7_U1_DCFG2 0x40010ee4
+#define CYREG_B0_P7_U1_DCFG3 0x40010ee6
+#define CYREG_B0_P7_U1_DCFG4 0x40010ee8
+#define CYREG_B0_P7_U1_DCFG5 0x40010eea
+#define CYREG_B0_P7_U1_DCFG6 0x40010eec
+#define CYREG_B0_P7_U1_DCFG7 0x40010eee
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_BASE 0x40011000
+#define CYDEV_UCFG_B1_SIZE 0x00000fef
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070
+#define CYREG_B1_P2_U0_PLD_IT0 0x40011400
+#define CYREG_B1_P2_U0_PLD_IT1 0x40011404
+#define CYREG_B1_P2_U0_PLD_IT2 0x40011408
+#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c
+#define CYREG_B1_P2_U0_PLD_IT4 0x40011410
+#define CYREG_B1_P2_U0_PLD_IT5 0x40011414
+#define CYREG_B1_P2_U0_PLD_IT6 0x40011418
+#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c
+#define CYREG_B1_P2_U0_PLD_IT8 0x40011420
+#define CYREG_B1_P2_U0_PLD_IT9 0x40011424
+#define CYREG_B1_P2_U0_PLD_IT10 0x40011428
+#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c
+#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430
+#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432
+#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434
+#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436
+#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438
+#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a
+#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c
+#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e
+#define CYREG_B1_P2_U0_CFG0 0x40011440
+#define CYREG_B1_P2_U0_CFG1 0x40011441
+#define CYREG_B1_P2_U0_CFG2 0x40011442
+#define CYREG_B1_P2_U0_CFG3 0x40011443
+#define CYREG_B1_P2_U0_CFG4 0x40011444
+#define CYREG_B1_P2_U0_CFG5 0x40011445
+#define CYREG_B1_P2_U0_CFG6 0x40011446
+#define CYREG_B1_P2_U0_CFG7 0x40011447
+#define CYREG_B1_P2_U0_CFG8 0x40011448
+#define CYREG_B1_P2_U0_CFG9 0x40011449
+#define CYREG_B1_P2_U0_CFG10 0x4001144a
+#define CYREG_B1_P2_U0_CFG11 0x4001144b
+#define CYREG_B1_P2_U0_CFG12 0x4001144c
+#define CYREG_B1_P2_U0_CFG13 0x4001144d
+#define CYREG_B1_P2_U0_CFG14 0x4001144e
+#define CYREG_B1_P2_U0_CFG15 0x4001144f
+#define CYREG_B1_P2_U0_CFG16 0x40011450
+#define CYREG_B1_P2_U0_CFG17 0x40011451
+#define CYREG_B1_P2_U0_CFG18 0x40011452
+#define CYREG_B1_P2_U0_CFG19 0x40011453
+#define CYREG_B1_P2_U0_CFG20 0x40011454
+#define CYREG_B1_P2_U0_CFG21 0x40011455
+#define CYREG_B1_P2_U0_CFG22 0x40011456
+#define CYREG_B1_P2_U0_CFG23 0x40011457
+#define CYREG_B1_P2_U0_CFG24 0x40011458
+#define CYREG_B1_P2_U0_CFG25 0x40011459
+#define CYREG_B1_P2_U0_CFG26 0x4001145a
+#define CYREG_B1_P2_U0_CFG27 0x4001145b
+#define CYREG_B1_P2_U0_CFG28 0x4001145c
+#define CYREG_B1_P2_U0_CFG29 0x4001145d
+#define CYREG_B1_P2_U0_CFG30 0x4001145e
+#define CYREG_B1_P2_U0_CFG31 0x4001145f
+#define CYREG_B1_P2_U0_DCFG0 0x40011460
+#define CYREG_B1_P2_U0_DCFG1 0x40011462
+#define CYREG_B1_P2_U0_DCFG2 0x40011464
+#define CYREG_B1_P2_U0_DCFG3 0x40011466
+#define CYREG_B1_P2_U0_DCFG4 0x40011468
+#define CYREG_B1_P2_U0_DCFG5 0x4001146a
+#define CYREG_B1_P2_U0_DCFG6 0x4001146c
+#define CYREG_B1_P2_U0_DCFG7 0x4001146e
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070
+#define CYREG_B1_P2_U1_PLD_IT0 0x40011480
+#define CYREG_B1_P2_U1_PLD_IT1 0x40011484
+#define CYREG_B1_P2_U1_PLD_IT2 0x40011488
+#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c
+#define CYREG_B1_P2_U1_PLD_IT4 0x40011490
+#define CYREG_B1_P2_U1_PLD_IT5 0x40011494
+#define CYREG_B1_P2_U1_PLD_IT6 0x40011498
+#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c
+#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0
+#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4
+#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8
+#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac
+#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0
+#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2
+#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4
+#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6
+#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8
+#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba
+#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc
+#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be
+#define CYREG_B1_P2_U1_CFG0 0x400114c0
+#define CYREG_B1_P2_U1_CFG1 0x400114c1
+#define CYREG_B1_P2_U1_CFG2 0x400114c2
+#define CYREG_B1_P2_U1_CFG3 0x400114c3
+#define CYREG_B1_P2_U1_CFG4 0x400114c4
+#define CYREG_B1_P2_U1_CFG5 0x400114c5
+#define CYREG_B1_P2_U1_CFG6 0x400114c6
+#define CYREG_B1_P2_U1_CFG7 0x400114c7
+#define CYREG_B1_P2_U1_CFG8 0x400114c8
+#define CYREG_B1_P2_U1_CFG9 0x400114c9
+#define CYREG_B1_P2_U1_CFG10 0x400114ca
+#define CYREG_B1_P2_U1_CFG11 0x400114cb
+#define CYREG_B1_P2_U1_CFG12 0x400114cc
+#define CYREG_B1_P2_U1_CFG13 0x400114cd
+#define CYREG_B1_P2_U1_CFG14 0x400114ce
+#define CYREG_B1_P2_U1_CFG15 0x400114cf
+#define CYREG_B1_P2_U1_CFG16 0x400114d0
+#define CYREG_B1_P2_U1_CFG17 0x400114d1
+#define CYREG_B1_P2_U1_CFG18 0x400114d2
+#define CYREG_B1_P2_U1_CFG19 0x400114d3
+#define CYREG_B1_P2_U1_CFG20 0x400114d4
+#define CYREG_B1_P2_U1_CFG21 0x400114d5
+#define CYREG_B1_P2_U1_CFG22 0x400114d6
+#define CYREG_B1_P2_U1_CFG23 0x400114d7
+#define CYREG_B1_P2_U1_CFG24 0x400114d8
+#define CYREG_B1_P2_U1_CFG25 0x400114d9
+#define CYREG_B1_P2_U1_CFG26 0x400114da
+#define CYREG_B1_P2_U1_CFG27 0x400114db
+#define CYREG_B1_P2_U1_CFG28 0x400114dc
+#define CYREG_B1_P2_U1_CFG29 0x400114dd
+#define CYREG_B1_P2_U1_CFG30 0x400114de
+#define CYREG_B1_P2_U1_CFG31 0x400114df
+#define CYREG_B1_P2_U1_DCFG0 0x400114e0
+#define CYREG_B1_P2_U1_DCFG1 0x400114e2
+#define CYREG_B1_P2_U1_DCFG2 0x400114e4
+#define CYREG_B1_P2_U1_DCFG3 0x400114e6
+#define CYREG_B1_P2_U1_DCFG4 0x400114e8
+#define CYREG_B1_P2_U1_DCFG5 0x400114ea
+#define CYREG_B1_P2_U1_DCFG6 0x400114ec
+#define CYREG_B1_P2_U1_DCFG7 0x400114ee
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070
+#define CYREG_B1_P3_U0_PLD_IT0 0x40011600
+#define CYREG_B1_P3_U0_PLD_IT1 0x40011604
+#define CYREG_B1_P3_U0_PLD_IT2 0x40011608
+#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c
+#define CYREG_B1_P3_U0_PLD_IT4 0x40011610
+#define CYREG_B1_P3_U0_PLD_IT5 0x40011614
+#define CYREG_B1_P3_U0_PLD_IT6 0x40011618
+#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c
+#define CYREG_B1_P3_U0_PLD_IT8 0x40011620
+#define CYREG_B1_P3_U0_PLD_IT9 0x40011624
+#define CYREG_B1_P3_U0_PLD_IT10 0x40011628
+#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c
+#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630
+#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632
+#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634
+#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636
+#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638
+#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a
+#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c
+#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e
+#define CYREG_B1_P3_U0_CFG0 0x40011640
+#define CYREG_B1_P3_U0_CFG1 0x40011641
+#define CYREG_B1_P3_U0_CFG2 0x40011642
+#define CYREG_B1_P3_U0_CFG3 0x40011643
+#define CYREG_B1_P3_U0_CFG4 0x40011644
+#define CYREG_B1_P3_U0_CFG5 0x40011645
+#define CYREG_B1_P3_U0_CFG6 0x40011646
+#define CYREG_B1_P3_U0_CFG7 0x40011647
+#define CYREG_B1_P3_U0_CFG8 0x40011648
+#define CYREG_B1_P3_U0_CFG9 0x40011649
+#define CYREG_B1_P3_U0_CFG10 0x4001164a
+#define CYREG_B1_P3_U0_CFG11 0x4001164b
+#define CYREG_B1_P3_U0_CFG12 0x4001164c
+#define CYREG_B1_P3_U0_CFG13 0x4001164d
+#define CYREG_B1_P3_U0_CFG14 0x4001164e
+#define CYREG_B1_P3_U0_CFG15 0x4001164f
+#define CYREG_B1_P3_U0_CFG16 0x40011650
+#define CYREG_B1_P3_U0_CFG17 0x40011651
+#define CYREG_B1_P3_U0_CFG18 0x40011652
+#define CYREG_B1_P3_U0_CFG19 0x40011653
+#define CYREG_B1_P3_U0_CFG20 0x40011654
+#define CYREG_B1_P3_U0_CFG21 0x40011655
+#define CYREG_B1_P3_U0_CFG22 0x40011656
+#define CYREG_B1_P3_U0_CFG23 0x40011657
+#define CYREG_B1_P3_U0_CFG24 0x40011658
+#define CYREG_B1_P3_U0_CFG25 0x40011659
+#define CYREG_B1_P3_U0_CFG26 0x4001165a
+#define CYREG_B1_P3_U0_CFG27 0x4001165b
+#define CYREG_B1_P3_U0_CFG28 0x4001165c
+#define CYREG_B1_P3_U0_CFG29 0x4001165d
+#define CYREG_B1_P3_U0_CFG30 0x4001165e
+#define CYREG_B1_P3_U0_CFG31 0x4001165f
+#define CYREG_B1_P3_U0_DCFG0 0x40011660
+#define CYREG_B1_P3_U0_DCFG1 0x40011662
+#define CYREG_B1_P3_U0_DCFG2 0x40011664
+#define CYREG_B1_P3_U0_DCFG3 0x40011666
+#define CYREG_B1_P3_U0_DCFG4 0x40011668
+#define CYREG_B1_P3_U0_DCFG5 0x4001166a
+#define CYREG_B1_P3_U0_DCFG6 0x4001166c
+#define CYREG_B1_P3_U0_DCFG7 0x4001166e
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070
+#define CYREG_B1_P3_U1_PLD_IT0 0x40011680
+#define CYREG_B1_P3_U1_PLD_IT1 0x40011684
+#define CYREG_B1_P3_U1_PLD_IT2 0x40011688
+#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c
+#define CYREG_B1_P3_U1_PLD_IT4 0x40011690
+#define CYREG_B1_P3_U1_PLD_IT5 0x40011694
+#define CYREG_B1_P3_U1_PLD_IT6 0x40011698
+#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c
+#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0
+#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4
+#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8
+#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac
+#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0
+#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2
+#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4
+#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6
+#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8
+#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba
+#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc
+#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be
+#define CYREG_B1_P3_U1_CFG0 0x400116c0
+#define CYREG_B1_P3_U1_CFG1 0x400116c1
+#define CYREG_B1_P3_U1_CFG2 0x400116c2
+#define CYREG_B1_P3_U1_CFG3 0x400116c3
+#define CYREG_B1_P3_U1_CFG4 0x400116c4
+#define CYREG_B1_P3_U1_CFG5 0x400116c5
+#define CYREG_B1_P3_U1_CFG6 0x400116c6
+#define CYREG_B1_P3_U1_CFG7 0x400116c7
+#define CYREG_B1_P3_U1_CFG8 0x400116c8
+#define CYREG_B1_P3_U1_CFG9 0x400116c9
+#define CYREG_B1_P3_U1_CFG10 0x400116ca
+#define CYREG_B1_P3_U1_CFG11 0x400116cb
+#define CYREG_B1_P3_U1_CFG12 0x400116cc
+#define CYREG_B1_P3_U1_CFG13 0x400116cd
+#define CYREG_B1_P3_U1_CFG14 0x400116ce
+#define CYREG_B1_P3_U1_CFG15 0x400116cf
+#define CYREG_B1_P3_U1_CFG16 0x400116d0
+#define CYREG_B1_P3_U1_CFG17 0x400116d1
+#define CYREG_B1_P3_U1_CFG18 0x400116d2
+#define CYREG_B1_P3_U1_CFG19 0x400116d3
+#define CYREG_B1_P3_U1_CFG20 0x400116d4
+#define CYREG_B1_P3_U1_CFG21 0x400116d5
+#define CYREG_B1_P3_U1_CFG22 0x400116d6
+#define CYREG_B1_P3_U1_CFG23 0x400116d7
+#define CYREG_B1_P3_U1_CFG24 0x400116d8
+#define CYREG_B1_P3_U1_CFG25 0x400116d9
+#define CYREG_B1_P3_U1_CFG26 0x400116da
+#define CYREG_B1_P3_U1_CFG27 0x400116db
+#define CYREG_B1_P3_U1_CFG28 0x400116dc
+#define CYREG_B1_P3_U1_CFG29 0x400116dd
+#define CYREG_B1_P3_U1_CFG30 0x400116de
+#define CYREG_B1_P3_U1_CFG31 0x400116df
+#define CYREG_B1_P3_U1_DCFG0 0x400116e0
+#define CYREG_B1_P3_U1_DCFG1 0x400116e2
+#define CYREG_B1_P3_U1_DCFG2 0x400116e4
+#define CYREG_B1_P3_U1_DCFG3 0x400116e6
+#define CYREG_B1_P3_U1_DCFG4 0x400116e8
+#define CYREG_B1_P3_U1_DCFG5 0x400116ea
+#define CYREG_B1_P3_U1_DCFG6 0x400116ec
+#define CYREG_B1_P3_U1_DCFG7 0x400116ee
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070
+#define CYREG_B1_P4_U0_PLD_IT0 0x40011800
+#define CYREG_B1_P4_U0_PLD_IT1 0x40011804
+#define CYREG_B1_P4_U0_PLD_IT2 0x40011808
+#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c
+#define CYREG_B1_P4_U0_PLD_IT4 0x40011810
+#define CYREG_B1_P4_U0_PLD_IT5 0x40011814
+#define CYREG_B1_P4_U0_PLD_IT6 0x40011818
+#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c
+#define CYREG_B1_P4_U0_PLD_IT8 0x40011820
+#define CYREG_B1_P4_U0_PLD_IT9 0x40011824
+#define CYREG_B1_P4_U0_PLD_IT10 0x40011828
+#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c
+#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830
+#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832
+#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834
+#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836
+#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838
+#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a
+#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c
+#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e
+#define CYREG_B1_P4_U0_CFG0 0x40011840
+#define CYREG_B1_P4_U0_CFG1 0x40011841
+#define CYREG_B1_P4_U0_CFG2 0x40011842
+#define CYREG_B1_P4_U0_CFG3 0x40011843
+#define CYREG_B1_P4_U0_CFG4 0x40011844
+#define CYREG_B1_P4_U0_CFG5 0x40011845
+#define CYREG_B1_P4_U0_CFG6 0x40011846
+#define CYREG_B1_P4_U0_CFG7 0x40011847
+#define CYREG_B1_P4_U0_CFG8 0x40011848
+#define CYREG_B1_P4_U0_CFG9 0x40011849
+#define CYREG_B1_P4_U0_CFG10 0x4001184a
+#define CYREG_B1_P4_U0_CFG11 0x4001184b
+#define CYREG_B1_P4_U0_CFG12 0x4001184c
+#define CYREG_B1_P4_U0_CFG13 0x4001184d
+#define CYREG_B1_P4_U0_CFG14 0x4001184e
+#define CYREG_B1_P4_U0_CFG15 0x4001184f
+#define CYREG_B1_P4_U0_CFG16 0x40011850
+#define CYREG_B1_P4_U0_CFG17 0x40011851
+#define CYREG_B1_P4_U0_CFG18 0x40011852
+#define CYREG_B1_P4_U0_CFG19 0x40011853
+#define CYREG_B1_P4_U0_CFG20 0x40011854
+#define CYREG_B1_P4_U0_CFG21 0x40011855
+#define CYREG_B1_P4_U0_CFG22 0x40011856
+#define CYREG_B1_P4_U0_CFG23 0x40011857
+#define CYREG_B1_P4_U0_CFG24 0x40011858
+#define CYREG_B1_P4_U0_CFG25 0x40011859
+#define CYREG_B1_P4_U0_CFG26 0x4001185a
+#define CYREG_B1_P4_U0_CFG27 0x4001185b
+#define CYREG_B1_P4_U0_CFG28 0x4001185c
+#define CYREG_B1_P4_U0_CFG29 0x4001185d
+#define CYREG_B1_P4_U0_CFG30 0x4001185e
+#define CYREG_B1_P4_U0_CFG31 0x4001185f
+#define CYREG_B1_P4_U0_DCFG0 0x40011860
+#define CYREG_B1_P4_U0_DCFG1 0x40011862
+#define CYREG_B1_P4_U0_DCFG2 0x40011864
+#define CYREG_B1_P4_U0_DCFG3 0x40011866
+#define CYREG_B1_P4_U0_DCFG4 0x40011868
+#define CYREG_B1_P4_U0_DCFG5 0x4001186a
+#define CYREG_B1_P4_U0_DCFG6 0x4001186c
+#define CYREG_B1_P4_U0_DCFG7 0x4001186e
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070
+#define CYREG_B1_P4_U1_PLD_IT0 0x40011880
+#define CYREG_B1_P4_U1_PLD_IT1 0x40011884
+#define CYREG_B1_P4_U1_PLD_IT2 0x40011888
+#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c
+#define CYREG_B1_P4_U1_PLD_IT4 0x40011890
+#define CYREG_B1_P4_U1_PLD_IT5 0x40011894
+#define CYREG_B1_P4_U1_PLD_IT6 0x40011898
+#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c
+#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0
+#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4
+#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8
+#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac
+#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0
+#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2
+#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4
+#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6
+#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8
+#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba
+#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc
+#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be
+#define CYREG_B1_P4_U1_CFG0 0x400118c0
+#define CYREG_B1_P4_U1_CFG1 0x400118c1
+#define CYREG_B1_P4_U1_CFG2 0x400118c2
+#define CYREG_B1_P4_U1_CFG3 0x400118c3
+#define CYREG_B1_P4_U1_CFG4 0x400118c4
+#define CYREG_B1_P4_U1_CFG5 0x400118c5
+#define CYREG_B1_P4_U1_CFG6 0x400118c6
+#define CYREG_B1_P4_U1_CFG7 0x400118c7
+#define CYREG_B1_P4_U1_CFG8 0x400118c8
+#define CYREG_B1_P4_U1_CFG9 0x400118c9
+#define CYREG_B1_P4_U1_CFG10 0x400118ca
+#define CYREG_B1_P4_U1_CFG11 0x400118cb
+#define CYREG_B1_P4_U1_CFG12 0x400118cc
+#define CYREG_B1_P4_U1_CFG13 0x400118cd
+#define CYREG_B1_P4_U1_CFG14 0x400118ce
+#define CYREG_B1_P4_U1_CFG15 0x400118cf
+#define CYREG_B1_P4_U1_CFG16 0x400118d0
+#define CYREG_B1_P4_U1_CFG17 0x400118d1
+#define CYREG_B1_P4_U1_CFG18 0x400118d2
+#define CYREG_B1_P4_U1_CFG19 0x400118d3
+#define CYREG_B1_P4_U1_CFG20 0x400118d4
+#define CYREG_B1_P4_U1_CFG21 0x400118d5
+#define CYREG_B1_P4_U1_CFG22 0x400118d6
+#define CYREG_B1_P4_U1_CFG23 0x400118d7
+#define CYREG_B1_P4_U1_CFG24 0x400118d8
+#define CYREG_B1_P4_U1_CFG25 0x400118d9
+#define CYREG_B1_P4_U1_CFG26 0x400118da
+#define CYREG_B1_P4_U1_CFG27 0x400118db
+#define CYREG_B1_P4_U1_CFG28 0x400118dc
+#define CYREG_B1_P4_U1_CFG29 0x400118dd
+#define CYREG_B1_P4_U1_CFG30 0x400118de
+#define CYREG_B1_P4_U1_CFG31 0x400118df
+#define CYREG_B1_P4_U1_DCFG0 0x400118e0
+#define CYREG_B1_P4_U1_DCFG1 0x400118e2
+#define CYREG_B1_P4_U1_DCFG2 0x400118e4
+#define CYREG_B1_P4_U1_DCFG3 0x400118e6
+#define CYREG_B1_P4_U1_DCFG4 0x400118e8
+#define CYREG_B1_P4_U1_DCFG5 0x400118ea
+#define CYREG_B1_P4_U1_DCFG6 0x400118ec
+#define CYREG_B1_P4_U1_DCFG7 0x400118ee
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070
+#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00
+#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04
+#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08
+#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c
+#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10
+#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14
+#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18
+#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c
+#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20
+#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24
+#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28
+#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c
+#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30
+#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32
+#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34
+#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36
+#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38
+#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a
+#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c
+#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e
+#define CYREG_B1_P5_U0_CFG0 0x40011a40
+#define CYREG_B1_P5_U0_CFG1 0x40011a41
+#define CYREG_B1_P5_U0_CFG2 0x40011a42
+#define CYREG_B1_P5_U0_CFG3 0x40011a43
+#define CYREG_B1_P5_U0_CFG4 0x40011a44
+#define CYREG_B1_P5_U0_CFG5 0x40011a45
+#define CYREG_B1_P5_U0_CFG6 0x40011a46
+#define CYREG_B1_P5_U0_CFG7 0x40011a47
+#define CYREG_B1_P5_U0_CFG8 0x40011a48
+#define CYREG_B1_P5_U0_CFG9 0x40011a49
+#define CYREG_B1_P5_U0_CFG10 0x40011a4a
+#define CYREG_B1_P5_U0_CFG11 0x40011a4b
+#define CYREG_B1_P5_U0_CFG12 0x40011a4c
+#define CYREG_B1_P5_U0_CFG13 0x40011a4d
+#define CYREG_B1_P5_U0_CFG14 0x40011a4e
+#define CYREG_B1_P5_U0_CFG15 0x40011a4f
+#define CYREG_B1_P5_U0_CFG16 0x40011a50
+#define CYREG_B1_P5_U0_CFG17 0x40011a51
+#define CYREG_B1_P5_U0_CFG18 0x40011a52
+#define CYREG_B1_P5_U0_CFG19 0x40011a53
+#define CYREG_B1_P5_U0_CFG20 0x40011a54
+#define CYREG_B1_P5_U0_CFG21 0x40011a55
+#define CYREG_B1_P5_U0_CFG22 0x40011a56
+#define CYREG_B1_P5_U0_CFG23 0x40011a57
+#define CYREG_B1_P5_U0_CFG24 0x40011a58
+#define CYREG_B1_P5_U0_CFG25 0x40011a59
+#define CYREG_B1_P5_U0_CFG26 0x40011a5a
+#define CYREG_B1_P5_U0_CFG27 0x40011a5b
+#define CYREG_B1_P5_U0_CFG28 0x40011a5c
+#define CYREG_B1_P5_U0_CFG29 0x40011a5d
+#define CYREG_B1_P5_U0_CFG30 0x40011a5e
+#define CYREG_B1_P5_U0_CFG31 0x40011a5f
+#define CYREG_B1_P5_U0_DCFG0 0x40011a60
+#define CYREG_B1_P5_U0_DCFG1 0x40011a62
+#define CYREG_B1_P5_U0_DCFG2 0x40011a64
+#define CYREG_B1_P5_U0_DCFG3 0x40011a66
+#define CYREG_B1_P5_U0_DCFG4 0x40011a68
+#define CYREG_B1_P5_U0_DCFG5 0x40011a6a
+#define CYREG_B1_P5_U0_DCFG6 0x40011a6c
+#define CYREG_B1_P5_U0_DCFG7 0x40011a6e
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070
+#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80
+#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84
+#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88
+#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c
+#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90
+#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94
+#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98
+#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c
+#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0
+#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4
+#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8
+#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac
+#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0
+#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2
+#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4
+#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6
+#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8
+#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba
+#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc
+#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe
+#define CYREG_B1_P5_U1_CFG0 0x40011ac0
+#define CYREG_B1_P5_U1_CFG1 0x40011ac1
+#define CYREG_B1_P5_U1_CFG2 0x40011ac2
+#define CYREG_B1_P5_U1_CFG3 0x40011ac3
+#define CYREG_B1_P5_U1_CFG4 0x40011ac4
+#define CYREG_B1_P5_U1_CFG5 0x40011ac5
+#define CYREG_B1_P5_U1_CFG6 0x40011ac6
+#define CYREG_B1_P5_U1_CFG7 0x40011ac7
+#define CYREG_B1_P5_U1_CFG8 0x40011ac8
+#define CYREG_B1_P5_U1_CFG9 0x40011ac9
+#define CYREG_B1_P5_U1_CFG10 0x40011aca
+#define CYREG_B1_P5_U1_CFG11 0x40011acb
+#define CYREG_B1_P5_U1_CFG12 0x40011acc
+#define CYREG_B1_P5_U1_CFG13 0x40011acd
+#define CYREG_B1_P5_U1_CFG14 0x40011ace
+#define CYREG_B1_P5_U1_CFG15 0x40011acf
+#define CYREG_B1_P5_U1_CFG16 0x40011ad0
+#define CYREG_B1_P5_U1_CFG17 0x40011ad1
+#define CYREG_B1_P5_U1_CFG18 0x40011ad2
+#define CYREG_B1_P5_U1_CFG19 0x40011ad3
+#define CYREG_B1_P5_U1_CFG20 0x40011ad4
+#define CYREG_B1_P5_U1_CFG21 0x40011ad5
+#define CYREG_B1_P5_U1_CFG22 0x40011ad6
+#define CYREG_B1_P5_U1_CFG23 0x40011ad7
+#define CYREG_B1_P5_U1_CFG24 0x40011ad8
+#define CYREG_B1_P5_U1_CFG25 0x40011ad9
+#define CYREG_B1_P5_U1_CFG26 0x40011ada
+#define CYREG_B1_P5_U1_CFG27 0x40011adb
+#define CYREG_B1_P5_U1_CFG28 0x40011adc
+#define CYREG_B1_P5_U1_CFG29 0x40011add
+#define CYREG_B1_P5_U1_CFG30 0x40011ade
+#define CYREG_B1_P5_U1_CFG31 0x40011adf
+#define CYREG_B1_P5_U1_DCFG0 0x40011ae0
+#define CYREG_B1_P5_U1_DCFG1 0x40011ae2
+#define CYREG_B1_P5_U1_DCFG2 0x40011ae4
+#define CYREG_B1_P5_U1_DCFG3 0x40011ae6
+#define CYREG_B1_P5_U1_DCFG4 0x40011ae8
+#define CYREG_B1_P5_U1_DCFG5 0x40011aea
+#define CYREG_B1_P5_U1_DCFG6 0x40011aec
+#define CYREG_B1_P5_U1_DCFG7 0x40011aee
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI0_BASE 0x40014000
+#define CYDEV_UCFG_DSI0_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI1_BASE 0x40014100
+#define CYDEV_UCFG_DSI1_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI2_BASE 0x40014200
+#define CYDEV_UCFG_DSI2_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI3_BASE 0x40014300
+#define CYDEV_UCFG_DSI3_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI4_BASE 0x40014400
+#define CYDEV_UCFG_DSI4_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI5_BASE 0x40014500
+#define CYDEV_UCFG_DSI5_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI6_BASE 0x40014600
+#define CYDEV_UCFG_DSI6_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI7_BASE 0x40014700
+#define CYDEV_UCFG_DSI7_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI8_BASE 0x40014800
+#define CYDEV_UCFG_DSI8_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI9_BASE 0x40014900
+#define CYDEV_UCFG_DSI9_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00
+#define CYDEV_UCFG_DSI12_SIZE 0x000000ef
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00
+#define CYDEV_UCFG_DSI13_SIZE 0x000000ef
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010
+#define CYREG_BCTL0_MDCLK_EN 0x40015000
+#define CYREG_BCTL0_MBCLK_EN 0x40015001
+#define CYREG_BCTL0_WAIT_CFG 0x40015002
+#define CYREG_BCTL0_BANK_CTL 0x40015003
+#define CYREG_BCTL0_UDB_TEST_3 0x40015007
+#define CYREG_BCTL0_DCLK_EN0 0x40015008
+#define CYREG_BCTL0_BCLK_EN0 0x40015009
+#define CYREG_BCTL0_DCLK_EN1 0x4001500a
+#define CYREG_BCTL0_BCLK_EN1 0x4001500b
+#define CYREG_BCTL0_DCLK_EN2 0x4001500c
+#define CYREG_BCTL0_BCLK_EN2 0x4001500d
+#define CYREG_BCTL0_DCLK_EN3 0x4001500e
+#define CYREG_BCTL0_BCLK_EN3 0x4001500f
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010
+#define CYREG_BCTL1_MDCLK_EN 0x40015010
+#define CYREG_BCTL1_MBCLK_EN 0x40015011
+#define CYREG_BCTL1_WAIT_CFG 0x40015012
+#define CYREG_BCTL1_BANK_CTL 0x40015013
+#define CYREG_BCTL1_UDB_TEST_3 0x40015017
+#define CYREG_BCTL1_DCLK_EN0 0x40015018
+#define CYREG_BCTL1_BCLK_EN0 0x40015019
+#define CYREG_BCTL1_DCLK_EN1 0x4001501a
+#define CYREG_BCTL1_BCLK_EN1 0x4001501b
+#define CYREG_BCTL1_DCLK_EN2 0x4001501c
+#define CYREG_BCTL1_BCLK_EN2 0x4001501d
+#define CYREG_BCTL1_DCLK_EN3 0x4001501e
+#define CYREG_BCTL1_BCLK_EN3 0x4001501f
+#define CYDEV_IDMUX_BASE 0x40015100
+#define CYDEV_IDMUX_SIZE 0x00000016
+#define CYREG_IDMUX_IRQ_CTL0 0x40015100
+#define CYREG_IDMUX_IRQ_CTL1 0x40015101
+#define CYREG_IDMUX_IRQ_CTL2 0x40015102
+#define CYREG_IDMUX_IRQ_CTL3 0x40015103
+#define CYREG_IDMUX_IRQ_CTL4 0x40015104
+#define CYREG_IDMUX_IRQ_CTL5 0x40015105
+#define CYREG_IDMUX_IRQ_CTL6 0x40015106
+#define CYREG_IDMUX_IRQ_CTL7 0x40015107
+#define CYREG_IDMUX_DRQ_CTL0 0x40015110
+#define CYREG_IDMUX_DRQ_CTL1 0x40015111
+#define CYREG_IDMUX_DRQ_CTL2 0x40015112
+#define CYREG_IDMUX_DRQ_CTL3 0x40015113
+#define CYREG_IDMUX_DRQ_CTL4 0x40015114
+#define CYREG_IDMUX_DRQ_CTL5 0x40015115
+#define CYDEV_CACHERAM_BASE 0x40030000
+#define CYDEV_CACHERAM_SIZE 0x00000400
+#define CYREG_CACHERAM_DATA_MBASE 0x40030000
+#define CYREG_CACHERAM_DATA_MSIZE 0x00000400
+#define CYDEV_SFR_BASE 0x40050100
+#define CYDEV_SFR_SIZE 0x000000fb
+#define CYREG_SFR_GPIO0 0x40050180
+#define CYREG_SFR_GPIRD0 0x40050189
+#define CYREG_SFR_GPIO0_SEL 0x4005018a
+#define CYREG_SFR_GPIO1 0x40050190
+#define CYREG_SFR_GPIRD1 0x40050191
+#define CYREG_SFR_GPIO2 0x40050198
+#define CYREG_SFR_GPIRD2 0x40050199
+#define CYREG_SFR_GPIO2_SEL 0x4005019a
+#define CYREG_SFR_GPIO1_SEL 0x400501a2
+#define CYREG_SFR_GPIO3 0x400501b0
+#define CYREG_SFR_GPIRD3 0x400501b1
+#define CYREG_SFR_GPIO3_SEL 0x400501b2
+#define CYREG_SFR_GPIO4 0x400501c0
+#define CYREG_SFR_GPIRD4 0x400501c1
+#define CYREG_SFR_GPIO4_SEL 0x400501c2
+#define CYREG_SFR_GPIO5 0x400501c8
+#define CYREG_SFR_GPIRD5 0x400501c9
+#define CYREG_SFR_GPIO5_SEL 0x400501ca
+#define CYREG_SFR_GPIO6 0x400501d8
+#define CYREG_SFR_GPIRD6 0x400501d9
+#define CYREG_SFR_GPIO6_SEL 0x400501da
+#define CYREG_SFR_GPIO12 0x400501e8
+#define CYREG_SFR_GPIRD12 0x400501e9
+#define CYREG_SFR_GPIO12_SEL 0x400501f2
+#define CYREG_SFR_GPIO15 0x400501f8
+#define CYREG_SFR_GPIRD15 0x400501f9
+#define CYREG_SFR_GPIO15_SEL 0x400501fa
+#define CYDEV_P3BA_BASE 0x40050300
+#define CYDEV_P3BA_SIZE 0x0000002b
+#define CYREG_P3BA_Y_START 0x40050300
+#define CYREG_P3BA_YROLL 0x40050301
+#define CYREG_P3BA_YCFG 0x40050302
+#define CYREG_P3BA_X_START1 0x40050303
+#define CYREG_P3BA_X_START2 0x40050304
+#define CYREG_P3BA_XROLL1 0x40050305
+#define CYREG_P3BA_XROLL2 0x40050306
+#define CYREG_P3BA_XINC 0x40050307
+#define CYREG_P3BA_XCFG 0x40050308
+#define CYREG_P3BA_OFFSETADDR1 0x40050309
+#define CYREG_P3BA_OFFSETADDR2 0x4005030a
+#define CYREG_P3BA_OFFSETADDR3 0x4005030b
+#define CYREG_P3BA_ABSADDR1 0x4005030c
+#define CYREG_P3BA_ABSADDR2 0x4005030d
+#define CYREG_P3BA_ABSADDR3 0x4005030e
+#define CYREG_P3BA_ABSADDR4 0x4005030f
+#define CYREG_P3BA_DATCFG1 0x40050310
+#define CYREG_P3BA_DATCFG2 0x40050311
+#define CYREG_P3BA_CMP_RSLT1 0x40050314
+#define CYREG_P3BA_CMP_RSLT2 0x40050315
+#define CYREG_P3BA_CMP_RSLT3 0x40050316
+#define CYREG_P3BA_CMP_RSLT4 0x40050317
+#define CYREG_P3BA_DATA_REG1 0x40050318
+#define CYREG_P3BA_DATA_REG2 0x40050319
+#define CYREG_P3BA_DATA_REG3 0x4005031a
+#define CYREG_P3BA_DATA_REG4 0x4005031b
+#define CYREG_P3BA_EXP_DATA1 0x4005031c
+#define CYREG_P3BA_EXP_DATA2 0x4005031d
+#define CYREG_P3BA_EXP_DATA3 0x4005031e
+#define CYREG_P3BA_EXP_DATA4 0x4005031f
+#define CYREG_P3BA_MSTR_HRDATA1 0x40050320
+#define CYREG_P3BA_MSTR_HRDATA2 0x40050321
+#define CYREG_P3BA_MSTR_HRDATA3 0x40050322
+#define CYREG_P3BA_MSTR_HRDATA4 0x40050323
+#define CYREG_P3BA_BIST_EN 0x40050324
+#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325
+#define CYREG_P3BA_SEQCFG1 0x40050326
+#define CYREG_P3BA_SEQCFG2 0x40050327
+#define CYREG_P3BA_Y_CURR 0x40050328
+#define CYREG_P3BA_X_CURR1 0x40050329
+#define CYREG_P3BA_X_CURR2 0x4005032a
+#define CYDEV_PANTHER_BASE 0x40080000
+#define CYDEV_PANTHER_SIZE 0x00000020
+#define CYREG_PANTHER_STCALIB_CFG 0x40080000
+#define CYREG_PANTHER_WAITPIPE 0x40080004
+#define CYREG_PANTHER_TRACE_CFG 0x40080008
+#define CYREG_PANTHER_DBG_CFG 0x4008000c
+#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018
+#define CYREG_PANTHER_DEVICE_ID 0x4008001c
+#define CYDEV_FLSECC_BASE 0x48000000
+#define CYDEV_FLSECC_SIZE 0x00008000
+#define CYREG_FLSECC_DATA_MBASE 0x48000000
+#define CYREG_FLSECC_DATA_MSIZE 0x00008000
+#define CYDEV_FLSHID_BASE 0x49000000
+#define CYDEV_FLSHID_SIZE 0x00000200
+#define CYREG_FLSHID_RSVD_MBASE 0x49000000
+#define CYREG_FLSHID_RSVD_MSIZE 0x00000080
+#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080
+#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040
+#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100
+#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101
+#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102
+#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103
+#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104
+#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105
+#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106
+#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107
+#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108
+#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109
+#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a
+#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b
+#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c
+#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d
+#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e
+#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117
+#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118
+#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119
+#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a
+#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b
+#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c
+#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d
+#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e
+#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080
+#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba
+#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce
+#define CYDEV_EXTMEM_BASE 0x60000000
+#define CYDEV_EXTMEM_SIZE 0x00800000
+#define CYREG_EXTMEM_DATA_MBASE 0x60000000
+#define CYREG_EXTMEM_DATA_MSIZE 0x00800000
+#define CYDEV_ITM_BASE 0xe0000000
+#define CYDEV_ITM_SIZE 0x00001000
+#define CYREG_ITM_TRACE_EN 0xe0000e00
+#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40
+#define CYREG_ITM_TRACE_CTRL 0xe0000e80
+#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0
+#define CYREG_ITM_LOCK_STATUS 0xe0000fb4
+#define CYREG_ITM_PID4 0xe0000fd0
+#define CYREG_ITM_PID5 0xe0000fd4
+#define CYREG_ITM_PID6 0xe0000fd8
+#define CYREG_ITM_PID7 0xe0000fdc
+#define CYREG_ITM_PID0 0xe0000fe0
+#define CYREG_ITM_PID1 0xe0000fe4
+#define CYREG_ITM_PID2 0xe0000fe8
+#define CYREG_ITM_PID3 0xe0000fec
+#define CYREG_ITM_CID0 0xe0000ff0
+#define CYREG_ITM_CID1 0xe0000ff4
+#define CYREG_ITM_CID2 0xe0000ff8
+#define CYREG_ITM_CID3 0xe0000ffc
+#define CYDEV_DWT_BASE 0xe0001000
+#define CYDEV_DWT_SIZE 0x0000005c
+#define CYREG_DWT_CTRL 0xe0001000
+#define CYREG_DWT_CYCLE_COUNT 0xe0001004
+#define CYREG_DWT_CPI_COUNT 0xe0001008
+#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c
+#define CYREG_DWT_SLEEP_COUNT 0xe0001010
+#define CYREG_DWT_LSU_COUNT 0xe0001014
+#define CYREG_DWT_FOLD_COUNT 0xe0001018
+#define CYREG_DWT_PC_SAMPLE 0xe000101c
+#define CYREG_DWT_COMP_0 0xe0001020
+#define CYREG_DWT_MASK_0 0xe0001024
+#define CYREG_DWT_FUNCTION_0 0xe0001028
+#define CYREG_DWT_COMP_1 0xe0001030
+#define CYREG_DWT_MASK_1 0xe0001034
+#define CYREG_DWT_FUNCTION_1 0xe0001038
+#define CYREG_DWT_COMP_2 0xe0001040
+#define CYREG_DWT_MASK_2 0xe0001044
+#define CYREG_DWT_FUNCTION_2 0xe0001048
+#define CYREG_DWT_COMP_3 0xe0001050
+#define CYREG_DWT_MASK_3 0xe0001054
+#define CYREG_DWT_FUNCTION_3 0xe0001058
+#define CYDEV_FPB_BASE 0xe0002000
+#define CYDEV_FPB_SIZE 0x00001000
+#define CYREG_FPB_CTRL 0xe0002000
+#define CYREG_FPB_REMAP 0xe0002004
+#define CYREG_FPB_FP_COMP_0 0xe0002008
+#define CYREG_FPB_FP_COMP_1 0xe000200c
+#define CYREG_FPB_FP_COMP_2 0xe0002010
+#define CYREG_FPB_FP_COMP_3 0xe0002014
+#define CYREG_FPB_FP_COMP_4 0xe0002018
+#define CYREG_FPB_FP_COMP_5 0xe000201c
+#define CYREG_FPB_FP_COMP_6 0xe0002020
+#define CYREG_FPB_FP_COMP_7 0xe0002024
+#define CYREG_FPB_PID4 0xe0002fd0
+#define CYREG_FPB_PID5 0xe0002fd4
+#define CYREG_FPB_PID6 0xe0002fd8
+#define CYREG_FPB_PID7 0xe0002fdc
+#define CYREG_FPB_PID0 0xe0002fe0
+#define CYREG_FPB_PID1 0xe0002fe4
+#define CYREG_FPB_PID2 0xe0002fe8
+#define CYREG_FPB_PID3 0xe0002fec
+#define CYREG_FPB_CID0 0xe0002ff0
+#define CYREG_FPB_CID1 0xe0002ff4
+#define CYREG_FPB_CID2 0xe0002ff8
+#define CYREG_FPB_CID3 0xe0002ffc
+#define CYDEV_NVIC_BASE 0xe000e000
+#define CYDEV_NVIC_SIZE 0x00000d3c
+#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004
+#define CYREG_NVIC_SYSTICK_CTL 0xe000e010
+#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014
+#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018
+#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c
+#define CYREG_NVIC_SETENA0 0xe000e100
+#define CYREG_NVIC_CLRENA0 0xe000e180
+#define CYREG_NVIC_SETPEND0 0xe000e200
+#define CYREG_NVIC_CLRPEND0 0xe000e280
+#define CYREG_NVIC_ACTIVE0 0xe000e300
+#define CYREG_NVIC_PRI_0 0xe000e400
+#define CYREG_NVIC_PRI_1 0xe000e401
+#define CYREG_NVIC_PRI_2 0xe000e402
+#define CYREG_NVIC_PRI_3 0xe000e403
+#define CYREG_NVIC_PRI_4 0xe000e404
+#define CYREG_NVIC_PRI_5 0xe000e405
+#define CYREG_NVIC_PRI_6 0xe000e406
+#define CYREG_NVIC_PRI_7 0xe000e407
+#define CYREG_NVIC_PRI_8 0xe000e408
+#define CYREG_NVIC_PRI_9 0xe000e409
+#define CYREG_NVIC_PRI_10 0xe000e40a
+#define CYREG_NVIC_PRI_11 0xe000e40b
+#define CYREG_NVIC_PRI_12 0xe000e40c
+#define CYREG_NVIC_PRI_13 0xe000e40d
+#define CYREG_NVIC_PRI_14 0xe000e40e
+#define CYREG_NVIC_PRI_15 0xe000e40f
+#define CYREG_NVIC_PRI_16 0xe000e410
+#define CYREG_NVIC_PRI_17 0xe000e411
+#define CYREG_NVIC_PRI_18 0xe000e412
+#define CYREG_NVIC_PRI_19 0xe000e413
+#define CYREG_NVIC_PRI_20 0xe000e414
+#define CYREG_NVIC_PRI_21 0xe000e415
+#define CYREG_NVIC_PRI_22 0xe000e416
+#define CYREG_NVIC_PRI_23 0xe000e417
+#define CYREG_NVIC_PRI_24 0xe000e418
+#define CYREG_NVIC_PRI_25 0xe000e419
+#define CYREG_NVIC_PRI_26 0xe000e41a
+#define CYREG_NVIC_PRI_27 0xe000e41b
+#define CYREG_NVIC_PRI_28 0xe000e41c
+#define CYREG_NVIC_PRI_29 0xe000e41d
+#define CYREG_NVIC_PRI_30 0xe000e41e
+#define CYREG_NVIC_PRI_31 0xe000e41f
+#define CYREG_NVIC_CPUID_BASE 0xe000ed00
+#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04
+#define CYREG_NVIC_VECT_OFFSET 0xe000ed08
+#define CYREG_NVIC_APPLN_INTR 0xe000ed0c
+#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10
+#define CYREG_NVIC_CFG_CONTROL 0xe000ed14
+#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18
+#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c
+#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20
+#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24
+#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28
+#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29
+#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a
+#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c
+#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30
+#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34
+#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38
+#define CYDEV_CORE_DBG_BASE 0xe000edf0
+#define CYDEV_CORE_DBG_SIZE 0x00000010
+#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0
+#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4
+#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8
+#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc
+#define CYDEV_TPIU_BASE 0xe0040000
+#define CYDEV_TPIU_SIZE 0x00001000
+#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000
+#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004
+#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010
+#define CYREG_TPIU_PROTOCOL 0xe00400f0
+#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300
+#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304
+#define CYREG_TPIU_TRIGGER 0xe0040ee8
+#define CYREG_TPIU_ITETMDATA 0xe0040eec
+#define CYREG_TPIU_ITATBCTR2 0xe0040ef0
+#define CYREG_TPIU_ITATBCTR0 0xe0040ef8
+#define CYREG_TPIU_ITITMDATA 0xe0040efc
+#define CYREG_TPIU_ITCTRL 0xe0040f00
+#define CYREG_TPIU_DEVID 0xe0040fc8
+#define CYREG_TPIU_DEVTYPE 0xe0040fcc
+#define CYREG_TPIU_PID4 0xe0040fd0
+#define CYREG_TPIU_PID5 0xe0040fd4
+#define CYREG_TPIU_PID6 0xe0040fd8
+#define CYREG_TPIU_PID7 0xe0040fdc
+#define CYREG_TPIU_PID0 0xe0040fe0
+#define CYREG_TPIU_PID1 0xe0040fe4
+#define CYREG_TPIU_PID2 0xe0040fe8
+#define CYREG_TPIU_PID3 0xe0040fec
+#define CYREG_TPIU_CID0 0xe0040ff0
+#define CYREG_TPIU_CID1 0xe0040ff4
+#define CYREG_TPIU_CID2 0xe0040ff8
+#define CYREG_TPIU_CID3 0xe0040ffc
+#define CYDEV_ETM_BASE 0xe0041000
+#define CYDEV_ETM_SIZE 0x00001000
+#define CYREG_ETM_CTL 0xe0041000
+#define CYREG_ETM_CFG_CODE 0xe0041004
+#define CYREG_ETM_TRIG_EVENT 0xe0041008
+#define CYREG_ETM_STATUS 0xe0041010
+#define CYREG_ETM_SYS_CFG 0xe0041014
+#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020
+#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024
+#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c
+#define CYREG_ETM_SYNC_FREQ 0xe00411e0
+#define CYREG_ETM_ETM_ID 0xe00411e4
+#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8
+#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0
+#define CYREG_ETM_CS_TRACE_ID 0xe0041200
+#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300
+#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304
+#define CYREG_ETM_PDSR 0xe0041314
+#define CYREG_ETM_ITMISCIN 0xe0041ee0
+#define CYREG_ETM_ITTRIGOUT 0xe0041ee8
+#define CYREG_ETM_ITATBCTR2 0xe0041ef0
+#define CYREG_ETM_ITATBCTR0 0xe0041ef8
+#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00
+#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0
+#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4
+#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0
+#define CYREG_ETM_LOCK_STATUS 0xe0041fb4
+#define CYREG_ETM_AUTH_STATUS 0xe0041fb8
+#define CYREG_ETM_DEV_TYPE 0xe0041fcc
+#define CYREG_ETM_PID4 0xe0041fd0
+#define CYREG_ETM_PID5 0xe0041fd4
+#define CYREG_ETM_PID6 0xe0041fd8
+#define CYREG_ETM_PID7 0xe0041fdc
+#define CYREG_ETM_PID0 0xe0041fe0
+#define CYREG_ETM_PID1 0xe0041fe4
+#define CYREG_ETM_PID2 0xe0041fe8
+#define CYREG_ETM_PID3 0xe0041fec
+#define CYREG_ETM_CID0 0xe0041ff0
+#define CYREG_ETM_CID1 0xe0041ff4
+#define CYREG_ETM_CID2 0xe0041ff8
+#define CYREG_ETM_CID3 0xe0041ffc
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000
+#define CYDEV_ROM_TABLE_SIZE 0x00001000
+#define CYREG_ROM_TABLE_NVIC 0xe00ff000
+#define CYREG_ROM_TABLE_DWT 0xe00ff004
+#define CYREG_ROM_TABLE_FPB 0xe00ff008
+#define CYREG_ROM_TABLE_ITM 0xe00ff00c
+#define CYREG_ROM_TABLE_TPIU 0xe00ff010
+#define CYREG_ROM_TABLE_ETM 0xe00ff014
+#define CYREG_ROM_TABLE_END 0xe00ff018
+#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc
+#define CYREG_ROM_TABLE_PID4 0xe00fffd0
+#define CYREG_ROM_TABLE_PID5 0xe00fffd4
+#define CYREG_ROM_TABLE_PID6 0xe00fffd8
+#define CYREG_ROM_TABLE_PID7 0xe00fffdc
+#define CYREG_ROM_TABLE_PID0 0xe00fffe0
+#define CYREG_ROM_TABLE_PID1 0xe00fffe4
+#define CYREG_ROM_TABLE_PID2 0xe00fffe8
+#define CYREG_ROM_TABLE_PID3 0xe00fffec
+#define CYREG_ROM_TABLE_CID0 0xe00ffff0
+#define CYREG_ROM_TABLE_CID1 0xe00ffff4
+#define CYREG_ROM_TABLE_CID2 0xe00ffff8
+#define CYREG_ROM_TABLE_CID3 0xe00ffffc
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000
+#define CYDEV_FLS_ROW_SIZE 0x00000100
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000
+#define CYDEV_ECC_ROW_SIZE 0x00000020
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE
+#define CYCLK_LD_DISABLE 0x00000004
+#define CYCLK_LD_SYNC_EN 0x00000002
+#define CYCLK_LD_LOAD 0x00000001
+#define CYCLK_PIPE 0x00000080
+#define CYCLK_SSS 0x00000040
+#define CYCLK_EARLY 0x00000020
+#define CYCLK_DUTY 0x00000010
+#define CYCLK_SYNC 0x00000008
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0
+#define CYCLK_SRC_SEL_SYNC_DIG 0
+#define CYCLK_SRC_SEL_IMO 1
+#define CYCLK_SRC_SEL_XTAL_MHZ 2
+#define CYCLK_SRC_SEL_XTALM 2
+#define CYCLK_SRC_SEL_ILO 3
+#define CYCLK_SRC_SEL_PLL 4
+#define CYCLK_SRC_SEL_XTAL_KHZ 5
+#define CYCLK_SRC_SEL_XTALK 5
+#define CYCLK_SRC_SEL_DSI_G 6
+#define CYCLK_SRC_SEL_DSI_D 7
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0
+#define CYCLK_SRC_SEL_DSI_A 7

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc

@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 2.2 Component Pack 6
+; PSoC Creator 3.0
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc

@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator 2.2 Component Pack 6
+; PSoC Creator 3.0
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h

@@ -0,0 +1,5 @@
+#ifndef INCLUDED_CYDISABLEDSHEETS_H
+#define INCLUDED_CYDISABLEDSHEETS_H
+
+
+#endif /* INCLUDED_CYDISABLEDSHEETS_H */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -3,25 +3,15 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 
-/* SDCard_RxInternalInterrupt */
-#define SDCard_RxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SDCard_RxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SDCard_RxInternalInterrupt__INTC_MASK 0x01u
-#define SDCard_RxInternalInterrupt__INTC_NUMBER 0u
-#define SDCard_RxInternalInterrupt__INTC_PRIOR_NUM 7u
-#define SDCard_RxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define SDCard_RxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SDCard_RxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SDCard_TxInternalInterrupt */
-#define SDCard_TxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SDCard_TxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SDCard_TxInternalInterrupt__INTC_MASK 0x02u
-#define SDCard_TxInternalInterrupt__INTC_NUMBER 1u
-#define SDCard_TxInternalInterrupt__INTC_PRIOR_NUM 7u
-#define SDCard_TxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define SDCard_TxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SDCard_TxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_ATN_ISR */
+#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_ATN_ISR__INTC_MASK 0x01u
+#define SCSI_ATN_ISR__INTC_NUMBER 0u
+#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__MASK 0x01u
@@ -62,6 +52,38 @@
 #define SCSI_Out_DBx__BIT_MASK CYREG_PRT0_BIT_MASK
 #define SCSI_Out_DBx__BYP CYREG_PRT0_BYP
 #define SCSI_Out_DBx__CTL CYREG_PRT0_CTL
+#define SCSI_Out_DBx__DB0__MASK 0x01u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT0_PC0
+#define SCSI_Out_DBx__DB0__PORT 0u
+#define SCSI_Out_DBx__DB0__SHIFT 0
+#define SCSI_Out_DBx__DB1__MASK 0x02u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT0_PC1
+#define SCSI_Out_DBx__DB1__PORT 0u
+#define SCSI_Out_DBx__DB1__SHIFT 1
+#define SCSI_Out_DBx__DB2__MASK 0x04u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT0_PC2
+#define SCSI_Out_DBx__DB2__PORT 0u
+#define SCSI_Out_DBx__DB2__SHIFT 2
+#define SCSI_Out_DBx__DB3__MASK 0x08u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT0_PC3
+#define SCSI_Out_DBx__DB3__PORT 0u
+#define SCSI_Out_DBx__DB3__SHIFT 3
+#define SCSI_Out_DBx__DB4__MASK 0x10u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT0_PC4
+#define SCSI_Out_DBx__DB4__PORT 0u
+#define SCSI_Out_DBx__DB4__SHIFT 4
+#define SCSI_Out_DBx__DB5__MASK 0x20u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT0_PC5
+#define SCSI_Out_DBx__DB5__PORT 0u
+#define SCSI_Out_DBx__DB5__SHIFT 5
+#define SCSI_Out_DBx__DB6__MASK 0x40u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT0_PC6
+#define SCSI_Out_DBx__DB6__PORT 0u
+#define SCSI_Out_DBx__DB6__SHIFT 6
+#define SCSI_Out_DBx__DB7__MASK 0x80u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT0_PC7
+#define SCSI_Out_DBx__DB7__PORT 0u
+#define SCSI_Out_DBx__DB7__SHIFT 7
 #define SCSI_Out_DBx__DM0 CYREG_PRT0_DM0
 #define SCSI_Out_DBx__DM1 CYREG_PRT0_DM1
 #define SCSI_Out_DBx__DM2 CYREG_PRT0_DM2
@@ -80,70 +102,48 @@
 #define SCSI_Out_DBx__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
 #define SCSI_Out_DBx__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
 #define SCSI_Out_DBx__PS CYREG_PRT0_PS
-#define SCSI_Out_DBx__SCSI_Out_DB0__MASK 0x01u
-#define SCSI_Out_DBx__SCSI_Out_DB0__PC CYREG_PRT0_PC0
-#define SCSI_Out_DBx__SCSI_Out_DB0__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB0__SHIFT 0
-#define SCSI_Out_DBx__SCSI_Out_DB1__MASK 0x02u
-#define SCSI_Out_DBx__SCSI_Out_DB1__PC CYREG_PRT0_PC1
-#define SCSI_Out_DBx__SCSI_Out_DB1__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB1__SHIFT 1
-#define SCSI_Out_DBx__SCSI_Out_DB2__MASK 0x04u
-#define SCSI_Out_DBx__SCSI_Out_DB2__PC CYREG_PRT0_PC2
-#define SCSI_Out_DBx__SCSI_Out_DB2__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB2__SHIFT 2
-#define SCSI_Out_DBx__SCSI_Out_DB3__MASK 0x08u
-#define SCSI_Out_DBx__SCSI_Out_DB3__PC CYREG_PRT0_PC3
-#define SCSI_Out_DBx__SCSI_Out_DB3__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB3__SHIFT 3
-#define SCSI_Out_DBx__SCSI_Out_DB4__MASK 0x10u
-#define SCSI_Out_DBx__SCSI_Out_DB4__PC CYREG_PRT0_PC4
-#define SCSI_Out_DBx__SCSI_Out_DB4__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB4__SHIFT 4
-#define SCSI_Out_DBx__SCSI_Out_DB5__MASK 0x20u
-#define SCSI_Out_DBx__SCSI_Out_DB5__PC CYREG_PRT0_PC5
-#define SCSI_Out_DBx__SCSI_Out_DB5__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB5__SHIFT 5
-#define SCSI_Out_DBx__SCSI_Out_DB6__MASK 0x40u
-#define SCSI_Out_DBx__SCSI_Out_DB6__PC CYREG_PRT0_PC6
-#define SCSI_Out_DBx__SCSI_Out_DB6__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB6__SHIFT 6
-#define SCSI_Out_DBx__SCSI_Out_DB7__MASK 0x80u
-#define SCSI_Out_DBx__SCSI_Out_DB7__PC CYREG_PRT0_PC7
-#define SCSI_Out_DBx__SCSI_Out_DB7__PORT 0u
-#define SCSI_Out_DBx__SCSI_Out_DB7__SHIFT 7
 #define SCSI_Out_DBx__SHIFT 0
 #define SCSI_Out_DBx__SLW CYREG_PRT0_SLW
 
+/* SCSI_RST_ISR */
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RST_ISR__INTC_MASK 0x400u
+#define SCSI_RST_ISR__INTC_NUMBER 10u
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -151,13 +151,13 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@@ -167,28 +167,28 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB07_08_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB07_08_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB07_08_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB07_08_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB07_08_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB07_08_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB07_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB07_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB07_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB07_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB07_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB07_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB07_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB07_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB07_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
 
 /* SCSI_In_DBx */
 #define SCSI_In_DBx__0__MASK 0x01u
@@ -229,6 +229,38 @@
 #define SCSI_In_DBx__BIT_MASK CYREG_PRT2_BIT_MASK
 #define SCSI_In_DBx__BYP CYREG_PRT2_BYP
 #define SCSI_In_DBx__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB0__MASK 0x01u
+#define SCSI_In_DBx__DB0__PC CYREG_PRT2_PC0
+#define SCSI_In_DBx__DB0__PORT 2u
+#define SCSI_In_DBx__DB0__SHIFT 0
+#define SCSI_In_DBx__DB1__MASK 0x02u
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC1
+#define SCSI_In_DBx__DB1__PORT 2u
+#define SCSI_In_DBx__DB1__SHIFT 1
+#define SCSI_In_DBx__DB2__MASK 0x04u
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC2
+#define SCSI_In_DBx__DB2__PORT 2u
+#define SCSI_In_DBx__DB2__SHIFT 2
+#define SCSI_In_DBx__DB3__MASK 0x08u
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC3
+#define SCSI_In_DBx__DB3__PORT 2u
+#define SCSI_In_DBx__DB3__SHIFT 3
+#define SCSI_In_DBx__DB4__MASK 0x10u
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__DB4__PORT 2u
+#define SCSI_In_DBx__DB4__SHIFT 4
+#define SCSI_In_DBx__DB5__MASK 0x20u
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__DB5__PORT 2u
+#define SCSI_In_DBx__DB5__SHIFT 5
+#define SCSI_In_DBx__DB6__MASK 0x40u
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC6
+#define SCSI_In_DBx__DB6__PORT 2u
+#define SCSI_In_DBx__DB6__SHIFT 6
+#define SCSI_In_DBx__DB7__MASK 0x80u
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC7
+#define SCSI_In_DBx__DB7__PORT 2u
+#define SCSI_In_DBx__DB7__SHIFT 7
 #define SCSI_In_DBx__DM0 CYREG_PRT2_DM0
 #define SCSI_In_DBx__DM1 CYREG_PRT2_DM1
 #define SCSI_In_DBx__DM2 CYREG_PRT2_DM2
@@ -247,38 +279,6 @@
 #define SCSI_In_DBx__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
 #define SCSI_In_DBx__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
 #define SCSI_In_DBx__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__SCSI_Out_DB0__MASK 0x01u
-#define SCSI_In_DBx__SCSI_Out_DB0__PC CYREG_PRT2_PC0
-#define SCSI_In_DBx__SCSI_Out_DB0__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB0__SHIFT 0
-#define SCSI_In_DBx__SCSI_Out_DB1__MASK 0x02u
-#define SCSI_In_DBx__SCSI_Out_DB1__PC CYREG_PRT2_PC1
-#define SCSI_In_DBx__SCSI_Out_DB1__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB1__SHIFT 1
-#define SCSI_In_DBx__SCSI_Out_DB2__MASK 0x04u
-#define SCSI_In_DBx__SCSI_Out_DB2__PC CYREG_PRT2_PC2
-#define SCSI_In_DBx__SCSI_Out_DB2__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB2__SHIFT 2
-#define SCSI_In_DBx__SCSI_Out_DB3__MASK 0x08u
-#define SCSI_In_DBx__SCSI_Out_DB3__PC CYREG_PRT2_PC3
-#define SCSI_In_DBx__SCSI_Out_DB3__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB3__SHIFT 3
-#define SCSI_In_DBx__SCSI_Out_DB4__MASK 0x10u
-#define SCSI_In_DBx__SCSI_Out_DB4__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__SCSI_Out_DB4__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB4__SHIFT 4
-#define SCSI_In_DBx__SCSI_Out_DB5__MASK 0x20u
-#define SCSI_In_DBx__SCSI_Out_DB5__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__SCSI_Out_DB5__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB5__SHIFT 5
-#define SCSI_In_DBx__SCSI_Out_DB6__MASK 0x40u
-#define SCSI_In_DBx__SCSI_Out_DB6__PC CYREG_PRT2_PC6
-#define SCSI_In_DBx__SCSI_Out_DB6__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB6__SHIFT 6
-#define SCSI_In_DBx__SCSI_Out_DB7__MASK 0x80u
-#define SCSI_In_DBx__SCSI_Out_DB7__PC CYREG_PRT2_PC7
-#define SCSI_In_DBx__SCSI_Out_DB7__PORT 2u
-#define SCSI_In_DBx__SCSI_Out_DB7__SHIFT 7
 #define SCSI_In_DBx__SHIFT 0
 #define SCSI_In_DBx__SLW CYREG_PRT2_SLW
 
@@ -307,24 +307,24 @@
 /* SD_Clk_Ctl */
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
 #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
 
 /* PARITY_EN */
 #define PARITY_EN__0__MASK 0x10u
@@ -358,6 +358,41 @@
 #define PARITY_EN__SHIFT 4
 #define PARITY_EN__SLW CYREG_PRT5_SLW
 
+/* SCSI_ATN */
+#define SCSI_ATN__0__MASK 0x20u
+#define SCSI_ATN__0__PC CYREG_PRT12_PC5
+#define SCSI_ATN__0__PORT 12u
+#define SCSI_ATN__0__SHIFT 5
+#define SCSI_ATN__AG CYREG_PRT12_AG
+#define SCSI_ATN__BIE CYREG_PRT12_BIE
+#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_ATN__BYP CYREG_PRT12_BYP
+#define SCSI_ATN__DM0 CYREG_PRT12_DM0
+#define SCSI_ATN__DM1 CYREG_PRT12_DM1
+#define SCSI_ATN__DM2 CYREG_PRT12_DM2
+#define SCSI_ATN__DR CYREG_PRT12_DR
+#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_ATN__INT__MASK 0x20u
+#define SCSI_ATN__INT__PC CYREG_PRT12_PC5
+#define SCSI_ATN__INT__PORT 12u
+#define SCSI_ATN__INT__SHIFT 5
+#define SCSI_ATN__MASK 0x20u
+#define SCSI_ATN__PORT 12u
+#define SCSI_ATN__PRT CYREG_PRT12_PRT
+#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_ATN__PS CYREG_PRT12_PS
+#define SCSI_ATN__SHIFT 5
+#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_ATN__SLW CYREG_PRT12_SLW
+
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT4_AG
 #define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
@@ -900,6 +935,44 @@
 #define SCSI_Out__SEL__SHIFT 0
 #define SCSI_Out__SEL__SLW CYREG_PRT6_SLW
 
+/* SCSI_RST */
+#define SCSI_RST__0__MASK 0x40u
+#define SCSI_RST__0__PC CYREG_PRT6_PC6
+#define SCSI_RST__0__PORT 6u
+#define SCSI_RST__0__SHIFT 6
+#define SCSI_RST__AG CYREG_PRT6_AG
+#define SCSI_RST__AMUX CYREG_PRT6_AMUX
+#define SCSI_RST__BIE CYREG_PRT6_BIE
+#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_RST__BYP CYREG_PRT6_BYP
+#define SCSI_RST__CTL CYREG_PRT6_CTL
+#define SCSI_RST__DM0 CYREG_PRT6_DM0
+#define SCSI_RST__DM1 CYREG_PRT6_DM1
+#define SCSI_RST__DM2 CYREG_PRT6_DM2
+#define SCSI_RST__DR CYREG_PRT6_DR
+#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT
+#define SCSI_RST__INT__MASK 0x40u
+#define SCSI_RST__INT__PC CYREG_PRT6_PC6
+#define SCSI_RST__INT__PORT 6u
+#define SCSI_RST__INT__SHIFT 6
+#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_RST__MASK 0x40u
+#define SCSI_RST__PORT 6u
+#define SCSI_RST__PRT CYREG_PRT6_PRT
+#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_RST__PS CYREG_PRT6_PS
+#define SCSI_RST__SHIFT 6
+#define SCSI_RST__SLW CYREG_PRT6_SLW
+#define SCSI_RST__SNAP CYREG_PICU6_SNAP
+
 /* SCSI_ID */
 #define SCSI_ID__0__MASK 0x80u
 #define SCSI_ID__0__PC CYREG_PRT5_PC7
@@ -965,32 +1038,33 @@
 #define SCSI_In__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
 #define SCSI_In__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
 #define SCSI_In__0__SLW CYREG_PRT12_SLW
-#define SCSI_In__1__AG CYREG_PRT12_AG
-#define SCSI_In__1__BIE CYREG_PRT12_BIE
-#define SCSI_In__1__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In__1__BYP CYREG_PRT12_BYP
-#define SCSI_In__1__DM0 CYREG_PRT12_DM0
-#define SCSI_In__1__DM1 CYREG_PRT12_DM1
-#define SCSI_In__1__DM2 CYREG_PRT12_DM2
-#define SCSI_In__1__DR CYREG_PRT12_DR
-#define SCSI_In__1__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In__1__MASK 0x20u
-#define SCSI_In__1__PC CYREG_PRT12_PC5
-#define SCSI_In__1__PORT 12u
-#define SCSI_In__1__PRT CYREG_PRT12_PRT
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In__1__PS CYREG_PRT12_PS
-#define SCSI_In__1__SHIFT 5
-#define SCSI_In__1__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In__1__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In__1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In__1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In__1__SLW CYREG_PRT12_SLW
+#define SCSI_In__1__AG CYREG_PRT6_AG
+#define SCSI_In__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_In__1__BIE CYREG_PRT6_BIE
+#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In__1__BYP CYREG_PRT6_BYP
+#define SCSI_In__1__CTL CYREG_PRT6_CTL
+#define SCSI_In__1__DM0 CYREG_PRT6_DM0
+#define SCSI_In__1__DM1 CYREG_PRT6_DM1
+#define SCSI_In__1__DM2 CYREG_PRT6_DM2
+#define SCSI_In__1__DR CYREG_PRT6_DR
+#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In__1__MASK 0x10u
+#define SCSI_In__1__PC CYREG_PRT6_PC4
+#define SCSI_In__1__PORT 6u
+#define SCSI_In__1__PRT CYREG_PRT6_PRT
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In__1__PS CYREG_PRT6_PS
+#define SCSI_In__1__SHIFT 4
+#define SCSI_In__1__SLW CYREG_PRT6_SLW
 #define SCSI_In__2__AG CYREG_PRT6_AG
 #define SCSI_In__2__AMUX CYREG_PRT6_AMUX
 #define SCSI_In__2__BIE CYREG_PRT6_BIE
@@ -1004,8 +1078,8 @@
 #define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS
 #define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
 #define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__2__MASK 0x10u
-#define SCSI_In__2__PC CYREG_PRT6_PC4
+#define SCSI_In__2__MASK 0x20u
+#define SCSI_In__2__PC CYREG_PRT6_PC5
 #define SCSI_In__2__PORT 6u
 #define SCSI_In__2__PRT CYREG_PRT6_PRT
 #define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
@@ -1016,7 +1090,7 @@
 #define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
 #define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
 #define SCSI_In__2__PS CYREG_PRT6_PS
-#define SCSI_In__2__SHIFT 4
+#define SCSI_In__2__SHIFT 5
 #define SCSI_In__2__SLW CYREG_PRT6_SLW
 #define SCSI_In__3__AG CYREG_PRT6_AG
 #define SCSI_In__3__AMUX CYREG_PRT6_AMUX
@@ -1031,8 +1105,8 @@
 #define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS
 #define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
 #define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__3__MASK 0x20u
-#define SCSI_In__3__PC CYREG_PRT6_PC5
+#define SCSI_In__3__MASK 0x80u
+#define SCSI_In__3__PC CYREG_PRT6_PC7
 #define SCSI_In__3__PORT 6u
 #define SCSI_In__3__PRT CYREG_PRT6_PRT
 #define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
@@ -1043,62 +1117,62 @@
 #define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
 #define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
 #define SCSI_In__3__PS CYREG_PRT6_PS
-#define SCSI_In__3__SHIFT 5
+#define SCSI_In__3__SHIFT 7
 #define SCSI_In__3__SLW CYREG_PRT6_SLW
-#define SCSI_In__4__AG CYREG_PRT6_AG
-#define SCSI_In__4__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__4__BIE CYREG_PRT6_BIE
-#define SCSI_In__4__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__4__BYP CYREG_PRT6_BYP
-#define SCSI_In__4__CTL CYREG_PRT6_CTL
-#define SCSI_In__4__DM0 CYREG_PRT6_DM0
-#define SCSI_In__4__DM1 CYREG_PRT6_DM1
-#define SCSI_In__4__DM2 CYREG_PRT6_DM2
-#define SCSI_In__4__DR CYREG_PRT6_DR
-#define SCSI_In__4__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__4__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__4__MASK 0x40u
-#define SCSI_In__4__PC CYREG_PRT6_PC6
-#define SCSI_In__4__PORT 6u
-#define SCSI_In__4__PRT CYREG_PRT6_PRT
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__4__PS CYREG_PRT6_PS
-#define SCSI_In__4__SHIFT 6
-#define SCSI_In__4__SLW CYREG_PRT6_SLW
-#define SCSI_In__5__AG CYREG_PRT6_AG
-#define SCSI_In__5__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__5__BIE CYREG_PRT6_BIE
-#define SCSI_In__5__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__5__BYP CYREG_PRT6_BYP
-#define SCSI_In__5__CTL CYREG_PRT6_CTL
-#define SCSI_In__5__DM0 CYREG_PRT6_DM0
-#define SCSI_In__5__DM1 CYREG_PRT6_DM1
-#define SCSI_In__5__DM2 CYREG_PRT6_DM2
-#define SCSI_In__5__DR CYREG_PRT6_DR
-#define SCSI_In__5__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__5__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__5__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__5__MASK 0x80u
-#define SCSI_In__5__PC CYREG_PRT6_PC7
-#define SCSI_In__5__PORT 6u
-#define SCSI_In__5__PRT CYREG_PRT6_PRT
-#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__5__PS CYREG_PRT6_PS
-#define SCSI_In__5__SHIFT 7
-#define SCSI_In__5__SLW CYREG_PRT6_SLW
+#define SCSI_In__4__AG CYREG_PRT5_AG
+#define SCSI_In__4__AMUX CYREG_PRT5_AMUX
+#define SCSI_In__4__BIE CYREG_PRT5_BIE
+#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In__4__BYP CYREG_PRT5_BYP
+#define SCSI_In__4__CTL CYREG_PRT5_CTL
+#define SCSI_In__4__DM0 CYREG_PRT5_DM0
+#define SCSI_In__4__DM1 CYREG_PRT5_DM1
+#define SCSI_In__4__DM2 CYREG_PRT5_DM2
+#define SCSI_In__4__DR CYREG_PRT5_DR
+#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In__4__MASK 0x01u
+#define SCSI_In__4__PC CYREG_PRT5_PC0
+#define SCSI_In__4__PORT 5u
+#define SCSI_In__4__PRT CYREG_PRT5_PRT
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In__4__PS CYREG_PRT5_PS
+#define SCSI_In__4__SHIFT 0
+#define SCSI_In__4__SLW CYREG_PRT5_SLW
+#define SCSI_In__5__AG CYREG_PRT5_AG
+#define SCSI_In__5__AMUX CYREG_PRT5_AMUX
+#define SCSI_In__5__BIE CYREG_PRT5_BIE
+#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In__5__BYP CYREG_PRT5_BYP
+#define SCSI_In__5__CTL CYREG_PRT5_CTL
+#define SCSI_In__5__DM0 CYREG_PRT5_DM0
+#define SCSI_In__5__DM1 CYREG_PRT5_DM1
+#define SCSI_In__5__DM2 CYREG_PRT5_DM2
+#define SCSI_In__5__DR CYREG_PRT5_DR
+#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In__5__MASK 0x02u
+#define SCSI_In__5__PC CYREG_PRT5_PC1
+#define SCSI_In__5__PORT 5u
+#define SCSI_In__5__PRT CYREG_PRT5_PRT
+#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In__5__PS CYREG_PRT5_PS
+#define SCSI_In__5__SHIFT 1
+#define SCSI_In__5__SLW CYREG_PRT5_SLW
 #define SCSI_In__6__AG CYREG_PRT5_AG
 #define SCSI_In__6__AMUX CYREG_PRT5_AMUX
 #define SCSI_In__6__BIE CYREG_PRT5_BIE
@@ -1112,8 +1186,8 @@
 #define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS
 #define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
 #define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In__6__MASK 0x01u
-#define SCSI_In__6__PC CYREG_PRT5_PC0
+#define SCSI_In__6__MASK 0x04u
+#define SCSI_In__6__PC CYREG_PRT5_PC2
 #define SCSI_In__6__PORT 5u
 #define SCSI_In__6__PRT CYREG_PRT5_PRT
 #define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
@@ -1124,7 +1198,7 @@
 #define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
 #define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
 #define SCSI_In__6__PS CYREG_PRT5_PS
-#define SCSI_In__6__SHIFT 0
+#define SCSI_In__6__SHIFT 2
 #define SCSI_In__6__SLW CYREG_PRT5_SLW
 #define SCSI_In__7__AG CYREG_PRT5_AG
 #define SCSI_In__7__AMUX CYREG_PRT5_AMUX
@@ -1139,8 +1213,8 @@
 #define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS
 #define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
 #define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In__7__MASK 0x02u
-#define SCSI_In__7__PC CYREG_PRT5_PC1
+#define SCSI_In__7__MASK 0x08u
+#define SCSI_In__7__PC CYREG_PRT5_PC3
 #define SCSI_In__7__PORT 5u
 #define SCSI_In__7__PRT CYREG_PRT5_PRT
 #define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
@@ -1151,62 +1225,8 @@
 #define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
 #define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
 #define SCSI_In__7__PS CYREG_PRT5_PS
-#define SCSI_In__7__SHIFT 1
+#define SCSI_In__7__SHIFT 3
 #define SCSI_In__7__SLW CYREG_PRT5_SLW
-#define SCSI_In__8__AG CYREG_PRT5_AG
-#define SCSI_In__8__AMUX CYREG_PRT5_AMUX
-#define SCSI_In__8__BIE CYREG_PRT5_BIE
-#define SCSI_In__8__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In__8__BYP CYREG_PRT5_BYP
-#define SCSI_In__8__CTL CYREG_PRT5_CTL
-#define SCSI_In__8__DM0 CYREG_PRT5_DM0
-#define SCSI_In__8__DM1 CYREG_PRT5_DM1
-#define SCSI_In__8__DM2 CYREG_PRT5_DM2
-#define SCSI_In__8__DR CYREG_PRT5_DR
-#define SCSI_In__8__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In__8__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In__8__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In__8__MASK 0x04u
-#define SCSI_In__8__PC CYREG_PRT5_PC2
-#define SCSI_In__8__PORT 5u
-#define SCSI_In__8__PRT CYREG_PRT5_PRT
-#define SCSI_In__8__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In__8__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In__8__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In__8__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In__8__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In__8__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In__8__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In__8__PS CYREG_PRT5_PS
-#define SCSI_In__8__SHIFT 2
-#define SCSI_In__8__SLW CYREG_PRT5_SLW
-#define SCSI_In__9__AG CYREG_PRT5_AG
-#define SCSI_In__9__AMUX CYREG_PRT5_AMUX
-#define SCSI_In__9__BIE CYREG_PRT5_BIE
-#define SCSI_In__9__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In__9__BYP CYREG_PRT5_BYP
-#define SCSI_In__9__CTL CYREG_PRT5_CTL
-#define SCSI_In__9__DM0 CYREG_PRT5_DM0
-#define SCSI_In__9__DM1 CYREG_PRT5_DM1
-#define SCSI_In__9__DM2 CYREG_PRT5_DM2
-#define SCSI_In__9__DR CYREG_PRT5_DR
-#define SCSI_In__9__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In__9__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In__9__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In__9__MASK 0x08u
-#define SCSI_In__9__PC CYREG_PRT5_PC3
-#define SCSI_In__9__PORT 5u
-#define SCSI_In__9__PRT CYREG_PRT5_PRT
-#define SCSI_In__9__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In__9__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In__9__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In__9__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In__9__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In__9__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In__9__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In__9__PS CYREG_PRT5_PS
-#define SCSI_In__9__SHIFT 3
-#define SCSI_In__9__SLW CYREG_PRT5_SLW
 #define SCSI_In__ACK__AG CYREG_PRT6_AG
 #define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX
 #define SCSI_In__ACK__BIE CYREG_PRT6_BIE
@@ -1234,32 +1254,6 @@
 #define SCSI_In__ACK__PS CYREG_PRT6_PS
 #define SCSI_In__ACK__SHIFT 5
 #define SCSI_In__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_In__ATN__AG CYREG_PRT12_AG
-#define SCSI_In__ATN__BIE CYREG_PRT12_BIE
-#define SCSI_In__ATN__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In__ATN__BYP CYREG_PRT12_BYP
-#define SCSI_In__ATN__DM0 CYREG_PRT12_DM0
-#define SCSI_In__ATN__DM1 CYREG_PRT12_DM1
-#define SCSI_In__ATN__DM2 CYREG_PRT12_DM2
-#define SCSI_In__ATN__DR CYREG_PRT12_DR
-#define SCSI_In__ATN__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In__ATN__MASK 0x20u
-#define SCSI_In__ATN__PC CYREG_PRT12_PC5
-#define SCSI_In__ATN__PORT 12u
-#define SCSI_In__ATN__PRT CYREG_PRT12_PRT
-#define SCSI_In__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In__ATN__PS CYREG_PRT12_PS
-#define SCSI_In__ATN__SHIFT 5
-#define SCSI_In__ATN__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In__ATN__SLW CYREG_PRT12_SLW
 #define SCSI_In__BSY__AG CYREG_PRT6_AG
 #define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX
 #define SCSI_In__BSY__BIE CYREG_PRT6_BIE
@@ -1421,33 +1415,6 @@
 #define SCSI_In__REQ__PS CYREG_PRT5_PS
 #define SCSI_In__REQ__SHIFT 2
 #define SCSI_In__REQ__SLW CYREG_PRT5_SLW
-#define SCSI_In__RST__AG CYREG_PRT6_AG
-#define SCSI_In__RST__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__RST__BIE CYREG_PRT6_BIE
-#define SCSI_In__RST__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__RST__BYP CYREG_PRT6_BYP
-#define SCSI_In__RST__CTL CYREG_PRT6_CTL
-#define SCSI_In__RST__DM0 CYREG_PRT6_DM0
-#define SCSI_In__RST__DM1 CYREG_PRT6_DM1
-#define SCSI_In__RST__DM2 CYREG_PRT6_DM2
-#define SCSI_In__RST__DR CYREG_PRT6_DR
-#define SCSI_In__RST__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__RST__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__RST__MASK 0x40u
-#define SCSI_In__RST__PC CYREG_PRT6_PC6
-#define SCSI_In__RST__PORT 6u
-#define SCSI_In__RST__PRT CYREG_PRT6_PRT
-#define SCSI_In__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__RST__PS CYREG_PRT6_PS
-#define SCSI_In__RST__SHIFT 6
-#define SCSI_In__RST__SLW CYREG_PRT6_SLW
 #define SCSI_In__SEL__AG CYREG_PRT5_AG
 #define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX
 #define SCSI_In__SEL__BIE CYREG_PRT5_BIE
@@ -1831,7 +1798,6 @@
 #define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
 #define CYDEV_DEBUGGING_ENABLE 1
-#define CYDEV_DEBUGGING_REQXRES 1
 #define CYDEV_DEBUGGING_XRES 0
 #define CYDEV_DEBUG_ENABLE_MASK 0x20u
 #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
@@ -1839,7 +1805,7 @@
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x1000
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x00000003u
+#define CYDEV_INTR_RISING 0x00000001u
 #define CYDEV_PROJ_TYPE 0
 #define CYDEV_PROJ_TYPE_BOOTLOADER 1
 #define CYDEV_PROJ_TYPE_LOADABLE 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.c
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * Description:
 * This file is automatically generated by PSoC Creator with device 
@@ -21,6 +21,62 @@
 #include <CyLib.h>
 #include <cyfitter_cfg.h>
 
+#define CY_NEED_CYCLOCKSTARTUPERROR 1
+
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+    #define CYPACKED 
+    #define CYPACKED_ATTR __attribute__ ((packed))
+    #define CYALIGNED __attribute__ ((aligned))
+    #define CY_CFG_UNUSED __attribute__ ((unused))
+    #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
+    
+    #if defined(__ARMCC_VERSION)
+        #define CY_CFG_MEMORY_BARRIER() __memory_changed()
+    #else
+        #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
+    #endif
+    
+#elif defined(__ICCARM__)
+    #include <intrinsics.h>
+
+    #define CYPACKED __packed
+    #define CYPACKED_ATTR 
+    #define CYALIGNED _Pragma("data_alignment=4")
+    #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
+    #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
+    
+    #define CY_CFG_MEMORY_BARRIER() __DMB()
+    
+#else
+    #error Unsupported toolchain
+#endif
+
+
+CY_CFG_UNUSED
+static void CYMEMZERO(void *s, size_t n);
+CY_CFG_UNUSED
+static void CYMEMZERO(void *s, size_t n)
+{
+	(void)memset(s, 0, n);
+}
+CY_CFG_UNUSED
+static void CYCONFIGCPY(void *dest, const void *src, size_t n);
+CY_CFG_UNUSED
+static void CYCONFIGCPY(void *dest, const void *src, size_t n)
+{
+	(void)memcpy(dest, src, n);
+}
+CY_CFG_UNUSED
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
+CY_CFG_UNUSED
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
+{
+	(void)memcpy(dest, src, n);
+}
+
+
+
 /* Clock startup error codes                                                   */
 #define CYCLOCKSTART_NO_ERROR    0u
 #define CYCLOCKSTART_XTAL_ERROR  1u
@@ -43,13 +99,9 @@
 *   void
 *
 *******************************************************************************/
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)
-__attribute__ ((unused))
-#endif
+CY_CFG_UNUSED
 static void CyClockStartupError(uint8 errorCode);
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)
-__attribute__ ((unused))
-#endif
+CY_CFG_UNUSED
 static void CyClockStartupError(uint8 errorCode)
 {
     /* To remove the compiler warning if errorCode not used.                */
@@ -69,79 +121,42 @@ static void CyClockStartupError(uint8 errorCode)
 }
 #endif
 
-
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)
-	#define CYPACKED __attribute__ ((packed))
-	#define CYALIGNED __attribute__ ((aligned))
-	
-	#if defined(__ARMCC_VERSION)
-		#define CY_CFG_MEMORY_BARRIER() __memory_changed()
-	#else
-		#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
-	#endif
-	
-
-	__attribute__ ((unused))
-	static void CYMEMZERO(void *s, size_t n);
-	__attribute__ ((unused))
-	static void CYMEMZERO(void *s, size_t n)
-	{
-		(void)memset(s, 0, n);
-	}
-	__attribute__ ((unused))
-	static void CYCONFIGCPY(void *dest, const void *src, size_t n);
-	__attribute__ ((unused))
-	static void CYCONFIGCPY(void *dest, const void *src, size_t n)
-	{
-		(void)memcpy(dest, src, n);
-	}
-	__attribute__ ((unused))
-	static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
-	__attribute__ ((unused))
-	static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
-	{
-		(void)memcpy(dest, src, n);
-	}
-#else
-	#error Unsupported toolchain
-#endif
-
-#define CY_CFG_BASE_ADDR_COUNT 16u
-typedef struct
+#define CY_CFG_BASE_ADDR_COUNT 22u
+CYPACKED typedef struct
 {
 	uint8 offset;
 	uint8 value;
-} CYPACKED cy_cfg_addrvalue_t;
+} CYPACKED_ATTR cy_cfg_addrvalue_t;
 
 #define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)
-#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000040u)
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)
 
-/* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */
-#define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)0x480002D4u)
+/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */
+#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)
 
 /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000354u)
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)
 
 /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
-#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x4800035Cu)
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)
 
 /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */
-#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x48000368u)
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)
 
 /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000370u)
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)
 
 /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
-#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000378u)
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)
 
 /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000384u)
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)
 
 /* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */
-#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x4800038Cu)
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)
 
 /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
-#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000398u)
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)
 
 
 /*******************************************************************************
@@ -216,13 +231,19 @@ static void ClockSetup(void)
 
 	/* Configure PLL based on settings from Clock DWR */
 	CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0F15u);
-	CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u);
+	CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
 	/* Wait up to 250us for the PLL to lock */
 	pllLock = 0u;
-	for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { 
+	for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
+	{ 
 		pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
 		CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
 	}
+	/* If we ran out of time the PLL didn't lock so go to the error function */
+	if (timeout == 0u)
+	{
+		CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
+	}
 
 	/* Configure Bus/Master Clock based on settings from Clock DWR */
 	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
@@ -258,8 +279,8 @@ static void AnalogSetDefault(void);
 static void AnalogSetDefault(void)
 {
 	uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
-	CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT0, bg_xover_inl_trim & 0x07u);
-	CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT1, ((uint8)((uint8)bg_xover_inl_trim >> 4)) & 0x0Fu);
+	CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
+	CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
 	CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
 }
 
@@ -332,25 +353,25 @@ void cyfitter_cfg(void)
 
 	{
 
-		typedef struct {
+		CYPACKED typedef struct {
 			void CYFAR *address;
 			uint16 size;
-		} CYPACKED cfg_memset_t;
+		} CYPACKED_ATTR cfg_memset_t;
 
 
-		typedef struct {
+		CYPACKED typedef struct {
 			void CYFAR *dest;
 			const void CYFAR *src;
 			uint16 size;
-		} CYPACKED cfg_memcpy_t;
+		} CYPACKED_ATTR cfg_memcpy_t;
 
 		static const cfg_memset_t CYCODE cfg_memset_list [] = {
 			/* address, size */
 			{(void CYFAR *)(CYREG_PRT1_DR), 16u},
 			{(void CYFAR *)(CYREG_PRT15_DR), 16u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
-			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 640u},
-			{(void CYFAR *)(CYDEV_UCFG_B1_P3_ROUTE_BASE), 1280u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},
+			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
 			{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
@@ -358,7 +379,7 @@ void cyfitter_cfg(void)
 
 		static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
 			/* dest, src, size */
-			{(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), BS_UDB_1_1_0_CONFIG_VAL, 128u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},
 		};
 
 		uint8 CYDATA i;
@@ -402,7 +423,7 @@ void cyfitter_cfg(void)
 	CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);
 
 	/* Switch Boost to the precision bandgap reference from its internal reference */
-	CY_SET_REG8((void CYXDATA *)CYDEV_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYDEV_BOOST_CR2) | 0x08u));
+	CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
 
 	/* Perform basic analog initialization to defaults */
 	AnalogSetDefault();

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator 2.2 Component Pack 6
+* PSoC Creator 3.0
 *
 * Description:
 * This file is automatically generated by PSoC Creator.

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -3,25 +3,15 @@
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
-/* SDCard_RxInternalInterrupt */
-.set SDCard_RxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SDCard_RxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SDCard_RxInternalInterrupt__INTC_MASK, 0x01
-.set SDCard_RxInternalInterrupt__INTC_NUMBER, 0
-.set SDCard_RxInternalInterrupt__INTC_PRIOR_NUM, 7
-.set SDCard_RxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set SDCard_RxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SDCard_RxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SDCard_TxInternalInterrupt */
-.set SDCard_TxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SDCard_TxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SDCard_TxInternalInterrupt__INTC_MASK, 0x02
-.set SDCard_TxInternalInterrupt__INTC_NUMBER, 1
-.set SDCard_TxInternalInterrupt__INTC_PRIOR_NUM, 7
-.set SDCard_TxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set SDCard_TxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SDCard_TxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_ATN_ISR */
+.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_ATN_ISR__INTC_MASK, 0x01
+.set SCSI_ATN_ISR__INTC_NUMBER, 0
+.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__MASK, 0x01
@@ -62,6 +52,38 @@
 .set SCSI_Out_DBx__BIT_MASK, CYREG_PRT0_BIT_MASK
 .set SCSI_Out_DBx__BYP, CYREG_PRT0_BYP
 .set SCSI_Out_DBx__CTL, CYREG_PRT0_CTL
+.set SCSI_Out_DBx__DB0__MASK, 0x01
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT0_PC0
+.set SCSI_Out_DBx__DB0__PORT, 0
+.set SCSI_Out_DBx__DB0__SHIFT, 0
+.set SCSI_Out_DBx__DB1__MASK, 0x02
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT0_PC1
+.set SCSI_Out_DBx__DB1__PORT, 0
+.set SCSI_Out_DBx__DB1__SHIFT, 1
+.set SCSI_Out_DBx__DB2__MASK, 0x04
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT0_PC2
+.set SCSI_Out_DBx__DB2__PORT, 0
+.set SCSI_Out_DBx__DB2__SHIFT, 2
+.set SCSI_Out_DBx__DB3__MASK, 0x08
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT0_PC3
+.set SCSI_Out_DBx__DB3__PORT, 0
+.set SCSI_Out_DBx__DB3__SHIFT, 3
+.set SCSI_Out_DBx__DB4__MASK, 0x10
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT0_PC4
+.set SCSI_Out_DBx__DB4__PORT, 0
+.set SCSI_Out_DBx__DB4__SHIFT, 4
+.set SCSI_Out_DBx__DB5__MASK, 0x20
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT0_PC5
+.set SCSI_Out_DBx__DB5__PORT, 0
+.set SCSI_Out_DBx__DB5__SHIFT, 5
+.set SCSI_Out_DBx__DB6__MASK, 0x40
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT0_PC6
+.set SCSI_Out_DBx__DB6__PORT, 0
+.set SCSI_Out_DBx__DB6__SHIFT, 6
+.set SCSI_Out_DBx__DB7__MASK, 0x80
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT0_PC7
+.set SCSI_Out_DBx__DB7__PORT, 0
+.set SCSI_Out_DBx__DB7__SHIFT, 7
 .set SCSI_Out_DBx__DM0, CYREG_PRT0_DM0
 .set SCSI_Out_DBx__DM1, CYREG_PRT0_DM1
 .set SCSI_Out_DBx__DM2, CYREG_PRT0_DM2
@@ -80,70 +102,48 @@
 .set SCSI_Out_DBx__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
 .set SCSI_Out_DBx__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
 .set SCSI_Out_DBx__PS, CYREG_PRT0_PS
-.set SCSI_Out_DBx__SCSI_Out_DB0__MASK, 0x01
-.set SCSI_Out_DBx__SCSI_Out_DB0__PC, CYREG_PRT0_PC0
-.set SCSI_Out_DBx__SCSI_Out_DB0__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB0__SHIFT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB1__MASK, 0x02
-.set SCSI_Out_DBx__SCSI_Out_DB1__PC, CYREG_PRT0_PC1
-.set SCSI_Out_DBx__SCSI_Out_DB1__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB1__SHIFT, 1
-.set SCSI_Out_DBx__SCSI_Out_DB2__MASK, 0x04
-.set SCSI_Out_DBx__SCSI_Out_DB2__PC, CYREG_PRT0_PC2
-.set SCSI_Out_DBx__SCSI_Out_DB2__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB2__SHIFT, 2
-.set SCSI_Out_DBx__SCSI_Out_DB3__MASK, 0x08
-.set SCSI_Out_DBx__SCSI_Out_DB3__PC, CYREG_PRT0_PC3
-.set SCSI_Out_DBx__SCSI_Out_DB3__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB3__SHIFT, 3
-.set SCSI_Out_DBx__SCSI_Out_DB4__MASK, 0x10
-.set SCSI_Out_DBx__SCSI_Out_DB4__PC, CYREG_PRT0_PC4
-.set SCSI_Out_DBx__SCSI_Out_DB4__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB4__SHIFT, 4
-.set SCSI_Out_DBx__SCSI_Out_DB5__MASK, 0x20
-.set SCSI_Out_DBx__SCSI_Out_DB5__PC, CYREG_PRT0_PC5
-.set SCSI_Out_DBx__SCSI_Out_DB5__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB5__SHIFT, 5
-.set SCSI_Out_DBx__SCSI_Out_DB6__MASK, 0x40
-.set SCSI_Out_DBx__SCSI_Out_DB6__PC, CYREG_PRT0_PC6
-.set SCSI_Out_DBx__SCSI_Out_DB6__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB6__SHIFT, 6
-.set SCSI_Out_DBx__SCSI_Out_DB7__MASK, 0x80
-.set SCSI_Out_DBx__SCSI_Out_DB7__PC, CYREG_PRT0_PC7
-.set SCSI_Out_DBx__SCSI_Out_DB7__PORT, 0
-.set SCSI_Out_DBx__SCSI_Out_DB7__SHIFT, 7
 .set SCSI_Out_DBx__SHIFT, 0
 .set SCSI_Out_DBx__SLW, CYREG_PRT0_SLW
 
+/* SCSI_RST_ISR */
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RST_ISR__INTC_MASK, 0x400
+.set SCSI_RST_ISR__INTC_NUMBER, 10
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -151,13 +151,13 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@@ -167,28 +167,28 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB07_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB07_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB07_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB07_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB07_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB07_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
 
 /* SCSI_In_DBx */
 .set SCSI_In_DBx__0__MASK, 0x01
@@ -229,6 +229,38 @@
 .set SCSI_In_DBx__BIT_MASK, CYREG_PRT2_BIT_MASK
 .set SCSI_In_DBx__BYP, CYREG_PRT2_BYP
 .set SCSI_In_DBx__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB0__MASK, 0x01
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT2_PC0
+.set SCSI_In_DBx__DB0__PORT, 2
+.set SCSI_In_DBx__DB0__SHIFT, 0
+.set SCSI_In_DBx__DB1__MASK, 0x02
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC1
+.set SCSI_In_DBx__DB1__PORT, 2
+.set SCSI_In_DBx__DB1__SHIFT, 1
+.set SCSI_In_DBx__DB2__MASK, 0x04
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC2
+.set SCSI_In_DBx__DB2__PORT, 2
+.set SCSI_In_DBx__DB2__SHIFT, 2
+.set SCSI_In_DBx__DB3__MASK, 0x08
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC3
+.set SCSI_In_DBx__DB3__PORT, 2
+.set SCSI_In_DBx__DB3__SHIFT, 3
+.set SCSI_In_DBx__DB4__MASK, 0x10
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__DB4__PORT, 2
+.set SCSI_In_DBx__DB4__SHIFT, 4
+.set SCSI_In_DBx__DB5__MASK, 0x20
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__DB5__PORT, 2
+.set SCSI_In_DBx__DB5__SHIFT, 5
+.set SCSI_In_DBx__DB6__MASK, 0x40
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC6
+.set SCSI_In_DBx__DB6__PORT, 2
+.set SCSI_In_DBx__DB6__SHIFT, 6
+.set SCSI_In_DBx__DB7__MASK, 0x80
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC7
+.set SCSI_In_DBx__DB7__PORT, 2
+.set SCSI_In_DBx__DB7__SHIFT, 7
 .set SCSI_In_DBx__DM0, CYREG_PRT2_DM0
 .set SCSI_In_DBx__DM1, CYREG_PRT2_DM1
 .set SCSI_In_DBx__DM2, CYREG_PRT2_DM2
@@ -247,38 +279,6 @@
 .set SCSI_In_DBx__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
 .set SCSI_In_DBx__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
 .set SCSI_In_DBx__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__SCSI_Out_DB0__MASK, 0x01
-.set SCSI_In_DBx__SCSI_Out_DB0__PC, CYREG_PRT2_PC0
-.set SCSI_In_DBx__SCSI_Out_DB0__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB0__SHIFT, 0
-.set SCSI_In_DBx__SCSI_Out_DB1__MASK, 0x02
-.set SCSI_In_DBx__SCSI_Out_DB1__PC, CYREG_PRT2_PC1
-.set SCSI_In_DBx__SCSI_Out_DB1__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB1__SHIFT, 1
-.set SCSI_In_DBx__SCSI_Out_DB2__MASK, 0x04
-.set SCSI_In_DBx__SCSI_Out_DB2__PC, CYREG_PRT2_PC2
-.set SCSI_In_DBx__SCSI_Out_DB2__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB2__SHIFT, 2
-.set SCSI_In_DBx__SCSI_Out_DB3__MASK, 0x08
-.set SCSI_In_DBx__SCSI_Out_DB3__PC, CYREG_PRT2_PC3
-.set SCSI_In_DBx__SCSI_Out_DB3__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB3__SHIFT, 3
-.set SCSI_In_DBx__SCSI_Out_DB4__MASK, 0x10
-.set SCSI_In_DBx__SCSI_Out_DB4__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__SCSI_Out_DB4__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB4__SHIFT, 4
-.set SCSI_In_DBx__SCSI_Out_DB5__MASK, 0x20
-.set SCSI_In_DBx__SCSI_Out_DB5__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__SCSI_Out_DB5__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB5__SHIFT, 5
-.set SCSI_In_DBx__SCSI_Out_DB6__MASK, 0x40
-.set SCSI_In_DBx__SCSI_Out_DB6__PC, CYREG_PRT2_PC6
-.set SCSI_In_DBx__SCSI_Out_DB6__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB6__SHIFT, 6
-.set SCSI_In_DBx__SCSI_Out_DB7__MASK, 0x80
-.set SCSI_In_DBx__SCSI_Out_DB7__PC, CYREG_PRT2_PC7
-.set SCSI_In_DBx__SCSI_Out_DB7__PORT, 2
-.set SCSI_In_DBx__SCSI_Out_DB7__SHIFT, 7
 .set SCSI_In_DBx__SHIFT, 0
 .set SCSI_In_DBx__SLW, CYREG_PRT2_SLW
 
@@ -307,24 +307,24 @@
 /* SD_Clk_Ctl */
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
 .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
 
 /* PARITY_EN */
 .set PARITY_EN__0__MASK, 0x10
@@ -358,6 +358,41 @@
 .set PARITY_EN__SHIFT, 4
 .set PARITY_EN__SLW, CYREG_PRT5_SLW
 
+/* SCSI_ATN */
+.set SCSI_ATN__0__MASK, 0x20
+.set SCSI_ATN__0__PC, CYREG_PRT12_PC5
+.set SCSI_ATN__0__PORT, 12
+.set SCSI_ATN__0__SHIFT, 5
+.set SCSI_ATN__AG, CYREG_PRT12_AG
+.set SCSI_ATN__BIE, CYREG_PRT12_BIE
+.set SCSI_ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_ATN__BYP, CYREG_PRT12_BYP
+.set SCSI_ATN__DM0, CYREG_PRT12_DM0
+.set SCSI_ATN__DM1, CYREG_PRT12_DM1
+.set SCSI_ATN__DM2, CYREG_PRT12_DM2
+.set SCSI_ATN__DR, CYREG_PRT12_DR
+.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_ATN__INT__MASK, 0x20
+.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5
+.set SCSI_ATN__INT__PORT, 12
+.set SCSI_ATN__INT__SHIFT, 5
+.set SCSI_ATN__MASK, 0x20
+.set SCSI_ATN__PORT, 12
+.set SCSI_ATN__PRT, CYREG_PRT12_PRT
+.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_ATN__PS, CYREG_PRT12_PS
+.set SCSI_ATN__SHIFT, 5
+.set SCSI_ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_ATN__SLW, CYREG_PRT12_SLW
+
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT4_AG
 .set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX
@@ -900,6 +935,44 @@
 .set SCSI_Out__SEL__SHIFT, 0
 .set SCSI_Out__SEL__SLW, CYREG_PRT6_SLW
 
+/* SCSI_RST */
+.set SCSI_RST__0__MASK, 0x40
+.set SCSI_RST__0__PC, CYREG_PRT6_PC6
+.set SCSI_RST__0__PORT, 6
+.set SCSI_RST__0__SHIFT, 6
+.set SCSI_RST__AG, CYREG_PRT6_AG
+.set SCSI_RST__AMUX, CYREG_PRT6_AMUX
+.set SCSI_RST__BIE, CYREG_PRT6_BIE
+.set SCSI_RST__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_RST__BYP, CYREG_PRT6_BYP
+.set SCSI_RST__CTL, CYREG_PRT6_CTL
+.set SCSI_RST__DM0, CYREG_PRT6_DM0
+.set SCSI_RST__DM1, CYREG_PRT6_DM1
+.set SCSI_RST__DM2, CYREG_PRT6_DM2
+.set SCSI_RST__DR, CYREG_PRT6_DR
+.set SCSI_RST__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_RST__INTSTAT, CYREG_PICU6_INTSTAT
+.set SCSI_RST__INT__MASK, 0x40
+.set SCSI_RST__INT__PC, CYREG_PRT6_PC6
+.set SCSI_RST__INT__PORT, 6
+.set SCSI_RST__INT__SHIFT, 6
+.set SCSI_RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_RST__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_RST__MASK, 0x40
+.set SCSI_RST__PORT, 6
+.set SCSI_RST__PRT, CYREG_PRT6_PRT
+.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_RST__PS, CYREG_PRT6_PS
+.set SCSI_RST__SHIFT, 6
+.set SCSI_RST__SLW, CYREG_PRT6_SLW
+.set SCSI_RST__SNAP, CYREG_PICU6_SNAP
+
 /* SCSI_ID */
 .set SCSI_ID__0__MASK, 0x80
 .set SCSI_ID__0__PC, CYREG_PRT5_PC7
@@ -965,32 +1038,33 @@
 .set SCSI_In__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
 .set SCSI_In__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 .set SCSI_In__0__SLW, CYREG_PRT12_SLW
-.set SCSI_In__1__AG, CYREG_PRT12_AG
-.set SCSI_In__1__BIE, CYREG_PRT12_BIE
-.set SCSI_In__1__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In__1__BYP, CYREG_PRT12_BYP
-.set SCSI_In__1__DM0, CYREG_PRT12_DM0
-.set SCSI_In__1__DM1, CYREG_PRT12_DM1
-.set SCSI_In__1__DM2, CYREG_PRT12_DM2
-.set SCSI_In__1__DR, CYREG_PRT12_DR
-.set SCSI_In__1__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In__1__MASK, 0x20
-.set SCSI_In__1__PC, CYREG_PRT12_PC5
-.set SCSI_In__1__PORT, 12
-.set SCSI_In__1__PRT, CYREG_PRT12_PRT
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In__1__PS, CYREG_PRT12_PS
-.set SCSI_In__1__SHIFT, 5
-.set SCSI_In__1__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In__1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In__1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In__1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In__1__SLW, CYREG_PRT12_SLW
+.set SCSI_In__1__AG, CYREG_PRT6_AG
+.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In__1__BIE, CYREG_PRT6_BIE
+.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In__1__BYP, CYREG_PRT6_BYP
+.set SCSI_In__1__CTL, CYREG_PRT6_CTL
+.set SCSI_In__1__DM0, CYREG_PRT6_DM0
+.set SCSI_In__1__DM1, CYREG_PRT6_DM1
+.set SCSI_In__1__DM2, CYREG_PRT6_DM2
+.set SCSI_In__1__DR, CYREG_PRT6_DR
+.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In__1__MASK, 0x10
+.set SCSI_In__1__PC, CYREG_PRT6_PC4
+.set SCSI_In__1__PORT, 6
+.set SCSI_In__1__PRT, CYREG_PRT6_PRT
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In__1__PS, CYREG_PRT6_PS
+.set SCSI_In__1__SHIFT, 4
+.set SCSI_In__1__SLW, CYREG_PRT6_SLW
 .set SCSI_In__2__AG, CYREG_PRT6_AG
 .set SCSI_In__2__AMUX, CYREG_PRT6_AMUX
 .set SCSI_In__2__BIE, CYREG_PRT6_BIE
@@ -1004,8 +1078,8 @@
 .set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS
 .set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
 .set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__2__MASK, 0x10
-.set SCSI_In__2__PC, CYREG_PRT6_PC4
+.set SCSI_In__2__MASK, 0x20
+.set SCSI_In__2__PC, CYREG_PRT6_PC5
 .set SCSI_In__2__PORT, 6
 .set SCSI_In__2__PRT, CYREG_PRT6_PRT
 .set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
@@ -1016,7 +1090,7 @@
 .set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
 .set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
 .set SCSI_In__2__PS, CYREG_PRT6_PS
-.set SCSI_In__2__SHIFT, 4
+.set SCSI_In__2__SHIFT, 5
 .set SCSI_In__2__SLW, CYREG_PRT6_SLW
 .set SCSI_In__3__AG, CYREG_PRT6_AG
 .set SCSI_In__3__AMUX, CYREG_PRT6_AMUX
@@ -1031,8 +1105,8 @@
 .set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS
 .set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
 .set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__3__MASK, 0x20
-.set SCSI_In__3__PC, CYREG_PRT6_PC5
+.set SCSI_In__3__MASK, 0x80
+.set SCSI_In__3__PC, CYREG_PRT6_PC7
 .set SCSI_In__3__PORT, 6
 .set SCSI_In__3__PRT, CYREG_PRT6_PRT
 .set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
@@ -1043,62 +1117,62 @@
 .set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
 .set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
 .set SCSI_In__3__PS, CYREG_PRT6_PS
-.set SCSI_In__3__SHIFT, 5
+.set SCSI_In__3__SHIFT, 7
 .set SCSI_In__3__SLW, CYREG_PRT6_SLW
-.set SCSI_In__4__AG, CYREG_PRT6_AG
-.set SCSI_In__4__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__4__BIE, CYREG_PRT6_BIE
-.set SCSI_In__4__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__4__BYP, CYREG_PRT6_BYP
-.set SCSI_In__4__CTL, CYREG_PRT6_CTL
-.set SCSI_In__4__DM0, CYREG_PRT6_DM0
-.set SCSI_In__4__DM1, CYREG_PRT6_DM1
-.set SCSI_In__4__DM2, CYREG_PRT6_DM2
-.set SCSI_In__4__DR, CYREG_PRT6_DR
-.set SCSI_In__4__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__4__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__4__MASK, 0x40
-.set SCSI_In__4__PC, CYREG_PRT6_PC6
-.set SCSI_In__4__PORT, 6
-.set SCSI_In__4__PRT, CYREG_PRT6_PRT
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__4__PS, CYREG_PRT6_PS
-.set SCSI_In__4__SHIFT, 6
-.set SCSI_In__4__SLW, CYREG_PRT6_SLW
-.set SCSI_In__5__AG, CYREG_PRT6_AG
-.set SCSI_In__5__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__5__BIE, CYREG_PRT6_BIE
-.set SCSI_In__5__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__5__BYP, CYREG_PRT6_BYP
-.set SCSI_In__5__CTL, CYREG_PRT6_CTL
-.set SCSI_In__5__DM0, CYREG_PRT6_DM0
-.set SCSI_In__5__DM1, CYREG_PRT6_DM1
-.set SCSI_In__5__DM2, CYREG_PRT6_DM2
-.set SCSI_In__5__DR, CYREG_PRT6_DR
-.set SCSI_In__5__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__5__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__5__MASK, 0x80
-.set SCSI_In__5__PC, CYREG_PRT6_PC7
-.set SCSI_In__5__PORT, 6
-.set SCSI_In__5__PRT, CYREG_PRT6_PRT
-.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__5__PS, CYREG_PRT6_PS
-.set SCSI_In__5__SHIFT, 7
-.set SCSI_In__5__SLW, CYREG_PRT6_SLW
+.set SCSI_In__4__AG, CYREG_PRT5_AG
+.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In__4__BIE, CYREG_PRT5_BIE
+.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In__4__BYP, CYREG_PRT5_BYP
+.set SCSI_In__4__CTL, CYREG_PRT5_CTL
+.set SCSI_In__4__DM0, CYREG_PRT5_DM0
+.set SCSI_In__4__DM1, CYREG_PRT5_DM1
+.set SCSI_In__4__DM2, CYREG_PRT5_DM2
+.set SCSI_In__4__DR, CYREG_PRT5_DR
+.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In__4__MASK, 0x01
+.set SCSI_In__4__PC, CYREG_PRT5_PC0
+.set SCSI_In__4__PORT, 5
+.set SCSI_In__4__PRT, CYREG_PRT5_PRT
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In__4__PS, CYREG_PRT5_PS
+.set SCSI_In__4__SHIFT, 0
+.set SCSI_In__4__SLW, CYREG_PRT5_SLW
+.set SCSI_In__5__AG, CYREG_PRT5_AG
+.set SCSI_In__5__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In__5__BIE, CYREG_PRT5_BIE
+.set SCSI_In__5__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In__5__BYP, CYREG_PRT5_BYP
+.set SCSI_In__5__CTL, CYREG_PRT5_CTL
+.set SCSI_In__5__DM0, CYREG_PRT5_DM0
+.set SCSI_In__5__DM1, CYREG_PRT5_DM1
+.set SCSI_In__5__DM2, CYREG_PRT5_DM2
+.set SCSI_In__5__DR, CYREG_PRT5_DR
+.set SCSI_In__5__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In__5__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In__5__MASK, 0x02
+.set SCSI_In__5__PC, CYREG_PRT5_PC1
+.set SCSI_In__5__PORT, 5
+.set SCSI_In__5__PRT, CYREG_PRT5_PRT
+.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In__5__PS, CYREG_PRT5_PS
+.set SCSI_In__5__SHIFT, 1
+.set SCSI_In__5__SLW, CYREG_PRT5_SLW
 .set SCSI_In__6__AG, CYREG_PRT5_AG
 .set SCSI_In__6__AMUX, CYREG_PRT5_AMUX
 .set SCSI_In__6__BIE, CYREG_PRT5_BIE
@@ -1112,8 +1186,8 @@
 .set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS
 .set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
 .set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In__6__MASK, 0x01
-.set SCSI_In__6__PC, CYREG_PRT5_PC0
+.set SCSI_In__6__MASK, 0x04
+.set SCSI_In__6__PC, CYREG_PRT5_PC2
 .set SCSI_In__6__PORT, 5
 .set SCSI_In__6__PRT, CYREG_PRT5_PRT
 .set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
@@ -1124,7 +1198,7 @@
 .set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
 .set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
 .set SCSI_In__6__PS, CYREG_PRT5_PS
-.set SCSI_In__6__SHIFT, 0
+.set SCSI_In__6__SHIFT, 2
 .set SCSI_In__6__SLW, CYREG_PRT5_SLW
 .set SCSI_In__7__AG, CYREG_PRT5_AG
 .set SCSI_In__7__AMUX, CYREG_PRT5_AMUX
@@ -1139,8 +1213,8 @@
 .set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS
 .set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
 .set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In__7__MASK, 0x02
-.set SCSI_In__7__PC, CYREG_PRT5_PC1
+.set SCSI_In__7__MASK, 0x08
+.set SCSI_In__7__PC, CYREG_PRT5_PC3
 .set SCSI_In__7__PORT, 5
 .set SCSI_In__7__PRT, CYREG_PRT5_PRT
 .set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
@@ -1151,62 +1225,8 @@
 .set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
 .set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
 .set SCSI_In__7__PS, CYREG_PRT5_PS
-.set SCSI_In__7__SHIFT, 1
+.set SCSI_In__7__SHIFT, 3
 .set SCSI_In__7__SLW, CYREG_PRT5_SLW
-.set SCSI_In__8__AG, CYREG_PRT5_AG
-.set SCSI_In__8__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In__8__BIE, CYREG_PRT5_BIE
-.set SCSI_In__8__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In__8__BYP, CYREG_PRT5_BYP
-.set SCSI_In__8__CTL, CYREG_PRT5_CTL
-.set SCSI_In__8__DM0, CYREG_PRT5_DM0
-.set SCSI_In__8__DM1, CYREG_PRT5_DM1
-.set SCSI_In__8__DM2, CYREG_PRT5_DM2
-.set SCSI_In__8__DR, CYREG_PRT5_DR
-.set SCSI_In__8__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In__8__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In__8__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In__8__MASK, 0x04
-.set SCSI_In__8__PC, CYREG_PRT5_PC2
-.set SCSI_In__8__PORT, 5
-.set SCSI_In__8__PRT, CYREG_PRT5_PRT
-.set SCSI_In__8__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In__8__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In__8__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In__8__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In__8__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In__8__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In__8__PS, CYREG_PRT5_PS
-.set SCSI_In__8__SHIFT, 2
-.set SCSI_In__8__SLW, CYREG_PRT5_SLW
-.set SCSI_In__9__AG, CYREG_PRT5_AG
-.set SCSI_In__9__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In__9__BIE, CYREG_PRT5_BIE
-.set SCSI_In__9__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In__9__BYP, CYREG_PRT5_BYP
-.set SCSI_In__9__CTL, CYREG_PRT5_CTL
-.set SCSI_In__9__DM0, CYREG_PRT5_DM0
-.set SCSI_In__9__DM1, CYREG_PRT5_DM1
-.set SCSI_In__9__DM2, CYREG_PRT5_DM2
-.set SCSI_In__9__DR, CYREG_PRT5_DR
-.set SCSI_In__9__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In__9__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In__9__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In__9__MASK, 0x08
-.set SCSI_In__9__PC, CYREG_PRT5_PC3
-.set SCSI_In__9__PORT, 5
-.set SCSI_In__9__PRT, CYREG_PRT5_PRT
-.set SCSI_In__9__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In__9__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In__9__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In__9__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In__9__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In__9__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In__9__PS, CYREG_PRT5_PS
-.set SCSI_In__9__SHIFT, 3
-.set SCSI_In__9__SLW, CYREG_PRT5_SLW
 .set SCSI_In__ACK__AG, CYREG_PRT6_AG
 .set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX
 .set SCSI_In__ACK__BIE, CYREG_PRT6_BIE
@@ -1234,32 +1254,6 @@
 .set SCSI_In__ACK__PS, CYREG_PRT6_PS
 .set SCSI_In__ACK__SHIFT, 5
 .set SCSI_In__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_In__ATN__AG, CYREG_PRT12_AG
-.set SCSI_In__ATN__BIE, CYREG_PRT12_BIE
-.set SCSI_In__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In__ATN__BYP, CYREG_PRT12_BYP
-.set SCSI_In__ATN__DM0, CYREG_PRT12_DM0
-.set SCSI_In__ATN__DM1, CYREG_PRT12_DM1
-.set SCSI_In__ATN__DM2, CYREG_PRT12_DM2
-.set SCSI_In__ATN__DR, CYREG_PRT12_DR
-.set SCSI_In__ATN__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In__ATN__MASK, 0x20
-.set SCSI_In__ATN__PC, CYREG_PRT12_PC5
-.set SCSI_In__ATN__PORT, 12
-.set SCSI_In__ATN__PRT, CYREG_PRT12_PRT
-.set SCSI_In__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In__ATN__PS, CYREG_PRT12_PS
-.set SCSI_In__ATN__SHIFT, 5
-.set SCSI_In__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In__ATN__SLW, CYREG_PRT12_SLW
 .set SCSI_In__BSY__AG, CYREG_PRT6_AG
 .set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX
 .set SCSI_In__BSY__BIE, CYREG_PRT6_BIE
@@ -1421,33 +1415,6 @@
 .set SCSI_In__REQ__PS, CYREG_PRT5_PS
 .set SCSI_In__REQ__SHIFT, 2
 .set SCSI_In__REQ__SLW, CYREG_PRT5_SLW
-.set SCSI_In__RST__AG, CYREG_PRT6_AG
-.set SCSI_In__RST__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__RST__BIE, CYREG_PRT6_BIE
-.set SCSI_In__RST__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__RST__BYP, CYREG_PRT6_BYP
-.set SCSI_In__RST__CTL, CYREG_PRT6_CTL
-.set SCSI_In__RST__DM0, CYREG_PRT6_DM0
-.set SCSI_In__RST__DM1, CYREG_PRT6_DM1
-.set SCSI_In__RST__DM2, CYREG_PRT6_DM2
-.set SCSI_In__RST__DR, CYREG_PRT6_DR
-.set SCSI_In__RST__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__RST__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__RST__MASK, 0x40
-.set SCSI_In__RST__PC, CYREG_PRT6_PC6
-.set SCSI_In__RST__PORT, 6
-.set SCSI_In__RST__PRT, CYREG_PRT6_PRT
-.set SCSI_In__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__RST__PS, CYREG_PRT6_PS
-.set SCSI_In__RST__SHIFT, 6
-.set SCSI_In__RST__SLW, CYREG_PRT6_SLW
 .set SCSI_In__SEL__AG, CYREG_PRT5_AG
 .set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX
 .set SCSI_In__SEL__BIE, CYREG_PRT5_BIE
@@ -1831,7 +1798,6 @@
 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
 .set CYDEV_DEBUGGING_ENABLE, 1
-.set CYDEV_DEBUGGING_REQXRES, 1
 .set CYDEV_DEBUGGING_XRES, 0
 .set CYDEV_DEBUG_ENABLE_MASK, 0x20
 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
@@ -1839,7 +1805,7 @@
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x1000
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x00000003
+.set CYDEV_INTR_RISING, 0x00000001
 .set CYDEV_PROJ_TYPE, 0
 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1
 .set CYDEV_PROJ_TYPE_LOADABLE, 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -0,0 +1,1834 @@
+#ifndef INCLUDED_CYFITTERIAR_INC
+#define INCLUDED_CYFITTERIAR_INC
+    INCLUDE cydeviceiar.inc
+    INCLUDE cydeviceiar_trm.inc
+
+/* SCSI_ATN_ISR */
+SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_ATN_ISR__INTC_MASK EQU 0x01
+SCSI_ATN_ISR__INTC_NUMBER EQU 0
+SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__MASK EQU 0x01
+SCSI_Out_DBx__0__PC EQU CYREG_PRT0_PC0
+SCSI_Out_DBx__0__PORT EQU 0
+SCSI_Out_DBx__0__SHIFT EQU 0
+SCSI_Out_DBx__1__MASK EQU 0x02
+SCSI_Out_DBx__1__PC EQU CYREG_PRT0_PC1
+SCSI_Out_DBx__1__PORT EQU 0
+SCSI_Out_DBx__1__SHIFT EQU 1
+SCSI_Out_DBx__2__MASK EQU 0x04
+SCSI_Out_DBx__2__PC EQU CYREG_PRT0_PC2
+SCSI_Out_DBx__2__PORT EQU 0
+SCSI_Out_DBx__2__SHIFT EQU 2
+SCSI_Out_DBx__3__MASK EQU 0x08
+SCSI_Out_DBx__3__PC EQU CYREG_PRT0_PC3
+SCSI_Out_DBx__3__PORT EQU 0
+SCSI_Out_DBx__3__SHIFT EQU 3
+SCSI_Out_DBx__4__MASK EQU 0x10
+SCSI_Out_DBx__4__PC EQU CYREG_PRT0_PC4
+SCSI_Out_DBx__4__PORT EQU 0
+SCSI_Out_DBx__4__SHIFT EQU 4
+SCSI_Out_DBx__5__MASK EQU 0x20
+SCSI_Out_DBx__5__PC EQU CYREG_PRT0_PC5
+SCSI_Out_DBx__5__PORT EQU 0
+SCSI_Out_DBx__5__SHIFT EQU 5
+SCSI_Out_DBx__6__MASK EQU 0x40
+SCSI_Out_DBx__6__PC EQU CYREG_PRT0_PC6
+SCSI_Out_DBx__6__PORT EQU 0
+SCSI_Out_DBx__6__SHIFT EQU 6
+SCSI_Out_DBx__7__MASK EQU 0x80
+SCSI_Out_DBx__7__PC EQU CYREG_PRT0_PC7
+SCSI_Out_DBx__7__PORT EQU 0
+SCSI_Out_DBx__7__SHIFT EQU 7
+SCSI_Out_DBx__AG EQU CYREG_PRT0_AG
+SCSI_Out_DBx__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE
+SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP
+SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL
+SCSI_Out_DBx__DB0__MASK EQU 0x01
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT0_PC0
+SCSI_Out_DBx__DB0__PORT EQU 0
+SCSI_Out_DBx__DB0__SHIFT EQU 0
+SCSI_Out_DBx__DB1__MASK EQU 0x02
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT0_PC1
+SCSI_Out_DBx__DB1__PORT EQU 0
+SCSI_Out_DBx__DB1__SHIFT EQU 1
+SCSI_Out_DBx__DB2__MASK EQU 0x04
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT0_PC2
+SCSI_Out_DBx__DB2__PORT EQU 0
+SCSI_Out_DBx__DB2__SHIFT EQU 2
+SCSI_Out_DBx__DB3__MASK EQU 0x08
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT0_PC3
+SCSI_Out_DBx__DB3__PORT EQU 0
+SCSI_Out_DBx__DB3__SHIFT EQU 3
+SCSI_Out_DBx__DB4__MASK EQU 0x10
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT0_PC4
+SCSI_Out_DBx__DB4__PORT EQU 0
+SCSI_Out_DBx__DB4__SHIFT EQU 4
+SCSI_Out_DBx__DB5__MASK EQU 0x20
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT0_PC5
+SCSI_Out_DBx__DB5__PORT EQU 0
+SCSI_Out_DBx__DB5__SHIFT EQU 5
+SCSI_Out_DBx__DB6__MASK EQU 0x40
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT0_PC6
+SCSI_Out_DBx__DB6__PORT EQU 0
+SCSI_Out_DBx__DB6__SHIFT EQU 6
+SCSI_Out_DBx__DB7__MASK EQU 0x80
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT0_PC7
+SCSI_Out_DBx__DB7__PORT EQU 0
+SCSI_Out_DBx__DB7__SHIFT EQU 7
+SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out_DBx__DR EQU CYREG_PRT0_DR
+SCSI_Out_DBx__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out_DBx__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out_DBx__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out_DBx__MASK EQU 0xFF
+SCSI_Out_DBx__PORT EQU 0
+SCSI_Out_DBx__PRT EQU CYREG_PRT0_PRT
+SCSI_Out_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out_DBx__PS EQU CYREG_PRT0_PS
+SCSI_Out_DBx__SHIFT EQU 0
+SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW
+
+/* SCSI_RST_ISR */
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x400
+SCSI_RST_ISR__INTC_NUMBER EQU 10
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SDCard_BSPIM */
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+
+/* SCSI_In_DBx */
+SCSI_In_DBx__0__MASK EQU 0x01
+SCSI_In_DBx__0__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__0__PORT EQU 2
+SCSI_In_DBx__0__SHIFT EQU 0
+SCSI_In_DBx__1__MASK EQU 0x02
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__1__PORT EQU 2
+SCSI_In_DBx__1__SHIFT EQU 1
+SCSI_In_DBx__2__MASK EQU 0x04
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__2__PORT EQU 2
+SCSI_In_DBx__2__SHIFT EQU 2
+SCSI_In_DBx__3__MASK EQU 0x08
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__3__PORT EQU 2
+SCSI_In_DBx__3__SHIFT EQU 3
+SCSI_In_DBx__4__MASK EQU 0x10
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__4__PORT EQU 2
+SCSI_In_DBx__4__SHIFT EQU 4
+SCSI_In_DBx__5__MASK EQU 0x20
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__5__PORT EQU 2
+SCSI_In_DBx__5__SHIFT EQU 5
+SCSI_In_DBx__6__MASK EQU 0x40
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__SHIFT EQU 6
+SCSI_In_DBx__7__MASK EQU 0x80
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__SHIFT EQU 7
+SCSI_In_DBx__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB0__MASK EQU 0x01
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__DB0__PORT EQU 2
+SCSI_In_DBx__DB0__SHIFT EQU 0
+SCSI_In_DBx__DB1__MASK EQU 0x02
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__DB1__PORT EQU 2
+SCSI_In_DBx__DB1__SHIFT EQU 1
+SCSI_In_DBx__DB2__MASK EQU 0x04
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB2__PORT EQU 2
+SCSI_In_DBx__DB2__SHIFT EQU 2
+SCSI_In_DBx__DB3__MASK EQU 0x08
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__SHIFT EQU 3
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB5__MASK EQU 0x20
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__SHIFT EQU 5
+SCSI_In_DBx__DB6__MASK EQU 0x40
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__SHIFT EQU 6
+SCSI_In_DBx__DB7__MASK EQU 0x80
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__SHIFT EQU 7
+SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__MASK EQU 0xFF
+SCSI_In_DBx__PORT EQU 2
+SCSI_In_DBx__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__SHIFT EQU 0
+SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW
+
+/* SD_Data_Clk */
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
+
+/* SD_Init_Clk */
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Init_Clk__INDEX EQU 0x01
+SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Init_Clk__PM_ACT_MSK EQU 0x02
+SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Init_Clk__PM_STBY_MSK EQU 0x02
+
+/* SD_Clk_Ctl */
+SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+
+/* PARITY_EN */
+PARITY_EN__0__MASK EQU 0x10
+PARITY_EN__0__PC EQU CYREG_PRT5_PC4
+PARITY_EN__0__PORT EQU 5
+PARITY_EN__0__SHIFT EQU 4
+PARITY_EN__AG EQU CYREG_PRT5_AG
+PARITY_EN__AMUX EQU CYREG_PRT5_AMUX
+PARITY_EN__BIE EQU CYREG_PRT5_BIE
+PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+PARITY_EN__BYP EQU CYREG_PRT5_BYP
+PARITY_EN__CTL EQU CYREG_PRT5_CTL
+PARITY_EN__DM0 EQU CYREG_PRT5_DM0
+PARITY_EN__DM1 EQU CYREG_PRT5_DM1
+PARITY_EN__DM2 EQU CYREG_PRT5_DM2
+PARITY_EN__DR EQU CYREG_PRT5_DR
+PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS
+PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN
+PARITY_EN__MASK EQU 0x10
+PARITY_EN__PORT EQU 5
+PARITY_EN__PRT EQU CYREG_PRT5_PRT
+PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+PARITY_EN__PS EQU CYREG_PRT5_PS
+PARITY_EN__SHIFT EQU 4
+PARITY_EN__SLW EQU CYREG_PRT5_SLW
+
+/* SCSI_ATN */
+SCSI_ATN__0__MASK EQU 0x20
+SCSI_ATN__0__PC EQU CYREG_PRT12_PC5
+SCSI_ATN__0__PORT EQU 12
+SCSI_ATN__0__SHIFT EQU 5
+SCSI_ATN__AG EQU CYREG_PRT12_AG
+SCSI_ATN__BIE EQU CYREG_PRT12_BIE
+SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_ATN__BYP EQU CYREG_PRT12_BYP
+SCSI_ATN__DM0 EQU CYREG_PRT12_DM0
+SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
+SCSI_ATN__DM2 EQU CYREG_PRT12_DM2
+SCSI_ATN__DR EQU CYREG_PRT12_DR
+SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_ATN__INT__MASK EQU 0x20
+SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5
+SCSI_ATN__INT__PORT EQU 12
+SCSI_ATN__INT__SHIFT EQU 5
+SCSI_ATN__MASK EQU 0x20
+SCSI_ATN__PORT EQU 12
+SCSI_ATN__PRT EQU CYREG_PRT12_PRT
+SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_ATN__PS EQU CYREG_PRT12_PS
+SCSI_ATN__SHIFT EQU 5
+SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_ATN__SLW EQU CYREG_PRT12_SLW
+
+/* SCSI_Out */
+SCSI_Out__0__AG EQU CYREG_PRT4_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__0__DR EQU CYREG_PRT4_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__0__MASK EQU 0x04
+SCSI_Out__0__PC EQU CYREG_PRT4_PC2
+SCSI_Out__0__PORT EQU 4
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT4_PS
+SCSI_Out__0__SHIFT EQU 2
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__1__AG EQU CYREG_PRT4_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__1__DR EQU CYREG_PRT4_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__1__MASK EQU 0x08
+SCSI_Out__1__PC EQU CYREG_PRT4_PC3
+SCSI_Out__1__PORT EQU 4
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT4_PS
+SCSI_Out__1__SHIFT EQU 3
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__2__AG EQU CYREG_PRT4_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__2__DR EQU CYREG_PRT4_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__2__MASK EQU 0x10
+SCSI_Out__2__PC EQU CYREG_PRT4_PC4
+SCSI_Out__2__PORT EQU 4
+SCSI_Out__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT4_PS
+SCSI_Out__2__SHIFT EQU 4
+SCSI_Out__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__3__AG EQU CYREG_PRT4_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__3__DR EQU CYREG_PRT4_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__3__MASK EQU 0x20
+SCSI_Out__3__PC EQU CYREG_PRT4_PC5
+SCSI_Out__3__PORT EQU 4
+SCSI_Out__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT4_PS
+SCSI_Out__3__SHIFT EQU 5
+SCSI_Out__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__4__AG EQU CYREG_PRT4_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__4__DR EQU CYREG_PRT4_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__4__MASK EQU 0x40
+SCSI_Out__4__PC EQU CYREG_PRT4_PC6
+SCSI_Out__4__PORT EQU 4
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT4_PS
+SCSI_Out__4__SHIFT EQU 6
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__5__AG EQU CYREG_PRT4_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__5__DR EQU CYREG_PRT4_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__5__MASK EQU 0x80
+SCSI_Out__5__PC EQU CYREG_PRT4_PC7
+SCSI_Out__5__PORT EQU 4
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT4_PS
+SCSI_Out__5__SHIFT EQU 7
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__6__AG EQU CYREG_PRT6_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__6__DR EQU CYREG_PRT6_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__6__MASK EQU 0x01
+SCSI_Out__6__PC EQU CYREG_PRT6_PC0
+SCSI_Out__6__PORT EQU 6
+SCSI_Out__6__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT6_PS
+SCSI_Out__6__SHIFT EQU 0
+SCSI_Out__6__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__7__AG EQU CYREG_PRT6_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__7__DR EQU CYREG_PRT6_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__7__MASK EQU 0x02
+SCSI_Out__7__PC EQU CYREG_PRT6_PC1
+SCSI_Out__7__PORT EQU 6
+SCSI_Out__7__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT6_PS
+SCSI_Out__7__SHIFT EQU 1
+SCSI_Out__7__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__8__AG EQU CYREG_PRT6_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__8__DR EQU CYREG_PRT6_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__8__MASK EQU 0x04
+SCSI_Out__8__PC EQU CYREG_PRT6_PC2
+SCSI_Out__8__PORT EQU 6
+SCSI_Out__8__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT6_PS
+SCSI_Out__8__SHIFT EQU 2
+SCSI_Out__8__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__9__AG EQU CYREG_PRT6_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__9__DR EQU CYREG_PRT6_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__9__MASK EQU 0x08
+SCSI_Out__9__PC EQU CYREG_PRT6_PC3
+SCSI_Out__9__PORT EQU 6
+SCSI_Out__9__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT6_PS
+SCSI_Out__9__SHIFT EQU 3
+SCSI_Out__9__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT4_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT4_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x20
+SCSI_Out__ACK__PC EQU CYREG_PRT4_PC5
+SCSI_Out__ACK__PORT EQU 4
+SCSI_Out__ACK__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT4_PS
+SCSI_Out__ACK__SHIFT EQU 5
+SCSI_Out__ACK__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x08
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC3
+SCSI_Out__ATN__PORT EQU 4
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS
+SCSI_Out__ATN__SHIFT EQU 3
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT4_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT4_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x10
+SCSI_Out__BSY__PC EQU CYREG_PRT4_PC4
+SCSI_Out__BSY__PORT EQU 4
+SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT4_PS
+SCSI_Out__BSY__SHIFT EQU 4
+SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__CD__AG EQU CYREG_PRT6_AG
+SCSI_Out__CD__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__CD__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__CD__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__CD__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__CD__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__CD__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__CD__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__CD__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__CD__DR EQU CYREG_PRT6_DR
+SCSI_Out__CD__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__CD__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__CD__MASK EQU 0x02
+SCSI_Out__CD__PC EQU CYREG_PRT6_PC1
+SCSI_Out__CD__PORT EQU 6
+SCSI_Out__CD__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__CD__PS EQU CYREG_PRT6_PS
+SCSI_Out__CD__SHIFT EQU 1
+SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__DBP__AG EQU CYREG_PRT4_AG
+SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__DBP__DR EQU CYREG_PRT4_DR
+SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__DBP__MASK EQU 0x04
+SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2
+SCSI_Out__DBP__PORT EQU 4
+SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__DBP__PS EQU CYREG_PRT4_PS
+SCSI_Out__DBP__SHIFT EQU 2
+SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__IO__AG EQU CYREG_PRT6_AG
+SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__IO__DR EQU CYREG_PRT6_DR
+SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__IO__MASK EQU 0x08
+SCSI_Out__IO__PC EQU CYREG_PRT6_PC3
+SCSI_Out__IO__PORT EQU 6
+SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__IO__PS EQU CYREG_PRT6_PS
+SCSI_Out__IO__SHIFT EQU 3
+SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__MSG__AG EQU CYREG_PRT4_AG
+SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
+SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__MSG__MASK EQU 0x80
+SCSI_Out__MSG__PC EQU CYREG_PRT4_PC7
+SCSI_Out__MSG__PORT EQU 4
+SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__MSG__PS EQU CYREG_PRT4_PS
+SCSI_Out__MSG__SHIFT EQU 7
+SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT6_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT6_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x04
+SCSI_Out__REQ__PC EQU CYREG_PRT6_PC2
+SCSI_Out__REQ__PORT EQU 6
+SCSI_Out__REQ__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT6_PS
+SCSI_Out__REQ__SHIFT EQU 2
+SCSI_Out__REQ__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__RST__MASK EQU 0x40
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC6
+SCSI_Out__RST__PORT EQU 4
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS
+SCSI_Out__RST__SHIFT EQU 6
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT6_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT6_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x01
+SCSI_Out__SEL__PC EQU CYREG_PRT6_PC0
+SCSI_Out__SEL__PORT EQU 6
+SCSI_Out__SEL__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT6_PS
+SCSI_Out__SEL__SHIFT EQU 0
+SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW
+
+/* SCSI_RST */
+SCSI_RST__0__MASK EQU 0x40
+SCSI_RST__0__PC EQU CYREG_PRT6_PC6
+SCSI_RST__0__PORT EQU 6
+SCSI_RST__0__SHIFT EQU 6
+SCSI_RST__AG EQU CYREG_PRT6_AG
+SCSI_RST__AMUX EQU CYREG_PRT6_AMUX
+SCSI_RST__BIE EQU CYREG_PRT6_BIE
+SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_RST__BYP EQU CYREG_PRT6_BYP
+SCSI_RST__CTL EQU CYREG_PRT6_CTL
+SCSI_RST__DM0 EQU CYREG_PRT6_DM0
+SCSI_RST__DM1 EQU CYREG_PRT6_DM1
+SCSI_RST__DM2 EQU CYREG_PRT6_DM2
+SCSI_RST__DR EQU CYREG_PRT6_DR
+SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT
+SCSI_RST__INT__MASK EQU 0x40
+SCSI_RST__INT__PC EQU CYREG_PRT6_PC6
+SCSI_RST__INT__PORT EQU 6
+SCSI_RST__INT__SHIFT EQU 6
+SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_RST__MASK EQU 0x40
+SCSI_RST__PORT EQU 6
+SCSI_RST__PRT EQU CYREG_PRT6_PRT
+SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_RST__PS EQU CYREG_PRT6_PS
+SCSI_RST__SHIFT EQU 6
+SCSI_RST__SLW EQU CYREG_PRT6_SLW
+SCSI_RST__SNAP EQU CYREG_PICU6_SNAP
+
+/* SCSI_ID */
+SCSI_ID__0__MASK EQU 0x80
+SCSI_ID__0__PC EQU CYREG_PRT5_PC7
+SCSI_ID__0__PORT EQU 5
+SCSI_ID__0__SHIFT EQU 7
+SCSI_ID__1__MASK EQU 0x40
+SCSI_ID__1__PC EQU CYREG_PRT5_PC6
+SCSI_ID__1__PORT EQU 5
+SCSI_ID__1__SHIFT EQU 6
+SCSI_ID__2__MASK EQU 0x20
+SCSI_ID__2__PC EQU CYREG_PRT5_PC5
+SCSI_ID__2__PORT EQU 5
+SCSI_ID__2__SHIFT EQU 5
+SCSI_ID__AG EQU CYREG_PRT5_AG
+SCSI_ID__AMUX EQU CYREG_PRT5_AMUX
+SCSI_ID__BIE EQU CYREG_PRT5_BIE
+SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_ID__BYP EQU CYREG_PRT5_BYP
+SCSI_ID__CTL EQU CYREG_PRT5_CTL
+SCSI_ID__DM0 EQU CYREG_PRT5_DM0
+SCSI_ID__DM1 EQU CYREG_PRT5_DM1
+SCSI_ID__DM2 EQU CYREG_PRT5_DM2
+SCSI_ID__DR EQU CYREG_PRT5_DR
+SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_ID__PORT EQU 5
+SCSI_ID__PRT EQU CYREG_PRT5_PRT
+SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_ID__PS EQU CYREG_PRT5_PS
+SCSI_ID__SLW EQU CYREG_PRT5_SLW
+
+/* SCSI_In */
+SCSI_In__0__AG EQU CYREG_PRT12_AG
+SCSI_In__0__BIE EQU CYREG_PRT12_BIE
+SCSI_In__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In__0__BYP EQU CYREG_PRT12_BYP
+SCSI_In__0__DM0 EQU CYREG_PRT12_DM0
+SCSI_In__0__DM1 EQU CYREG_PRT12_DM1
+SCSI_In__0__DM2 EQU CYREG_PRT12_DM2
+SCSI_In__0__DR EQU CYREG_PRT12_DR
+SCSI_In__0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In__0__MASK EQU 0x10
+SCSI_In__0__PC EQU CYREG_PRT12_PC4
+SCSI_In__0__PORT EQU 12
+SCSI_In__0__PRT EQU CYREG_PRT12_PRT
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In__0__PS EQU CYREG_PRT12_PS
+SCSI_In__0__SHIFT EQU 4
+SCSI_In__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In__0__SLW EQU CYREG_PRT12_SLW
+SCSI_In__1__AG EQU CYREG_PRT6_AG
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__1__DR EQU CYREG_PRT6_DR
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__1__MASK EQU 0x10
+SCSI_In__1__PC EQU CYREG_PRT6_PC4
+SCSI_In__1__PORT EQU 6
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__1__PS EQU CYREG_PRT6_PS
+SCSI_In__1__SHIFT EQU 4
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW
+SCSI_In__2__AG EQU CYREG_PRT6_AG
+SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__2__BIE EQU CYREG_PRT6_BIE
+SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__2__BYP EQU CYREG_PRT6_BYP
+SCSI_In__2__CTL EQU CYREG_PRT6_CTL
+SCSI_In__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__2__DR EQU CYREG_PRT6_DR
+SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__2__MASK EQU 0x20
+SCSI_In__2__PC EQU CYREG_PRT6_PC5
+SCSI_In__2__PORT EQU 6
+SCSI_In__2__PRT EQU CYREG_PRT6_PRT
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__2__PS EQU CYREG_PRT6_PS
+SCSI_In__2__SHIFT EQU 5
+SCSI_In__2__SLW EQU CYREG_PRT6_SLW
+SCSI_In__3__AG EQU CYREG_PRT6_AG
+SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__3__BIE EQU CYREG_PRT6_BIE
+SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__3__BYP EQU CYREG_PRT6_BYP
+SCSI_In__3__CTL EQU CYREG_PRT6_CTL
+SCSI_In__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__3__DR EQU CYREG_PRT6_DR
+SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__3__MASK EQU 0x80
+SCSI_In__3__PC EQU CYREG_PRT6_PC7
+SCSI_In__3__PORT EQU 6
+SCSI_In__3__PRT EQU CYREG_PRT6_PRT
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__3__PS EQU CYREG_PRT6_PS
+SCSI_In__3__SHIFT EQU 7
+SCSI_In__3__SLW EQU CYREG_PRT6_SLW
+SCSI_In__4__AG EQU CYREG_PRT5_AG
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__4__DR EQU CYREG_PRT5_DR
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__4__MASK EQU 0x01
+SCSI_In__4__PC EQU CYREG_PRT5_PC0
+SCSI_In__4__PORT EQU 5
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__4__PS EQU CYREG_PRT5_PS
+SCSI_In__4__SHIFT EQU 0
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW
+SCSI_In__5__AG EQU CYREG_PRT5_AG
+SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__5__BIE EQU CYREG_PRT5_BIE
+SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__5__BYP EQU CYREG_PRT5_BYP
+SCSI_In__5__CTL EQU CYREG_PRT5_CTL
+SCSI_In__5__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__5__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__5__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__5__DR EQU CYREG_PRT5_DR
+SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__5__MASK EQU 0x02
+SCSI_In__5__PC EQU CYREG_PRT5_PC1
+SCSI_In__5__PORT EQU 5
+SCSI_In__5__PRT EQU CYREG_PRT5_PRT
+SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__5__PS EQU CYREG_PRT5_PS
+SCSI_In__5__SHIFT EQU 1
+SCSI_In__5__SLW EQU CYREG_PRT5_SLW
+SCSI_In__6__AG EQU CYREG_PRT5_AG
+SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__6__BIE EQU CYREG_PRT5_BIE
+SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__6__BYP EQU CYREG_PRT5_BYP
+SCSI_In__6__CTL EQU CYREG_PRT5_CTL
+SCSI_In__6__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__6__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__6__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__6__DR EQU CYREG_PRT5_DR
+SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__6__MASK EQU 0x04
+SCSI_In__6__PC EQU CYREG_PRT5_PC2
+SCSI_In__6__PORT EQU 5
+SCSI_In__6__PRT EQU CYREG_PRT5_PRT
+SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__6__PS EQU CYREG_PRT5_PS
+SCSI_In__6__SHIFT EQU 2
+SCSI_In__6__SLW EQU CYREG_PRT5_SLW
+SCSI_In__7__AG EQU CYREG_PRT5_AG
+SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__7__BIE EQU CYREG_PRT5_BIE
+SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__7__BYP EQU CYREG_PRT5_BYP
+SCSI_In__7__CTL EQU CYREG_PRT5_CTL
+SCSI_In__7__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__7__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__7__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__7__DR EQU CYREG_PRT5_DR
+SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__7__MASK EQU 0x08
+SCSI_In__7__PC EQU CYREG_PRT5_PC3
+SCSI_In__7__PORT EQU 5
+SCSI_In__7__PRT EQU CYREG_PRT5_PRT
+SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__7__PS EQU CYREG_PRT5_PS
+SCSI_In__7__SHIFT EQU 3
+SCSI_In__7__SLW EQU CYREG_PRT5_SLW
+SCSI_In__ACK__AG EQU CYREG_PRT6_AG
+SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__ACK__DR EQU CYREG_PRT6_DR
+SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__ACK__MASK EQU 0x20
+SCSI_In__ACK__PC EQU CYREG_PRT6_PC5
+SCSI_In__ACK__PORT EQU 6
+SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__ACK__PS EQU CYREG_PRT6_PS
+SCSI_In__ACK__SHIFT EQU 5
+SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_In__BSY__AG EQU CYREG_PRT6_AG
+SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__BSY__DR EQU CYREG_PRT6_DR
+SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__BSY__MASK EQU 0x10
+SCSI_In__BSY__PC EQU CYREG_PRT6_PC4
+SCSI_In__BSY__PORT EQU 6
+SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__BSY__PS EQU CYREG_PRT6_PS
+SCSI_In__BSY__SHIFT EQU 4
+SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_In__CD__AG EQU CYREG_PRT5_AG
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__CD__DR EQU CYREG_PRT5_DR
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__CD__MASK EQU 0x02
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1
+SCSI_In__CD__PORT EQU 5
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__CD__PS EQU CYREG_PRT5_PS
+SCSI_In__CD__SHIFT EQU 1
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW
+SCSI_In__DBP__AG EQU CYREG_PRT12_AG
+SCSI_In__DBP__BIE EQU CYREG_PRT12_BIE
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In__DBP__BYP EQU CYREG_PRT12_BYP
+SCSI_In__DBP__DM0 EQU CYREG_PRT12_DM0
+SCSI_In__DBP__DM1 EQU CYREG_PRT12_DM1
+SCSI_In__DBP__DM2 EQU CYREG_PRT12_DM2
+SCSI_In__DBP__DR EQU CYREG_PRT12_DR
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In__DBP__MASK EQU 0x10
+SCSI_In__DBP__PC EQU CYREG_PRT12_PC4
+SCSI_In__DBP__PORT EQU 12
+SCSI_In__DBP__PRT EQU CYREG_PRT12_PRT
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In__DBP__PS EQU CYREG_PRT12_PS
+SCSI_In__DBP__SHIFT EQU 4
+SCSI_In__DBP__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In__DBP__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In__DBP__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In__DBP__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In__DBP__SLW EQU CYREG_PRT12_SLW
+SCSI_In__IO__AG EQU CYREG_PRT5_AG
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__IO__DR EQU CYREG_PRT5_DR
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__IO__MASK EQU 0x08
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3
+SCSI_In__IO__PORT EQU 5
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__IO__PS EQU CYREG_PRT5_PS
+SCSI_In__IO__SHIFT EQU 3
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__MSG__MASK EQU 0x80
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7
+SCSI_In__MSG__PORT EQU 6
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS
+SCSI_In__MSG__SHIFT EQU 7
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__REQ__MASK EQU 0x04
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2
+SCSI_In__REQ__PORT EQU 5
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS
+SCSI_In__REQ__SHIFT EQU 2
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW
+SCSI_In__SEL__AG EQU CYREG_PRT5_AG
+SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE
+SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP
+SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL
+SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__SEL__DR EQU CYREG_PRT5_DR
+SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__SEL__MASK EQU 0x01
+SCSI_In__SEL__PC EQU CYREG_PRT5_PC0
+SCSI_In__SEL__PORT EQU 5
+SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT
+SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__SEL__PS EQU CYREG_PRT5_PS
+SCSI_In__SEL__SHIFT EQU 0
+SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW
+
+/* SD_DAT1 */
+SD_DAT1__0__MASK EQU 0x20
+SD_DAT1__0__PC EQU CYREG_PRT3_PC5
+SD_DAT1__0__PORT EQU 3
+SD_DAT1__0__SHIFT EQU 5
+SD_DAT1__AG EQU CYREG_PRT3_AG
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT1__BIE EQU CYREG_PRT3_BIE
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT1__BYP EQU CYREG_PRT3_BYP
+SD_DAT1__CTL EQU CYREG_PRT3_CTL
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2
+SD_DAT1__DR EQU CYREG_PRT3_DR
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT1__MASK EQU 0x20
+SD_DAT1__PORT EQU 3
+SD_DAT1__PRT EQU CYREG_PRT3_PRT
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT1__PS EQU CYREG_PRT3_PS
+SD_DAT1__SHIFT EQU 5
+SD_DAT1__SLW EQU CYREG_PRT3_SLW
+
+/* SD_DAT2 */
+SD_DAT2__0__MASK EQU 0x01
+SD_DAT2__0__PC EQU CYREG_PRT3_PC0
+SD_DAT2__0__PORT EQU 3
+SD_DAT2__0__SHIFT EQU 0
+SD_DAT2__AG EQU CYREG_PRT3_AG
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT2__BIE EQU CYREG_PRT3_BIE
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT2__BYP EQU CYREG_PRT3_BYP
+SD_DAT2__CTL EQU CYREG_PRT3_CTL
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2
+SD_DAT2__DR EQU CYREG_PRT3_DR
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT2__MASK EQU 0x01
+SD_DAT2__PORT EQU 3
+SD_DAT2__PRT EQU CYREG_PRT3_PRT
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT2__PS EQU CYREG_PRT3_PS
+SD_DAT2__SHIFT EQU 0
+SD_DAT2__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MISO */
+SD_MISO__0__MASK EQU 0x10
+SD_MISO__0__PC EQU CYREG_PRT3_PC4
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 4
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x10
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 4
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MOSI */
+SD_MOSI__0__MASK EQU 0x04
+SD_MOSI__0__PC EQU CYREG_PRT3_PC2
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 2
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x04
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 2
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+/* SD_SCK */
+SD_SCK__0__MASK EQU 0x08
+SD_SCK__0__PC EQU CYREG_PRT3_PC3
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 3
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x08
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 3
+SD_SCK__SLW EQU CYREG_PRT3_SLW
+
+/* SD_CD */
+SD_CD__0__MASK EQU 0x40
+SD_CD__0__PC EQU CYREG_PRT3_PC6
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 6
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x40
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 6
+SD_CD__SLW EQU CYREG_PRT3_SLW
+
+/* SD_CS */
+SD_CS__0__MASK EQU 0x02
+SD_CS__0__PC EQU CYREG_PRT3_PC1
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 1
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x02
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 1
+SD_CS__SLW EQU CYREG_PRT3_SLW
+
+/* SD_WP */
+SD_WP__0__MASK EQU 0x80
+SD_WP__0__PC EQU CYREG_PRT3_PC7
+SD_WP__0__PORT EQU 3
+SD_WP__0__SHIFT EQU 7
+SD_WP__AG EQU CYREG_PRT3_AG
+SD_WP__AMUX EQU CYREG_PRT3_AMUX
+SD_WP__BIE EQU CYREG_PRT3_BIE
+SD_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_WP__BYP EQU CYREG_PRT3_BYP
+SD_WP__CTL EQU CYREG_PRT3_CTL
+SD_WP__DM0 EQU CYREG_PRT3_DM0
+SD_WP__DM1 EQU CYREG_PRT3_DM1
+SD_WP__DM2 EQU CYREG_PRT3_DM2
+SD_WP__DR EQU CYREG_PRT3_DR
+SD_WP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_WP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_WP__MASK EQU 0x80
+SD_WP__PORT EQU 3
+SD_WP__PRT EQU CYREG_PRT3_PRT
+SD_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_WP__PS EQU CYREG_PRT3_PS
+SD_WP__SHIFT EQU 7
+SD_WP__SLW EQU CYREG_PRT3_SLW
+
+/* LED1 */
+LED1__0__MASK EQU 0x08
+LED1__0__PC EQU CYREG_PRT12_PC3
+LED1__0__PORT EQU 12
+LED1__0__SHIFT EQU 3
+LED1__AG EQU CYREG_PRT12_AG
+LED1__BIE EQU CYREG_PRT12_BIE
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+LED1__BYP EQU CYREG_PRT12_BYP
+LED1__DM0 EQU CYREG_PRT12_DM0
+LED1__DM1 EQU CYREG_PRT12_DM1
+LED1__DM2 EQU CYREG_PRT12_DM2
+LED1__DR EQU CYREG_PRT12_DR
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS
+LED1__MASK EQU 0x08
+LED1__PORT EQU 12
+LED1__PRT EQU CYREG_PRT12_PRT
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+LED1__PS EQU CYREG_PRT12_PS
+LED1__SHIFT EQU 3
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+LED1__SLW EQU CYREG_PRT12_SLW
+
+/* Miscellaneous */
+/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
+CYDEV_CHIP_MEMBER_5B EQU 4
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 4
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
+BCLK__BUS_CLK__HZ EQU 63000000
+BCLK__BUS_CLK__KHZ EQU 63000
+BCLK__BUS_CLK__MHZ EQU 63
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_DIE_LEOPARD EQU 1
+CYDEV_CHIP_DIE_PANTHER EQU 3
+CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_UNKNOWN EQU 0
+CYDEV_CHIP_FAMILY_PSOC3 EQU 1
+CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
+CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
+CYDEV_CHIP_JTAG_ID EQU 0x2E12F069
+CYDEV_CHIP_MEMBER_3A EQU 1
+CYDEV_CHIP_MEMBER_4A EQU 2
+CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
+CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_REVISION_3A_ES1 EQU 0
+CYDEV_CHIP_REVISION_3A_ES2 EQU 1
+CYDEV_CHIP_REVISION_3A_ES3 EQU 3
+CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
+CYDEV_CHIP_REVISION_4A_ES0 EQU 17
+CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_5A_ES0 EQU 0
+CYDEV_CHIP_REVISION_5A_ES1 EQU 1
+CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
+CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CONFIGURATION_COMPRESSED EQU 1
+CYDEV_CONFIGURATION_DMA EQU 0
+CYDEV_CONFIGURATION_ECC EQU 1
+CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
+CYDEV_CONFIGURATION_MODE_DMA EQU 2
+CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUGGING_DPS_Disable EQU 3
+CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
+CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
+CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_ENABLE EQU 1
+CYDEV_DEBUGGING_XRES EQU 0
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
+CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
+CYDEV_ECC_ENABLE EQU 0
+CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
+CYDEV_INTR_RISING EQU 0x00000001
+CYDEV_PROJ_TYPE EQU 0
+CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
+CYDEV_PROJ_TYPE_STANDARD EQU 0
+CYDEV_PROTECTION_ENABLE EQU 0
+CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_USE_BUNDLED_CMSIS EQU 1
+CYDEV_VARIABLE_VDDA EQU 0
+CYDEV_VDDA_MV EQU 5000
+CYDEV_VDDD_MV EQU 5000
+CYDEV_VDDIO0_MV EQU 5000
+CYDEV_VDDIO1_MV EQU 5000
+CYDEV_VDDIO2_MV EQU 5000
+CYDEV_VDDIO3_MV EQU 3300
+CYDEV_VIO0 EQU 5
+CYDEV_VIO0_MV EQU 5000
+CYDEV_VIO1 EQU 5
+CYDEV_VIO1_MV EQU 5000
+CYDEV_VIO2 EQU 5
+CYDEV_VIO2_MV EQU 5000
+CYDEV_VIO3_MV EQU 3300
+DMA_CHANNELS_USED__MASK0 EQU 0x00000000
+CYDEV_BOOTLOADER_ENABLE EQU 0
+
+#endif /* INCLUDED_CYFITTERIAR_INC */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -3,25 +3,15 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
-; SDCard_RxInternalInterrupt
-SDCard_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SDCard_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SDCard_RxInternalInterrupt__INTC_MASK EQU 0x01
-SDCard_RxInternalInterrupt__INTC_NUMBER EQU 0
-SDCard_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7
-SDCard_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SDCard_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SDCard_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SDCard_TxInternalInterrupt
-SDCard_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SDCard_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SDCard_TxInternalInterrupt__INTC_MASK EQU 0x02
-SDCard_TxInternalInterrupt__INTC_NUMBER EQU 1
-SDCard_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7
-SDCard_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-SDCard_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SDCard_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_ATN_ISR
+SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_ATN_ISR__INTC_MASK EQU 0x01
+SCSI_ATN_ISR__INTC_NUMBER EQU 0
+SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__MASK EQU 0x01
@@ -62,6 +52,38 @@ SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE
 SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK
 SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP
 SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL
+SCSI_Out_DBx__DB0__MASK EQU 0x01
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT0_PC0
+SCSI_Out_DBx__DB0__PORT EQU 0
+SCSI_Out_DBx__DB0__SHIFT EQU 0
+SCSI_Out_DBx__DB1__MASK EQU 0x02
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT0_PC1
+SCSI_Out_DBx__DB1__PORT EQU 0
+SCSI_Out_DBx__DB1__SHIFT EQU 1
+SCSI_Out_DBx__DB2__MASK EQU 0x04
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT0_PC2
+SCSI_Out_DBx__DB2__PORT EQU 0
+SCSI_Out_DBx__DB2__SHIFT EQU 2
+SCSI_Out_DBx__DB3__MASK EQU 0x08
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT0_PC3
+SCSI_Out_DBx__DB3__PORT EQU 0
+SCSI_Out_DBx__DB3__SHIFT EQU 3
+SCSI_Out_DBx__DB4__MASK EQU 0x10
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT0_PC4
+SCSI_Out_DBx__DB4__PORT EQU 0
+SCSI_Out_DBx__DB4__SHIFT EQU 4
+SCSI_Out_DBx__DB5__MASK EQU 0x20
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT0_PC5
+SCSI_Out_DBx__DB5__PORT EQU 0
+SCSI_Out_DBx__DB5__SHIFT EQU 5
+SCSI_Out_DBx__DB6__MASK EQU 0x40
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT0_PC6
+SCSI_Out_DBx__DB6__PORT EQU 0
+SCSI_Out_DBx__DB6__SHIFT EQU 6
+SCSI_Out_DBx__DB7__MASK EQU 0x80
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT0_PC7
+SCSI_Out_DBx__DB7__PORT EQU 0
+SCSI_Out_DBx__DB7__SHIFT EQU 7
 SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0
 SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1
 SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2
@@ -80,70 +102,48 @@ SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
 SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
 SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
 SCSI_Out_DBx__PS EQU CYREG_PRT0_PS
-SCSI_Out_DBx__SCSI_Out_DB0__MASK EQU 0x01
-SCSI_Out_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT0_PC0
-SCSI_Out_DBx__SCSI_Out_DB0__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB0__SHIFT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB1__MASK EQU 0x02
-SCSI_Out_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT0_PC1
-SCSI_Out_DBx__SCSI_Out_DB1__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB1__SHIFT EQU 1
-SCSI_Out_DBx__SCSI_Out_DB2__MASK EQU 0x04
-SCSI_Out_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT0_PC2
-SCSI_Out_DBx__SCSI_Out_DB2__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB2__SHIFT EQU 2
-SCSI_Out_DBx__SCSI_Out_DB3__MASK EQU 0x08
-SCSI_Out_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT0_PC3
-SCSI_Out_DBx__SCSI_Out_DB3__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB3__SHIFT EQU 3
-SCSI_Out_DBx__SCSI_Out_DB4__MASK EQU 0x10
-SCSI_Out_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT0_PC4
-SCSI_Out_DBx__SCSI_Out_DB4__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB4__SHIFT EQU 4
-SCSI_Out_DBx__SCSI_Out_DB5__MASK EQU 0x20
-SCSI_Out_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT0_PC5
-SCSI_Out_DBx__SCSI_Out_DB5__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB5__SHIFT EQU 5
-SCSI_Out_DBx__SCSI_Out_DB6__MASK EQU 0x40
-SCSI_Out_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT0_PC6
-SCSI_Out_DBx__SCSI_Out_DB6__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB6__SHIFT EQU 6
-SCSI_Out_DBx__SCSI_Out_DB7__MASK EQU 0x80
-SCSI_Out_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT0_PC7
-SCSI_Out_DBx__SCSI_Out_DB7__PORT EQU 0
-SCSI_Out_DBx__SCSI_Out_DB7__SHIFT EQU 7
 SCSI_Out_DBx__SHIFT EQU 0
 SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW
 
+; SCSI_RST_ISR
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x400
+SCSI_RST_ISR__INTC_NUMBER EQU 10
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@@ -167,28 +167,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB07_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB07_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB07_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB07_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB07_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB07_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
 
 ; SCSI_In_DBx
 SCSI_In_DBx__0__MASK EQU 0x01
@@ -229,6 +229,38 @@ SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE
 SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK
 SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP
 SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB0__MASK EQU 0x01
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT2_PC0
+SCSI_In_DBx__DB0__PORT EQU 2
+SCSI_In_DBx__DB0__SHIFT EQU 0
+SCSI_In_DBx__DB1__MASK EQU 0x02
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__DB1__PORT EQU 2
+SCSI_In_DBx__DB1__SHIFT EQU 1
+SCSI_In_DBx__DB2__MASK EQU 0x04
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB2__PORT EQU 2
+SCSI_In_DBx__DB2__SHIFT EQU 2
+SCSI_In_DBx__DB3__MASK EQU 0x08
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__SHIFT EQU 3
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB5__MASK EQU 0x20
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__SHIFT EQU 5
+SCSI_In_DBx__DB6__MASK EQU 0x40
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__SHIFT EQU 6
+SCSI_In_DBx__DB7__MASK EQU 0x80
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__SHIFT EQU 7
 SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0
 SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1
 SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2
@@ -247,38 +279,6 @@ SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
 SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
 SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
 SCSI_In_DBx__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__SCSI_Out_DB0__MASK EQU 0x01
-SCSI_In_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT2_PC0
-SCSI_In_DBx__SCSI_Out_DB0__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB0__SHIFT EQU 0
-SCSI_In_DBx__SCSI_Out_DB1__MASK EQU 0x02
-SCSI_In_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT2_PC1
-SCSI_In_DBx__SCSI_Out_DB1__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB1__SHIFT EQU 1
-SCSI_In_DBx__SCSI_Out_DB2__MASK EQU 0x04
-SCSI_In_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__SCSI_Out_DB2__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB2__SHIFT EQU 2
-SCSI_In_DBx__SCSI_Out_DB3__MASK EQU 0x08
-SCSI_In_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT2_PC3
-SCSI_In_DBx__SCSI_Out_DB3__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB3__SHIFT EQU 3
-SCSI_In_DBx__SCSI_Out_DB4__MASK EQU 0x10
-SCSI_In_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__SCSI_Out_DB4__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB4__SHIFT EQU 4
-SCSI_In_DBx__SCSI_Out_DB5__MASK EQU 0x20
-SCSI_In_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__SCSI_Out_DB5__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB5__SHIFT EQU 5
-SCSI_In_DBx__SCSI_Out_DB6__MASK EQU 0x40
-SCSI_In_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__SCSI_Out_DB6__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB6__SHIFT EQU 6
-SCSI_In_DBx__SCSI_Out_DB7__MASK EQU 0x80
-SCSI_In_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT2_PC7
-SCSI_In_DBx__SCSI_Out_DB7__PORT EQU 2
-SCSI_In_DBx__SCSI_Out_DB7__SHIFT EQU 7
 SCSI_In_DBx__SHIFT EQU 0
 SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW
 
@@ -307,24 +307,24 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
 ; SD_Clk_Ctl
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
 
 ; PARITY_EN
 PARITY_EN__0__MASK EQU 0x10
@@ -358,6 +358,41 @@ PARITY_EN__PS EQU CYREG_PRT5_PS
 PARITY_EN__SHIFT EQU 4
 PARITY_EN__SLW EQU CYREG_PRT5_SLW
 
+; SCSI_ATN
+SCSI_ATN__0__MASK EQU 0x20
+SCSI_ATN__0__PC EQU CYREG_PRT12_PC5
+SCSI_ATN__0__PORT EQU 12
+SCSI_ATN__0__SHIFT EQU 5
+SCSI_ATN__AG EQU CYREG_PRT12_AG
+SCSI_ATN__BIE EQU CYREG_PRT12_BIE
+SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_ATN__BYP EQU CYREG_PRT12_BYP
+SCSI_ATN__DM0 EQU CYREG_PRT12_DM0
+SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
+SCSI_ATN__DM2 EQU CYREG_PRT12_DM2
+SCSI_ATN__DR EQU CYREG_PRT12_DR
+SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_ATN__INT__MASK EQU 0x20
+SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5
+SCSI_ATN__INT__PORT EQU 12
+SCSI_ATN__INT__SHIFT EQU 5
+SCSI_ATN__MASK EQU 0x20
+SCSI_ATN__PORT EQU 12
+SCSI_ATN__PRT EQU CYREG_PRT12_PRT
+SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_ATN__PS EQU CYREG_PRT12_PS
+SCSI_ATN__SHIFT EQU 5
+SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_ATN__SLW EQU CYREG_PRT12_SLW
+
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
 SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
@@ -900,6 +935,44 @@ SCSI_Out__SEL__PS EQU CYREG_PRT6_PS
 SCSI_Out__SEL__SHIFT EQU 0
 SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW
 
+; SCSI_RST
+SCSI_RST__0__MASK EQU 0x40
+SCSI_RST__0__PC EQU CYREG_PRT6_PC6
+SCSI_RST__0__PORT EQU 6
+SCSI_RST__0__SHIFT EQU 6
+SCSI_RST__AG EQU CYREG_PRT6_AG
+SCSI_RST__AMUX EQU CYREG_PRT6_AMUX
+SCSI_RST__BIE EQU CYREG_PRT6_BIE
+SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_RST__BYP EQU CYREG_PRT6_BYP
+SCSI_RST__CTL EQU CYREG_PRT6_CTL
+SCSI_RST__DM0 EQU CYREG_PRT6_DM0
+SCSI_RST__DM1 EQU CYREG_PRT6_DM1
+SCSI_RST__DM2 EQU CYREG_PRT6_DM2
+SCSI_RST__DR EQU CYREG_PRT6_DR
+SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT
+SCSI_RST__INT__MASK EQU 0x40
+SCSI_RST__INT__PC EQU CYREG_PRT6_PC6
+SCSI_RST__INT__PORT EQU 6
+SCSI_RST__INT__SHIFT EQU 6
+SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_RST__MASK EQU 0x40
+SCSI_RST__PORT EQU 6
+SCSI_RST__PRT EQU CYREG_PRT6_PRT
+SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_RST__PS EQU CYREG_PRT6_PS
+SCSI_RST__SHIFT EQU 6
+SCSI_RST__SLW EQU CYREG_PRT6_SLW
+SCSI_RST__SNAP EQU CYREG_PICU6_SNAP
+
 ; SCSI_ID
 SCSI_ID__0__MASK EQU 0x80
 SCSI_ID__0__PC EQU CYREG_PRT5_PC7
@@ -965,32 +1038,33 @@ SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
 SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 SCSI_In__0__SLW EQU CYREG_PRT12_SLW
-SCSI_In__1__AG EQU CYREG_PRT12_AG
-SCSI_In__1__BIE EQU CYREG_PRT12_BIE
-SCSI_In__1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In__1__BYP EQU CYREG_PRT12_BYP
-SCSI_In__1__DM0 EQU CYREG_PRT12_DM0
-SCSI_In__1__DM1 EQU CYREG_PRT12_DM1
-SCSI_In__1__DM2 EQU CYREG_PRT12_DM2
-SCSI_In__1__DR EQU CYREG_PRT12_DR
-SCSI_In__1__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In__1__MASK EQU 0x20
-SCSI_In__1__PC EQU CYREG_PRT12_PC5
-SCSI_In__1__PORT EQU 12
-SCSI_In__1__PRT EQU CYREG_PRT12_PRT
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In__1__PS EQU CYREG_PRT12_PS
-SCSI_In__1__SHIFT EQU 5
-SCSI_In__1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In__1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In__1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In__1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In__1__SLW EQU CYREG_PRT12_SLW
+SCSI_In__1__AG EQU CYREG_PRT6_AG
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_In__1__DR EQU CYREG_PRT6_DR
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__1__MASK EQU 0x10
+SCSI_In__1__PC EQU CYREG_PRT6_PC4
+SCSI_In__1__PORT EQU 6
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In__1__PS EQU CYREG_PRT6_PS
+SCSI_In__1__SHIFT EQU 4
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW
 SCSI_In__2__AG EQU CYREG_PRT6_AG
 SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX
 SCSI_In__2__BIE EQU CYREG_PRT6_BIE
@@ -1004,8 +1078,8 @@ SCSI_In__2__DR EQU CYREG_PRT6_DR
 SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS
 SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
 SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__2__MASK EQU 0x10
-SCSI_In__2__PC EQU CYREG_PRT6_PC4
+SCSI_In__2__MASK EQU 0x20
+SCSI_In__2__PC EQU CYREG_PRT6_PC5
 SCSI_In__2__PORT EQU 6
 SCSI_In__2__PRT EQU CYREG_PRT6_PRT
 SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
@@ -1016,7 +1090,7 @@ SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
 SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
 SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_In__2__PS EQU CYREG_PRT6_PS
-SCSI_In__2__SHIFT EQU 4
+SCSI_In__2__SHIFT EQU 5
 SCSI_In__2__SLW EQU CYREG_PRT6_SLW
 SCSI_In__3__AG EQU CYREG_PRT6_AG
 SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX
@@ -1031,8 +1105,8 @@ SCSI_In__3__DR EQU CYREG_PRT6_DR
 SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS
 SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
 SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__3__MASK EQU 0x20
-SCSI_In__3__PC EQU CYREG_PRT6_PC5
+SCSI_In__3__MASK EQU 0x80
+SCSI_In__3__PC EQU CYREG_PRT6_PC7
 SCSI_In__3__PORT EQU 6
 SCSI_In__3__PRT EQU CYREG_PRT6_PRT
 SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
@@ -1043,62 +1117,62 @@ SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
 SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
 SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_In__3__PS EQU CYREG_PRT6_PS
-SCSI_In__3__SHIFT EQU 5
+SCSI_In__3__SHIFT EQU 7
 SCSI_In__3__SLW EQU CYREG_PRT6_SLW
-SCSI_In__4__AG EQU CYREG_PRT6_AG
-SCSI_In__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__4__BIE EQU CYREG_PRT6_BIE
-SCSI_In__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__4__BYP EQU CYREG_PRT6_BYP
-SCSI_In__4__CTL EQU CYREG_PRT6_CTL
-SCSI_In__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__4__DR EQU CYREG_PRT6_DR
-SCSI_In__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__4__MASK EQU 0x40
-SCSI_In__4__PC EQU CYREG_PRT6_PC6
-SCSI_In__4__PORT EQU 6
-SCSI_In__4__PRT EQU CYREG_PRT6_PRT
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__4__PS EQU CYREG_PRT6_PS
-SCSI_In__4__SHIFT EQU 6
-SCSI_In__4__SLW EQU CYREG_PRT6_SLW
-SCSI_In__5__AG EQU CYREG_PRT6_AG
-SCSI_In__5__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__5__BIE EQU CYREG_PRT6_BIE
-SCSI_In__5__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__5__BYP EQU CYREG_PRT6_BYP
-SCSI_In__5__CTL EQU CYREG_PRT6_CTL
-SCSI_In__5__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__5__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__5__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__5__DR EQU CYREG_PRT6_DR
-SCSI_In__5__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__5__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__5__MASK EQU 0x80
-SCSI_In__5__PC EQU CYREG_PRT6_PC7
-SCSI_In__5__PORT EQU 6
-SCSI_In__5__PRT EQU CYREG_PRT6_PRT
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__5__PS EQU CYREG_PRT6_PS
-SCSI_In__5__SHIFT EQU 7
-SCSI_In__5__SLW EQU CYREG_PRT6_SLW
+SCSI_In__4__AG EQU CYREG_PRT5_AG
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__4__DR EQU CYREG_PRT5_DR
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__4__MASK EQU 0x01
+SCSI_In__4__PC EQU CYREG_PRT5_PC0
+SCSI_In__4__PORT EQU 5
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__4__PS EQU CYREG_PRT5_PS
+SCSI_In__4__SHIFT EQU 0
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW
+SCSI_In__5__AG EQU CYREG_PRT5_AG
+SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In__5__BIE EQU CYREG_PRT5_BIE
+SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In__5__BYP EQU CYREG_PRT5_BYP
+SCSI_In__5__CTL EQU CYREG_PRT5_CTL
+SCSI_In__5__DM0 EQU CYREG_PRT5_DM0
+SCSI_In__5__DM1 EQU CYREG_PRT5_DM1
+SCSI_In__5__DM2 EQU CYREG_PRT5_DM2
+SCSI_In__5__DR EQU CYREG_PRT5_DR
+SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In__5__MASK EQU 0x02
+SCSI_In__5__PC EQU CYREG_PRT5_PC1
+SCSI_In__5__PORT EQU 5
+SCSI_In__5__PRT EQU CYREG_PRT5_PRT
+SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In__5__PS EQU CYREG_PRT5_PS
+SCSI_In__5__SHIFT EQU 1
+SCSI_In__5__SLW EQU CYREG_PRT5_SLW
 SCSI_In__6__AG EQU CYREG_PRT5_AG
 SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX
 SCSI_In__6__BIE EQU CYREG_PRT5_BIE
@@ -1112,8 +1186,8 @@ SCSI_In__6__DR EQU CYREG_PRT5_DR
 SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS
 SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
 SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In__6__MASK EQU 0x01
-SCSI_In__6__PC EQU CYREG_PRT5_PC0
+SCSI_In__6__MASK EQU 0x04
+SCSI_In__6__PC EQU CYREG_PRT5_PC2
 SCSI_In__6__PORT EQU 5
 SCSI_In__6__PRT EQU CYREG_PRT5_PRT
 SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
@@ -1124,7 +1198,7 @@ SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
 SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
 SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
 SCSI_In__6__PS EQU CYREG_PRT5_PS
-SCSI_In__6__SHIFT EQU 0
+SCSI_In__6__SHIFT EQU 2
 SCSI_In__6__SLW EQU CYREG_PRT5_SLW
 SCSI_In__7__AG EQU CYREG_PRT5_AG
 SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX
@@ -1139,8 +1213,8 @@ SCSI_In__7__DR EQU CYREG_PRT5_DR
 SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS
 SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
 SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In__7__MASK EQU 0x02
-SCSI_In__7__PC EQU CYREG_PRT5_PC1
+SCSI_In__7__MASK EQU 0x08
+SCSI_In__7__PC EQU CYREG_PRT5_PC3
 SCSI_In__7__PORT EQU 5
 SCSI_In__7__PRT EQU CYREG_PRT5_PRT
 SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
@@ -1151,62 +1225,8 @@ SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
 SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
 SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
 SCSI_In__7__PS EQU CYREG_PRT5_PS
-SCSI_In__7__SHIFT EQU 1
+SCSI_In__7__SHIFT EQU 3
 SCSI_In__7__SLW EQU CYREG_PRT5_SLW
-SCSI_In__8__AG EQU CYREG_PRT5_AG
-SCSI_In__8__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In__8__BIE EQU CYREG_PRT5_BIE
-SCSI_In__8__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In__8__BYP EQU CYREG_PRT5_BYP
-SCSI_In__8__CTL EQU CYREG_PRT5_CTL
-SCSI_In__8__DM0 EQU CYREG_PRT5_DM0
-SCSI_In__8__DM1 EQU CYREG_PRT5_DM1
-SCSI_In__8__DM2 EQU CYREG_PRT5_DM2
-SCSI_In__8__DR EQU CYREG_PRT5_DR
-SCSI_In__8__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In__8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In__8__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In__8__MASK EQU 0x04
-SCSI_In__8__PC EQU CYREG_PRT5_PC2
-SCSI_In__8__PORT EQU 5
-SCSI_In__8__PRT EQU CYREG_PRT5_PRT
-SCSI_In__8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In__8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In__8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In__8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In__8__PS EQU CYREG_PRT5_PS
-SCSI_In__8__SHIFT EQU 2
-SCSI_In__8__SLW EQU CYREG_PRT5_SLW
-SCSI_In__9__AG EQU CYREG_PRT5_AG
-SCSI_In__9__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In__9__BIE EQU CYREG_PRT5_BIE
-SCSI_In__9__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In__9__BYP EQU CYREG_PRT5_BYP
-SCSI_In__9__CTL EQU CYREG_PRT5_CTL
-SCSI_In__9__DM0 EQU CYREG_PRT5_DM0
-SCSI_In__9__DM1 EQU CYREG_PRT5_DM1
-SCSI_In__9__DM2 EQU CYREG_PRT5_DM2
-SCSI_In__9__DR EQU CYREG_PRT5_DR
-SCSI_In__9__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In__9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In__9__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In__9__MASK EQU 0x08
-SCSI_In__9__PC EQU CYREG_PRT5_PC3
-SCSI_In__9__PORT EQU 5
-SCSI_In__9__PRT EQU CYREG_PRT5_PRT
-SCSI_In__9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In__9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In__9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In__9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In__9__PS EQU CYREG_PRT5_PS
-SCSI_In__9__SHIFT EQU 3
-SCSI_In__9__SLW EQU CYREG_PRT5_SLW
 SCSI_In__ACK__AG EQU CYREG_PRT6_AG
 SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX
 SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE
@@ -1234,32 +1254,6 @@ SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
 SCSI_In__ACK__PS EQU CYREG_PRT6_PS
 SCSI_In__ACK__SHIFT EQU 5
 SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_In__ATN__AG EQU CYREG_PRT12_AG
-SCSI_In__ATN__BIE EQU CYREG_PRT12_BIE
-SCSI_In__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In__ATN__BYP EQU CYREG_PRT12_BYP
-SCSI_In__ATN__DM0 EQU CYREG_PRT12_DM0
-SCSI_In__ATN__DM1 EQU CYREG_PRT12_DM1
-SCSI_In__ATN__DM2 EQU CYREG_PRT12_DM2
-SCSI_In__ATN__DR EQU CYREG_PRT12_DR
-SCSI_In__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In__ATN__MASK EQU 0x20
-SCSI_In__ATN__PC EQU CYREG_PRT12_PC5
-SCSI_In__ATN__PORT EQU 12
-SCSI_In__ATN__PRT EQU CYREG_PRT12_PRT
-SCSI_In__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In__ATN__PS EQU CYREG_PRT12_PS
-SCSI_In__ATN__SHIFT EQU 5
-SCSI_In__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In__ATN__SLW EQU CYREG_PRT12_SLW
 SCSI_In__BSY__AG EQU CYREG_PRT6_AG
 SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX
 SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE
@@ -1421,33 +1415,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
 SCSI_In__REQ__PS EQU CYREG_PRT5_PS
 SCSI_In__REQ__SHIFT EQU 2
 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW
-SCSI_In__RST__AG EQU CYREG_PRT6_AG
-SCSI_In__RST__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__RST__BIE EQU CYREG_PRT6_BIE
-SCSI_In__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__RST__BYP EQU CYREG_PRT6_BYP
-SCSI_In__RST__CTL EQU CYREG_PRT6_CTL
-SCSI_In__RST__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__RST__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__RST__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__RST__DR EQU CYREG_PRT6_DR
-SCSI_In__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__RST__MASK EQU 0x40
-SCSI_In__RST__PC EQU CYREG_PRT6_PC6
-SCSI_In__RST__PORT EQU 6
-SCSI_In__RST__PRT EQU CYREG_PRT6_PRT
-SCSI_In__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__RST__PS EQU CYREG_PRT6_PS
-SCSI_In__RST__SHIFT EQU 6
-SCSI_In__RST__SLW EQU CYREG_PRT6_SLW
 SCSI_In__SEL__AG EQU CYREG_PRT5_AG
 SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX
 SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE
@@ -1831,7 +1798,6 @@ CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
 CYDEV_DEBUGGING_ENABLE EQU 1
-CYDEV_DEBUGGING_REQXRES EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
 CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
@@ -1839,7 +1805,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x1000
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x00000003
+CYDEV_INTR_RISING EQU 0x00000001
 CYDEV_PROJ_TYPE EQU 0
 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
 CYDEV_PROJ_TYPE_LOADABLE EQU 2

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c

@@ -0,0 +1,230 @@
+/*******************************************************************************
+* FILENAME: cymetadata.c
+* 
+* PSoC Creator 3.0
+*
+* DESCRIPTION:
+* This file defines all extra memory spaces that need to be included.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+********************************************************************************/
+
+
+#include "cytypes.h"
+
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cyconfigecc"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cyconfigecc"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_meta_configecc[] = {
+    0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,
+    0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,
+    0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,
+    0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,
+    0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,
+    0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,
+    0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,
+    0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,
+    0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,
+    0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,
+    0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,
+    0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,
+    0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,
+    0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,
+    0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,
+    0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,
+    0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,
+    0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,
+    0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,
+    0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,
+    0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,
+    0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,
+    0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,
+    0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,
+    0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,
+    0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,
+    0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,
+    0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,
+    0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,
+    0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,
+    0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,
+    0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,
+    0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,
+    0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,
+    0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,
+    0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,
+    0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,
+    0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,
+    0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,
+    0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,
+    0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,
+    0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,
+    0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,
+    0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,
+    0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,
+    0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,
+    0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,
+    0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,
+    0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,
+    0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,
+    0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,
+    0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,
+    0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,
+    0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,
+    0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,
+    0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,
+    0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,
+    0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,
+    0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,
+    0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,
+    0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,
+    0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,
+    0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,
+    0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,
+    0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,
+    0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,
+    0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,
+    0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,
+    0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,
+    0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,
+    0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,
+    0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,
+    0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,
+    0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,
+    0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,
+    0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,
+    0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,
+    0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,
+    0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,
+    0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,
+    0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,
+    0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,
+    0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,
+    0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,
+    0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,
+    0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,
+    0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,
+    0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,
+    0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,
+    0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,
+    0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,
+    0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,
+    0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,
+    0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,
+    0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,
+    0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,
+    0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,
+    0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,
+    0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,
+    0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,
+    0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,
+    0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,
+    0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,
+    0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,
+    0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,
+    0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,
+    0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,
+    0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,
+    0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+    0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,
+    0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,
+    0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,
+    0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,
+    0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x01u
+};
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cycustnvl"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cycustnvl"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_meta_custnvl[] = {
+    0x00u, 0x00u, 0x40u, 0x05u
+};
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cywolatch"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cywolatch"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_meta_wonvl[] = {
+    0xBCu, 0x90u, 0xACu, 0xAFu
+};
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cyflashprotect"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cyflashprotect"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_meta_flashprotect[] = {
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u
+};
+
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cymeta"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cymeta"
+#else
+#error "Unsupported toolchain"
+#endif
+const uint8 cy_metadata[] = {
+    0x00u, 0x01u, 0x2Eu, 0x12u, 0xF0u, 0x69u, 0x00u, 0x01u,
+    0x00u, 0x00u, 0x00u, 0x00u
+};

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cypins.h
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   This file contains the function prototypes and constants used for port/pin

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cytypes.h
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *  CyTypes provides register access macros and approved types for use in
@@ -38,6 +38,12 @@
 #include "cyfitter.h"
 
 
+#if defined( __ICCARM__ )
+    /* Suppress warning for multiple volatile variables in an expression. */
+    /* This is common in component code and the usage is not order dependent. */
+    #pragma diag_suppress=Pa082
+#endif  /* defined( __ICCARM__ ) */
+
 
 /***************************************
 * Conditional Compilation Parameters
@@ -55,12 +61,21 @@
 /*******************************************************************************
 * MEMBER encodes both the family and the detailed architecture
 *******************************************************************************/
+#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#else
+    #define CY_PSOC4D   (0u != 0u)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#endif  /* CYDEV_CHIP_MEMBER_4D */
+
 #define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
 #ifdef CYDEV_CHIP_MEMBER_5B
-    #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
 #else
-    #define CY_PSOC5LP 0
-#endif
+    #define CY_PSOC5LP  (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_5B */
 
 
 /*******************************************************************************
@@ -103,23 +118,23 @@ typedef          char   char8;
     * endian conversion. These functions should be called through the
     * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros.
     ***************************************************************************/
-    extern uint8  cyread8       (volatile void far *addr);
+    extern uint8  cyread8       (const volatile void far *addr);
     extern void   cywrite8      (volatile void far *addr, uint8 value);
 
-    extern uint16 cyread16      (volatile void far *addr);
-    extern uint16 cyread16_nodpx(volatile void far *addr);
+    extern uint16 cyread16      (const volatile void far *addr);
+    extern uint16 cyread16_nodpx(const volatile void far *addr);
 
     extern void   cywrite16      (volatile void far *addr, uint16 value);
     extern void   cywrite16_nodpx(volatile void far *addr, uint16 value);
 
-    extern uint32 cyread24      (volatile void far *addr);
-    extern uint32 cyread24_nodpx(volatile void far *addr);
+    extern uint32 cyread24      (const volatile void far *addr);
+    extern uint32 cyread24_nodpx(const volatile void far *addr);
 
     extern void   cywrite24      (volatile void far *addr, uint32 value);
     extern void   cywrite24_nodpx(volatile void far *addr, uint32 value);
 
-    extern uint32 cyread32      (volatile void far *addr);
-    extern uint32 cyread32_nodpx(volatile void far *addr);
+    extern uint32 cyread32      (const volatile void far *addr);
+    extern uint32 cyread32_nodpx(const volatile void far *addr);
 
     extern void   cywrite32      (volatile void far *addr, uint32 value);
     extern void   cywrite32_nodpx(volatile void far *addr, uint32 value);
@@ -144,9 +159,9 @@ typedef          char   char8;
 
     #if(CY_PSOC4)
 
-        extern uint32 CyGetReg24(uint32 volatile * addr);
+        extern uint32 CyGetReg24(uint32 const volatile * addr);
 
-    #endif  /*(CY_PSOC4)*/
+    #endif  /* (CY_PSOC4) */
 
 #endif  /* (CY_PSOC3) */
 
@@ -169,7 +184,7 @@ typedef          char   char8;
     #define CYSMALL     small
     #define CYXDATA     xdata
     #define XDATA       xdata
-    
+
     #define CY_NOINIT
 
 #else
@@ -187,14 +202,22 @@ typedef          char   char8;
     #define CYSMALL
     #define CYXDATA
     #define XDATA
-    
+
     #if defined(__ARMCC_VERSION)
-        #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
+        #define CY_NOINIT           __attribute__ ((section(".noinit"), zero_init))
+        #define CY_NORETURN         __attribute__ ((noreturn))
+        #define CY_SECTION(name)    __attribute__ ((section(name)))
+        #define CY_ALIGN(align)     __align(align)
     #elif defined (__GNUC__)
-        #define CY_NOINIT __attribute__ ((section(".noinit")))
+        #define CY_NOINIT           __attribute__ ((section(".noinit")))
+        #define CY_NORETURN         __attribute__ ((noreturn))
+        #define CY_SECTION(name)    __attribute__ ((section(name)))
+        #define CY_ALIGN(align)     __attribute__ ((aligned(align)))
+    #elif defined (__ICCARM__)
+        #define CY_NOINIT           __no_init
+        #define CY_NORETURN         __noreturn
     #endif  /* (__ARMCC_VERSION) */
 
-
 #endif  /* (CY_PSOC3) */
 
 
@@ -234,6 +257,10 @@ typedef volatile uint32 CYXDATA reg32;
     #define CY_ISR_PROTO(FuncName)  void FuncName (void)
     typedef void (* cyisraddress)(void);
 
+    #if defined (__ICCARM__)
+        typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
+    #endif  /* defined (__ICCARM__) */
+
 #endif  /* (CY_PSOC3) */
 
 
@@ -252,50 +279,50 @@ typedef volatile uint32 CYXDATA reg32;
 
     /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
 
-    #define CY_GET_REG8(addr)               (*((reg8 *)(addr)))
+    #define CY_GET_REG8(addr)               (*((const reg8 *)(addr)))
     #define CY_SET_REG8(addr, value)        (*((reg8 *)(addr))  = (uint8)(value))
 
-    #define CY_GET_REG16(addr)              cyread16_nodpx ((volatile void far *)(reg16 *)(addr))
+    #define CY_GET_REG16(addr)              cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr))
     #define CY_SET_REG16(addr, value)       cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)
 
-    #define CY_GET_REG24(addr)              cyread24_nodpx ((volatile void far *)(reg32 *)(addr))
+    #define CY_GET_REG24(addr)              cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr))
     #define CY_SET_REG24(addr, value)       cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)
 
-    #define CY_GET_REG32(addr)              cyread32_nodpx ((volatile void far *)(reg32 *)(addr))
+    #define CY_GET_REG32(addr)              cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr))
     #define CY_SET_REG32(addr, value)       cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)
 
     /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */
-    #define CY_GET_XTND_REG8(addr)          cyread8((volatile void far *)(addr))
+    #define CY_GET_XTND_REG8(addr)          cyread8((const volatile void far *)(addr))
     #define CY_SET_XTND_REG8(addr, value)   cywrite8((volatile void far *)(addr), value)
 
-    #define CY_GET_XTND_REG16(addr)         cyread16((volatile void far *)(addr))
+    #define CY_GET_XTND_REG16(addr)         cyread16((const volatile void far *)(addr))
     #define CY_SET_XTND_REG16(addr, value)  cywrite16((volatile void far *)(addr), value)
 
-    #define CY_GET_XTND_REG24(addr)         cyread24((volatile void far *)(addr))
+    #define CY_GET_XTND_REG24(addr)         cyread24((const volatile void far *)(addr))
     #define CY_SET_XTND_REG24(addr, value)  cywrite24((volatile void far *)(addr), value)
 
-    #define CY_GET_XTND_REG32(addr)         cyread32((volatile void far *)(addr))
+    #define CY_GET_XTND_REG32(addr)         cyread32((const volatile void far *)(addr))
     #define CY_SET_XTND_REG32(addr, value)  cywrite32((volatile void far *)(addr), value)
 
 #else
 
     /* 8, 16, 24 and 32-bit register access macros */
-    #define CY_GET_REG8(addr)               (*((reg8 *)(addr)))
+    #define CY_GET_REG8(addr)               (*((const reg8 *)(addr)))
     #define CY_SET_REG8(addr, value)        (*((reg8 *)(addr))  = (uint8)(value))
 
-    #define CY_GET_REG16(addr)              (*((reg16 *)(addr)))
+    #define CY_GET_REG16(addr)              (*((const reg16 *)(addr)))
     #define CY_SET_REG16(addr, value)       (*((reg16 *)(addr)) = (uint16)(value))
 
 
     #define CY_SET_REG24(addr, value)       CySetReg24((reg32 *) (addr), (value))
     #if(CY_PSOC4)
-        #define CY_GET_REG24(addr)          CyGetReg24((reg32 *) (addr))
+        #define CY_GET_REG24(addr)          CyGetReg24((const reg32 *) (addr))
     #else
-        #define CY_GET_REG24(addr)          (*((reg32 *)(addr)) & 0x00FFFFFFu)
+        #define CY_GET_REG24(addr)          (*((const reg32 *)(addr)) & 0x00FFFFFFu)
     #endif  /* (CY_PSOC4) */
 
 
-    #define CY_GET_REG32(addr)              (*((reg32 *)(addr)))
+    #define CY_GET_REG32(addr)              (*((const reg32 *)(addr)))
     #define CY_SET_REG32(addr, value)       (*((reg32 *)(addr)) = (uint32)(value))
 
 
@@ -321,11 +348,11 @@ typedef volatile uint32 CYXDATA reg32;
 *******************************************************************************/
 
 /* Get 8 bits of a 16 bit value. */
-#define LO8(x)                  ((uint8) (x))
-#define HI8(x)                  ((uint8) ((x) >> 8))
+#define LO8(x)                  ((uint8) ((x) & 0xFFu))
+#define HI8(x)                  ((uint8) ((uint16)(x) >> 8))
 
 /* Get 16 bits of a 32 bit value. */
-#define LO16(x)                 ((uint16) (x))
+#define LO16(x)                 ((uint16) ((x) & 0xFFFFu))
 #define HI16(x)                 ((uint16) ((uint32)(x) >> 16))
 
 /* Swap the byte ordering of a 32 bit value */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyutils.c
-* Version 3.40
+* Version 4.0
 *
 *  Description:
 *   CyUtils provides function to handle 24-bit value writes.
@@ -65,12 +65,12 @@
         *  No
         *
         ***************************************************************************/
-        uint32 CyGetReg24(uint32 volatile * addr)
+        uint32 CyGetReg24(uint32 const volatile * addr)
         {
-            uint8 volatile *tmpAddr;
+            uint8 const volatile *tmpAddr;
             uint32 value;
 
-            tmpAddr = (uint8 volatile *) addr;
+            tmpAddr = (uint8 const volatile *) addr;
 
             value  =  (uint32) tmpAddr[0u];
             value |= ((uint32) tmpAddr[1u] << 8u );

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
- * File Name: project.h  
- * PSoC Creator 2.2 Component Pack 6
+ * File Name: project.h
+ * PSoC Creator 3.0
  *
  *  Description:
  *  This file is automatically generated by PSoC Creator and should not 
@@ -18,6 +18,7 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 #include <cyfitter.h>
+#include <cydisabledsheets.h>
 #include <SCSI_In_DBx_aliases.h>
 #include <SCSI_In_DBx.h>
 #include <SCSI_Out_DBx_aliases.h>
@@ -50,6 +51,12 @@
 #include <SD_Init_Clk.h>
 #include <SD_Data_Clk.h>
 #include <SD_Clk_Ctl.h>
+#include <SCSI_RST_aliases.h>
+#include <SCSI_RST.h>
+#include <SCSI_ATN_aliases.h>
+#include <SCSI_ATN.h>
+#include <SCSI_RST_ISR.h>
+#include <SCSI_ATN_ISR.h>
 #include <core_cm3_psoc5.h>
 #include <core_cm3.h>
 #include <CyDmac.h>
@@ -59,6 +66,8 @@
 #include <cyPm.h>
 #include <CySpc.h>
 #include <cytypes.h>
+#include <core_cmFunc.h>
+#include <core_cmInstr.h>
 
 /*[]*/
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml

@@ -0,0 +1,208 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
+<PSoCCreatorIdeExport Version="1">
+  <Device Part="CY8C5268AXI-LP047" Processor="CortexM3" DeviceID="2E12F069" />
+  <Toolchains>
+    <Toolchain Name="ARM GCC" Selected="True">
+      <Tool Name="prebuild" Command="" Options="" />
+      <Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
+      <Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />
+      <Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
+      <Tool Name="postbuild" Command="" Options="" />
+    </Toolchain>
+    <Toolchain Name="ARM Keil MDK" Selected="False">
+      <Tool Name="prebuild" Command="" Options="" />
+      <Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
+      <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
+      <Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
+      <Tool Name="postbuild" Command="" Options="" />
+    </Toolchain>
+  </Toolchains>
+  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" Version="4.0" Type="Normal">
+    <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
+    <Datasheet>SCSI2SD_datasheet.pdf</Datasheet>
+    <LinkerFiles>
+      <LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
+      <LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
+      <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
+    </LinkerFiles>
+    <Folders>
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+          <File BuildType="BUILD" Toolchain="">.\main.c</File>
+          <File BuildType="BUILD" Toolchain="">.\loopback.c</File>
+          <File BuildType="BUILD" Toolchain="">.\blinky.c</File>
+          <File BuildType="BUILD" Toolchain="">.\bits.c</File>
+          <File BuildType="BUILD" Toolchain="">.\device.h</File>
+          <File BuildType="BUILD" Toolchain="">.\blinky.h</File>
+          <File BuildType="BUILD" Toolchain="">.\loopback.h</File>
+          <File BuildType="BUILD" Toolchain="">.\bits.h</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="BUILD" Path="\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.c</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\led.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sense.h</File>
+          <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.h</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv.inc</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu_trm.inc</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv_trm.inc</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.c</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1_aliases.h</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.c</File>
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+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ID_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Cm3Start.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3_psoc5.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3.h</File>
+          <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\CyBootAsmGnu.s</File>
+          <File BuildType="BUILD" Toolchain="ARM RVDS">.\Generated_Source\PSoC5\CyBootAsmRv.s</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cypins.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cytypes.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyutils.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmFunc.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmInstr.h</File>
+          <File BuildType="BUILD" Toolchain="IAR EWARM">.\Generated_Source\PSoC5\CyBootAsmIar.s</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\project.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Init_Clk.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Init_Clk.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Clk_Ctl.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Clk_Ctl.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PM.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_INT.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PVT.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar.inc</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar_trm.inc</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitteriar.inc</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydisabledsheets.h</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
+          <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+          <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+          <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
+          <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
+        </Files>
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\codegentemp">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\DP8051">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\CortexM0">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+      <Folder BuildType="EXCLUDE" Path=".\CortexM3">
+        <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" />
+      </Folder>
+    </Folders>
+  </Project>
+</PSoCCreatorIdeExport>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -1,33 +0,0 @@
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-  <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
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-  <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -1055,7 +1055,7 @@
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-<Hidden v="False" />
+<Hidden v="True" />
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 <build_action v="ARM_C_FILE" />
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+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="core_cmFunc.h" persistent=".\Generated_Source\PSoC5\core_cmFunc.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
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+<Hidden v="False" />
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+<build_action v="NONE" />
+<PropertyDeltas />
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+<Hidden v="False" />
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+<PropertyDeltas />
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+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="CyBootAsmIar.s" persistent=".\Generated_Source\PSoC5\CyBootAsmIar.s">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="IAR_ASM_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
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 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
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 <filters />
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+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
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+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
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-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Pedantic Compilation" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Difference Tables" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
@@ -1495,7 +1659,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Difference Tables" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
@@ -1506,6 +1669,7 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
@@ -1527,7 +1691,6 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Difference Tables" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
@@ -1538,10 +1701,75 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Generate Map File" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Remove Unused Functions" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 </name>
 </platform>
 </platforms>
@@ -1549,9 +1777,9 @@
 <project_current_processor v="CortexM3" />
 <component_generation v="PSoC Creator  2.2 Component Pack 6" />
 <last_selected_tab v="Cypress" />
-<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , CP6) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 2.2SP1) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
-<WriteAppVersionLastSavedWith v="2.2.0.572" />
-<WriteAppMarketingVersionLastSavedWith v=" 2.2 Component Pack 6" />
+<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
+<WriteAppVersionLastSavedWith v="3.0.0.1539" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.0" />
 <project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />
 <custom_data>
 <CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">
@@ -1573,7 +1801,8 @@
 <CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
 <ignored_deps />
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v3_40" />
+<boot_component v="cy_boot_v4_0" />
 <BootloaderTag hexFile="" elfFile="" />
+<current_generation v="0" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd

@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
-  <name>CY8C5268AXI_LP047</name>
-  <version>0.1</version>
-  <description>CY8C52LP</description>
-  <addressUnitBits>8</addressUnitBits>
-  <width>32</width>
-  <peripherals>
-    <peripheral>
-      <name>SD_Clk_Ctl</name>
-      <description>No description available</description>
-      <baseAddress>0x40006476</baseAddress>
-      <addressBlock>
-        <offset>0</offset>
-        <size>0x1</size>
-        <usage>registers</usage>
-      </addressBlock>
-      <registers>
-        <register>
-          <name>SD_Clk_Ctl_CONTROL_REG</name>
-          <description>No description available</description>
-          <addressOffset>0x0</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0</resetMask>
-        </register>
-      </registers>
-    </peripheral>
-  </peripherals>
-</device>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvproj

@@ -697,6 +697,56 @@
               <FileType>5</FileType>
               <FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
             </File>
+            <File>
+              <FileName>SCSI_RST_aliases.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_aliases.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST_ISR.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST_ISR.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_ISR.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_ISR.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
+            </File>
           </Files>
         </Group>
       </Groups>
@@ -1396,6 +1446,56 @@
               <FileType>5</FileType>
               <FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
             </File>
+            <File>
+              <FileName>SCSI_RST_aliases.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_aliases.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST_ISR.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_RST_ISR.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_ISR.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
+            </File>
+            <File>
+              <FileName>SCSI_ATN_ISR.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
+            </File>
           </Files>
         </Group>
       </Groups>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c

@@ -30,9 +30,14 @@ static const uint8 StandardResponse[] =
 31, // standard length
 0, 0, //Reserved
 0, // We don't support anything at all
+/* TODO testing Apple Drive Setup. Make configurable!
 'c','o','d','e','s','r','c',' ',
 'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',
 '2','.','0','a'
+*/
+' ','S','E','A','G','A','T','E',
+' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','S','T','2','2','5','N',
+'1','.','0',' '
 };
 
 static const uint8 SupportedVitalPages[] =

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/loopback.c

@@ -16,6 +16,7 @@
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
 
 #include "loopback.h"
+#include "scsi.h"
 #include "device.h"
 
 // Return true if all inputs are un-asserted (1)
@@ -27,10 +28,10 @@ static int test_initial_inputs(void)
 	int result =
 		(dbx == 0xFF) &&
 		CyPins_ReadPin(SCSI_In_DBP) &&
-		CyPins_ReadPin(SCSI_In_ATN) &&
+		CyPins_ReadPin(SCSI_ATN_INT) &&
 		CyPins_ReadPin(SCSI_In_BSY)	&&
 		CyPins_ReadPin(SCSI_In_ACK) &&
-		CyPins_ReadPin(SCSI_In_RST) &&
+		CyPins_ReadPin(SCSI_RST_INT) &&
 		CyPins_ReadPin(SCSI_In_MSG) &&
 		CyPins_ReadPin(SCSI_In_SEL) &&
 		CyPins_ReadPin(SCSI_In_CD) &&
@@ -86,6 +87,25 @@ static int test_data_10MHz(void)
 	return result;
 }
 
+static int test_ATN_interrupt(void)
+{
+	int result = 1;
+	int i;
+	
+	scsiDev.atnFlag = 0;
+	for (i = 0; i < 100 && result; ++i)
+	{
+		// We write using Active High
+		CyPins_SetPin(SCSI_Out_ATN);
+		CyDelayCycles(2);
+		result &= scsiDev.atnFlag == 1;
+		scsiDev.atnFlag = 0;
+		CyPins_ClearPin(SCSI_Out_ATN);
+		result &= scsiDev.atnFlag == 0;
+	}
+	return result;
+}
+
 static void test_error(void)
 {
 	// Toggle LED.
@@ -111,7 +131,10 @@ static void test_success(void)
 }
 void scsi2sd_test_loopback(void)
 {
-	if (!test_initial_inputs() || !test_data_lines() || !test_data_10MHz())
+	if (!test_initial_inputs() ||
+		!test_data_lines() ||
+		!test_data_10MHz() ||
+		!test_ATN_interrupt())
 	{
 		test_error();
 	}

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/main.c

@@ -17,25 +17,30 @@
 
 #include "device.h"
 // #include "blinky.h"
-// #include "loopback.h"
+#include "loopback.h"
 #include "scsi.h"
+#include "scsiPhy.h"
 #include "disk.h"
 #include "led.h"
 
 const char* Notice = "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>";
 
-void main()
+int main()
 {
 	// scsi2sd_test_blinky(); // Initial test. Will not return.
-	// scsi2sd_test_loopback(); // Second test. Will not return.
 	ledOff();
 
-	/* Uncomment this line to enable global interrupts. */
-	// MM: Try to avoid interrupts completely, as it will screw with our
-	// timing.
-	 CyGlobalIntEnable;
-	 
-	// TODO insert any initialisation code here.
+	// Enable global interrupts.
+	// Needed for RST and ATN interrupt handlers.
+	CyGlobalIntEnable;
+
+	// Set interrupt handlers.
+	scsiPhyInit();
+	
+	// Loopback test requires the interrupt handers.
+	// Will not return if uncommented.
+	// scsi2sd_test_loopback();
+	
 	scsiInit(0, 1); // ID 0 is mac boot disk
 	scsiDiskInit();
 
@@ -49,5 +54,6 @@ void main()
 		scsiPoll();
 		scsiDiskPoll();
 	}
+	return 0;
 }
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/mode.c

@@ -93,6 +93,17 @@ static const uint8 ControlModePage[] =
 0x00, 0x00 // AEN holdoff period.
 };
 
+// Allow Apple 68k Drive Setup to format this drive.
+// Code
+// TODO make this string configurable.
+static const uint8 AppleVendorPage[] =
+{
+0x30, // Page code
+28, // Page length
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+'A','P','P','L','E',' ','C','O','M','P','U','T','E','R',',',' ','I','N','C','.'
+};
+
 static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen)
 {
 	memcpy(&scsiDev.data[dataIdx], pageData, pageLen);
@@ -235,6 +246,11 @@ static void doModeSense(
 			idx += sizeof(ControlModePage);
 			break;
 
+		case 0x30:
+			pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));
+			idx += sizeof(AppleVendorPage);
+			break;
+			
 		default:
 			// Unknown Page Code
 			pageFound = 0;

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsi.c

@@ -66,9 +66,6 @@ static void process_MessageIn()
 	scsiEnterPhase(MESSAGE_IN);
 	scsiWrite(scsiDev.msgIn);
 
-	scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
-
-
 	if (scsiDev.atnFlag)
 	{
 		// If there was a parity error, we go
@@ -122,9 +119,6 @@ static void process_DataIn()
 	{
 		scsiWrite(scsiDev.data[scsiDev.dataPtr]);
 		++scsiDev.dataPtr;
-
-		// scsiWrite will update resetFlag.
-		scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
 	}
 
 	if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
@@ -157,9 +151,6 @@ static void process_DataOut()
 			break;
 		}
 		++scsiDev.dataPtr;
-
-		// scsiRead will update resetFlag.
-		scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
 	}
 
 	if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
@@ -268,8 +259,6 @@ static void process_Command()
 	{
 		enter_Status(GOOD);
 	}
-
-	scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
 }
 
 static void doReserveRelease()
@@ -342,8 +331,6 @@ static void scsiReset()
 	SCSI_ClearPin(SCSI_Out_CD);
 	SCSI_ClearPin(SCSI_Out_IO);
 
-	scsiDev.resetFlag = 0;
-	scsiDev.atnFlag = 0;
 	scsiDev.parityError = 0;
 	scsiDev.phase = BUS_FREE;
 	
@@ -365,14 +352,18 @@ static void scsiReset()
 	do
 	{
 		CyDelay(10); // 10ms.
-		reset = SCSI_ReadPin(SCSI_In_RST);
+		reset = SCSI_ReadPin(SCSI_RST_INT);
 	} while (reset);
+	
+	scsiDev.resetFlag = 0;
+	scsiDev.atnFlag = 0;	
 }
 
 static void enter_SelectionPhase()
 {
-
-	scsiDev.atnFlag = 0;
+	// Ignore stale versions of this flag, but ensure we know the
+	// current value if the flag is still set.
+	scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);
 	scsiDev.parityError = 0;
 	scsiDev.dataPtr = 0;
 	scsiDev.savedDataPtr = 0;
@@ -385,7 +376,6 @@ static void process_SelectionPhase()
 	uint8 mask = ~SCSI_In_DBx_Read();
 	int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));
 
-	scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
 	int sel = SCSI_ReadPin(SCSI_In_SEL);
 	int bsy = SCSI_ReadPin(SCSI_In_BSY);
 	if (!bsy && sel &&
@@ -402,16 +392,12 @@ static void process_SelectionPhase()
 		ledOn();
 
 		// Wait until the end of the selection phase.
-		// Keep checking the ATN flag, as the initiator may assert it at any
-		// time before releasing SEL.
 		while (!scsiDev.resetFlag)
 		{
-			scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
 			if (!SCSI_ReadPin(SCSI_In_SEL))
 			{
 				break;
 			}
-			scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
 		}
 
 		// Save our initiator now that we're no longer in a time-critical
@@ -434,15 +420,13 @@ static void process_SelectionPhase()
 	{
 		scsiDev.phase = BUS_BUSY;
 	}
-
-	scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);
 }
 
 static void process_MessageOut()
 {
-	scsiDev.atnFlag = 0;
 	scsiEnterPhase(MESSAGE_OUT);
 
+	scsiDev.atnFlag = 0;
 	scsiDev.parityError = 0;
 	scsiDev.msgOut = scsiRead();
 
@@ -451,10 +435,9 @@ static void process_MessageOut()
 		// Skip the remaining message bytes, and then start the MESSAGE_OUT
 		// phase again from the start. The initiator will re-send the
 		// same set of messages.
-		while (SCSI_ReadPin(SCSI_In_ATN) && !scsiDev.resetFlag)
+		while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)
 		{
 			scsiRead();
-			scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);
 		}
 
 		// Go-back and try the message again.
@@ -559,15 +542,30 @@ static void process_MessageOut()
 	{
 		enter_MessageIn(MSG_REJECT);
 	}
-
-	// atnFlag will be forced to 1 if there was a parity error.
-	scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
+	
+	// Re-check the ATN flag. We won't get another interrupt if
+	// it stays asserted.
+	scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);
 }
 
 
+// TODO remove.
+// This is a hack until I work out why the ATN ISR isn't
+// running when it should.
+static int atnErrCount = 0;
+static void checkATN()
+{
+	int atn = SCSI_ReadPin(SCSI_ATN_INT);
+	if (atn && !scsiDev.atnFlag)
+	{
+		atnErrCount++;
+		scsiDev.atnFlag = 1;
+	}
+}
+
 void scsiPoll(void)
 {
-	if (scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST))
+	if (scsiDev.resetFlag)
 	{
 		scsiReset();
 	}
@@ -607,6 +605,7 @@ void scsiPoll(void)
 	break;
 
 	case COMMAND:
+		checkATN();
 		if (scsiDev.atnFlag)
 		{
 			process_MessageOut();
@@ -618,6 +617,7 @@ void scsiPoll(void)
 	break;
 
 	case DATA_IN:
+		checkATN();
 		if (scsiDev.atnFlag)
 		{
 			process_MessageOut();
@@ -629,6 +629,7 @@ void scsiPoll(void)
 	break;
 
 	case DATA_OUT:
+		checkATN();
 		if (scsiDev.atnFlag)
 		{
 			process_MessageOut();
@@ -636,10 +637,11 @@ void scsiPoll(void)
 		else
 		{
 			process_DataOut();
-		}	
+		}
 	break;
 
 	case STATUS:
+		checkATN();
 		if (scsiDev.atnFlag)
 		{
 			process_MessageOut();
@@ -651,6 +653,7 @@ void scsiPoll(void)
 	break;
 
 	case MESSAGE_IN:
+		checkATN();
 		if (scsiDev.atnFlag)
 		{
 			process_MessageOut();

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsi.h

@@ -70,10 +70,10 @@ typedef struct
 
 	// Set to true (1) if the ATN flag was set, and we need to
 	// enter the MESSAGE_OUT phase.
-	int atnFlag;
+	volatile int atnFlag;
 
 	// Set to true (1) if the RST flag was set.
-	int resetFlag;
+	volatile int resetFlag;
 
 	// Set to true (1) if a parity error was observed.
 	int parityError;

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c

@@ -20,43 +20,41 @@
 #include "scsiPhy.h"
 #include "bits.h"
 
+CY_ISR_PROTO(scsiResetISR);
+CY_ISR(scsiResetISR)
+{
+	scsiDev.resetFlag = 1;
+	SCSI_RST_ClearInterrupt();
+}
+
+CY_ISR_PROTO(scsiAttentionISR);
+CY_ISR(scsiAttentionISR)
+{
+	scsiDev.atnFlag = 1;
+	// Not needed when using pin value for interrupt SCSI_ATN_ClearInterrupt();
+}
+
 // Spins until the SCSI pin is true, or the reset flag is set.
-static void waitForPinTrue(int pin)
+static inline void waitForPinTrue(int pin)
 {
-	while (!scsiDev.resetFlag)
+	int finished = SCSI_ReadPin(pin);
+	while (!finished && !scsiDev.resetFlag)
 	{
-		// TODO put some hardware gates in front of the RST pin, and store
-		// the state in a register. The minimum "Reset hold time" is 25us, which
-		// we can easily satisfy within this loop, but perhaps hard to satisfy
-		// if we don't call this function often.
-		scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
-
-		if (SCSI_ReadPin(pin))
-		{
-			break;
-		}
+		finished = SCSI_ReadPin(pin);
 	}
 }
 
 // Spins until the SCSI pin is true, or the reset flag is set.
-static void waitForPinFalse(int pin)
+static inline void waitForPinFalse(int pin)
 {
-	while (!scsiDev.resetFlag)
+	int finished = !SCSI_ReadPin(pin);
+	while (!finished && !scsiDev.resetFlag)
 	{
-		// TODO put some hardware gates in front of the RST pin, and store
-		// the state in a register. The minimum "Reset hold time" is 25us, which
-		// we can easily satisfy within this loop, but perhaps hard to satisfy
-		// if we don't call this function often.
-		scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
-
-		if (!SCSI_ReadPin(pin))
-		{
-			break;
-		}
+		finished = !SCSI_ReadPin(pin);
 	}
 }
 
-static void deskewDelay(void)
+static inline void deskewDelay(void)
 {
 	// Delay for deskew + cable skew. total 55 nanoseconds.
 	// Assumes 66MHz.
@@ -148,3 +146,13 @@ void scsiEnterPhase(int phase)
 	busSettleDelay();
 }
 
+void scsiPhyInit()
+{
+	SCSI_RST_ISR_StartEx(scsiResetISR);
+	SCSI_ATN_ISR_StartEx(scsiAttentionISR);
+	
+	// Interrupts may have already been directed to the (empty)
+	// standard ISR generated by PSoC Creator.
+	SCSI_RST_ClearInterrupt();
+	// Not needed for pin level interrupt SCSI_ATN_ClearInterrupt();	
+}

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h

@@ -30,6 +30,7 @@
 // Contains the odd-parity flag for a given 8-bit value.
 extern const uint8 Lookup_OddParity[256];
 
+void scsiPhyInit();
 uint8 scsiRead(void);
 void scsiWrite(uint8 value);
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/sd.c

@@ -52,7 +52,7 @@ static uint8 sdSpiByte(uint8 value)
 	return SDCard_ReadRxData();
 }
 
-static void sdSendCommand(uint8 cmd, uint32 param)
+static void sdSendCRCCommand(uint8 cmd, uint32 param)
 {
 	uint8 send[6];
 
@@ -69,6 +69,23 @@ static void sdSendCommand(uint8 cmd, uint32 param)
 	}
 }
 
+static void sdSendCommand(uint8 cmd, uint32 param)
+{
+	uint8 send[6];
+
+	send[0] = cmd | 0x40;
+	send[1] = param >> 24;
+	send[2] = param >> 16;
+	send[3] = param >> 8;
+	send[4] = param;
+	send[5] = 0;
+
+	for(cmd = 0; cmd < sizeof(send); cmd++)
+	{
+		sdSpiByte(send[cmd]);
+	}
+}
+
 static uint8 sdReadResp()
 {
 	uint8 v;
@@ -100,6 +117,14 @@ static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)
 	return sdReadResp();
 }
 
+static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)
+{
+	SDCard_ClearRxBuffer();
+	sdSpiByte(0xFF);
+	sdSendCRCCommand(cmd, param);
+	return sdReadResp();
+}
+
 
 void sdPrepareRead(int nextBlockOffset)
 {
@@ -197,12 +222,12 @@ int sdWriteSector()
 
 			while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))
 			{}
-		
+		}
+				
 			SDCard_ReadRxData();
 			SDCard_ReadRxData();
 			SDCard_ReadRxData();
 			SDCard_ReadRxData();
-		}
 
 		sdSpiByte(0x00); // CRC
 		sdSpiByte(0x00); // CRC
@@ -260,7 +285,7 @@ static int sendIfCond()
 
 	do
 	{
-		uint8 status = sdCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
+		uint8 status = sdCRCCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
 
 		if (status == SD_R1_IDLE)
 		{
@@ -294,9 +319,9 @@ static int sdOpCond()
 	{
 		CyDelay(33); // Spec says to retry for 1 second.
 
-		sdCommandAndResponse(SD_APP_CMD, 0);
+		sdCRCCommandAndResponse(SD_APP_CMD, 0);
 		// Host Capacity Support = 1 (SDHC/SDXC supported)
-		status = sdCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
+		status = sdCRCCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
 	} while ((status != 0) && (--retries > 0));
 
 	return retries > 0;
@@ -304,7 +329,7 @@ static int sdOpCond()
 
 static int sdReadOCR()
 {
-	uint8 status = sdCommandAndResponse(SD_READ_OCR, 0);
+	uint8 status = sdCRCCommandAndResponse(SD_READ_OCR, 0);
 	if(status){goto bad;}
 
 	uint8 buf[4];
@@ -323,7 +348,7 @@ bad:
 
 static int sdReadCSD()
 {
-	uint8 status = sdCommandAndResponse(SD_SEND_CSD, 0);
+	uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);
 	if(status){goto bad;}
 	status = sdWaitResp();
 	if (status != 0xFE) { goto bad; }
@@ -389,7 +414,7 @@ int sdInit()
 	SD_CS_Write(0); // Set CS active (active low)
 	CyDelayUs(1);
 
-	uint8 v = sdCommandAndResponse(SD_GO_IDLE_STATE, 0);
+	uint8 v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);
 	if(v != 1){goto bad;}
 
 	if (!sendIfCond()) goto bad; // Sets V1 or V2 flag
@@ -398,9 +423,9 @@ int sdInit()
 
 	// This command will be ignored if sdDev.ccs is set.
 	// SDHC and SDXC are always 512bytes.
-	v = sdCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size
+	v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size
 	if(v){goto bad;}
-	v = sdCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
+	v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
 	if(v){goto bad;}
 
 	// now set the sd card up for full speed