Adjust SCSI REQ assertion timing

With the RP2350 at 150MHz, one clock cycle is 6.67 ns (150MHz) => delay 8.25 clocks or 9 clocks
.define REQ_DLY 9. Thanks, @morio

lib/ZuluSCSI_platform_RP2350/scsi_accel_target_Pico.pio

@@ -30,8 +30,8 @@
 
 ; Delay from data setup to REQ assertion.
 ; deskew delay + cable skew delay = 55 ns minimum
-; One clock cycle is 8 ns => delay 7 clocks
-.define REQ_DLY 7
+; One clock cycle is 6.67 ns (150MHz) => delay 8.25 clocks or 9 clocks
+.define REQ_DLY 9
 
 ; Adds parity to data that is to be written to SCSI
 ; This works by generating addresses for DMA to fetch data from.
@@ -121,4 +121,4 @@ parity_valid:
     push block                ; Push the data to RX fifo
     out x, 24                 ; Take the parity valid bit, and the rest of 32-bit word
     jmp x-- parity_valid      ; If parity valid bit is 1, repeat from start
-    irq set 0                 ; Parity error, set interrupt flag
+    irq set 0                 ; Parity error, set interrupt flag

lib/ZuluSCSI_platform_RP2350/scsi_accel_target_Pico.pio.h

@@ -49,7 +49,7 @@ static const uint16_t scsi_accel_async_write_program_instructions[] = {
             //     .wrap_target
     0x90e0, //  0: pull   ifempty block   side 1     
     0x7009, //  1: out    pins, 9         side 1     
-    0x7577, //  2: out    null, 23        side 1 [5] 
+    0x7777, //  2: out    null, 23        side 1 [7] 
     0x309a, //  3: wait   1 gpio, 26      side 1     
     0x201a, //  4: wait   0 gpio, 26      side 0     
             //     .wrap
@@ -222,4 +222,3 @@ static inline pio_sm_config scsi_read_parity_program_get_default_config(uint off
     return c;
 }
 #endif
-