Add all phase bits to a control register for atomic phase changes.

Slowed the SCSI bus clock to 30MHz to meet timing constraints. No
overall change in performance.

lib/SCSI2SD/CHANGELOG

@@ -1,3 +1,8 @@
+201404??		3.4
+	- Fix to ensure SCSI phase bits are set atomically.
+	- Decreased (unused) heap and stack sizes to prepare for a memory
+	write cache
+
 20140416		3.3
 	- Fix to SCSI Reset handling to avoid lockups
 	- Bug fixes to improve standards compatibility

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf

@@ -9,8 +9,8 @@ define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
 define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
 /*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x4000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__   = 0x0256;
 /**** End of ICF editor section. ###ICF###*/
 
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat

@@ -112,11 +112,11 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
         .ANY (+RW, +ZI)
     }
 
-    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0256 - 0x2000) EMPTY 0x0256
     {
     }
 
-    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000
     {
     }
 }

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c

@@ -0,0 +1,521 @@
+/*******************************************************************************
+* File Name: SCSI_CLK.c
+* Version 2.10
+*
+*  Description:
+*   This file provides the source code to the API for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SCSI_CLK.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD              (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2           (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK               (0x80u)
+#define CLK_DIST_DMASK           (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK           (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE   (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Start
+********************************************************************************
+*
+* Summary:
+*  Starts the clock. Note that on startup, clocks may be already running if the
+*  "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Start(void) 
+{
+    /* Set the bit to enable the clock. */
+    SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
+	SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Stop
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and returns immediately. This API does not require the
+*  source clock to be running but may return before the hardware is actually
+*  disabled. If the settings of the clock are changed after calling this
+*  function, the clock may glitch when it is started. To avoid the clock
+*  glitch, use the StopBlock function.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_Stop(void) 
+{
+    /* Clear the bit to disable the clock. */
+    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+	SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StopBlock
+********************************************************************************
+*
+* Summary:
+*  Stops the clock and waits for the hardware to actually be disabled before
+*  returning. This ensures that the clock is never truncated (high part of the
+*  cycle will terminate before the clock is disabled and the API returns).
+*  Note that the source clock must be running or this API will never return as
+*  a stopped clock cannot be disabled.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StopBlock(void) 
+{
+    if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+    {
+#if HAS_CLKDIST_LD_DISABLE
+        uint16 oldDivider;
+
+        CLK_DIST_LD = 0u;
+
+        /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+        CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_DMASK = 0x00u;
+#else
+        CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+        CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+
+        /* Clear mask of bus clock. */
+        CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+        oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
+        CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+        CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+        /* Wait for clock to be disabled */
+        while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+        /* Clear the bit to disable the clock. */
+        SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+        /* Clear the disable bit */
+        CLK_DIST_LD = 0x00u;
+        CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+    }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StandbyPower
+********************************************************************************
+*
+* Summary:
+*  Sets whether the clock is active in standby mode.
+*
+* Parameters:
+*  state:  0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_StandbyPower(uint8 state) 
+{
+    if(state == 0u)
+    {
+        SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+    }
+    else
+    {
+        SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Modifies the clock divider and, thus, the frequency. When the clock divider
+*  register is set to zero or changed from zero, the clock will be temporarily
+*  disabled in order to change the SSS mode bit. If the clock is enabled when
+*  SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+*  clkDivider:  Divider register value (0-65,535). This value is NOT the
+*    divider; the clock hardware divides by clkDivider plus one. For example,
+*    to divide the clock by 2, this parameter should be set to 1.
+*  restart:  If nonzero, restarts the clock divider: the current clock cycle
+*   will be truncated and the new divide value will take effect immediately. If
+*   zero, the new divide value will take effect at the end of the current clock
+*   cycle.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+                                
+{
+    uint8 enabled;
+
+    uint8 currSrc = SCSI_CLK_GetSourceRegister();
+    uint16 oldDivider = SCSI_CLK_GetDividerRegister();
+
+    if (clkDivider != oldDivider)
+    {
+        enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
+
+        if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+        {
+            /* Moving to/from SSS requires correct ordering to prevent halting the clock    */
+            if (oldDivider == 0u)
+            {
+                /* Moving away from SSS, set the divider first so when SSS is cleared we    */
+                /* don't halt the clock.  Using the shadow load isn't required as the       */
+                /* divider is ignored while SSS is set.                                     */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+                SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+            }
+            else
+            {
+                /* Moving to SSS, set SSS which then ignores the divider and we can set     */
+                /* it without bothering with the shadow load.                               */
+                SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+            }
+        }
+        else
+        {
+			
+            if (enabled != 0u)
+            {
+                CLK_DIST_LD = 0x00u;
+
+                /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+                CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_DMASK = 0x00u;
+#else
+                CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+                CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+                /* Clear mask of bus clock. */
+                CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+                /* If clock is currently enabled, disable it if async or going from N-to-1*/
+                if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+                {
+#if HAS_CLKDIST_LD_DISABLE
+                    CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+                    CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+                    /* Wait for clock to be disabled */
+                    while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+                    SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+                    /* Clear the disable bit */
+                    CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+                }
+            }
+
+            /* Load divide value. */
+            if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+            {
+                /* If the clock is still enabled, use the shadow registers */
+                CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+                CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+                while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+            }
+            else
+            {
+                /* If the clock is disabled, set the divider directly */
+                CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+				SCSI_CLK_CLKEN |= enabled;
+            }
+        }
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock divider register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Divide value of the clock minus 1. For example, if the clock is set to
+*  divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SCSI_CLK_GetDividerRegister(void) 
+{
+    return CY_GET_REG16(SCSI_CLK_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Sets flags that control the operating mode of the clock. This function only
+*  changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+*  To clear flags, use the ClearModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+*  Clears flags that control the operating mode of the clock. This function
+*  only changes flags from 1 to 0; flags that are already 0 will remain
+*  unchanged. To set flags, use the SetModeRegister function. The clock must be
+*  disabled before changing the mode.
+*
+* Parameters:
+*  clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+*   clkMode should be a set of the following optional bits or'ed together.
+*   - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+*                 occur when the divider count reaches half of the divide
+*                 value.
+*   - CYCLK_DUTY  Enable 50% duty cycle output. When enabled, the output clock
+*                 is asserted for approximately half of its period. When
+*                 disabled, the output clock is asserted for one period of the
+*                 source clock.
+*   - CYCLK_SYNC  Enable output synchronization to master clock. This should
+*                 be enabled for all synchronous clocks.
+*   See the Technical Reference Manual for details about setting the mode of
+*   the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) 
+{
+    SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetModeRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the clock mode register value.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Bit mask representing the enabled mode bits. See the SetModeRegister and
+*  ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetModeRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the input source of the clock. The clock must be disabled before
+*  changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+*  clkSource:  For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+*   following input sources:
+*   - CYCLK_SRC_SEL_SYNC_DIG
+*   - CYCLK_SRC_SEL_IMO
+*   - CYCLK_SRC_SEL_XTALM
+*   - CYCLK_SRC_SEL_ILO
+*   - CYCLK_SRC_SEL_PLL
+*   - CYCLK_SRC_SEL_XTALK
+*   - CYCLK_SRC_SEL_DSI_G
+*   - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+*   See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) 
+{
+    uint16 currDiv = SCSI_CLK_GetDividerRegister();
+    uint8 oldSrc = SCSI_CLK_GetSourceRegister();
+
+    if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+        (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching to Master and divider is 1, set SSS, which will output master, */
+        /* then set the source so we are consistent.                                */
+        SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+    else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && 
+            (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+    {
+        /* Switching from Master to not and divider is 1, set source, so we don't   */
+        /* lock when we clear SSS.                                                  */
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+        SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+    }
+    else
+    {
+        SCSI_CLK_MOD_SRC =
+            (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+*  Gets the input source of the clock.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetSourceRegister(void) 
+{
+    return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
+}
+
+
+#if defined(SCSI_CLK__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+*  Sets the phase delay of the analog clock. This function is only available
+*  for analog clocks. The clock must be disabled before changing the phase
+*  delay to avoid glitches.
+*
+* Parameters:
+*  clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+*   clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+*   disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 
+*   produces a 10ns delay.
+*
+* Returns:
+*  None
+*
+*******************************************************************************/
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) 
+{
+    SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetPhase
+********************************************************************************
+*
+* Summary:
+*  Gets the phase delay of the analog clock. This function is only available
+*  for analog clocks.
+*
+* Parameters:
+*  None
+*
+* Returns:
+*  Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetPhaseRegister(void) 
+{
+    return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
+}
+
+#endif /* SCSI_CLK__CFG3 */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h

@@ -0,0 +1,124 @@
+/*******************************************************************************
+* File Name: SCSI_CLK.h
+* Version 2.10
+*
+*  Description:
+*   Provides the function and constant definitions for the clock component.
+*
+*  Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SCSI_CLK_H)
+#define CY_CLOCK_SCSI_CLK_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+void SCSI_CLK_Start(void) ;
+void SCSI_CLK_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SCSI_CLK_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SCSI_CLK_StandbyPower(uint8 state) ;
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) 
+                                ;
+uint16 SCSI_CLK_GetDividerRegister(void) ;
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SCSI_CLK_GetModeRegister(void) ;
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
+uint8 SCSI_CLK_GetSourceRegister(void) ;
+#if defined(SCSI_CLK__CFG3)
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SCSI_CLK_GetPhaseRegister(void) ;
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#define SCSI_CLK_Enable()                       SCSI_CLK_Start()
+#define SCSI_CLK_Disable()                      SCSI_CLK_Stop()
+#define SCSI_CLK_SetDivider(clkDivider)         SCSI_CLK_SetDividerRegister(clkDivider, 1u)
+#define SCSI_CLK_SetDividerValue(clkDivider)    SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SCSI_CLK_SetMode(clkMode)               SCSI_CLK_SetModeRegister(clkMode)
+#define SCSI_CLK_SetSource(clkSource)           SCSI_CLK_SetSourceRegister(clkSource)
+#if defined(SCSI_CLK__CFG3)
+#define SCSI_CLK_SetPhase(clkPhase)             SCSI_CLK_SetPhaseRegister(clkPhase)
+#define SCSI_CLK_SetPhaseValue(clkPhase)        SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/***************************************
+*             Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKEN              (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
+#define SCSI_CLK_CLKEN_PTR          ((reg8 *) SCSI_CLK__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKSTBY            (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
+#define SCSI_CLK_CLKSTBY_PTR        ((reg8 *) SCSI_CLK__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SCSI_CLK_DIV_LSB            (* (reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_LSB_PTR        ((reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_PTR            ((reg16 *) SCSI_CLK__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SCSI_CLK_DIV_MSB            (* (reg8 *) SCSI_CLK__CFG1)
+#define SCSI_CLK_DIV_MSB_PTR        ((reg8 *) SCSI_CLK__CFG1)
+
+/* Mode and source configuration register */
+#define SCSI_CLK_MOD_SRC            (* (reg8 *) SCSI_CLK__CFG2)
+#define SCSI_CLK_MOD_SRC_PTR        ((reg8 *) SCSI_CLK__CFG2)
+
+#if defined(SCSI_CLK__CFG3)
+/* Analog clock phase configuration register */
+#define SCSI_CLK_PHASE              (* (reg8 *) SCSI_CLK__CFG3)
+#define SCSI_CLK_PHASE_PTR          ((reg8 *) SCSI_CLK__CFG3)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/**************************************
+*       Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SCSI_CLK_CLKEN_MASK         SCSI_CLK__PM_ACT_MSK
+#define SCSI_CLK_CLKSTBY_MASK       SCSI_CLK__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SCSI_CLK_SRC_SEL_MSK        SCSI_CLK__CFG2_SRC_SEL_MASK
+#define SCSI_CLK_MODE_MASK          (~(SCSI_CLK_SRC_SEL_MSK))
+
+#if defined(SCSI_CLK__CFG3)
+/* CFG3 phase mask */
+#define SCSI_CLK_PHASE_MASK         SCSI_CLK__CFG3_PHASE_DLY_MASK
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#endif /* CY_CLOCK_SCSI_CLK_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c → lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c

@@ -1,63 +1,63 @@
-/*******************************************************************************
-* File Name: SCSI_CTL_IO.c  
-* Version 1.70
-*
-* Description:
-*  This file contains API to enable firmware control of a Control Register.
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#include "SCSI_CTL_IO.h"
-
-#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_IO_Write
-********************************************************************************
-*
-* Summary:
-*  Write a byte to the Control Register.
-*
-* Parameters:
-*  control:  The value to be assigned to the Control Register.
-*
-* Return:
-*  None.
-*
-*******************************************************************************/
-void SCSI_CTL_IO_Write(uint8 control) 
-{
-    SCSI_CTL_IO_Control = control;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CTL_IO_Read
-********************************************************************************
-*
-* Summary:
-*  Reads the current value assigned to the Control Register.
-*
-* Parameters:
-*  None.
-*
-* Return:
-*  Returns the current value in the Control Register.
-*
-*******************************************************************************/
-uint8 SCSI_CTL_IO_Read(void) 
-{
-    return SCSI_CTL_IO_Control;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.c  
+* Version 1.70
+*
+* Description:
+*  This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Write
+********************************************************************************
+*
+* Summary:
+*  Write a byte to the Control Register.
+*
+* Parameters:
+*  control:  The value to be assigned to the Control Register.
+*
+* Return:
+*  None.
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Write(uint8 control) 
+{
+    SCSI_CTL_PHASE_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Read
+********************************************************************************
+*
+* Summary:
+*  Reads the current value assigned to the Control Register.
+*
+* Parameters:
+*  None.
+*
+* Return:
+*  Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_CTL_PHASE_Read(void) 
+{
+    return SCSI_CTL_PHASE_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h → lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h

@@ -1,42 +1,42 @@
-/*******************************************************************************
-* File Name: SCSI_CTL_IO.h  
-* Version 1.70
-*
-* Description:
-*  This file containts Control Register function prototypes and register defines
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions, 
-* disclaimers, and limitations in the end user license agreement accompanying 
-* the software package with which this file was provided.
-*******************************************************************************/
-
-#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */
-#define CY_CONTROL_REG_SCSI_CTL_IO_H
-
-#include "cytypes.h"
-
-
-/***************************************
-*         Function Prototypes 
-***************************************/
-
-void    SCSI_CTL_IO_Write(uint8 control) ;
-uint8   SCSI_CTL_IO_Read(void) ;
-
-
-/***************************************
-*            Registers        
-***************************************/
-
-/* Control Register */
-#define SCSI_CTL_IO_Control        (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
-#define SCSI_CTL_IO_Control_PTR    (  (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )
-
-#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */
-
-
-/* [] END OF FILE */
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE.h  
+* Version 1.70
+*
+* Description:
+*  This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions, 
+* disclaimers, and limitations in the end user license agreement accompanying 
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+#define CY_CONTROL_REG_SCSI_CTL_PHASE_H
+
+#include "cytypes.h"
+
+
+/***************************************
+*         Function Prototypes 
+***************************************/
+
+void    SCSI_CTL_PHASE_Write(uint8 control) ;
+uint8   SCSI_CTL_PHASE_Read(void) ;
+
+
+/***************************************
+*            Registers        
+***************************************/
+
+/* Control Register */
+#define SCSI_CTL_PHASE_Control        (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_CTL_PHASE_Control_PTR    (  (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */
+
+
+/* [] END OF FILE */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h

@@ -41,9 +41,9 @@
 #define SCSI_Out_BSY		SCSI_Out__BSY__PC
 #define SCSI_Out_ACK		SCSI_Out__ACK__PC
 #define SCSI_Out_RST		SCSI_Out__RST__PC
-#define SCSI_Out_MSG		SCSI_Out__MSG__PC
+#define SCSI_Out_MSG_raw		SCSI_Out__MSG_raw__PC
 #define SCSI_Out_SEL		SCSI_Out__SEL__PC
-#define SCSI_Out_CD		SCSI_Out__CD__PC
+#define SCSI_Out_CD_raw		SCSI_Out__CD_raw__PC
 #define SCSI_Out_REQ		SCSI_Out__REQ__PC
 #define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
 

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld

@@ -56,7 +56,7 @@ EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 PROVIDE(__cy_heap_start = _end);
 PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
 PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
-PROVIDE(__cy_heap_end = __cy_stack - 0x4000);
+PROVIDE(__cy_heap_end = __cy_stack - 0x2000);
 
 
 SECTIONS
@@ -217,14 +217,14 @@ SECTIONS
   .heap (NOLOAD) :
   {
     . = _end;
-    . += 0x1000;
+    . += 0x0256;
     __cy_heap_limit = .;
   } >ram
 
-  .stack (__cy_stack - 0x4000) (NOLOAD) :
+  .stack (__cy_stack - 0x2000) (NOLOAD) :
   {
     __cy_stack_limit = .;
-    . += 0x4000;
+    . += 0x2000;
   } >ram
   
   /* Check if data + heap + stack exceeds RAM limit */

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -13,6 +13,32 @@
 #define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
+/* SCSI_CTL_PHASE */
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+
 /* USBFS_arb_int */
 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@@ -478,34 +504,34 @@
 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_RxStsReg__4__POS 4
 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -513,13 +539,13 @@
 #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
 #define SDCard_BSPIM_RxStsReg__6__POS 6
 #define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@@ -529,28 +555,28 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
 
 /* USBFS_dp_int */
 #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -562,28 +588,6 @@
 #define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_IO */
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-
 /* SCSI_In_DBx */
 #define SCSI_In_DBx__0__AG CYREG_PRT12_AG
 #define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE
@@ -1028,21 +1032,21 @@
 #define SD_Data_Clk__PM_STBY_MSK 0x01u
 
 /* SD_Init_Clk */
-#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG2_CFG2
 #define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Init_Clk__INDEX 0x01u
+#define SD_Init_Clk__INDEX 0x02u
 #define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Init_Clk__PM_ACT_MSK 0x02u
+#define SD_Init_Clk__PM_ACT_MSK 0x04u
 #define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Init_Clk__PM_STBY_MSK 0x02u
+#define SD_Init_Clk__PM_STBY_MSK 0x04u
 
 /* scsiTarget */
 #define scsiTarget_StatusReg__0__MASK 0x01u
 #define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
 #define scsiTarget_StatusReg__2__MASK 0x04u
@@ -1050,76 +1054,76 @@
 #define scsiTarget_StatusReg__3__MASK 0x08u
 #define scsiTarget_StatusReg__3__POS 3
 #define scsiTarget_StatusReg__MASK 0x0Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
 
 /* SD_Clk_Ctl */
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
 #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
 
 /* USBFS_ep_0 */
 #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -1312,6 +1316,17 @@
 #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
 #define SCSI_ATN__SLW CYREG_PRT12_SLW
 
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
+
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT4_AG
 #define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
@@ -1664,33 +1679,33 @@
 #define SCSI_Out__BSY__PS CYREG_PRT0_PS
 #define SCSI_Out__BSY__SHIFT 7
 #define SCSI_Out__BSY__SLW CYREG_PRT0_SLW
-#define SCSI_Out__CD__AG CYREG_PRT0_AG
-#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__CD__BIE CYREG_PRT0_BIE
-#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__CD__BYP CYREG_PRT0_BYP
-#define SCSI_Out__CD__CTL CYREG_PRT0_CTL
-#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__CD__DR CYREG_PRT0_DR
-#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__CD__MASK 0x04u
-#define SCSI_Out__CD__PC CYREG_PRT0_PC2
-#define SCSI_Out__CD__PORT 0u
-#define SCSI_Out__CD__PRT CYREG_PRT0_PRT
-#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__CD__PS CYREG_PRT0_PS
-#define SCSI_Out__CD__SHIFT 2
-#define SCSI_Out__CD__SLW CYREG_PRT0_SLW
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__CD_raw__MASK 0x04u
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2
+#define SCSI_Out__CD_raw__PORT 0u
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__CD_raw__SHIFT 2
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
 #define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG
 #define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX
 #define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE
@@ -1745,33 +1760,33 @@
 #define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
 #define SCSI_Out__IO_raw__SHIFT 0
 #define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__MSG__AG CYREG_PRT0_AG
-#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE
-#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP
-#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL
-#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__MSG__DR CYREG_PRT0_DR
-#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__MSG__MASK 0x10u
-#define SCSI_Out__MSG__PC CYREG_PRT0_PC4
-#define SCSI_Out__MSG__PORT 0u
-#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT
-#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__MSG__PS CYREG_PRT0_PS
-#define SCSI_Out__MSG__SHIFT 4
-#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__MSG_raw__MASK 0x10u
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4
+#define SCSI_Out__MSG_raw__PORT 0u
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__MSG_raw__SHIFT 4
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
 #define SCSI_Out__REQ__AG CYREG_PRT0_AG
 #define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
 #define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
@@ -2720,7 +2735,7 @@
 #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
 #define CYDEV_ECC_ENABLE 0
-#define CYDEV_HEAP_SIZE 0x1000
+#define CYDEV_HEAP_SIZE 0x0256
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1
 #define CYDEV_INTR_RISING 0x00000000u
 #define CYDEV_PROJ_TYPE 2
@@ -2729,7 +2744,7 @@
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
 #define CYDEV_PROJ_TYPE_STANDARD 0
 #define CYDEV_PROTECTION_ENABLE 0
-#define CYDEV_STACK_SIZE 0x4000
+#define CYDEV_STACK_SIZE 0x2000
 #define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
 #define CYDEV_USE_BUNDLED_CMSIS 1
 #define CYDEV_VARIABLE_VDDA 0

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -13,6 +13,32 @@
 .set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
+/* SCSI_CTL_PHASE */
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+
 /* USBFS_arb_int */
 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@@ -478,34 +504,34 @@
 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_RxStsReg__4__POS, 4
 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -513,13 +539,13 @@
 .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
 .set SDCard_BSPIM_RxStsReg__6__POS, 6
 .set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@@ -529,28 +555,28 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
 
 /* USBFS_dp_int */
 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -562,28 +588,6 @@
 .set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_IO */
-.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-
 /* SCSI_In_DBx */
 .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG
 .set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE
@@ -1028,21 +1032,21 @@
 .set SD_Data_Clk__PM_STBY_MSK, 0x01
 
 /* SD_Init_Clk */
-.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG2_CFG2
 .set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Init_Clk__INDEX, 0x01
+.set SD_Init_Clk__INDEX, 0x02
 .set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Init_Clk__PM_ACT_MSK, 0x02
+.set SD_Init_Clk__PM_ACT_MSK, 0x04
 .set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Init_Clk__PM_STBY_MSK, 0x02
+.set SD_Init_Clk__PM_STBY_MSK, 0x04
 
 /* scsiTarget */
 .set scsiTarget_StatusReg__0__MASK, 0x01
 .set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
 .set scsiTarget_StatusReg__2__MASK, 0x04
@@ -1050,76 +1054,76 @@
 .set scsiTarget_StatusReg__3__MASK, 0x08
 .set scsiTarget_StatusReg__3__POS, 3
 .set scsiTarget_StatusReg__MASK, 0x0F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
 
 /* SD_Clk_Ctl */
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
 .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
 
 /* USBFS_ep_0 */
 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -1312,6 +1316,17 @@
 .set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 .set SCSI_ATN__SLW, CYREG_PRT12_SLW
 
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
+
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT4_AG
 .set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX
@@ -1664,33 +1679,33 @@
 .set SCSI_Out__BSY__PS, CYREG_PRT0_PS
 .set SCSI_Out__BSY__SHIFT, 7
 .set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__CD__AG, CYREG_PRT0_AG
-.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__CD__DR, CYREG_PRT0_DR
-.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__CD__MASK, 0x04
-.set SCSI_Out__CD__PC, CYREG_PRT0_PC2
-.set SCSI_Out__CD__PORT, 0
-.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__CD__PS, CYREG_PRT0_PS
-.set SCSI_Out__CD__SHIFT, 2
-.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__CD_raw__MASK, 0x04
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2
+.set SCSI_Out__CD_raw__PORT, 0
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__CD_raw__SHIFT, 2
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
 .set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG
 .set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX
 .set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE
@@ -1745,33 +1760,33 @@
 .set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
 .set SCSI_Out__IO_raw__SHIFT, 0
 .set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__MSG__AG, CYREG_PRT0_AG
-.set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__MSG__DR, CYREG_PRT0_DR
-.set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__MSG__MASK, 0x10
-.set SCSI_Out__MSG__PC, CYREG_PRT0_PC4
-.set SCSI_Out__MSG__PORT, 0
-.set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__MSG__PS, CYREG_PRT0_PS
-.set SCSI_Out__MSG__SHIFT, 4
-.set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__MSG_raw__MASK, 0x10
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4
+.set SCSI_Out__MSG_raw__PORT, 0
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__MSG_raw__SHIFT, 4
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW
 .set SCSI_Out__REQ__AG, CYREG_PRT0_AG
 .set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
 .set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
@@ -2720,7 +2735,7 @@
 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 .set CYDEV_ECC_ENABLE, 0
-.set CYDEV_HEAP_SIZE, 0x1000
+.set CYDEV_HEAP_SIZE, 0x0256
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1
 .set CYDEV_INTR_RISING, 0x00000000
 .set CYDEV_PROJ_TYPE, 2
@@ -2729,7 +2744,7 @@
 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 .set CYDEV_PROJ_TYPE_STANDARD, 0
 .set CYDEV_PROTECTION_ENABLE, 0
-.set CYDEV_STACK_SIZE, 0x4000
+.set CYDEV_STACK_SIZE, 0x2000
 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1
 .set CYDEV_USE_BUNDLED_CMSIS, 1
 .set CYDEV_VARIABLE_VDDA, 0

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -13,6 +13,32 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
+/* SCSI_CTL_PHASE */
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+
 /* USBFS_arb_int */
 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -478,34 +504,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -513,13 +539,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@@ -529,28 +555,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
 
 /* USBFS_dp_int */
 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -562,28 +588,6 @@ USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
 USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_IO */
-SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-
 /* SCSI_In_DBx */
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
 SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
@@ -1028,21 +1032,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
 /* SD_Init_Clk */
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
 SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Init_Clk__INDEX EQU 0x01
+SD_Init_Clk__INDEX EQU 0x02
 SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Init_Clk__PM_ACT_MSK EQU 0x02
+SD_Init_Clk__PM_ACT_MSK EQU 0x04
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Init_Clk__PM_STBY_MSK EQU 0x02
+SD_Init_Clk__PM_STBY_MSK EQU 0x04
 
 /* scsiTarget */
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
 scsiTarget_StatusReg__2__MASK EQU 0x04
@@ -1050,76 +1054,76 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
 scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__MASK EQU 0x0F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
 
 /* SD_Clk_Ctl */
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
 
 /* USBFS_ep_0 */
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -1312,6 +1316,17 @@ SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW
 
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
 /* SCSI_Out */
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
 SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
@@ -1664,33 +1679,33 @@ SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
 SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
 SCSI_Out__BSY__SHIFT EQU 7
 SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__CD__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD__MASK EQU 0x04
-SCSI_Out__CD__PC EQU CYREG_PRT0_PC2
-SCSI_Out__CD__PORT EQU 0
-SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD__SHIFT EQU 2
-SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x04
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 2
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
 SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
 SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
 SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
@@ -1745,33 +1760,33 @@ SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
 SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
 SCSI_Out__IO_raw__SHIFT EQU 0
 SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG__MASK EQU 0x10
-SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4
-SCSI_Out__MSG__PORT EQU 0
-SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG__SHIFT EQU 4
-SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
 SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
 SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
 SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
@@ -2720,7 +2735,7 @@ CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0256
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x00000000
 CYDEV_PROJ_TYPE EQU 2
@@ -2729,7 +2744,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x2000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -13,6 +13,32 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
+; SCSI_CTL_PHASE
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+
 ; USBFS_arb_int
 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -478,34 +504,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_RxStsReg__4__POS EQU 4
 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -513,13 +539,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
 SDCard_BSPIM_RxStsReg__6__POS EQU 6
 SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@@ -529,28 +555,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
 
 ; USBFS_dp_int
 USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -562,28 +588,6 @@ USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
 USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_CTL_IO
-SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-
 ; SCSI_In_DBx
 SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
 SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
@@ -1028,21 +1032,21 @@ SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
 SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
 ; SD_Init_Clk
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
 SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Init_Clk__INDEX EQU 0x01
+SD_Init_Clk__INDEX EQU 0x02
 SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Init_Clk__PM_ACT_MSK EQU 0x02
+SD_Init_Clk__PM_ACT_MSK EQU 0x04
 SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Init_Clk__PM_STBY_MSK EQU 0x02
+SD_Init_Clk__PM_STBY_MSK EQU 0x04
 
 ; scsiTarget
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
 scsiTarget_StatusReg__2__MASK EQU 0x04
@@ -1050,76 +1054,76 @@ scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
 scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__MASK EQU 0x0F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
 
 ; SD_Clk_Ctl
 SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
 SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
 
 ; USBFS_ep_0
 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -1312,6 +1316,17 @@ SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
 SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
 SCSI_ATN__SLW EQU CYREG_PRT12_SLW
 
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
 SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
@@ -1664,33 +1679,33 @@ SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
 SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
 SCSI_Out__BSY__SHIFT EQU 7
 SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__CD__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD__MASK EQU 0x04
-SCSI_Out__CD__PC EQU CYREG_PRT0_PC2
-SCSI_Out__CD__PORT EQU 0
-SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD__SHIFT EQU 2
-SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x04
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 2
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
 SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
 SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
 SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
@@ -1745,33 +1760,33 @@ SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
 SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
 SCSI_Out__IO_raw__SHIFT EQU 0
 SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG__MASK EQU 0x10
-SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4
-SCSI_Out__MSG__PORT EQU 0
-SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG__SHIFT EQU 4
-SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
 SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
 SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
 SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
@@ -2720,7 +2735,7 @@ CYDEV_DEBUG_ENABLE_MASK EQU 0x20
 CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0256
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x00000000
 CYDEV_PROJ_TYPE EQU 2
@@ -2729,7 +2744,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x2000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h

@@ -30,7 +30,7 @@
 #include <SD_DAT2.h>
 #include <SD_DAT1_aliases.h>
 #include <SD_DAT1.h>
-#include <SCSI_CTL_IO.h>
+#include <SCSI_CTL_PHASE.h>
 #include <SCSI_In_aliases.h>
 #include <SCSI_Out_aliases.h>
 #include <CFG_EEPROM.h>
@@ -40,6 +40,7 @@
 #include <SD_SCK.h>
 #include <SD_MOSI_aliases.h>
 #include <SD_MOSI.h>
+#include <SCSI_CLK.h>
 #include <SCSI_RST_aliases.h>
 #include <SCSI_RST.h>
 #include <SCSI_ATN_aliases.h>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8"?>
 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
-  <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+  <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -103,7 +103,7 @@
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+    <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
   </block>
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -111,7 +111,7 @@
   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-  <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+  <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
   </block>
 </blockRegMap>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -1703,14 +1703,14 @@
 <CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
 <CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO" persistent="">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
 <dependencies>
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.c">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="ARM_C_FILE" />
 <PropertyDeltas />
@@ -1719,7 +1719,7 @@
 <CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
 <CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_IO.h" persistent=".\Generated_Source\PSoC5\SCSI_CTL_IO.h">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="NONE" />
 <PropertyDeltas />
@@ -2387,6 +2387,66 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE.c" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CTL_PHASE.h" persistent=".\Generated_Source\PSoC5\SCSI_CTL_PHASE.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.c" persistent=".\Generated_Source\PSoC5\SCSI_CLK.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.h" persistent=".\Generated_Source\PSoC5\SCSI_CLK.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2990,4 +3050,4 @@
 <BootloaderTag hexFile="" elfFile="" />
 <current_generation v="2" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
+</CyXmlSerializer>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd

@@ -493,7 +493,7 @@
     <peripheral>
       <name>SD_Clk_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x4000647A</baseAddress>
+      <baseAddress>0x40006471</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x1</size>
@@ -512,9 +512,9 @@
       </registers>
     </peripheral>
     <peripheral>
-      <name>SCSI_CTL_IO</name>
+      <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x4000647B</baseAddress>
+      <baseAddress>0x40006472</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x1</size>
@@ -522,7 +522,7 @@
       </addressBlock>
       <registers>
         <register>
-          <name>SCSI_CTL_IO_CONTROL_REG</name>
+          <name>SCSI_CTL_PHASE_CONTROL_REG</name>
           <description>No description available</description>
           <addressOffset>0x0</addressOffset>
           <size>8</size>

lib/SCSI2SD/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v

@@ -204,7 +204,7 @@ end
 // The data output is valid during the DESKEW_INIT phase as well,
 // so we subtract 1.
 // D1 = [0.000000055 / (1 / clk)] - 1
-cy_psoc3_dp #(.d1_init(3), 
+cy_psoc3_dp #(.d1_init(1), 
 .cy_dpconfig(
 {
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,

lib/SCSI2SD/software/SCSI2SD/src/config.c

@@ -27,7 +27,7 @@
 #include <string.h>
 
 // CYDEV_EEPROM_ROW_SIZE == 16.
-static char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000002";
+static const char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000002";
 
 // Config shadow RAM (copy of EEPROM)
 static Config shadow =
@@ -35,7 +35,7 @@ static Config shadow =
 	0, // SCSI ID
 	" codesrc", // vendor  (68k Apple Drive Setup: Set to " SEAGATE")
 	"         SCSI2SD", //prodId (68k Apple Drive Setup: Set to "          ST225N")
-	" 3.3", // revision (68k Apple Drive Setup: Set to "1.0 ")
+	" 3.4", // revision (68k Apple Drive Setup: Set to "1.0 ")
 	1, // enable parity
 	1, // enable unit attention,
 	0, // RESERVED
@@ -140,6 +140,7 @@ void configInit()
 	{
 		memcpy(&shadow, eeprom, sizeof(shadow));
 	}
+
 	config = &shadow;
 	CFG_EEPROM_Stop();
 

lib/SCSI2SD/software/SCSI2SD/src/scsi.c

@@ -54,9 +54,7 @@ static void enter_BusFree()
 
 	SCSI_ClearPin(SCSI_Out_BSY);
 	// We now have a Bus Clear Delay of 800ns to release remaining signals.
-	SCSI_ClearPin(SCSI_Out_MSG);
-	SCSI_ClearPin(SCSI_Out_CD);
-	SCSI_CTL_IO_Write(0);
+	SCSI_CTL_PHASE_Write(0);
 
 	// Wait for the initiator to cease driving signals
 	// Bus settle delay + bus clear delay = 1200ns

lib/SCSI2SD/software/SCSI2SD/src/scsiPhy.c

@@ -123,35 +123,12 @@ static void busSettleDelay(void)
 
 void scsiEnterPhase(int phase)
 {
-	if (phase > 0)
+	int newPhase = phase > 0 ? phase : 0;
+	if (newPhase != SCSI_CTL_PHASE_Read())
 	{
-		if (phase & __scsiphase_msg)
-		{
-			SCSI_SetPin(SCSI_Out_MSG);
-		}
-		else
-		{
-			SCSI_ClearPin(SCSI_Out_MSG);
-		}
-
-		if (phase & __scsiphase_cd)
-		{
-			SCSI_SetPin(SCSI_Out_CD);
-		}
-		else
-		{
-			SCSI_ClearPin(SCSI_Out_CD);
-		}
-
-		SCSI_CTL_IO_Write(phase & __scsiphase_io ? 1 : 0);
-	}
-	else
-	{
-		SCSI_ClearPin(SCSI_Out_MSG);
-		SCSI_ClearPin(SCSI_Out_CD);
-		SCSI_CTL_IO_Write(0);
+		SCSI_CTL_PHASE_Write(phase > 0 ? phase : 0);
+		busSettleDelay();
 	}
-	busSettleDelay();
 }
 
 void scsiPhyReset()
@@ -165,15 +142,13 @@ void scsiPhyReset()
 	// duration.
 	SCSI_SetPin(SCSI_Out_RST);
 
-	SCSI_CTL_IO_Write(0);
+	SCSI_CTL_PHASE_Write(0);
 	SCSI_ClearPin(SCSI_Out_ATN);
 	SCSI_ClearPin(SCSI_Out_BSY);
 	SCSI_ClearPin(SCSI_Out_ACK);
 	SCSI_ClearPin(SCSI_Out_RST);
 	SCSI_ClearPin(SCSI_Out_SEL);
 	SCSI_ClearPin(SCSI_Out_REQ);
-	SCSI_ClearPin(SCSI_Out_MSG);
-	SCSI_ClearPin(SCSI_Out_CD);
 
 	// Allow the FIFOs to fill up again.
 	SCSI_ClearPin(SCSI_Out_RST);

lib/SCSI2SD/software/SCSI2SD/src/sd.c

@@ -183,11 +183,7 @@ static void doReadSector(uint32_t numBytes)
 		return;
 	}
 
-	// Don't do a bus settle delay if we're already in the correct phase.
-	if (transfer.currentBlock == 0)
-	{
-		scsiEnterPhase(DATA_IN);
-	}
+	scsiEnterPhase(DATA_IN);
 
 	// Quickly seed the FIFO
 	prep = 4;
@@ -383,11 +379,7 @@ static int doWriteSector(uint32_t numBytes)
 	int result, maxWait;
 	uint8 dataToken;
 
-	// Don't do a bus settle delay if we're already in the correct phase.
-	if (transfer.currentBlock == 0)
-	{
-		scsiEnterPhase(DATA_OUT);
-	}
+	scsiEnterPhase(DATA_OUT);
 	
 	sdSpiByte(0xFC); // MULTIPLE byte start token