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+// Copyright (C) 2015 James Laird-Wah <james@laird-wah.net>
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+//
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+// This file is part of SCSI2SD.
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+//
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+// SCSI2SD is free software: you can redistribute it and/or modify
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+// it under the terms of the GNU General Public License as published by
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+// the Free Software Foundation, either version 3 of the License, or
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+// (at your option) any later version.
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+//
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+// SCSI2SD is distributed in the hope that it will be useful,
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+// but WITHOUT ANY WARRANTY; without even the implied warranty of
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+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+// GNU General Public License for more details.
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+//
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+// You should have received a copy of the GNU General Public License
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+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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+
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+#include <core_cm3_psoc5.h>
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+#include <stdint.h>
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+#include <cyfitter.h>
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+#include <cytypes.h>
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+#include <device.h>
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+#include "trace.h"
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+
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+// configure desired baud rate on the SWV pin.
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+// up to the lower of CPU_clk/2 or 33MHz
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+#define BAUD_RATE 921600
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+
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+// Cortex-M3 Trace Port Interface Unit (TPIU)
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+#define TPIU_BASE 0xe0040000
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+#define MMIO32(addr) *((volatile uint32_t*)(addr))
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+#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
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+#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
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+#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
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+#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
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+#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
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+#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
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+
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+#define TPIU_CSPSR_BYTE (1 << 0)
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+#define TPIU_CSPSR_HALFWORD (1 << 1)
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+#define TPIU_CSPSR_WORD (1 << 3)
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+
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+#define TPIU_SPPR_SYNC (0x0)
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+#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
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+#define TPIU_SPPR_ASYNC_NRZ (0x2)
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+
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+#define TPIU_FFCR_ENFCONT (1 << 1)
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+
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+void traceInit(void) {
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+ // enable the trace module clocks
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+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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+
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+ // set SWV clock = CPU clock / 2, and enable
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+ CY_SET_REG8(CYDEV_MFGCFG_MLOGIC_DEBUG, 0xc); // swv_clk_sel = CPU_clk / 2, swv_clk enable
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+
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+ // unlock the ETM/TPIU registers
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+ *((volatile uint32_t*)0xE0000FB0) = 0xC5ACCE55;
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+
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+ // NRZ is "UART mode"
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+ TPIU_SPPR = TPIU_SPPR_ASYNC_NRZ;
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+ // prescaler, 0 = divide by 1
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+ TPIU_ACPR = (BCLK__BUS_CLK__HZ/2/BAUD_RATE) - 1;
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+ // can write 1, 2 or 4 byte ports
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+ TPIU_CSPSR = TPIU_CSPSR_BYTE;
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+
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+ // bypass formatter (puts sync & stuff in otherwise)
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+ TPIU_FFCR &= ~TPIU_FFCR_ENFCONT;
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+ // enable ITM, enable the first 2 stimulus ports
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+ ITM->TCR = ITM_TCR_ITMENA_Msk;
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+ ITM->TER = 0x3;
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+
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+ trace(trace_begin);
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+}
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Michael McMaster