Fix compile issue with the orginal DaynaPORT build

Also fixed a couple of compiler warning

lib/ZuluSCSI_platform_RP2MCU/ZuluSCSI_platform.cpp

@@ -133,7 +133,7 @@ zuluscsi_speed_grade_t platform_string_to_speed_grade(const char *speed_grade_st
 #ifdef ENABLE_AUDIO_OUTPUT
     logmsg("Audio output enabled, reclocking isn't possible");
     return SPEED_GRADE_DEFAULT;
-#endif;
+#endif
 
     if (strcasecmp(speed_grade_str, sg_default) == 0)
       grade = SPEED_GRADE_DEFAULT;

lib/ZuluSCSI_platform_RP2MCU/custom_timings.cpp

@@ -46,10 +46,6 @@ bool CustomTimings::set_timings_from_file()
     const char scsi_5_section[] = "scsi_5";
     const char sdio_section[] = "sdio";
 
-
-    zuluscsi_timings_t custom_timings;
-
-
     // pll
     int32_t vco = ini_getl(pll_section, "vco_freq_hz", g_zuluscsi_timings->pll.vco_freq, CUSTOM_TIMINGS_FILE);
     int32_t post_div1 = ini_getl(pll_section, "pd1", g_zuluscsi_timings->pll.post_div1, CUSTOM_TIMINGS_FILE);

lib/ZuluSCSI_platform_RP2MCU/timings_RP2MCU.c

@@ -302,7 +302,7 @@ static zuluscsi_timings_t  predefined_timings[]  = {
 
 bool set_timings(zuluscsi_speed_grade_t speed_grade)
 {
-    uint8_t timings_index;
+    uint8_t timings_index = 0;
 
     switch (speed_grade)
     {

platformio.ini

@@ -201,6 +201,7 @@ build_flags =
     -DZULUSCSI_MCU_RP20XX
     -DZULUSCSI_NETWORK
     -DZULUSCSI_DAYNAPORT
+    -DCYW43_PIO_CLOCK_DIV_DYNAMIC=1
     -DROMDRIVE_OFFSET=${env:ZuluSCSI_Pico_DaynaPORT.program_flash_allocation}
 ; These take a large portion of the SRAM and can be adjusted
     -DLOGBUFSIZE=8192