# This is the template file for creating symbols with tragesym # every line starting with '#' is a comment line. [options] # wordswap swaps labels if the pin is on the right side an looks like this: # "PB1 (CLK)". That's useful for micro controller port labels # rotate_labels rotates the pintext of top and bottom pins # this is useful for large symbols like FPGAs with more than 100 pins # sort_labels will sort the pins by it's labels # useful for address ports, busses, ... wordswap=yes rotate_labels=yes sort_labels=no generate_pinseq=yes sym_width=18000 pinwidthvertical=700 pinwidthhorizontal=700 [geda_attr] # name will be printed in the top of the symbol # name is only some graphical text, not an attribute # version specifies a gschem version. # if you have a device with slots, you'll have to use slot= and slotdef= # use comment= if there are special information you want to add version=20060113 1 name=CY8C53 device=CY8C53 refdes=U? footprint=TQFP100_14 description=Cypress PSoC5 CY8C53 documentation=http://www.cypress.com/?id=2233 author=Michael McMaster dist-license=gpl3+ use-license=gpl3+ numslots=0 #slot=1 #slotdef=1: #slotdef=2: #slotdef=3: #slotdef=4: #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # ---------------------------------------- # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets. # net specifies the name of the net. Vcc or GND for example. # label represents the pinlabel. # negation lines can be added with "\_" example: \_enable\_ # if you want to write a "\" use "\\" as escape sequence #----------------------------------------------------- #pinnr seq type style posit. net label #----------------------------------------------------- 1 io line l P2[5] 2 io line l P2[6] 3 io line l P2[7] 4 io line l P12[4] 5 io line l P12[5] 6 io line l P6[4] 7 io line l P6[5] 8 io line l P6[6] 9 io line l P6[7] 10 pwr line l GND VSSD 11 io line l NC 12 pwr line l GND VSSD 13 pwr line l GND VSSD 14 pwr line l GND VSSD 15 in line l \_XRES\_ 16 io line l P5[0] 17 io line l P5[1] 18 io line l P5[2] 19 io line l P5[3] 20 io line l SWDIO,TMS,P1[0] 21 io line l SWDCK,TCK,P1[1] 22 io line l P1[2] 23 io line l SWV,TDO,P1[3] 24 io line l TDI,P1[4] 25 io line l NTRST,P1[5] 26 pwr line b VDDIO1 27 io line b P1[6] 28 io line b P1[7] 29 io line b P12[6] 30 io line b P12[7] 31 io line b P5[4] 32 io line b P5[5] 33 io line b P5[6] 34 io line b P5[7] 35 io line b SWDIO,USB D+ 36 io line b SWDCK,USB D- 37 pwr line b VDDD 38 pwr line b GND VSSD 39 pwr line b VCCD 40 io line b NC 41 io line b NC 42 clk clk b MHZ XTAL XO 43 clk clk b MHZ XTAL XI 44 io line b P3[0] 45 io line b P3[1] 46 io line b P3[2] 47 io line b P3[3] 48 io line b P3[4] 49 io line b P3[5] 50 pwr line b VDDIO3 75 pwr line r VDDIO0 74 io line r P0[3] 73 io line r P0[2] 72 io line r P0[1] 71 io line r P0[0] 70 io line r P4[1] 69 io line r P4[0] 68 io line r P12[3] 67 io line r P12[2] 66 pwr line r GND VSSD 65 pwr line r VDDA 64 pwr line r GND VSSA 63 pwr line r VCCA 62 io line r NC 61 io line r NC 60 io line r NC 59 io line r NC 58 io line r NC 57 io line r NC 56 io line r P15[3],KHZ XTAL XI 55 io line r P15[2],KHZ XTAL XO 54 io line r P12[1] 53 io line r P12[0] 52 io line r P3[7] 51 io line r P3[6] 100 pwr line t VDDIO2 99 io line t P2[4] 98 io line t P2[3] 97 io line t P2[2] 96 io line t P2[1] 95 io line t P2[0] 94 io line t P15[5] 93 io line t P15[4] 92 io line t P6[3] 91 io line t P6[2] 90 io line t P6[1] 89 io line t P6[0] 88 pwr line t VDDD 87 pwr line t GND VSSD 86 pwr line t VCCD 85 io line t P4[7] 84 io line t P4[6] 83 io line t P4[5] 82 io line t P4[4] 81 io line t P4[3] 80 io line t P4[2] 79 io line t P0[7] 78 io line t P0[6] 77 io line t P0[5] 76 io line t P0[4]