CyBootAsmIar.s 5.4 KB

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  1. ;-------------------------------------------------------------------------------
  2. ; FILENAME: CyBootAsmIar.s
  3. ; Version 4.0
  4. ;
  5. ; DESCRIPTION:
  6. ; Assembly routines for IAR Embedded Workbench IDE.
  7. ;
  8. ;-------------------------------------------------------------------------------
  9. ; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
  10. ; You may use this file only in accordance with the license, terms, conditions,
  11. ; disclaimers, and limitations in the end user license agreement accompanying
  12. ; the software package with which this file was provided.
  13. ;-------------------------------------------------------------------------------
  14. SECTION .text:CODE:ROOT(4)
  15. PUBLIC CyDelayCycles
  16. PUBLIC CyEnterCriticalSection
  17. PUBLIC CyExitCriticalSection
  18. INCLUDE cyfitteriar.inc
  19. THUMB
  20. ;-------------------------------------------------------------------------------
  21. ; Function Name: CyEnterCriticalSection
  22. ;-------------------------------------------------------------------------------
  23. ;
  24. ; Summary:
  25. ; CyEnterCriticalSection disables interrupts and returns a value indicating
  26. ; whether interrupts were previously enabled.
  27. ;
  28. ; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
  29. ; with interrupts still enabled. The test and set of the interrupt bits is not
  30. ; atomic. Therefore, to avoid corrupting processor state, it must be the policy
  31. ; that all interrupt routines restore the interrupt enable bits as they were
  32. ; found on entry.
  33. ;
  34. ; Parameters:
  35. ; None
  36. ;
  37. ; Return:
  38. ; uint8
  39. ; Returns 0 if interrupts were previously enabled or 1 if interrupts
  40. ; were previously disabled.
  41. ;
  42. ;-------------------------------------------------------------------------------
  43. ; uint8 CyEnterCriticalSection(void)
  44. CyEnterCriticalSection:
  45. MRS r0, PRIMASK ; Save and return interrupt state
  46. CPSID I ; Disable interrupts
  47. BX lr
  48. ;-------------------------------------------------------------------------------
  49. ; Function Name: CyExitCriticalSection
  50. ;-------------------------------------------------------------------------------
  51. ;
  52. ; Summary:
  53. ; CyExitCriticalSection re-enables interrupts if they were enabled before
  54. ; CyEnterCriticalSection was called. The argument should be the value returned
  55. ; from CyEnterCriticalSection.
  56. ;
  57. ; Parameters:
  58. ; uint8 savedIntrStatus:
  59. ; Saved interrupt status returned by the CyEnterCriticalSection function.
  60. ;
  61. ; Return:
  62. ; None
  63. ;
  64. ;-------------------------------------------------------------------------------
  65. ; void CyExitCriticalSection(uint8 savedIntrStatus)
  66. CyExitCriticalSection:
  67. MSR PRIMASK, r0 ; Restore interrupt state
  68. BX lr
  69. ;-------------------------------------------------------------------------------
  70. ; Function Name: CyDelayCycles
  71. ;-------------------------------------------------------------------------------
  72. ;
  73. ; Summary:
  74. ; Delays for the specified number of cycles.
  75. ;
  76. ; Parameters:
  77. ; uint32 cycles: number of cycles to delay.
  78. ;
  79. ; Return:
  80. ; None
  81. ;
  82. ;-------------------------------------------------------------------------------
  83. ; void CyDelayCycles(uint32 cycles)
  84. CyDelayCycles:
  85. IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
  86. ; cycles bytes
  87. ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
  88. LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
  89. BEQ CyDelayCycles_done ; 2 2 Skip if 0
  90. NOP ; 1 2 Loop alignment padding
  91. CyDelayCycles_loop:
  92. SUBS r0, r0, #1 ; 1 2
  93. MOV r0, r0 ; 1 2 Pad loop to power of two cycles
  94. BNE CyDelayCycles_loop ; 2 2
  95. CyDelayCycles_done:
  96. BX lr ; 3 2
  97. ELSE
  98. CMP r0, #20 ; 1 2 If delay is short - jump to cycle
  99. BLS CyDelayCycles_short ; 1 2
  100. PUSH {r1} ; 2 2 PUSH r1 to stack
  101. MOVS r1, #1 ; 1 2
  102. SUBS r0, r0, #20 ; 1 2 Subtract overhead
  103. LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value
  104. LDRB r1, [r1, #0] ; 2 2
  105. ANDS r1, r1, #0xC0 ; 1 2
  106. LSRS r1, r1, #6 ; 1 2
  107. PUSH {r2} ; 1 2 PUSH r2 to stack
  108. LDR r2, =cy_flash_cycles ; 2 2
  109. LDRB r1, [r2, r1] ; 2 2
  110. POP {r2} ; 2 2 POP r2 from stack
  111. NOP ; 1 2 Alignment padding
  112. NOP ; 1 2 Alignment padding
  113. NOP ; 1 2 Alignment padding
  114. CyDelayCycles_loop:
  115. SBCS r0, r0, r1 ; 1 2
  116. BPL CyDelayCycles_loop ; 3 2
  117. NOP ; 1 2 Loop alignment padding
  118. NOP ; 1 2 Loop alignment padding
  119. POP {r1} ; 2 2 POP r1 from stack
  120. CyDelayCycles_done:
  121. BX lr ; 3 2
  122. NOP ; 1 2 Alignment padding
  123. NOP ; 1 2 Alignment padding
  124. CyDelayCycles_short:
  125. SBCS r0, r0, #4 ; 1 2
  126. BPL CyDelayCycles_short ; 3 2
  127. BX lr ; 3 2
  128. NOP ; 1 2 Loop alignment padding
  129. DATA
  130. cy_flash_cycles:
  131. byte_1 DCB 0x0B
  132. byte_2 DCB 0x05
  133. byte_3 DCB 0x07
  134. byte_4 DCB 0x09
  135. ENDIF
  136. END