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pm
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BlueSCSI-v2
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BlueSCSI-v2
/
lib
/
SCSI2SD
/
software
/
SCSI2SD
/
v4
/
SCSI2SD.cydsn
/
SCSI2SD.cycdx

SCSI2SD.cycdx 24 KB
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  1. <?xml version="1.0" encoding="utf-8"?>
    2. 

  2. <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
    3. 

  3.   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    4. 

  4.   <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    5. 

  5.   <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    6. 

  6.   <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    7. 

  7.     <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
    8. 

  8.     <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
    9. 

  9.     <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
    10. 

  10.       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
    11. 

  11.         <value name="ENABLED" value="1" desc="Enable counter" />
    12. 

  12.         <value name="DISABLED" value="0" desc="Disable counter" />
    13. 

  13.       </field>
    14. 

  14.       <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
    15. 

  15.         <value name="ENABLED" value="1" desc="Interrupt enabled" />
    16. 

  16.         <value name="DISABLED" value="0" desc="Interrupt disabled" />
    17. 

  17.       </field>
    18. 

  18.       <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
    19. 

  19.         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
    20. 

  20.         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
    21. 

  21.       </field>
    22. 

  22.       <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
    23. 

  23.         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
    24. 

  24.         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
    25. 

  25.       </field>
    26. 

  26.       <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
    27. 

  27.         <value name="ENABLED" value="1" desc="Clear FIFO state" />
    28. 

  28.         <value name="DISABLED" value="0" desc="Normal FIFO operation" />
    29. 

  29.       </field>
    30. 

  30.       <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
    31. 

  31.         <value name="ENABLED" value="1" desc="Clear FIFO state" />
    32. 

  32.         <value name="DISABLED" value="0" desc="Normal FIFO operation" />
    33. 

  33.       </field>
    34. 

  34.     </register>
    35. 

  35.   </block>
    36. 

  36.   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    37. 

  37.   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    38. 

  38.   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    39. 

  39.   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    40. 

  40.   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    41. 

  41.   <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    42. 

  42.   <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    43. 

  43.   <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    44. 

  44.   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    45. 

  45.     <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />
    46. 

  46.     <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />
    47. 

  47.     <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">
    48. 

  48.       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
    49. 

  49.         <value name="ENABLED" value="1" desc="Enable counter" />
    50. 

  50.         <value name="DISABLED" value="0" desc="Disable counter" />
    51. 

  51.       </field>
    52. 

  52.       <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
    53. 

  53.         <value name="ENABLED" value="1" desc="Interrupt enabled" />
    54. 

  54.         <value name="DISABLED" value="0" desc="Interrupt disabled" />
    55. 

  55.       </field>
    56. 

  56.       <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
    57. 

  57.         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
    58. 

  58.         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
    59. 

  59.       </field>
    60. 

  60.       <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
    61. 

  61.         <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
    62. 

  62.         <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
    63. 

  63.       </field>
    64. 

  64.       <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
    65. 

  65.         <value name="ENABLED" value="1" desc="Clear FIFO state" />
    66. 

  66.         <value name="DISABLED" value="0" desc="Normal FIFO operation" />
    67. 

  67.       </field>
    68. 

  68.       <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
    69. 

  69.         <value name="ENABLED" value="1" desc="Clear FIFO state" />
    70. 

  70.         <value name="DISABLED" value="0" desc="Normal FIFO operation" />
    71. 

  71.       </field>
    72. 

  72.     </register>
    73. 

  73.   </block>
    74. 

  74.   <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    75. 

  75.   <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    76. 

  76.   <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    77. 

  77.   <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    78. 

  78.   <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    79. 

  79.     <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
    80. 

  80.   </block>
    81. 

  81.   <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    82. 

  82.   <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    83. 

  83.   <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    84. 

  84.   <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    85. 

  85.   <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    86. 

  86.   <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    87. 

  87.   <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    88. 

  88.   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    89. 

  89.     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    90. 

  90.     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    91. 

  91.     <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    92. 

  92.     <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    93. 

  93.     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    94. 

  94.     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    95. 

  95.     <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
    96. 

  96.       <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
    97. 

  97.     </register>
    98. 

  98.     <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
    99. 

  99.       <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
    100. 

  100.       <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
    101. 

  101.         <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
    102. 

  102.         <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
    103. 

  103.       </field>
    104. 

  104.       <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
    105. 

  105.       <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
    106. 

  106.       <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
    107. 

  107.       <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
    108. 

  108.         <value name="Timer" value="0" desc="CMP and TC are output." />
    109. 

  109.         <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
    110. 

  110.       </field>
    111. 

  111.       <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
    112. 

  112.     </register>
    113. 

  113.     <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
    114. 

  114.       <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
    115. 

  115.       <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
    116. 

  116.         <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
    117. 

  117.         <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
    118. 

  118.       </field>
    119. 

  119.       <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
    120. 

  120.       <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
    121. 

  121.       <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
    122. 

  122.       <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
    123. 

  123.     </register>
    124. 

  124.     <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
    125. 

  125.       <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
    126. 

  126.         <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
    127. 

  127.         <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
    128. 

  128.         <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
    129. 

  129.         <value name="Irq" value="11" desc="Timer runs until IRQ." />
    130. 

  130.       </field>
    131. 

  131.       <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
    132. 

  132.       <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
    133. 

  133.       <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
    134. 

  134.         <value name="Equal" value="0" desc="Compare Equal " />
    135. 

  135.         <value name="Less than" value="1" desc="Compare Less Than " />
    136. 

  136.         <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
    137. 

  137.         <value name="Greater" value="11" desc="Compare Greater Than ." />
    138. 

  138.         <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
    139. 

  139.       </field>
    140. 

  140.       <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
    141. 

  141.     </register>
    142. 

  142.     <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
    143. 

  143.     <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
    144. 

  144.   </block>
    145. 

  145.   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    146. 

  146.   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    147. 

  147.   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    148. 

  148.   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    149. 

  149.   <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    150. 

  150.   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    151. 

  151.   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    152. 

  152.   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    153. 

  153.   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    154. 

  154.   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    155. 

  155.   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    156. 

  156.     <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
    157. 

  157.   </block>
    158. 

  158.   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    159. 

  159.   <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    160. 

  160.   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    161. 

  161.   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
    162. 

  162.     <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    163. 

  163.     <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    164. 

  164.     <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    165. 

  165.     <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    166. 

  166.     <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    167. 

  167.     <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    168. 

  168.     <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    169. 

  169.     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    170. 

  170.     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    171. 

  171.     <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    172. 

  172.     <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    173. 

  173.     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    174. 

  174.     <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    175. 

  175.     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    176. 

  176.     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    177. 

  177.     <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    178. 

  178.     <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    179. 

  179.     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    180. 

  180.     <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    181. 

  181.     <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    182. 

  182.     <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    183. 

  183.     <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    184. 

  184.     <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    185. 

  185.     <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    186. 

  186.     <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    187. 

  187.     <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    188. 

  188.     <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    189. 

  189.     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    190. 

  190.     <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    191. 

  191.     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">
    192. 

  192.       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
    193. 

  193.       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
    194. 

  194.       <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />
    195. 

  195.     </register>
    196. 

  196.     <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />
    197. 

  197.     <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />
    198. 

  198.     <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">
    199. 

  199.       <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />
    200. 

  200.       <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />
    201. 

  201.     </register>
    202. 

  202.     <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
    203. 

  203.       <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />
    204. 

  204.       <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />
    205. 

  205.     </register>
    206. 

  206.     <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
    207. 

  207.       <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />
    208. 

  208.       <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />
    209. 

  209.     </register>
    210. 

  210.     <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">
    211. 

  211.       <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />
    212. 

  212.       <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />
    213. 

  213.     </register>
    214. 

  214.     <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />
    215. 

  215.     <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />
    216. 

  216.     <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />
    217. 

  217.     <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />
    218. 

  218.     <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />
    219. 

  219.     <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />
    220. 

  220.     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />
    221. 

  221.     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />
    222. 

  222.     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">
    223. 

  223.       <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
    224. 

  224.       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
    225. 

  225.     </register>
    226. 

  226.     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">
    227. 

  227.       <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />
    228. 

  228.       <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />
    229. 

  229.       <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />
    230. 

  230.       <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />
    231. 

  231.     </register>
    232. 

  232.     <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />
    233. 

  233.     <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">
    234. 

  234.       <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />
    235. 

  235.       <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />
    236. 

  236.       <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />
    237. 

  237.       <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />
    238. 

  238.     </register>
    239. 

  239.     <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">
    240. 

  240.       <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />
    241. 

  241.       <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />
    242. 

  242.       <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />
    243. 

  243.       <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />
    244. 

  244.     </register>
    245. 

  245.     <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />
    246. 

  246.     <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />
    247. 

  247.     <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />
    248. 

  248.     <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />
    249. 

  249.     <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />
    250. 

  250.     <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />
    251. 

  251.     <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />
    252. 

  252.     <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />
    253. 

  253.     <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />
    254. 

  254.     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />
    255. 

  255.     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
    256. 

  256.   </block>
    257. 

  257.   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    258. 

  258.   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    259. 

  259.     <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
    260. 

  260.   </block>
    261. 

  261.   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    262. 

  262.     <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
    263. 

  263.   </block>
    264. 

  264.   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    265. 

  265.   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    266. 

  266.   <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    267. 

  267.   <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    268. 

  268.   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
    269. 

  269.     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    270. 

  270.     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    271. 

  271.     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    272. 

  272.     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    273. 

  273.     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    274. 

  274.   </block>
    275. 

  275.   <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    276. 

  276.   <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
    277. 

  277. </blockRegMap>
    278.