BlueSCSI-v2/lib/SCSI2SD/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt

Loading plugins phase: Elapsed time ==> 0s.529ms
Initializing data phase: Elapsed time ==> 4s.249ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 8s.312ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 1s.015ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  USB_Bootloader.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
======================================================================

======================================================================
Compiling:  USB_Bootloader.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
======================================================================

======================================================================
Compiling:  USB_Bootloader.v
Program  :   vlogfe
Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Thu Aug 28 22:24:58 2014


======================================================================
Compiling:  USB_Bootloader.v
Program  :   vpp
Options  :    -yv2 -q10 USB_Bootloader.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Thu Aug 28 22:24:59 2014


vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'USB_Bootloader.ctl'.

vlogfe:  No errors.


======================================================================
Compiling:  USB_Bootloader.v
Program  :   tovif
Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Thu Aug 28 22:25:00 2014

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.
Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.

tovif:  No errors.


======================================================================
Compiling:  USB_Bootloader.v
Program  :   topld
Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Thu Aug 28 22:25:02 2014

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.
Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing one to \USBFS:tmpOE__Dm_net_0\
Aliasing \USBFS:tmpOE__Dp_net_0\ to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_7 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_6 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_5 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_4 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_3 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_2 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_1 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_DBx_net_0 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_9 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_8 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_7 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_6 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_5 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_4 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SD_PULLUP_net_4 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\
Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\
Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[32]
Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[49] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_6[50] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_5[51] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_4[52] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_3[53] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_2[54] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_1[55] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_0[56] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_9[84] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_8[85] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_7[86] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_6[87] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_5[88] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_4[89] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_3[90] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_2[91] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_1[92] = one[37]
Removing Lhs of wire tmpOE__SCSI_Out_net_0[93] = one[37]
Removing Lhs of wire tmpOE__SD_PULLUP_net_4[127] = one[37]
Removing Lhs of wire tmpOE__SD_PULLUP_net_3[128] = one[37]
Removing Lhs of wire tmpOE__SD_PULLUP_net_2[129] = one[37]
Removing Lhs of wire tmpOE__SD_PULLUP_net_1[130] = one[37]
Removing Lhs of wire tmpOE__SD_PULLUP_net_0[131] = one[37]

------------------------------------------------------
Aliased 0 equations, 25 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:


----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

topld:  No errors.

CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp
Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 10s.236ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Thursday, 28 August 2014 22:25:08
Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.344ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
Assigning clock USBFS_Clock_vbus to clock BUS_CLK because it is a pass-through
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
</CYPRESSTAG>
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = SCSI_Out(0)
        Attributes:
            Alias: DBP_raw
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(0)__PA ,
            pad => SCSI_Out(0)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(1)
        Attributes:
            Alias: ATN
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(1)__PA ,
            pad => SCSI_Out(1)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(2)
        Attributes:
            Alias: BSY
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(2)__PA ,
            pad => SCSI_Out(2)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(3)
        Attributes:
            Alias: ACK
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(3)__PA ,
            pad => SCSI_Out(3)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(4)
        Attributes:
            Alias: RST
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(4)__PA ,
            pad => SCSI_Out(4)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(5)
        Attributes:
            Alias: MSG
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(5)__PA ,
            pad => SCSI_Out(5)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(6)
        Attributes:
            Alias: SEL
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(6)__PA ,
            pad => SCSI_Out(6)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(7)
        Attributes:
            Alias: CD
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(7)__PA ,
            pad => SCSI_Out(7)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(8)
        Attributes:
            Alias: REQ
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(8)__PA ,
            pad => SCSI_Out(8)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out(9)
        Attributes:
            Alias: IO_raw
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out(9)__PA ,
            pad => SCSI_Out(9)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(0)
        Attributes:
            Alias: DB0
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(0)__PA ,
            pad => SCSI_Out_DBx(0)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(1)
        Attributes:
            Alias: DB1
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(1)__PA ,
            pad => SCSI_Out_DBx(1)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(2)
        Attributes:
            Alias: DB2
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(2)__PA ,
            pad => SCSI_Out_DBx(2)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(3)
        Attributes:
            Alias: DB3
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(3)__PA ,
            pad => SCSI_Out_DBx(3)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(4)
        Attributes:
            Alias: DB4
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(4)__PA ,
            pad => SCSI_Out_DBx(4)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(5)
        Attributes:
            Alias: DB5
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(5)__PA ,
            pad => SCSI_Out_DBx(5)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(6)
        Attributes:
            Alias: DB6
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => SCSI_Out_DBx(6)__PA ,
            pad => SCSI_Out_DBx(6)_PAD );
        Properties:
        {
        }

    Pin : Name = SCSI_Out_DBx(7)
        Attributes:
            Alias: DB7
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 0
            IO Voltage: 5
        PORT MAP (
            pa_out => SCSI_Out_DBx(7)__PA ,
            pad => SCSI_Out_DBx(7)_PAD );
        Properties:
        {
        }

    Pin : Name = SD_PULLUP(0)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 3.3
        PORT MAP (
            pa_out => SD_PULLUP(0)__PA ,
            pad => SD_PULLUP(0)_PAD );
        Properties:
        {
        }

    Pin : Name = SD_PULLUP(1)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SD_PULLUP(1)__PA ,
            pad => SD_PULLUP(1)_PAD );
        Properties:
        {
        }

    Pin : Name = SD_PULLUP(2)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SD_PULLUP(2)__PA ,
            pad => SD_PULLUP(2)_PAD );
        Properties:
        {
        }

    Pin : Name = SD_PULLUP(3)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SD_PULLUP(3)__PA ,
            pad => SD_PULLUP(3)_PAD );
        Properties:
        {
        }

    Pin : Name = SD_PULLUP(4)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: DIGITAL
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SD_PULLUP(4)__PA ,
            pad => SD_PULLUP(4)_PAD );
        Properties:
        {
        }

    Pin : Name = \USBFS:Dm(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: False
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: USB_D_MINUS
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \USBFS:Dm(0)\__PA ,
            analog_term => \USBFS:Net_597\ ,
            pad => \USBFS:Dm(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \USBFS:Dp(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: True
            Interrupt mode: FALLING
            Drive mode: HI_Z_ANALOG
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO RefSel: VCC_IO
            Required Capabilitites: USB_D_PLUS
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \USBFS:Dp(0)\__PA ,
            analog_term => \USBFS:Net_1000\ ,
            pad => \USBFS:Dp(0)_PAD\ );
        Properties:
        {
        }
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">

    ------------------------------------------------------------
    Interrupt listing
    ------------------------------------------------------------

    interrupt: Name =\USBFS:arb_int\
        PORT MAP (
            interrupt => \USBFS:Net_79\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:bus_reset\
        PORT MAP (
            interrupt => \USBFS:Net_81\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:dp_int\
        PORT MAP (
            interrupt => \USBFS:Net_1010\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:ep_0\
        PORT MAP (
            interrupt => \USBFS:ept_int_0\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:ep_1\
        PORT MAP (
            interrupt => \USBFS:ept_int_1\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:ep_2\
        PORT MAP (
            interrupt => \USBFS:ept_int_2\ );
        Properties:
        {
            int_type = "10"
        }

    interrupt: Name =\USBFS:sof_int\
        PORT MAP (
            interrupt => Net_40 );
        Properties:
        {
            int_type = "10"
        }
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital clock dividers        :    0 :    8 :    8 :   0.00%
Analog clock dividers         :    0 :    4 :    4 :   0.00%
Pins                          :   28 :   44 :   72 :  38.89%
UDB Macrocells                :    0 :  192 :  192 :   0.00%
UDB Unique Pterms             :    0 :  384 :  384 :   0.00%
UDB Datapath Cells            :    0 :   24 :   24 :   0.00%
UDB Status Cells              :    0 :   24 :   24 :   0.00%
UDB Control Cells             :    0 :   24 :   24 :   0.00%
DMA Channels                  :    0 :   24 :   24 :   0.00%
Interrupts                    :    7 :   25 :   32 :  21.88%
VIDAC Fixed Blocks            :    0 :    1 :    1 :   0.00%
Comparator Fixed Blocks       :    0 :    2 :    2 :   0.00%
CapSense Buffers              :    0 :    2 :    2 :   0.00%
I2C Fixed Blocks              :    0 :    1 :    1 :   0.00%
Timer Fixed Blocks            :    0 :    4 :    4 :   0.00%
USB Fixed Blocks              :    1 :    0 :    1 : 100.00%
LCD Fixed Blocks              :    0 :    1 :    1 :   0.00%
EMIF Fixed Blocks             :    0 :    1 :    1 :   0.00%
LPF Fixed Blocks              :    0 :    2 :    2 :   0.00%
SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.406ms
Tech mapping phase: Elapsed time ==> 0s.702ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
Initial Analog Placement Results:
IO_3@[IOP=(4)][IoId=(3)] : SCSI_Out(0) (fixed)
IO_2@[IOP=(4)][IoId=(2)] : SCSI_Out(1) (fixed)
IO_7@[IOP=(0)][IoId=(7)] : SCSI_Out(2) (fixed)
IO_6@[IOP=(0)][IoId=(6)] : SCSI_Out(3) (fixed)
IO_5@[IOP=(0)][IoId=(5)] : SCSI_Out(4) (fixed)
IO_4@[IOP=(0)][IoId=(4)] : SCSI_Out(5) (fixed)
IO_3@[IOP=(0)][IoId=(3)] : SCSI_Out(6) (fixed)
IO_2@[IOP=(0)][IoId=(2)] : SCSI_Out(7) (fixed)
IO_1@[IOP=(0)][IoId=(1)] : SCSI_Out(8) (fixed)
IO_0@[IOP=(0)][IoId=(0)] : SCSI_Out(9) (fixed)
IO_3@[IOP=(6)][IoId=(3)] : SCSI_Out_DBx(0) (fixed)
IO_2@[IOP=(6)][IoId=(2)] : SCSI_Out_DBx(1) (fixed)
IO_1@[IOP=(6)][IoId=(1)] : SCSI_Out_DBx(2) (fixed)
IO_0@[IOP=(6)][IoId=(0)] : SCSI_Out_DBx(3) (fixed)
IO_7@[IOP=(4)][IoId=(7)] : SCSI_Out_DBx(4) (fixed)
IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out_DBx(5) (fixed)
IO_5@[IOP=(4)][IoId=(5)] : SCSI_Out_DBx(6) (fixed)
IO_4@[IOP=(4)][IoId=(4)] : SCSI_Out_DBx(7) (fixed)
IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(0) (fixed)
IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(1) (fixed)
IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(2) (fixed)
IO_4@[IOP=(3)][IoId=(4)] : SD_PULLUP(3) (fixed)
IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed)
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)
USB[0]@[FFB(USB,0)] : \USBFS:USB\
Analog Placement phase: Elapsed time ==> 0s.109ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 1s.453ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2076: Total run-time: 4.1 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary">
No PLDs were packed.
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.063ms
</CYPRESSTAG>
<CYPRESSTAG name="Simulated Annealing">
Annealing: Elapsed time ==> 0s.014ms
<CYPRESSTAG name="Simulated Annealing Results">
The seed used for moves was 114161200.
Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          0 :       0.00 :       0.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
UDB [UDB=(0,0)] is empty.
UDB [UDB=(0,1)] is empty.
UDB [UDB=(0,2)] is empty.
UDB [UDB=(0,3)] is empty.
UDB [UDB=(0,4)] is empty.
UDB [UDB=(0,5)] is empty.
UDB [UDB=(1,0)] is empty.
UDB [UDB=(1,1)] is empty.
UDB [UDB=(1,2)] is empty.
UDB [UDB=(1,3)] is empty.
UDB [UDB=(1,4)] is empty.
UDB [UDB=(1,5)] is empty.
UDB [UDB=(2,0)] is empty.
UDB [UDB=(2,1)] is empty.
UDB [UDB=(2,2)] is empty.
UDB [UDB=(2,3)] is empty.
UDB [UDB=(2,4)] is empty.
UDB [UDB=(2,5)] is empty.
UDB [UDB=(3,0)] is empty.
UDB [UDB=(3,1)] is empty.
UDB [UDB=(3,2)] is empty.
UDB [UDB=(3,3)] is empty.
UDB [UDB=(3,4)] is empty.
UDB [UDB=(3,5)] is empty.
Intr hod @ [IntrHod=(0)]: 
  Intr@ [IntrHod=(0)][IntrId=(0)] 
    interrupt: Name =\USBFS:ep_1\
        PORT MAP (
            interrupt => \USBFS:ept_int_1\ );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(1)] 
    interrupt: Name =\USBFS:ep_2\
        PORT MAP (
            interrupt => \USBFS:ept_int_2\ );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(12)] 
    interrupt: Name =\USBFS:dp_int\
        PORT MAP (
            interrupt => \USBFS:Net_1010\ );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(21)] 
    interrupt: Name =\USBFS:sof_int\
        PORT MAP (
            interrupt => Net_40 );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(22)] 
    interrupt: Name =\USBFS:arb_int\
        PORT MAP (
            interrupt => \USBFS:Net_79\ );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(23)] 
    interrupt: Name =\USBFS:bus_reset\
        PORT MAP (
            interrupt => \USBFS:Net_81\ );
        Properties:
        {
            int_type = "10"
        }
  Intr@ [IntrHod=(0)][IntrId=(24)] 
    interrupt: Name =\USBFS:ep_0\
        PORT MAP (
            interrupt => \USBFS:ept_int_0\ );
        Properties:
        {
            int_type = "10"
        }
Drq hod @ [DrqHod=(0)]: empty
Port 0 contains the following IO cells:
[IoId=0]: 
Pin : Name = SCSI_Out(9)
    Attributes:
        Alias: IO_raw
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(9)__PA ,
        pad => SCSI_Out(9)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = SCSI_Out(8)
    Attributes:
        Alias: REQ
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(8)__PA ,
        pad => SCSI_Out(8)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = SCSI_Out(7)
    Attributes:
        Alias: CD
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(7)__PA ,
        pad => SCSI_Out(7)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = SCSI_Out(6)
    Attributes:
        Alias: SEL
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(6)__PA ,
        pad => SCSI_Out(6)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = SCSI_Out(5)
    Attributes:
        Alias: MSG
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(5)__PA ,
        pad => SCSI_Out(5)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = SCSI_Out(4)
    Attributes:
        Alias: RST
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(4)__PA ,
        pad => SCSI_Out(4)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = SCSI_Out(3)
    Attributes:
        Alias: ACK
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(3)__PA ,
        pad => SCSI_Out(3)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = SCSI_Out(2)
    Attributes:
        Alias: BSY
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(2)__PA ,
        pad => SCSI_Out(2)_PAD );
    Properties:
    {
    }

Port 1 is empty
Port 2 is empty
Port 3 contains the following IO cells:
[IoId=1]: 
Pin : Name = SD_PULLUP(0)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 3.3
    PORT MAP (
        pa_out => SD_PULLUP(0)__PA ,
        pad => SD_PULLUP(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = SD_PULLUP(1)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SD_PULLUP(1)__PA ,
        pad => SD_PULLUP(1)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = SD_PULLUP(2)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SD_PULLUP(2)__PA ,
        pad => SD_PULLUP(2)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = SD_PULLUP(3)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SD_PULLUP(3)__PA ,
        pad => SD_PULLUP(3)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = SD_PULLUP(4)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SD_PULLUP(4)__PA ,
        pad => SD_PULLUP(4)_PAD );
    Properties:
    {
    }

Port 4 contains the following IO cells:
[IoId=2]: 
Pin : Name = SCSI_Out(1)
    Attributes:
        Alias: ATN
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(1)__PA ,
        pad => SCSI_Out(1)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = SCSI_Out(0)
    Attributes:
        Alias: DBP_raw
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out(0)__PA ,
        pad => SCSI_Out(0)_PAD );
    Properties:
    {
    }

[IoId=4]: 
Pin : Name = SCSI_Out_DBx(7)
    Attributes:
        Alias: DB7
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 5
    PORT MAP (
        pa_out => SCSI_Out_DBx(7)__PA ,
        pad => SCSI_Out_DBx(7)_PAD );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = SCSI_Out_DBx(6)
    Attributes:
        Alias: DB6
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(6)__PA ,
        pad => SCSI_Out_DBx(6)_PAD );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = SCSI_Out_DBx(5)
    Attributes:
        Alias: DB5
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(5)__PA ,
        pad => SCSI_Out_DBx(5)_PAD );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = SCSI_Out_DBx(4)
    Attributes:
        Alias: DB4
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(4)__PA ,
        pad => SCSI_Out_DBx(4)_PAD );
    Properties:
    {
    }

Port 5 is empty
Port 6 contains the following IO cells:
[IoId=0]: 
Pin : Name = SCSI_Out_DBx(3)
    Attributes:
        Alias: DB3
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(3)__PA ,
        pad => SCSI_Out_DBx(3)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = SCSI_Out_DBx(2)
    Attributes:
        Alias: DB2
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(2)__PA ,
        pad => SCSI_Out_DBx(2)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = SCSI_Out_DBx(1)
    Attributes:
        Alias: DB1
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(1)__PA ,
        pad => SCSI_Out_DBx(1)_PAD );
    Properties:
    {
    }

[IoId=3]: 
Pin : Name = SCSI_Out_DBx(0)
    Attributes:
        Alias: DB0
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => SCSI_Out_DBx(0)__PA ,
        pad => SCSI_Out_DBx(0)_PAD );
    Properties:
    {
    }

Port 12 is empty
Port 15 generates interrupt for logical port:
    logicalport: Name =\USBFS:Dp\
        PORT MAP (
            in_clock_en => one ,
            in_reset => zero ,
            out_clock_en => one ,
            out_reset => zero ,
            interrupt => \USBFS:Net_1010\ ,
            in_clock => ClockBlock_BUS_CLK );
        Properties:
        {
            drive_mode = "000"
            ibuf_enabled = "0"
            id = "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42"
            init_dr_st = "0"
            input_clk_en = 0
            input_sync = "1"
            input_sync_mode = "0"
            intr_mode = "10"
            invert_in_clock = 0
            invert_in_clock_en = 0
            invert_in_reset = 0
            invert_out_clock = 0
            invert_out_clock_en = 0
            invert_out_reset = 0
            io_voltage = ""
            layout_mode = "CONTIGUOUS"
            oe_conn = "0"
            oe_reset = 0
            oe_sync = "0"
            output_clk_en = 0
            output_clock_mode = "0"
            output_conn = "0"
            output_mode = "0"
            output_reset = 0
            output_sync = "0"
            pa_in_clock = -1
            pa_in_clock_en = -1
            pa_in_reset = -1
            pa_out_clock = -1
            pa_out_clock_en = -1
            pa_out_reset = -1
            pin_aliases = ""
            pin_mode = "I"
            por_state = 4
            port_alias_group = ""
            port_alias_required = 0
            sio_group_cnt = 0
            sio_hifreq = ""
            sio_hyst = "0"
            sio_ibuf = "00000000"
            sio_info = "00"
            sio_obuf = "00000000"
            sio_refsel = "00000000"
            sio_vtrip = "00000000"
            slew_rate = "0"
            spanning = 0
            sw_only = 0
            use_annotation = "0"
            vtrip = "00"
            width = 1
        }
    and contains the following IO cells:
[IoId=6]: 
Pin : Name = \USBFS:Dp(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: True
        Interrupt mode: FALLING
        Drive mode: HI_Z_ANALOG
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: USB_D_PLUS
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \USBFS:Dp(0)\__PA ,
        analog_term => \USBFS:Net_1000\ ,
        pad => \USBFS:Dp(0)_PAD\ );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = \USBFS:Dm(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: False
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO RefSel: VCC_IO
        Required Capabilitites: USB_D_MINUS
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \USBFS:Dm(0)\__PA ,
        analog_term => \USBFS:Net_597\ ,
        pad => \USBFS:Dm(0)_PAD\ );
    Properties:
    {
    }

Fixed Function block hod @ [FFB(CAN,0)]: empty
Fixed Function block hod @ [FFB(Cache,0)]: empty
Fixed Function block hod @ [FFB(CapSense,0)]: empty
Fixed Function block hod @ [FFB(Clock,0)]: 
    Clock Block @ [FFB(Clock,0)]: 
    clockblockcell: Name =ClockBlock
        PORT MAP (
            clk_bus_glb => ClockBlock_BUS_CLK ,
            clk_bus => ClockBlock_BUS_CLK_local ,
            clk_sync => ClockBlock_MASTER_CLK ,
            clk_32k_xtal => ClockBlock_XTAL_32KHZ ,
            xtal => ClockBlock_XTAL ,
            ilo => ClockBlock_ILO ,
            clk_100k => ClockBlock_100k ,
            clk_1k => ClockBlock_1k ,
            clk_32k => ClockBlock_32k ,
            pllout => ClockBlock_PLL_OUT ,
            imo => ClockBlock_IMO );
        Properties:
        {
        }
Fixed Function block hod @ [FFB(Comparator,0)]: empty
Fixed Function block hod @ [FFB(DFB,0)]: empty
Fixed Function block hod @ [FFB(DSM,0)]: empty
Fixed Function block hod @ [FFB(Decimator,0)]: empty
Fixed Function block hod @ [FFB(EMIF,0)]: empty
Fixed Function block hod @ [FFB(I2C,0)]: empty
Fixed Function block hod @ [FFB(LCD,0)]: empty
Fixed Function block hod @ [FFB(LVD,0)]: empty
Fixed Function block hod @ [FFB(PM,0)]: empty
Fixed Function block hod @ [FFB(SPC,0)]: empty
Fixed Function block hod @ [FFB(Timer,0)]: empty
Fixed Function block hod @ [FFB(USB,0)]: 
    USB Block @ [FFB(USB,0)]: 
    usbcell: Name =\USBFS:USB\
        PORT MAP (
            dp => \USBFS:Net_1000\ ,
            dm => \USBFS:Net_597\ ,
            sof_int => Net_40 ,
            arb_int => \USBFS:Net_79\ ,
            usb_int => \USBFS:Net_81\ ,
            ept_int_8 => \USBFS:ept_int_8\ ,
            ept_int_7 => \USBFS:ept_int_7\ ,
            ept_int_6 => \USBFS:ept_int_6\ ,
            ept_int_5 => \USBFS:ept_int_5\ ,
            ept_int_4 => \USBFS:ept_int_4\ ,
            ept_int_3 => \USBFS:ept_int_3\ ,
            ept_int_2 => \USBFS:ept_int_2\ ,
            ept_int_1 => \USBFS:ept_int_1\ ,
            ept_int_0 => \USBFS:ept_int_0\ ,
            ord_int => \USBFS:Net_95\ ,
            dma_req_7 => \USBFS:dma_req_7\ ,
            dma_req_6 => \USBFS:dma_req_6\ ,
            dma_req_5 => \USBFS:dma_req_5\ ,
            dma_req_4 => \USBFS:dma_req_4\ ,
            dma_req_3 => \USBFS:dma_req_3\ ,
            dma_req_2 => \USBFS:dma_req_2\ ,
            dma_req_1 => \USBFS:dma_req_1\ ,
            dma_req_0 => \USBFS:dma_req_0\ ,
            dma_termin => \USBFS:Net_824\ );
        Properties:
        {
            cy_registers = ""
        }
Fixed Function block hod @ [FFB(VIDAC,0)]: empty
Fixed Function block hod @ [FFB(CsAbuf,0)]: empty
Fixed Function block hod @ [FFB(Vref,0)]: empty
Fixed Function block hod @ [FFB(LPF,0)]: empty
Fixed Function block hod @ [FFB(SAR,0)]: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |                 | 
Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connections
-----+-----+-------+-----------+------------------+-----------------+-------------------------
   0 |   0 |     * |      NONE |         CMOS_OUT |     SCSI_Out(9) | 
     |   1 |     * |      NONE |         CMOS_OUT |     SCSI_Out(8) | 
     |   2 |     * |      NONE |         CMOS_OUT |     SCSI_Out(7) | 
     |   3 |     * |      NONE |         CMOS_OUT |     SCSI_Out(6) | 
     |   4 |     * |      NONE |         CMOS_OUT |     SCSI_Out(5) | 
     |   5 |     * |      NONE |         CMOS_OUT |     SCSI_Out(4) | 
     |   6 |     * |      NONE |         CMOS_OUT |     SCSI_Out(3) | 
     |   7 |     * |      NONE |         CMOS_OUT |     SCSI_Out(2) | 
-----+-----+-------+-----------+------------------+-----------------+-------------------------
   3 |   1 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(0) | 
     |   2 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(1) | 
     |   3 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(2) | 
     |   4 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(3) | 
     |   5 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(4) | 
-----+-----+-------+-----------+------------------+-----------------+-------------------------
   4 |   2 |     * |      NONE |         CMOS_OUT |     SCSI_Out(1) | 
     |   3 |     * |      NONE |         CMOS_OUT |     SCSI_Out(0) | 
     |   4 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(7) | 
     |   5 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(6) | 
     |   6 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(5) | 
     |   7 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(4) | 
-----+-----+-------+-----------+------------------+-----------------+-------------------------
   6 |   0 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(3) | 
     |   1 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(2) | 
     |   2 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(1) | 
     |   3 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(0) | 
-----+-----+-------+-----------+------------------+-----------------+-------------------------
  15 |   6 |     * |   FALLING |      HI_Z_ANALOG |   \USBFS:Dp(0)\ | Analog(\USBFS:Net_1000\)
     |   7 |     * |      NONE |      HI_Z_ANALOG |   \USBFS:Dm(0)\ | Analog(\USBFS:Net_597\)
----------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.359ms
Digital Placement phase: Elapsed time ==> 7s.578ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
Routing successful.
Digital Routing phase: Elapsed time ==> 9s.796ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream and API generation">
Bitstream and API generation phase: Elapsed time ==> 25s.390ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream verification">
Bitstream verification phase: Elapsed time ==> 0s.158ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Timing report is in USB_Bootloader_timing.html.
Static timing analysis phase: Elapsed time ==> 4s.278ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.656ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 50s.921ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 50s.997ms
API generation phase: Elapsed time ==> 24s.640ms
Dependency generation phase: Elapsed time ==> 0s.859ms
Cleanup phase: Elapsed time ==> 0s.844ms