SCSI2SD.cycdx 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279
  1. <?xml version="1.0" encoding="utf-8"?>
  2. <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
  3. <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  4. <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  5. <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  6. <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  7. <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  8. <register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
  9. <register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />
  10. <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">
  11. <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
  12. <value name="ENABLED" value="1" desc="Enable counter" />
  13. <value name="DISABLED" value="0" desc="Disable counter" />
  14. </field>
  15. <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
  16. <value name="ENABLED" value="1" desc="Interrupt enabled" />
  17. <value name="DISABLED" value="0" desc="Interrupt disabled" />
  18. </field>
  19. <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
  20. <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
  21. <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
  22. </field>
  23. <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
  24. <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
  25. <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
  26. </field>
  27. <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
  28. <value name="ENABLED" value="1" desc="Clear FIFO state" />
  29. <value name="DISABLED" value="0" desc="Normal FIFO operation" />
  30. </field>
  31. <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
  32. <value name="ENABLED" value="1" desc="Clear FIFO state" />
  33. <value name="DISABLED" value="0" desc="Normal FIFO operation" />
  34. </field>
  35. </register>
  36. </block>
  37. <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  38. <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
  39. <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
  40. <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
  41. <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
  42. <value name="ENABLED" value="1" desc="Enable counter" />
  43. <value name="DISABLED" value="0" desc="Disable counter" />
  44. </field>
  45. <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
  46. <value name="ENABLED" value="1" desc="Interrupt enabled" />
  47. <value name="DISABLED" value="0" desc="Interrupt disabled" />
  48. </field>
  49. <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
  50. <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
  51. <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
  52. </field>
  53. <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
  54. <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
  55. <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
  56. </field>
  57. <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
  58. <value name="ENABLED" value="1" desc="Clear FIFO state" />
  59. <value name="DISABLED" value="0" desc="Normal FIFO operation" />
  60. </field>
  61. <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
  62. <value name="ENABLED" value="1" desc="Clear FIFO state" />
  63. <value name="DISABLED" value="0" desc="Normal FIFO operation" />
  64. </field>
  65. </register>
  66. </block>
  67. <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  68. <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  69. <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  70. <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  71. <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  72. <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  73. <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  74. <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  75. <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  76. <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  77. <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  78. <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  79. <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
  80. </block>
  81. <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  82. <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  83. <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  84. <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  85. <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  86. <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  87. <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  88. <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  89. <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  90. <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  91. <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  92. <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  93. <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  94. <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  95. <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  96. <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  97. <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  98. <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  99. <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  100. <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  101. <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  102. <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
  103. </block>
  104. <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  105. <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  106. <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  107. <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
  108. <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  109. <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  110. <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  111. <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  112. <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  113. <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  114. <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  115. <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  116. <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  117. <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  118. <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  119. <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  120. <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  121. <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  122. <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  123. <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  124. <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  125. <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  126. <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  127. <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  128. <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  129. <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  130. <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  131. <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  132. <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  133. <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  134. <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  135. <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  136. <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  137. <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">
  138. <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
  139. <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
  140. <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />
  141. </register>
  142. <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />
  143. <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />
  144. <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">
  145. <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />
  146. <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />
  147. </register>
  148. <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
  149. <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />
  150. <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />
  151. </register>
  152. <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
  153. <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />
  154. <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />
  155. </register>
  156. <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">
  157. <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />
  158. <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />
  159. </register>
  160. <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />
  161. <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />
  162. <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />
  163. <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />
  164. <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />
  165. <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />
  166. <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />
  167. <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />
  168. <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">
  169. <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
  170. <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
  171. </register>
  172. <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">
  173. <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />
  174. <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />
  175. <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />
  176. <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />
  177. </register>
  178. <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />
  179. <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">
  180. <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />
  181. <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />
  182. <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />
  183. <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />
  184. </register>
  185. <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">
  186. <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />
  187. <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />
  188. <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />
  189. <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />
  190. </register>
  191. <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />
  192. <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />
  193. <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />
  194. <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />
  195. <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />
  196. <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />
  197. <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />
  198. <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />
  199. <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />
  200. <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />
  201. <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
  202. </block>
  203. <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  204. <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  205. <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  206. <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  207. <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  208. <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  209. <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  210. <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
  211. <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
  212. </register>
  213. <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
  214. <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
  215. <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
  216. <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
  217. <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
  218. </field>
  219. <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
  220. <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
  221. <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
  222. <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
  223. <value name="Timer" value="0" desc="CMP and TC are output." />
  224. <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
  225. </field>
  226. <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
  227. </register>
  228. <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
  229. <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
  230. <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
  231. <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
  232. <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
  233. </field>
  234. <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
  235. <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
  236. <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
  237. <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
  238. </register>
  239. <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
  240. <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
  241. <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
  242. <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
  243. <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
  244. <value name="Irq" value="11" desc="Timer runs until IRQ." />
  245. </field>
  246. <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
  247. <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
  248. <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
  249. <value name="Equal" value="0" desc="Compare Equal " />
  250. <value name="Less than" value="1" desc="Compare Less Than " />
  251. <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
  252. <value name="Greater" value="11" desc="Compare Greater Than ." />
  253. <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
  254. </field>
  255. <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
  256. </register>
  257. <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
  258. <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
  259. </block>
  260. <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  261. <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />
  262. </block>
  263. <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  264. <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />
  265. </block>
  266. <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  267. <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  268. <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  269. <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  270. <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
  271. <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  272. <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  273. <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  274. <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  275. <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  276. </block>
  277. <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  278. <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
  279. </blockRegMap>