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@@ -111,14 +111,13 @@ SPISettings readSettings(SPISPEED, MSBFIRST, SPI_MODE0);
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uint8_t readRegister(uint8_t addr)
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{
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-
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SPI.beginTransaction(readSettings);
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digitalWrite(pins.ss, LOW); // Select Receiver
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- SPI.transfer(addr & 0x7F); // First address bit 0x00 is read
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- uint8_t res = (uint8_t) SPI.transfer(0x00);
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+ SPI.transfer(addr & 0x7F); // First address bit means read
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+ uint8_t res = (uint8_t) SPI.transfer(0x00); // Read address
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digitalWrite(pins.ss, HIGH); // Unselect Receiver
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SPI.endTransaction();
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- return((uint8_t) res);
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+ return((uint8_t) res) & 0xFF;
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}
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@@ -161,17 +160,18 @@ void writeRegister(uint8_t addr, uint8_t value)
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void writeBuffer(uint8_t addr, uint8_t *buf, uint8_t len)
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{
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- //noInterrupts(); // XXX
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+ //noInterrupts(); // MMM
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SPI.beginTransaction(writeSettings);
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- digitalWrite(pins.ss, LOW); // Select Receiver
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+ digitalWrite(pins.ss, LOW); // put SPI slave on
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SPI.transfer((addr | 0x80) & 0xFF); // write buffer address
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for (uint8_t i=0; i<len; i++) { // write all bytes of buffer
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SPI.transfer(buf[i] & 0xFF);
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}
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- digitalWrite(pins.ss, HIGH); // Unselect Receiver
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+ digitalWrite(pins.ss, HIGH); // Unselect SPI slave
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+
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SPI.endTransaction();
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//interrupts();
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@@ -207,7 +207,7 @@ void setRate(uint8_t sf, uint8_t crc)
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// Set rate based on Spreading Factor etc
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if (sx1272) {
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- mc1= 0x0A; // SX1276_MC1_BW_250 0x80 | SX1276_MC1_CR_4_5 0x02 (MMM define BW)
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+ mc1= 0x0A; // SX1276_MC1_BW_250 0x80 | SX1276_MC1_CR_4_5 0x02 (MMM define BW)
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mc2= ((sf<<4) | crc) % 0xFF;
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// SX1276_MC1_BW_250 0x80 | SX1276_MC1_CR_4_5 0x02 | SX1276_MC1_IMPLICIT_HEADER_MODE_ON 0x01
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if (sf == SF11 || sf == SF12) {
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@@ -217,22 +217,19 @@ void setRate(uint8_t sf, uint8_t crc)
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// For sx1276 chips is the CRC is either ON for receive or OFF for transmit
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else {
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-
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- //if (sf==SF8) {
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- // mc1= 0x78; // SX1276_MC1_BW_125==0x70 | SX1276_MC1_CR_4_8==0x08
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- //}
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- //else {
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- mc1= 0x72; // SX1276_MC1_BW_125==0x70 | SX1276_MC1_CR_4_5==0x02 (4/5)
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- // MMM Read this from the freq table
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- //
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- mc2= ((sf<<4) | crc) & 0xFF; // crc is 0x00 or 0x04==SX1276_MC2_RX_PAYLOAD_CRCON
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- mc3= 0x04; // 0x04; SX1276_MC3_AGCAUTO
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- if (sf == SF11 || sf == SF12) { mc3|= 0x08; } // 0x08 | 0x04
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+
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+ mc1= 0x72; // SX1276_MC1_BW_125==0x70 | SX1276_MC1_CR_4_5==0x02 (4/5)
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+
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+ mc2= ((sf<<4) | crc) & 0xFF; // crc is 0x00 or 0x04==SX1276_MC2_RX_PAYLOAD_CRCON
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+ //mc3= 0x04; // 0x04; SX1276_MC3_AGCAUTO
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+ if (sf == SF11 || sf == SF12) {
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+ mc3|= 0x08; // 0x08 | 0x04
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+ }
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}
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-
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+
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// Implicit Header (IH), for CLASS B beacons (&& SF6)
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//if (getIh(LMIC.rps)) {
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- // mc1 |= SX1276_MC1_IMPLICIT_HEADER_MODE_ON;
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+ // mc1 |= SX1276_MC1_IMPLICIT_HEADER_MODE_ON; // SF6, Not Supported
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// writeRegister(REG_PAYLOAD_LENGTH, getIh(LMIC.rps)); // required length
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//}
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@@ -243,7 +240,8 @@ void setRate(uint8_t sf, uint8_t crc)
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// Symbol timeout settings
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if (sf == SF10 || sf == SF11 || sf == SF12) {
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writeRegister(REG_SYMB_TIMEOUT_LSB, (uint8_t) 0x05);
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- } else {
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+ }
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+ else {
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writeRegister(REG_SYMB_TIMEOUT_LSB, (uint8_t) 0x08);
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}
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return;
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@@ -259,30 +257,39 @@ void setRate(uint8_t sf, uint8_t crc)
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void setFreq(uint32_t freq)
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{
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// set frequency
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- uint64_t frf = ((uint64_t)freq << 19) / 32000000;
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- writeRegister(REG_FRF_MSB, (uint8_t)(frf>>16) );
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- writeRegister(REG_FRF_MID, (uint8_t)(frf>> 8) );
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- writeRegister(REG_FRF_LSB, (uint8_t)(frf>> 0) );
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-
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+ uint32_t frf = (((uint64_t)freq << 19) / 32000000) & 0xFFFFFFFF;
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+ //uint32_t frf = (((uint64_t)(freq << 8)) / 15265) & 0xFFFFFFFF;
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+
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+ writeRegister(REG_FRF_MSB, ((uint8_t)(frf>>16)) & 0xFF );
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+ writeRegister(REG_FRF_MID, ((uint8_t)(frf>> 8)) & 0xFF );
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+ writeRegister(REG_FRF_LSB, ((uint8_t)(frf>> 0)) & 0xFF );
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return;
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}
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// ----------------------------------------------------------------------------------------
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-// Set Power for our gateway
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+// Set Power for our gateway
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+// Note: Power settings for CFG_sx1272 are different
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// ----------------------------------------------------------------------------------------
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-void setPow(uint8_t powe)
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+void setPow(uint8_t pow)
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{
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- if (powe > 15) powe = 15;
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- else if (powe < 2) powe = 2;
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-
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- ASSERT((powe>=2)&&(powe<=15));
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-
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- uint8_t pac = (0x80 | (powe & 0xF)) & 0xFF;
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- writeRegister(REG_PAC, (uint8_t)pac); // set 0x09 to pac
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-
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- // Note: Power settings for CFG_sx1272 are different
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+ uint8_t pac = 0x00;
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+ if (pow > 17) {
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+ pac = 0x8F;
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+ }
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+ else if (pow < 2) {
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+ pac = 2;
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+ }
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+ else if (pow<=12) {
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+ pac=0x20+pow+3;
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+ }
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+ else {
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+ //pac = 0x40 | pow;
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+ pac=0x80+pow-2;
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+ }
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+ ASSERT(((pac&0x0F)>=2) &&((pac&0x0F)<=20));
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+ writeRegister(REG_PAC, (uint8_t) pac); // set register 0x09 to pac
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return;
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}
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@@ -299,10 +306,11 @@ void opmode(uint8_t mode)
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# ifdef CFG_sx1276_radio
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//mode |= 0x08; // TBD: sx1276 high freq
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# endif
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- writeRegister(REG_OPMODE, (uint8_t) mode);
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+ writeRegister(REG_OPMODE, 0xFF & (uint8_t) mode );
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}
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else {
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- writeRegister(REG_OPMODE, (uint8_t)((readRegister(REG_OPMODE) & ~OPMODE_MASK) | mode));
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+ // If in OPMODE_LORA, leave it is (0x80)
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+ writeRegister(REG_OPMODE, 0xFF & (uint8_t)((readRegister(REG_OPMODE) & 0x80) | mode));
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}
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}
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@@ -339,7 +347,7 @@ void hop()
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writeRegister(REG_MAX_PAYLOAD_LENGTH,MAX_PAYLOAD_LENGTH); // set 0x23 to 0x80==128 bytes
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writeRegister(REG_PAYLOAD_LENGTH,PAYLOAD_LENGTH); // 0x22, 0x40==64Byte long
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- writeRegister(REG_FIFO_ADDR_PTR, (uint8_t) readRegister(REG_FIFO_RX_BASE_AD)); // set reg 0x0D to 0x0F
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+ writeRegister(REG_FIFO_ADDR_PTR,(uint8_t)readRegister(REG_FIFO_RX_BASE_AD)); // set reg 0x0D to reg 0x0F(==0x00)
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writeRegister(REG_HOP_PERIOD,0x00); // reg 0x24, set to 0x00
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// 5. Config PA Ramp up time // set reg 0x0A
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@@ -366,7 +374,8 @@ void hop()
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# endif //_MONITOR
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// Remember the last time we hop
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hopTime = micros(); // At what time did we hop
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-}
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+
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+} //hop
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// ------------------------------------- UP -----------------------------------------------
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@@ -408,7 +417,7 @@ uint8_t receivePkt(uint8_t *payload)
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statc.msg_ttl++; // Receive statistics counter
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uint8_t irqflags = readRegister(REG_IRQ_FLAGS); // 0x12; read back flags
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- uint8_t crcUsed = readRegister(REG_HOP_CHANNEL); // Is CRC used? (Register 0x1C)
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+ uint8_t crcUsed = readRegister(REG_HOP_CHANNEL); // Is CRC used? (Register 0x1C)
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if (crcUsed & 0x40) {
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# if _DUSB>=1
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if (( debug>=2) && (pdebug & P_RX )) {
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@@ -416,7 +425,7 @@ uint8_t receivePkt(uint8_t *payload)
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}
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# endif //_DUSB
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}
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-
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+
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// Check for payload IRQ_LORA_CRCERR_MASK=0x20 set
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if (irqflags & IRQ_LORA_CRCERR_MASK) // Is CRC error?
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{
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@@ -429,7 +438,7 @@ uint8_t receivePkt(uint8_t *payload)
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# endif //_MONITOR
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return 0;
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}
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-
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+
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// Is header OK?
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// Please note that if we reset the HEADER interrupt in RX,
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// that we would here conclude that there is no HEADER
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@@ -444,7 +453,7 @@ uint8_t receivePkt(uint8_t *payload)
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writeRegister(REG_IRQ_FLAGS, (uint8_t)(IRQ_LORA_HEADER_MASK | IRQ_LORA_RXDONE_MASK)); // 0x12; clear HEADER (== 0x10) flag
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return 0;
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}
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-
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+
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// If there are no error messages, read the buffer from the FIFO
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// This means "Set FifoAddrPtr to FifoRxBaseAddr"
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else {
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@@ -456,16 +465,16 @@ uint8_t receivePkt(uint8_t *payload)
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}
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if (readRegister(REG_FIFO_RX_CURRENT_ADDR) != readRegister(REG_FIFO_RX_BASE_AD)) {
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-# if _MONITOR>=1
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+# if _MONITOR>=1
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if ((debug>=1) && (pdebug & P_RADIO)) {
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mPrint("RX BASE <" + String(readRegister(REG_FIFO_RX_BASE_AD)) + "> != RX CURRENT <" + String(readRegister(REG_FIFO_RX_CURRENT_ADDR)) + ">" );
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}
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# endif //_MONITOR
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}
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-
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+
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//uint8_t currentAddr = readRegister(REG_FIFO_RX_CURRENT_ADDR); // 0x10
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- uint8_t currentAddr = readRegister(REG_FIFO_RX_BASE_AD); // 0x0F
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- uint8_t receivedCount = readRegister(REG_RX_NB_BYTES); // 0x13; How many bytes were read
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+ uint8_t currentAddr = readRegister(REG_FIFO_RX_BASE_AD); // 0x0F
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+ uint8_t receivedCount = readRegister(REG_RX_BYTES_NB); // 0x13; How many bytes were read
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# if _MONITOR>=1
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if ((debug>=1) && (currentAddr > 64)) { // More than 64 read?
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mPrint("rxPkt:: ERROR Rx addr>64"+String(currentAddr));
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@@ -487,17 +496,15 @@ uint8_t receivePkt(uint8_t *payload)
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payload[i] = readRegister(REG_FIFO); // 0x00, FIFO will auto shift register
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}
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- writeRegister(REG_IRQ_FLAGS, (uint8_t) 0xFF); // Reset ALL interrupts
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-
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// As long as _MONITOR is enabled, and P_RX debug messages are selected,
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// the received packet is displayed on the output.
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-# if _MONITOR>=1
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+# if _MONITOR>=1
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if ((debug>=1) && (pdebug & P_RX)) {
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-
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+
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String response = "^ receivePkt:: rxPkt: t=";
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stringTime(now(), response);
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response += ", f=" + String(gwayConfig.ch) + ", sf=" + String(sf);
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-
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+
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response += ", a=";
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uint8_t DevAddr [4];
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DevAddr[0] = payload[4];
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@@ -505,14 +512,14 @@ uint8_t receivePkt(uint8_t *payload)
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DevAddr[2] = payload[2];
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DevAddr[3] = payload[1];
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printHex((IPAddress)DevAddr, ':', response);
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-
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+
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response += ", flags=" + String(irqflags,HEX);
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response += ", addr=" + String(currentAddr);
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response += ", len=" + String(receivedCount);
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// If debug level 1 is specified, we display the content of the message as well
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// We need to decode the message as well will it make any sense
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-# if _TRUSTED_DECODE>=2
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+# if _LOCALSERVER>=1
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if (debug>=1) { // Must be 1 for operational use
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int index; // The index of the codex struct to decode
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@@ -527,23 +534,30 @@ uint8_t receivePkt(uint8_t *payload)
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}
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// ------------------------------
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-
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+
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Serial.print(F(", data="));
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for (int i=0; i<receivedCount; i++) { // Copy array
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- data[i] = payload[i];
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+ data[i]= payload[i];
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}
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- uint16_t frameCount=payload[7]*256 + payload[6];
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-
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- // The message received has a length, but data starts at byte 9, and stops 4 bytes
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- // before the end since those are MIC bytes
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- uint8_t CodeLength = encodePacket((uint8_t *)(data + 9), receivedCount-9-4, (uint16_t)frameCount, DevAddr, decodes[index].appKey, 0);
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+ uint16_t frameCount= payload[7]*256 + payload[6];
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+
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+ // The message received has a length, but data starts at byte 9,
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+ // and stops 4 bytes before the end since those are MIC bytes
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+ uint8_t CodeLength= encodePacket(
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+ (uint8_t *)(data + 9),
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+ receivedCount-9-4,
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+ (uint16_t)frameCount,
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+ DevAddr,
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+ decodes[index].appKey,
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+ 0
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+ );
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Serial.print(F("- NEW fc="));
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Serial.print(frameCount);
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Serial.print(F(", addr="));
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-
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+
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for (int i=0; i<4; i++) {
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if (DevAddr[i]<=0xF) {
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Serial.print('0');
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@@ -551,15 +565,13 @@ uint8_t receivePkt(uint8_t *payload)
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Serial.print(DevAddr[i], HEX);
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Serial.print(' ');
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}
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-
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Serial.print(F(", len="));
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Serial.print(CodeLength);
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-
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}
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-# endif //_TRUSTED_DECODE
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+# endif //_LOCALSERVER
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mPrint(response); // Print response for Serial or mPrint
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-
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+
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// ONLY on USB
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Serial.print(F(", paylength="));
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Serial.print(receivedCount);
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@@ -571,10 +583,12 @@ uint8_t receivePkt(uint8_t *payload)
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}
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Serial.println();
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}
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-# endif //_MONITOR
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+# endif //_MONITOR
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+
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return(receivedCount);
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}
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+ // Reset all relevant interrupts
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writeRegister(REG_IRQ_FLAGS, (uint8_t) (
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IRQ_LORA_RXDONE_MASK |
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IRQ_LORA_RXTOUT_MASK |
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@@ -582,7 +596,7 @@ uint8_t receivePkt(uint8_t *payload)
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IRQ_LORA_CRCERR_MASK)); // 0x12; Clear RxDone IRQ_LORA_RXDONE_MASK
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return 0;
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-
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+
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} //receivePkt UP
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@@ -604,20 +618,27 @@ bool sendPkt(uint8_t *payLoad, uint8_t payLength)
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{
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# if _MONITOR>=1
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if (payLength>=128) {
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- if (debug>=2) {
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+ if ((debug>=2) && (pdebug & P_TX)) {
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mPrint("V sendPkt:: len="+String(payLength));
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}
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return false;
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}
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# endif //_MONITOR
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+ payLoad[payLength] = 0x00; // terminate buffer
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+
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// MMM?
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writeRegister(REG_FIFO_ADDR_PTR, (uint8_t) readRegister(REG_FIFO_TX_BASE_AD)); // 0x0D, 0x0E
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-
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- writeRegister(REG_PAYLOAD_LENGTH, (uint8_t) payLength); // 0x22
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- payLoad[payLength] = 0x00; // terminate buffer
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+ writeRegister(REG_PAYLOAD_LENGTH, (uint8_t) payLength); // 0x22
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+
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writeBuffer(REG_FIFO, (uint8_t *) payLoad, payLength);
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-
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+
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+# if _MONITOR>=1
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+ if ((debug >=1) && (pdebug & P_TX)) {
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+ mPrint("sendPkt:: payLength="+String(payLength)+", REG_FIFO=0x"+String(readRegister(REG_FIFO),HEX) );
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+ }
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+# endif
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+
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return true;
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} // sendPkt()
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@@ -658,14 +679,14 @@ int loraWait(struct LoraDown *LoraDown)
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return(1);
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}
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- int32_t delayTmst = (int32_t)(LoraDown->tmst - micros()) + gwayConfig.txDelay;
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+ int32_t delayTmst = (int32_t)(LoraDown->tmst - micros()) -1000 + gwayConfig.txDelay;
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// delayTmst based on txDelay and spreading factor
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- if ((delayTmst > 8000000) || (delayTmst < 0)) { // Delay is > 8 secs or less than 0
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+ if ((delayTmst > 8000000) || (delayTmst < -1000)) { // Delay is > 8 secs or less than 0
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# if _MONITOR>=1
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if (delayTmst > 8000000) {
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String response= "v loraWait:: ERROR: ";
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- printDwn(LoraDown,response);
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+ printDwn(LoraDown, response);
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mPrint(response);
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}
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else {
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@@ -712,8 +733,8 @@ int loraWait(struct LoraDown *LoraDown)
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// 6. config Power
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// 7. RegLoRaSyncWord LORA_MAC_PREAMBLE
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// 8. write REG dio mapping (dio0)
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-// 9. write REG IRQ flags
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-// 10. write REG IRQ mask
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+// 9. write REG IRQ mask
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+// 10. write REG IRQ flags
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// 11. write REG LoRa Fifo Base Address
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// 12. write REG LoRa Fifo Addr Ptr
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// 13. write REG LoRa Payload Length
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@@ -729,81 +750,74 @@ void txLoraModem(struct LoraDown *LoraDown)
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_state = S_TX;
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// 1. Select LoRa modem from sleep mode
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- //opmode(OPMODE_SLEEP);
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- //opmode(OPMODE_LORA); // set register 0x01 to 0x80
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+ //opmode(OPMODE_SLEEP); // set 0x01
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+ //opmode(OPMODE_LORA); // set 0x01 to 0x80
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// Assert the value of the current mode
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ASSERT((readRegister(REG_OPMODE) & OPMODE_LORA) != 0);
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// 2. enter standby mode (required for FIFO loading))
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- opmode(OPMODE_STANDBY); // set 0x01 to 0x01
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+ opmode(OPMODE_STANDBY); // set 0x01 to 0x01
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// 3. Init spreading factor and other Modem setting
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setRate(LoraDown->sf, LoraDown->crc);
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// Frequency hopping
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- //writeRegister(REG_HOP_PERIOD, (uint8_t) 0x00); // set 0x24 to 0x00 only for receivers
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+ //writeRegister(REG_HOP_PERIOD, (uint8_t) 0x00); // set 0x24 to 0x00 only for receivers
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// 4. Init Frequency, config channel
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setFreq(LoraDown->freq);
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+ writeRegister(REG_SYNC_WORD, (uint8_t) 0x34); // set 0x39 to 0x34==LORA_MAC_PREAMBLE
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+ writeRegister(REG_PREAMBLE_LSB, (uint8_t) LoraDown->prea & 0xFF);
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+ writeRegister(REG_PARAMP, (readRegister(REG_PARAMP) & 0xF0) | 0x08); // set 0x0A ramp-up time 50 uSec
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+ writeRegister(REG_PADAC_SX1276, 0x84); // set 0x4D (PADAC) to 0x84
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+ writeRegister(REG_DET_TRESH, 0x0A); // Detection Treshhold
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+ writeRegister(REG_LNA, (uint8_t) LNA_MAX_GAIN); // set reg 0x0C to 0x23
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+
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|
// 6. Set power level, REG_PAC
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|
|
setPow(LoraDown->powe);
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|
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// 7. prevent node to node communication
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- writeRegister(REG_INVERTIQ, readRegister(REG_INVERTIQ) | (uint8_t)(LoraDown->iiq)); // 0x33, (0x27 up or |0x40 down)
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+ //writeRegister(REG_INVERTIQ, readRegister(REG_INVERTIQ) | (uint8_t)(LoraDown->iiq)); // set 0x33, (0x27 up or |0x40 down)
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+ writeRegister(REG_INVERTIQ, readRegister(REG_INVERTIQ) | (uint8_t)(LoraDown->iiq)); // set 0x33 to (0x27 (reserved) | 0x40) for downstream
|
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|
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|
|
// 8. set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP (or less for 1ch gateway)
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|
|
writeRegister(REG_DIO_MAPPING_1, (uint8_t)(
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|
|
MAP_DIO0_LORA_TXDONE |
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|
|
MAP_DIO1_LORA_NOP |
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|
|
MAP_DIO2_LORA_NOP |
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|
|
- MAP_DIO3_LORA_NOP)); // was MAP_DIO3_LORA_CRC
|
|
|
-
|
|
|
- // 9. clear all radio IRQ flags
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|
|
- writeRegister(REG_IRQ_FLAGS, (uint8_t) 0xFF);
|
|
|
-
|
|
|
- // 10. mask all IRQs but TxDone
|
|
|
+ MAP_DIO3_LORA_NOP)); // was MAP_DIO3_LORA_CRC
|
|
|
+
|
|
|
+ // 9. mask all IRQs but TxDone
|
|
|
writeRegister(REG_IRQ_FLAGS_MASK, (uint8_t) ~IRQ_LORA_TXDONE_MASK);
|
|
|
|
|
|
- // txLora
|
|
|
- opmode(OPMODE_FSTX); // set reg 0x01 to 0x02 (actual value becomes 0x82)
|
|
|
-
|
|
|
- // 11, 12, 13, 14. write the buffer to the FiFo
|
|
|
- sendPkt(LoraDown->payLoad, LoraDown->size);
|
|
|
-
|
|
|
+ // 10. clear all radio IRQ flags
|
|
|
+ writeRegister(REG_IRQ_FLAGS, (uint8_t) 0xFF);
|
|
|
+ //writeRegister(REG_IRQ_FLAGS, (uint8_t) IRQ_LORA_TXDONE_MASK); // set reg 0x12 to 0x08, clear TXDONE
|
|
|
+
|
|
|
+ // FSTX setting
|
|
|
+ opmode(OPMODE_FSTX); // set reg 0x01 to 0x02 (actual value becomes 0x82)
|
|
|
+ delay(1); // MMM
|
|
|
+
|
|
|
//Set the base addres of the transmit buffer in FIFO
|
|
|
writeRegister(REG_FIFO_ADDR_PTR, (uint8_t) readRegister(REG_FIFO_TX_BASE_AD)); // set 0x0D to 0x0F (contains 0x80);
|
|
|
-
|
|
|
+
|
|
|
//For TX we have to set the PAYLOAD_LENGTH
|
|
|
- writeRegister(REG_PAYLOAD_LENGTH, (uint8_t) LoraDown->size); // set reg 0x22 to 0x40==64Byte long
|
|
|
-
|
|
|
+ writeRegister(REG_PAYLOAD_LENGTH, (uint8_t) LoraDown->size); // set reg 0x22 to 0x40==64Byte long
|
|
|
+
|
|
|
//For TX we have to set the MAX_PAYLOAD_LENGTH
|
|
|
writeRegister(REG_MAX_PAYLOAD_LENGTH, (uint8_t) MAX_PAYLOAD_LENGTH); // set reg 0x22, max 0x40==64Byte long
|
|
|
+
|
|
|
+ // 11, 12, 13, 14. write the buffer to the FiFo
|
|
|
+ sendPkt(LoraDown->payLoad, LoraDown->size);
|
|
|
|
|
|
- // Reset the IRQ register
|
|
|
- writeRegister(REG_IRQ_FLAGS_MASK, (uint8_t) 0x00); // Clear the mask
|
|
|
-// writeRegister(REG_IRQ_FLAGS, (uint8_t) IRQ_LORA_TXDONE_MASK); // set reg 0x12 to 0x08, clear TXDONE
|
|
|
- writeRegister(REG_IRQ_FLAGS, (uint8_t) 0xFF); // set reg 0x12 to 0xFF, clear TXDONE and others
|
|
|
-
|
|
|
- // 16. Initiate actual transmission of FiFo
|
|
|
- opmode(OPMODE_TX); // set reg 0x01 to 0x03 (actual value becomes 0x83)
|
|
|
+ // 16. Initiate actual transmission of FiFo, after opmode TX it switches to standby mode
|
|
|
+ delay(5); // MMM works
|
|
|
+ opmode(OPMODE_TX); // set reg 0x01 to 0x03 (actual value becomes 0x83)
|
|
|
|
|
|
// After message transmitted the sender switches to STANDBY state, and issues TXDONE
|
|
|
|
|
|
-# if _MONITOR>=1
|
|
|
- if ((debug>=1) && (pdebug & P_TX)) {
|
|
|
- String response = "v txLoraModem:: end=";
|
|
|
- printDwn(LoraDown, response);
|
|
|
- response += ", size=" + String(LoraDown->size);
|
|
|
- response += ", data=";
|
|
|
- for(int i=0; i<LoraDown->size; i++) {
|
|
|
- response += String(LoraDown->payLoad[i],HEX) + " ";
|
|
|
- }
|
|
|
- mPrint(response);
|
|
|
- }
|
|
|
-# endif //_MONITOR
|
|
|
-
|
|
|
}// txLoraModem
|
|
|
|
|
|
|
|
@@ -858,9 +872,9 @@ void rxLoraModem()
|
|
|
|
|
|
// 5. Accept no interrupts except RXDONE, RXTOUT en RXCRC
|
|
|
writeRegister(REG_IRQ_FLAGS_MASK, (uint8_t) ~(
|
|
|
- IRQ_LORA_RXDONE_MASK |
|
|
|
- IRQ_LORA_RXTOUT_MASK |
|
|
|
- IRQ_LORA_HEADER_MASK |
|
|
|
+ IRQ_LORA_RXDONE_MASK |
|
|
|
+ IRQ_LORA_RXTOUT_MASK |
|
|
|
+ IRQ_LORA_HEADER_MASK |
|
|
|
IRQ_LORA_CRCERR_MASK));
|
|
|
|
|
|
// set frequency hopping
|
|
@@ -1011,20 +1025,23 @@ void initLoraModem()
|
|
|
|
|
|
// 5. Set chip type/version
|
|
|
uint8_t version = readRegister(REG_VERSION); // read reg 0x34 the LoRa chip version id
|
|
|
- if (version == 0x22) { // sx1272==0x22
|
|
|
-# if _DUSB>=2
|
|
|
- Serial.println(F("WARNING:: SX1272 detected"));
|
|
|
+ if (version == 0x12) { // sx1276==0x12
|
|
|
+# if _DUSB>=1
|
|
|
+ if ((debug>=2) && (pdebug & P_MAIN)) {
|
|
|
+ Serial.println(F("SX1276 starting"));
|
|
|
+ }
|
|
|
+# endif
|
|
|
+ sx1272= false;
|
|
|
+ }
|
|
|
+ else if (version == 0x22) { // sx1272==0x22
|
|
|
+# if _DUSB>=1
|
|
|
+ if ((debug>=1) && (pdebug & P_MAIN)) {
|
|
|
+ Serial.println(F("WARNING:: SX1272 detected"));
|
|
|
+ }
|
|
|
# endif
|
|
|
- sx1272 = true;
|
|
|
+ sx1272= true;
|
|
|
}
|
|
|
|
|
|
- else if (version == 0x12) { // sx1276==0x12
|
|
|
-# if _DUSB>=2
|
|
|
- if (debug >=1)
|
|
|
- Serial.println(F("SX1276 starting"));
|
|
|
-# endif
|
|
|
- sx1272 = false;
|
|
|
- }
|
|
|
else {
|
|
|
// Normally this means that we connected the wrong type of board and
|
|
|
// therefore specified the wrong type of wiring/pins to the software
|
|
@@ -1066,7 +1083,7 @@ void initLoraModem()
|
|
|
// Set 0x4D PADAC for SX1276 ; XXX register is 0x5a for sx1272
|
|
|
//Semtech rev. 5, Aug 2016, para
|
|
|
writeRegister(REG_PADAC_SX1276, 0x84); // set reg 0x4D (PADAC) to 0x84
|
|
|
- //writeRegister(REG_PADAC, readRegister(REG_PADAC) | 0x4);
|
|
|
+ //writeRegister(REG_PADAC_SX1276, readRegister(REG_PADAC_SX1276) | 0x4);
|
|
|
|
|
|
// Set treshold according to sx1276 specs
|
|
|
writeRegister(REG_DET_TRESH, 0x0A);
|