loraModem.h 21 KB

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  1. // 1-channel LoRa Gateway for ESP8266
  2. // Copyright (c) 2016, 2017, 2018, 2019 Maarten Westenberg version for ESP8266
  3. //
  4. // based on work done by Thomas Telkamp for Raspberry PI 1ch gateway
  5. // and many other contributors.
  6. //
  7. // All rights reserved. This program and the accompanying materials
  8. // are made available under the terms of the MIT License
  9. // which accompanies this distribution, and is available at
  10. // https://opensource.org/licenses/mit-license.php
  11. //
  12. // NO WARRANTY OF ANY KIND IS PROVIDED
  13. //
  14. // Author: Maarten Westenberg (mw12554@hotmail.com)
  15. //
  16. // This file contains a number of compile-time settings and declarations that are
  17. // specific to the LoRa rfm95, sx1276, sx1272 radio of the gateway.
  18. //
  19. //
  20. // ------------------------------------------------------------------------------------
  21. // ----------------------------------------
  22. // Used by REG_PAYLOAD_LENGTH to set receive payload length
  23. #define PAYLOAD_LENGTH 0x40 // 64 bytes
  24. #define MAX_PAYLOAD_LENGTH 0x80 // 128 bytes
  25. // In order to make the CAD behaviour dynamic we set a variable
  26. // when the CAD functions are defined. Value of 3 is minimum frequencies a
  27. // gateway should support to be fully LoRa compliant.
  28. // For performance reasons, 3 is the maximum as well!
  29. //
  30. #define NUM_HOPS 3
  31. // Do not change these setting for RSSI detection. They are used for CAD
  32. // Given the correction factor of 157, we can get to -122dB with this rating
  33. //
  34. #define RSSI_LIMIT 35 //
  35. // How long to wait in LoRa mode before using the RSSI value.
  36. // This period should be as short as possible, yet sufficient
  37. //
  38. #define RSSI_WAIT 6 // was 25
  39. // How long will it take when hopping before a CDONE or CDETD value
  40. // is present and can be measured.
  41. //
  42. #define EVENT_WAIT 15000 // XXX 180520 was 25 milliseconds before CDDETD timeout
  43. #define DONE_WAIT 1950 // 2000 microseconds (1/500) sec between CDDONE events
  44. // SPI setting. 8MHz seems to be the max
  45. #define SPISPEED 8000000 // Set to 8 * 10E6
  46. // Frequencies
  47. // Set center frequency. If in doubt, choose the first one, comment out all others
  48. // Each "real" gateway should support the first 3 frequencies according to LoRa spec.
  49. // NOTE: This means you have to specify at least 3 frequencies here for the single
  50. // channel gateway to work.
  51. struct vector {
  52. // Upstream messages
  53. uint32_t upFreq; // 4 bytes
  54. uint16_t upBW; // 2 bytes
  55. uint8_t upLo; // 1 bytes
  56. uint8_t upHi; // 1 bytes
  57. // Downstream messages
  58. uint32_t dwnFreq; // 4 bytes Unsigned ubt Frequency
  59. uint16_t dwnBW; // 2 bytes BW Specification
  60. uint8_t dwnLo; // 1 bytes Spreading Factor
  61. uint8_t dwnHi; // 1 bytes
  62. };
  63. #ifdef EU863_870
  64. // This the the EU863_870 format as used in most of Europe
  65. // It is also the default for most of the single channel gateway work.
  66. // For each frequency SF7-SF12 are used.
  67. vector freqs [] =
  68. {
  69. { 868100000, 125, 7, 12, 868100000, 125, 7, 12}, // Channel 0, 868.1 MHz/125 primary
  70. { 868300000, 125, 7, 12, 868300000, 125, 7, 12}, // Channel 1, 868.3 MHz/125 mandatory and (SF7BW250)
  71. { 868500000, 125, 7, 12, 868500000, 125, 7, 12}, // Channel 2, 868.5 MHz/125 mandatory
  72. { 867100000, 125, 7, 12, 867100000, 125, 7, 12}, // Channel 3, 867.1 MHz/125 Optional
  73. { 867300000, 125, 7, 12, 867300000, 125, 7, 12}, // Channel 4, 867.3 MHz/125 Optional
  74. { 867500000, 125, 7, 12, 867500000, 125, 7, 12}, // Channel 5, 867.5 MHz/125 Optional
  75. { 867700000, 125, 7, 12, 867700000, 125, 7, 12}, // Channel 6, 867.7 MHz/125 Optional
  76. { 867900000, 125, 7, 12, 867900000, 125, 7, 12}, // Channel 7, 867.9 MHz/125 Optional
  77. { 868800000, 125, 7, 12, 868800000, 125, 7, 12}, // Channel 8, 868.9 MHz/125 FSK Only
  78. { 0, 0 , 0, 0, 869525000, 125, 9, 9} // Channel 9, 869.5 MHz/125 for RX2 responses SF9(10%)
  79. // TTN defines an additional channel at 869.525 MHz using SF9 for class B. Not used
  80. };
  81. #elif defined(EU433)
  82. // The following 3 frequencies should be defined/used in an EU433
  83. // environment. The plan is not defined for TTN yet so we use this one.
  84. vector freqs [] = {
  85. { 433175000, 125, 7, 12, 433175000, 125, 7, 12}, // Channel 0, 433.175 MHz/125 primary
  86. { 433375000, 125, 7, 12, 433375000, 125, 7, 12}, // Channel 1, 433.375 MHz primary
  87. { 433575000, 125, 7, 12, 433575000, 125, 7, 12}, // Channel 2, 433.575 MHz primary
  88. { 433775000, 125, 7, 12, 433775000, 125, 7, 12}, // Channel 3, 433.775 MHz primary
  89. { 433975000, 125, 7, 12, 433975000, 125, 7, 12}, // Channel 4, 433.975 MHz primary
  90. { 434175000, 125, 7, 12, 434175000, 125, 7, 12}, // Channel 5, 434.175 MHz primary
  91. { 434375000, 125, 7, 12, 434375000, 125, 7, 12}, // Channel 6, 434.375 MHz primary
  92. { 434575000, 125, 7, 12, 434575000, 125, 7, 12}, // Channel 7, 434.575 MHz primary
  93. { 434775000, 125, 7, 12, 434775000, 125, 7, 12} // Channel 8, 434.775 MHz primary
  94. };
  95. #elif defined(US902_928)
  96. // The frequency plan for USA is a difficult one. As yout can see, the uplink protocol uses
  97. // SF7-SF10 and BW125 whereas the downlink protocol uses SF7-SF12 and BW500.
  98. // Also the number of chanels is not equal.
  99. vector freqs [] = {
  100. // Uplink
  101. { 903900000, 125, 7, 10, 923300000, 500, 7, 12}, // Up Ch 0, SF7BW125 to SF10BW125 primary
  102. { 904100000, 125, 7, 10, 923900000, 500, 7, 12}, // Up Ch 1, SF7BW125 to SF10BW125
  103. { 904300000, 125, 7, 10, 924500000, 500, 7, 12}, // Up Ch 2, SF7BW125 to SF10BW125, Dwn SF7-SF12 924,5 BW500
  104. { 904500000, 125, 7, 10, 925100000, 500, 7, 12}, // Up Ch 3, SF7BW125 to SF10BW125, Dwn SF7-SF12 925,1 BW500
  105. { 904700000, 125, 7, 10, 925700000, 500, 7, 12}, // Up Ch 3, SF7BW125 to SF10BW125, Dwn SF7-SF12 925,1
  106. { 904900000, 125, 7, 10, 926300000, 500, 7, 12}, // Up Ch 4, SF7BW125 to SF10BW125, Dwn SF7-SF12
  107. { 905100000, 125, 7, 10, 926900000, 500, 7, 12}, // Up Ch 5, SF7BW125 to SF10BW125, Dwn SF7-SF12
  108. { 905300000, 125, 7, 10, 927500000, 500, 7, 12}, // Up Ch 6, SF7BW125 to SF10BW125, Dwn SF7-SF12
  109. { 904600000, 500, 8, 8, 0 , 0, 0, 00}, // Up Ch 7, SF8BW5000, no Dwn 0 // SFxxxBW500
  110. };
  111. #elif defined(AU925_928)
  112. // Australian plan or TTN/Lora frequencies
  113. vector freqs [] = {
  114. { 916800000, 125, 7, 10, 916800000, 125, 7, 12}, // Channel 0, 916.8 MHz primary
  115. { 917000000, 125, 7, 10, 917000000, 125, 7, 12}, // Channel 1, 917.0 MHz mandatory
  116. { 917200000, 125, 7, 10, 917200000, 125, 7, 12}, // Channel 2, 917.2 MHz mandatory
  117. { 917400000, 125, 7, 10, 917400000, 125, 7, 12}, // Channel 3, 917.4 MHz Optional
  118. { 917600000, 125, 7, 10, 917600000, 125, 7, 12}, // Channel 4, 917.6 MHz Optional
  119. { 917800000, 125, 7, 10, 917800000, 125, 7, 12}, // Channel 5, 917.8 MHz Optional
  120. { 918000000, 125, 7, 10, 918000000, 125, 7, 12}, // Channel 6, 918.0 MHz Optional
  121. { 918200000, 125, 7, 10, 918200000, 125, 7, 12} , // Channel 7, 918.2 MHz Optional
  122. { 917500000, 500, 8, 8, 0, 0, 0, 0} // Channel 8, 917.5 SF8BW500 MHz Optional Uplink
  123. };
  124. #elif defined(CN470_510)
  125. // China plan for TTN frequencies
  126. vector freqs [] = {
  127. { 486300000, 125, 7, 12, 486300000, 125, 7, 12}, // 486.3 - SF7BW125 to SF12BW125
  128. { 486500000, 125, 7, 12, 486500000, 125, 7, 12}, // 486.5 - SF7BW125 to SF12BW125
  129. { 486700000, 125, 7, 12, 486700000, 125, 7, 12}, // 486.7 - SF7BW125 to SF12BW125
  130. { 486900000, 125, 7, 12, 486900000, 125, 7, 12}, // 486.9 - SF7BW125 to SF12BW125
  131. { 487100000, 125, 7, 12, 487100000, 125, 7, 12}, // 487.1 - SF7BW125 to SF12BW125
  132. { 487300000, 125, 7, 12, 487300000, 125, 7, 12}, // 487.3 - SF7BW125 to SF12BW125
  133. { 487500000, 125, 7, 12, 487500000, 125, 7, 12}, // 487.5 - SF7BW125 to SF12BW125
  134. { 487700000, 125, 7, 12, 487700000, 125, 7, 12} // 487.7 - SF7BW125 to SF12BW125
  135. };
  136. #elif defined(IN865_867)
  137. vector freqs [] = {
  138. { 865062500, 125, 7, 12, 865062500, 125, 7, 12}, // And RX1
  139. { 865402500, 125, 7, 12, 865402500, 125, 7, 12},
  140. { 865985000, 125, 7, 12, 865985000, 125, 7, 12},
  141. { 0, 0, 0, 0, 866550000, 125, 10, 10} // RX2
  142. };
  143. #else
  144. int freqs [] = {
  145. // Print an Error, Not supported
  146. # error "Sorry, but your frequency plan is not supported"
  147. };
  148. #endif
  149. // Set the structure for spreading factor
  150. enum sf_t { SF6=6, SF7, SF8, SF9, SF10, SF11, SF12 };
  151. // The state of the receiver. See Semtech Datasheet (rev 4, March 2015) page 43
  152. // The _state is of the enum type (and should be cast when used as a number)
  153. enum state_t { S_INIT=0, S_SCAN, S_CAD, S_RX, S_TX, S_TXDONE};
  154. volatile state_t _state=S_INIT;
  155. volatile uint8_t _event=0;
  156. // rssi is measured at specific moments and reported on others
  157. // so we need to store the current value we like to work with
  158. uint8_t _rssi;
  159. bool _cad= (bool) _CAD; // Set to true for Channel Activity Detection, only when dio 1 connected
  160. bool _hop= (bool) false;// experimental; frequency hopping. Only use when dio2 connected
  161. unsigned long nowTime=0;
  162. unsigned long msgTime=0;
  163. unsigned long hopTime=0;
  164. unsigned long detTime=0;
  165. #if _PIN_OUT==1
  166. // ----------------------------------------------------------------------------
  167. // Definition of the GPIO pins used by the Gateway for Hallard type boards
  168. //
  169. struct pins {
  170. uint8_t dio0=15; // GPIO15 / D8. For the Hallard board shared between DIO0/DIO1/DIO2
  171. uint8_t dio1=15; // GPIO15 / D8. Used for CAD, may or not be shared with DIO0
  172. uint8_t dio2=15; // GPIO15 / D8. Used for frequency hopping, don't care
  173. uint8_t ss=16; // GPIO16 / D0. Select pin connected to GPIO16 / D0
  174. uint8_t rst=0; // GPIO 0 / D3. Reset pin not used
  175. // MISO 12 / D6
  176. // MOSI 13 / D7
  177. // CLK 14 / D5
  178. } pins;
  179. #elif _PIN_OUT==2
  180. // ----------------------------------------------------------------------------
  181. // For ComResult gateway PCB use the following settings
  182. struct pins {
  183. uint8_t dio0=5; // GPIO5 / D1. Dio0 used for one frequency and one SF
  184. uint8_t dio1=4; // GPIO4 / D2. Used for CAD, may or not be shared with DIO0
  185. uint8_t dio2=0; // GPIO0 / D3. Used for frequency hopping, don't care
  186. uint8_t ss=15; // GPIO15 / D8. Select pin connected to GPIO15
  187. uint8_t rst=0; // GPIO0 / D3. Reset pin not used
  188. } pins;
  189. #elif _PIN_OUT==3
  190. // ----------------------------------------------------------------------------
  191. // For ESP32/Wemos based board
  192. // SCK == GPIO5/ PIN5
  193. // SS == GPIO18/PIN18
  194. // MISO == GPIO19/ PIN19
  195. // MOSI == GPIO27/ PIN27
  196. // RST == GPIO14/ PIN14
  197. // This Pinning is not used and is under construction
  198. struct pins {
  199. uint8_t dio0=26; // GPIO26 / Dio0 used for one frequency and one SF
  200. uint8_t dio1=26; // GPIO26 / Used for CAD, may or not be shared with DIO0
  201. uint8_t dio2=26; // GPI2O6 / Used for frequency hopping, don't care
  202. uint8_t ss=18; // GPIO18 / Dx. Select pin connected to GPIO18
  203. uint8_t rst=14; // GPIO0 / D3. Reset pin not used
  204. } pins;
  205. #elif _PIN_OUT==4
  206. // ----------------------------------------------------------------------------
  207. // For ESP32/TTGO based board.
  208. // SCK == GPIO5/ PIN5
  209. // SS == GPIO18/ PIN18 CS
  210. // MISO == GPIO19/ PIN19
  211. // MOSI == GPIO27/ PIN27
  212. // RST == GPIO14/ PIN14
  213. struct pins {
  214. uint8_t dio0=26; // GPIO26 / Dio0 used for one frequency and one SF
  215. uint8_t dio1=33; // GPIO33 / Used for CAD, may or not be shared with DIO0
  216. uint8_t dio2=32; // GPIO32 / Used for frequency hopping, don't care
  217. uint8_t ss=18; // GPIO18 / CS. Select pin connected to GPIO18
  218. uint8_t rst=14; // GPIO14 / D3. Reset pin not used
  219. } pins;
  220. #define SCK 5
  221. #define MISO 19
  222. #define MOSI 27
  223. #define RST 14
  224. #define SS 18
  225. #if _GPS==1
  226. #define GPS_RX 15
  227. #define GPS_TX 12
  228. #endif // _GPS
  229. #else
  230. // ----------------------------------------------------------------------------
  231. // Use your own pin definitions, and comment #error line below
  232. // MISO 12 / D6
  233. // MOSI 13 / D7
  234. // CLK 14 / D5
  235. // SS 16 / D0
  236. #error "Pin Definitions _PIN_OUT must be defined in loraModem.h"
  237. #endif
  238. // stat_t contains the statistics that are kept by message.
  239. // Each time a message is received or sent the statistics are updated.
  240. // In case _STATISTICS==1 we define the last MAX_STAT messages as statistics
  241. struct stat_t {
  242. unsigned long tmst; // Time since 1970 in seconds
  243. unsigned long node; // 4-byte DEVaddr (the only one known to gateway)
  244. uint8_t ch; // Channel index to freqs array
  245. uint8_t sf;
  246. #if RSSI==1
  247. int8_t rssi; // XXX Can be < -128
  248. #endif
  249. int8_t prssi; // XXX Can be < -128
  250. #if _LOCALSERVER==1
  251. uint8_t data[23]; // For memory purposes, only 23 chars
  252. uint8_t datal; // Length of decoded message 1 char
  253. #endif
  254. } stat_t;
  255. #if _STATISTICS >= 1
  256. // statc_c contains the statistic that are gateway related and not per
  257. // message. Example: Number of messages received on SF7 or number of (re) boots
  258. // So where statr contains the statistics gathered per packet the statc_c
  259. // contains general statistics of the node
  260. struct stat_c {
  261. unsigned long msg_ok;
  262. unsigned long msg_ttl;
  263. unsigned long msg_down;
  264. #if _STATISTICS >= 2 // Only if we explicitly set it higher
  265. unsigned long sf7; // Spreading factor 7 statistics/Count
  266. unsigned long sf8; // Spreading factor 8
  267. unsigned long sf9; // Spreading factor 9
  268. unsigned long sf10; // Spreading factor 10
  269. unsigned long sf11; // Spreading factor 11
  270. unsigned long sf12; // Spreading factor 12
  271. // If _STATISTICS is 3, we add statistics about the channel
  272. // When only one channel is used, we normally know the spread of
  273. // statistics, but when HOP mode is selected we migth want to add this info
  274. #if _STATISTICS >=3
  275. unsigned long msg_ok_0, msg_ok_1, msg_ok_2;
  276. unsigned long msg_ttl_0, msg_ttl_1, msg_ttl_2;
  277. unsigned long msg_down_0, msg_down_1, msg_down_2;
  278. unsigned long sf7_0, sf7_1, sf7_2;
  279. unsigned long sf8_0, sf8_1, sf8_2;
  280. unsigned long sf9_0, sf9_1, sf9_2;
  281. unsigned long sf10_0, sf10_1, sf10_2;
  282. unsigned long sf11_0, sf11_1, sf11_2;
  283. unsigned long sf12_0, sf12_1, sf12_2;
  284. #endif //3
  285. uint16_t boots; // Number of boots
  286. uint16_t resets;
  287. #endif // 2
  288. } stat_c;
  289. struct stat_c statc;
  290. // History of received uplink and downlink messages from nodes
  291. struct stat_t statr[MAX_STAT];
  292. #else // _STATISTICS==0
  293. struct stat_t statr[1]; // Always have at least one element to store in
  294. #endif
  295. // Define the payload structure used to separate interrupt ans SPI
  296. // processing from the loop() part
  297. uint8_t payLoad[128]; // Payload i
  298. struct LoraBuffer {
  299. uint8_t * payLoad;
  300. uint8_t payLength;
  301. uint32_t tmst; // in millis()
  302. uint8_t sfTx;
  303. uint8_t powe;
  304. uint32_t fff;
  305. uint8_t crc;
  306. uint8_t iiq;
  307. } LoraDown;
  308. // Up buffer (from Lora sensor to UDP)
  309. // This struct contains all data of the buffer received from devices to gateway
  310. struct LoraUp {
  311. uint8_t payLoad[128];
  312. uint8_t payLength;
  313. int prssi;
  314. long snr;
  315. int rssicorr;
  316. uint8_t sf;
  317. } LoraUp;
  318. // ============================================================================
  319. // Set all definitions for Gateway
  320. // ============================================================================
  321. // Register definitions. These are the addresses of the RFM95, SX1276 that we
  322. // need to set in the program.
  323. #define REG_FIFO 0x00 // rw FIFO address
  324. #define REG_OPMODE 0x01
  325. // Register 2 to 5 are unused for LoRa
  326. #define REG_FRF_MSB 0x06
  327. #define REG_FRF_MID 0x07
  328. #define REG_FRF_LSB 0x08
  329. #define REG_PAC 0x09
  330. #define REG_PARAMP 0x0A
  331. #define REG_LNA 0x0C
  332. #define REG_FIFO_ADDR_PTR 0x0D // rw SPI interface address pointer in FIFO data buffer
  333. #define REG_FIFO_TX_BASE_AD 0x0E // rw write base address in FIFO data buffer for TX modulator
  334. #define REG_FIFO_RX_BASE_AD 0x0F // rw read base address in FIFO data buffer for RX demodulator (0x00)
  335. #define REG_FIFO_RX_CURRENT_ADDR 0x10 // r Address of last packet received
  336. #define REG_IRQ_FLAGS_MASK 0x11
  337. #define REG_IRQ_FLAGS 0x12
  338. #define REG_RX_NB_BYTES 0x13
  339. #define REG_PKT_SNR_VALUE 0x19
  340. #define REG_PKT_RSSI 0x1A // latest package
  341. #define REG_RSSI 0x1B // Current RSSI, section 6.4, or 5.5.5
  342. #define REG_HOP_CHANNEL 0x1C
  343. #define REG_MODEM_CONFIG1 0x1D
  344. #define REG_MODEM_CONFIG2 0x1E
  345. #define REG_SYMB_TIMEOUT_LSB 0x1F
  346. #define REG_PAYLOAD_LENGTH 0x22
  347. #define REG_MAX_PAYLOAD_LENGTH 0x23
  348. #define REG_HOP_PERIOD 0x24
  349. #define REG_MODEM_CONFIG3 0x26
  350. #define REG_RSSI_WIDEBAND 0x2C
  351. #define REG_INVERTIQ 0x33
  352. #define REG_DET_TRESH 0x37 // SF6
  353. #define REG_SYNC_WORD 0x39
  354. #define REG_TEMP 0x3C
  355. #define REG_DIO_MAPPING_1 0x40
  356. #define REG_DIO_MAPPING_2 0x41
  357. #define REG_VERSION 0x42
  358. #define REG_PADAC 0x5A
  359. #define REG_PADAC_SX1272 0x5A
  360. #define REG_PADAC_SX1276 0x4D
  361. // ----------------------------------------
  362. // opModes
  363. #define SX72_MODE_SLEEP 0x80
  364. #define SX72_MODE_STANDBY 0x81
  365. #define SX72_MODE_FSTX 0x82
  366. #define SX72_MODE_TX 0x83 // 0x80 | 0x03
  367. #define SX72_MODE_RX_CONTINUOS 0x85
  368. // ----------------------------------------
  369. // LMIC Constants for radio registers
  370. #define OPMODE_LORA 0x80
  371. #define OPMODE_MASK 0x07
  372. #define OPMODE_SLEEP 0x00
  373. #define OPMODE_STANDBY 0x01
  374. #define OPMODE_FSTX 0x02
  375. #define OPMODE_TX 0x03
  376. #define OPMODE_FSRX 0x04
  377. #define OPMODE_RX 0x05
  378. #define OPMODE_RX_SINGLE 0x06
  379. #define OPMODE_CAD 0x07
  380. // ----------------------------------------
  381. // LOW NOISE AMPLIFIER
  382. #define LNA_MAX_GAIN 0x23 // Max gain 0x20 | Boost 0x03
  383. #define LNA_OFF_GAIN 0x00
  384. #define LNA_LOW_GAIN 0x20
  385. // CONF REG
  386. #define REG1 0x0A
  387. #define REG2 0x84
  388. // ----------------------------------------
  389. // MC1 sx1276 RegModemConfig1
  390. #define SX1276_MC1_BW_125 0x70
  391. #define SX1276_MC1_BW_250 0x80
  392. #define SX1276_MC1_BW_500 0x90
  393. #define SX1276_MC1_CR_4_5 0x02 // sx1276
  394. #define SX1276_MC1_CR_4_6 0x04
  395. #define SX1276_MC1_CR_4_7 0x06
  396. #define SX1276_MC1_CR_4_8 0x08
  397. #define SX1276_MC1_IMPLICIT_HEADER_MODE_ON 0x01
  398. #define SX72_MC1_LOW_DATA_RATE_OPTIMIZE 0x01 // mandated for SF11 and SF12
  399. // ----------------------------------------
  400. // MC2 definitions
  401. #define SX72_MC2_FSK 0x00
  402. #define SX72_MC2_SF7 0x70 // SF7 == 0x07, so (SF7<<4) == SX7_MC2_SF7
  403. #define SX72_MC2_SF8 0x80
  404. #define SX72_MC2_SF9 0x90
  405. #define SX72_MC2_SF10 0xA0
  406. #define SX72_MC2_SF11 0xB0
  407. #define SX72_MC2_SF12 0xC0
  408. // ----------------------------------------
  409. // MC3
  410. #define SX1276_MC3_LOW_DATA_RATE_OPTIMIZE 0x08
  411. #define SX1276_MC3_AGCAUTO 0x04
  412. // ----------------------------------------
  413. // FRF
  414. #define FRF_MSB 0xD9 // 868.1 MHz
  415. #define FRF_MID 0x06
  416. #define FRF_LSB 0x66
  417. // ----------------------------------------
  418. // DIO function mappings D0D1D2D3
  419. #define MAP_DIO0_LORA_RXDONE 0x00 // 00------ bit 7 and 6
  420. #define MAP_DIO0_LORA_TXDONE 0x40 // 01------
  421. #define MAP_DIO0_LORA_CADDONE 0x80 // 10------
  422. #define MAP_DIO0_LORA_NOP 0xC0 // 11------
  423. #define MAP_DIO1_LORA_RXTOUT 0x00 // --00---- bit 5 and 4
  424. #define MAP_DIO1_LORA_FCC 0x10 // --01----
  425. #define MAP_DIO1_LORA_CADDETECT 0x20 // --10----
  426. #define MAP_DIO1_LORA_NOP 0x30 // --11----
  427. #define MAP_DIO2_LORA_FCC0 0x00 // ----00-- bit 3 and 2
  428. #define MAP_DIO2_LORA_FCC1 0x04 // ----01-- bit 3 and 2
  429. #define MAP_DIO2_LORA_FCC2 0x08 // ----10-- bit 3 and 2
  430. #define MAP_DIO2_LORA_NOP 0x0C // ----11-- bit 3 and 2
  431. #define MAP_DIO3_LORA_CADDONE 0x00 // ------00 bit 1 and 0
  432. #define MAP_DIO3_LORA_HEADER 0x01 // ------01
  433. #define MAP_DIO3_LORA_CRC 0x02 // ------10
  434. #define MAP_DIO3_LORA_NOP 0x03 // ------11
  435. // FSK specific
  436. #define MAP_DIO0_FSK_READY 0x00 // 00------ (packet sent / payload ready)
  437. #define MAP_DIO1_FSK_NOP 0x30 // --11----
  438. #define MAP_DIO2_FSK_TXNOP 0x04 // ----01--
  439. #define MAP_DIO2_FSK_TIMEOUT 0x08 // ----10--
  440. // ----------------------------------------
  441. // Bits masking the corresponding IRQs from the radio
  442. #define IRQ_LORA_RXTOUT_MASK 0x80 // RXTOUT
  443. #define IRQ_LORA_RXDONE_MASK 0x40 // RXDONE after receiving the header and CRC, we receive payload part
  444. #define IRQ_LORA_CRCERR_MASK 0x20 // CRC error detected. Note that RXDONE will also be set
  445. #define IRQ_LORA_HEADER_MASK 0x10 // valid HEADER mask. This interrupt is first when receiving a message
  446. #define IRQ_LORA_TXDONE_MASK 0x08 // End of TRansmission
  447. #define IRQ_LORA_CDDONE_MASK 0x04 // CDDONE
  448. #define IRQ_LORA_FHSSCH_MASK 0x02
  449. #define IRQ_LORA_CDDETD_MASK 0x01 // Detect preamble channel
  450. // ----------------------------------------
  451. // Definitions for UDP message arriving from server
  452. #define PROTOCOL_VERSION 0x01
  453. #define PKT_PUSH_DATA 0x00
  454. #define PKT_PUSH_ACK 0x01
  455. #define PKT_PULL_DATA 0x02
  456. #define PKT_PULL_RESP 0x03
  457. #define PKT_PULL_ACK 0x04
  458. #define PKT_TX_ACK 0x05
  459. #define MGT_RESET 0x15 // Not a LoRa Gateway Spec message
  460. #define MGT_SET_SF 0x16
  461. #define MGT_SET_FREQ 0x17