Move cache operations into intrinsics/cortex files.

inc/intrinsics.h

@@ -162,6 +162,28 @@ static always_inline unsigned long __cmpxchg(
 /* Cortex initialisation */
 void cortex_init(void);
 
+#if defined(CORTEX_M7)
+
+/* Cache operations */
+void icache_invalidate_all(void);
+void icache_enable(void);
+void dcache_invalidate_all(void);
+void dcache_clear_and_invalidate_all(void);
+void dcache_enable(void);
+void dcache_disable(void);
+
+#elif defined(CORTEX_M3)
+
+/* No caches in Cortex M3 */
+#define icache_invalidate_all() ((void)0)
+#define icache_enable() ((void)0)
+#define dcache_invalidate_all() ((void)0)
+#define dcache_clear_and_invalidate_all() ((void)0)
+#define dcache_enable() ((void)0)
+#define dcache_disable() ((void)0)
+
+#endif
+
 /*
  * Local variables:
  * mode: C

inc/stm32/f1.h

@@ -9,6 +9,8 @@
  * See the file COPYING for more details, or visit <http://unlicense.org>.
  */
 
+#define CORTEX_M3 1
+
 /* C pointer types */
 #define BKP volatile struct bkp * const
 #define AFIO volatile struct afio * const

inc/stm32/f7.h

@@ -9,6 +9,8 @@
  * See the file COPYING for more details, or visit <http://unlicense.org>.
  */
 
+#define CORTEX_M7 1
+
 /* C pointer types */
 #define CPUFEAT volatile struct cpufeat * const
 #define CACHE volatile struct cache * const
@@ -84,8 +86,6 @@ void peripheral_clock_delay(void);
 
 void gpio_set_af(GPIO gpio, unsigned int pin, unsigned int af);
 
-void dcache_disable(void);
-
 #define section_ext_ram __attribute__((section(".ext_ram")))
 
 /*

src/cortex.c

@@ -122,6 +122,66 @@ void system_reset(void)
     for (;;) ;
 }
 
+#if defined(CORTEX_M7)
+
+void icache_invalidate_all(void)
+{
+    cpu_sync(); 
+    cache->iciallu = 0;
+    cpu_sync(); 
+}
+
+void icache_enable(void)
+{
+    icache_invalidate_all();
+    scb->ccr |= SCB_CCR_IC;
+    cpu_sync(); 
+}
+
+static void _dcache_op_all(volatile uint32_t *opreg)
+{
+    uint32_t ccsidr;
+    unsigned int sets, ways;
+
+    cpufeat->csselr = 0; /* L1 DCache */
+    cpu_sync();
+    ccsidr = cpufeat->ccsidr;
+    sets = CCSIDR_SETS(ccsidr);
+    do {
+        ways = CCSIDR_WAYS(ccsidr);
+        do {
+            *opreg = DCISW_SET(sets) | DCISW_WAY(ways);
+        } while (ways--);
+    } while (sets--);
+    cpu_sync();
+}
+
+void dcache_invalidate_all(void)
+{
+    _dcache_op_all(&cache->dcisw);
+}
+
+void dcache_clear_and_invalidate_all(void)
+{
+    _dcache_op_all(&cache->dccisw);
+}
+
+void dcache_enable(void)
+{
+    dcache_invalidate_all();
+    scb->ccr |= SCB_CCR_DC;
+    cpu_sync();
+}
+
+void dcache_disable(void)
+{
+    scb->ccr &= ~SCB_CCR_DC;
+    cpu_sync();
+    dcache_clear_and_invalidate_all();
+}
+
+#endif
+
 /*
  * Local variables:
  * mode: C

src/stm32f7.c

@@ -52,62 +52,6 @@ static void clock_init(void)
     stk->ctrl = STK_CTRL_ENABLE;
 }
 
-static void icache_invalidate_all(void)
-{
-    cpu_sync(); 
-    cache->iciallu = 0;
-    cpu_sync(); 
-}
-
-static void icache_enable(void)
-{
-    icache_invalidate_all();
-    scb->ccr |= SCB_CCR_IC;
-    cpu_sync(); 
-}
-
-static void _dcache_op_all(volatile uint32_t *opreg)
-{
-    uint32_t ccsidr;
-    unsigned int sets, ways;
-
-    cpufeat->csselr = 0; /* L1 DCache */
-    cpu_sync();
-    ccsidr = cpufeat->ccsidr;
-    sets = CCSIDR_SETS(ccsidr);
-    do {
-        ways = CCSIDR_WAYS(ccsidr);
-        do {
-            *opreg = DCISW_SET(sets) | DCISW_WAY(ways);
-        } while (ways--);
-    } while (sets--);
-    cpu_sync();
-}
-
-static void dcache_invalidate_all(void)
-{
-    _dcache_op_all(&cache->dcisw);
-}
-
-static void dcache_clear_and_invalidate_all(void)
-{
-    _dcache_op_all(&cache->dccisw);
-}
-
-static void dcache_enable(void)
-{
-    dcache_invalidate_all();
-    scb->ccr |= SCB_CCR_DC;
-    cpu_sync();
-}
-
-void dcache_disable(void)
-{
-    scb->ccr &= ~SCB_CCR_DC;
-    cpu_sync();
-    dcache_clear_and_invalidate_all();
-}
-
 void peripheral_clock_delay(void)
 {
     delay_ticks(2);