AT32F403: Increase core clock speed to 144MHz.

inc/mcu/at32/f4.h

@@ -17,3 +17,9 @@ void identify_board_config(void);
 void early_fatal(int blinks) __attribute__((noreturn));
 #define early_delay_ms(ms) (delay_ticks((ms)*1000))
 #define early_delay_us(us) (delay_ticks((us)*1))
+
+#undef SYSCLK_MHZ
+#define SYSCLK_MHZ 144
+#define AHB_MHZ (SYSCLK_MHZ / 1)  /* 144MHz */
+#define APB1_MHZ (SYSCLK_MHZ / 2) /* 72MHz */
+#define APB2_MHZ (SYSCLK_MHZ / 2) /* 72MHz */

inc/mcu/at32/f4_regs.h

@@ -1,4 +1,10 @@
 
 #include "../stm32/f1_regs.h"
 
+#define RCC_CFGR_PLLRANGE_GT72MHZ (1u<<31)
+#define RCC_CFGR_PLLMUL_18 ((uint32_t)0x20040000)
+#define RCC_CFGR_USBPSC_3  ((uint32_t)0x08400000)
+#define RCC_CFGR_APB2PSC_2 (4u<<11)
+#define RCC_CFGR_APB1PSC_2 (4u<< 8)
+
 #define TIM_CR1_PMEN (1u<<10)

src/console.c

@@ -15,10 +15,8 @@
 
 #if MCU == STM32F1
 #define PCLK SYSCLK
-#elif MCU == STM32F7
+#else
 #define PCLK (APB2_MHZ * 1000000)
-#elif MCU == AT32F4
-#define PCLK SYSCLK
 #endif
 
 #define USART1_IRQ 37

src/mcu/at32f4/stm32.c

@@ -28,10 +28,13 @@ static void clock_init(void)
         delay_ms(2);
 
     /* PLLs, scalers, muxes. */
-    rcc->cfgr = (RCC_CFGR_PLLMUL(9) |        /* PLL = 9*8MHz = 72MHz */
+    rcc->cfgr = (RCC_CFGR_PLLRANGE_GT72MHZ |
+                 RCC_CFGR_PLLMUL_18 |        /* PLL = 18*8MHz = 144MHz */
+                 RCC_CFGR_USBPSC_3 |         /* USB = 144/3MHz = 48MHz */
                  RCC_CFGR_PLLSRC_PREDIV1 |
                  RCC_CFGR_ADCPRE_DIV8 |
-                 RCC_CFGR_PPRE1_DIV2);
+                 RCC_CFGR_APB2PSC_2 |        /* APB2 = 144/2MHz = 72MHz */
+                 RCC_CFGR_APB1PSC_2);        /* APB1 = 144/2MHz = 72MHz */
 
     /* Enable and stabilise the PLL. */
     rcc->cr |= RCC_CR_PLLON;