f7: Enable instruction cache.

inc/stm32/common_regs.h

@@ -45,12 +45,15 @@ struct scb {
     uint32_t bfar;     /* 38: Bus fault address */
 };
 
-#define SCB_CCR_STKALIGN       (1u<<9)
-#define SCB_CCR_BFHFNMIGN      (1u<<8)
-#define SCB_CCR_DIV_0_TRP      (1u<<4)
-#define SCB_CCR_UNALIGN_TRP    (1u<<3)
-#define SCB_CCR_USERSETMPEND   (1u<<1)
-#define SCB_CCR_NONBASETHRDENA (1u<<0)
+#define SCB_CCR_BP             (1u<<18)
+#define SCB_CCR_IC             (1u<<17)
+#define SCB_CCR_DC             (1u<<16)
+#define SCB_CCR_STKALIGN       (1u<< 9)
+#define SCB_CCR_BFHFNMIGN      (1u<< 8)
+#define SCB_CCR_DIV_0_TRP      (1u<< 4)
+#define SCB_CCR_UNALIGN_TRP    (1u<< 3)
+#define SCB_CCR_USERSETMPEND   (1u<< 1)
+#define SCB_CCR_NONBASETHRDENA (1u<< 0)
 
 #define SCB_SHCSR_USGFAULTENA    (1u<<18)
 #define SCB_SHCSR_BUSFAULTENA    (1u<<17)

inc/stm32/f7.h

@@ -10,6 +10,7 @@
  */
 
 /* C pointer types */
+#define CACHE volatile struct cache * const
 #define SYSCFG volatile struct syscfg * const
 #define DMA_STR volatile struct dma_str * const
 #define HSPHYC volatile struct hsphyc * const
@@ -19,6 +20,7 @@ static STK stk = (struct stk *)STK_BASE;
 static SCB scb = (struct scb *)SCB_BASE;
 static NVIC nvic = (struct nvic *)NVIC_BASE;
 static DBG dbg = (struct dbg *)DBG_BASE;
+static CACHE cache = (struct cache *)CACHE_BASE;
 static FLASH flash = (struct flash *)FLASH_BASE;
 static PWR pwr = (struct pwr *)PWR_BASE;
 static RCC rcc = (struct rcc *)RCC_BASE;

inc/stm32/f7_regs.h

@@ -18,6 +18,22 @@ struct dbg {
 
 #define DBG_BASE 0xe0042000
 
+struct cache {
+    uint32_t iciallu;    /* 00: ICache invalidate all to PoU */
+    uint32_t _unused0;
+    uint32_t icimvau;    /* 08: ICache invalidate by address to PoU */
+    uint32_t dcimvac;    /* 0C: DCache invalidate by address to PoC */
+    uint32_t dcisw;      /* 10: DCache invalidate by set/way */
+    uint32_t dccmvau;    /* 14: DCache clean by adress to PoU */
+    uint32_t dccmvac;    /* 18: DCache clean by address to PoC */
+    uint32_t dccsw;      /* 1C: DCache clean by set/way */
+    uint32_t dccimvac;   /* 20: DCache clean & invalidate by address to PoC */
+    uint32_t dccisw;     /* 24: DCache clean & invalidate by set/way */
+    uint32_t bpiall;
+};
+
+#define CACHE_BASE 0xe000ef50    
+
 /* Flash memory interface */
 struct flash {
     uint32_t acr;      /* 00: Flash access control */

src/stm32f7.c

@@ -52,6 +52,20 @@ static void clock_init(void)
     stk->ctrl = STK_CTRL_ENABLE;
 }
 
+static void icache_invalidate_all(void)
+{
+    cpu_sync(); 
+    cache->iciallu = 0;
+    cpu_sync(); 
+}
+
+static void icache_enable(void)
+{
+    icache_invalidate_all();
+    scb->ccr |= SCB_CCR_IC;
+    cpu_sync(); 
+}
+
 void peripheral_clock_delay(void)
 {
     delay_ticks(2);
@@ -79,6 +93,7 @@ void stm32_init(void)
 {
     cortex_init();
     clock_init();
+    icache_enable();
     peripheral_init();
     cpu_sync();
 }