|  | @@ -53,7 +53,6 @@ static unsigned int GPI_bus;
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														|  |  #define dma_wdata   (dma1->ch3)
 |  |  #define dma_wdata   (dma1->ch3)
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														|  |  
 |  |  
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														|  |  typedef uint16_t timcnt_t;
 |  |  typedef uint16_t timcnt_t;
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														|  | -#define TIM_PSC 0
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														|  |  
 |  |  
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														|  |  #define irq_index 23
 |  |  #define irq_index 23
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														|  |  void IRQ_23(void) __attribute__((alias("IRQ_INDEX_changed"))); /* EXTI9_5 */
 |  |  void IRQ_23(void) __attribute__((alias("IRQ_INDEX_changed"))); /* EXTI9_5 */
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														|  | @@ -83,13 +82,13 @@ static void floppy_mcu_init(void)
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														|  |  static void rdata_prep(void)
 |  |  static void rdata_prep(void)
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														|  |  {
 |  |  {
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														|  |      /* RDATA Timer setup: 
 |  |      /* RDATA Timer setup: 
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														|  | -     * The counter runs from 0x0000-0xFFFF inclusive at full SYSCLK rate.
 |  | 
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														|  | 
 |  | +     * The counter runs from 0x0000-0xFFFF inclusive at SAMPLE rate.
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														|  |       *  
 |  |       *  
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														|  |       * Ch.2 (RDATA) is in Input Capture mode, sampling on every clock and with
 |  |       * Ch.2 (RDATA) is in Input Capture mode, sampling on every clock and with
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														|  |       * no input prescaling or filtering. Samples are captured on the falling 
 |  |       * no input prescaling or filtering. Samples are captured on the falling 
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														|  |       * edge of the input (CCxP=1). DMA is used to copy the sample into a ring
 |  |       * edge of the input (CCxP=1). DMA is used to copy the sample into a ring
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														|  |       * buffer for batch processing in the DMA-completion ISR. */
 |  |       * buffer for batch processing in the DMA-completion ISR. */
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														|  | -    tim_rdata->psc = 0;
 |  | 
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														|  | 
 |  | +    tim_rdata->psc = TIM_PSC-1;
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														|  |      tim_rdata->arr = 0xffff;
 |  |      tim_rdata->arr = 0xffff;
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														|  |      tim_rdata->ccmr1 = TIM_CCMR1_CC2S(TIM_CCS_INPUT_TI1);
 |  |      tim_rdata->ccmr1 = TIM_CCMR1_CC2S(TIM_CCS_INPUT_TI1);
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														|  |      tim_rdata->dier = TIM_DIER_CC2DE;
 |  |      tim_rdata->dier = TIM_DIER_CC2DE;
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														|  | @@ -113,17 +112,17 @@ static void rdata_prep(void)
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														|  |  static void wdata_prep(void)
 |  |  static void wdata_prep(void)
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														|  |  {
 |  |  {
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														|  |      /* WDATA Timer setup:
 |  |      /* WDATA Timer setup:
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														|  | -     * The counter is incremented at full SYSCLK rate. 
 |  | 
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														|  | 
 |  | +     * The counter is incremented at SAMPLE rate. 
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														|  |       *  
 |  |       *  
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														|  |       * Ch.1 (WDATA) is in PWM mode 1. It outputs O_TRUE for 400ns and then 
 |  |       * Ch.1 (WDATA) is in PWM mode 1. It outputs O_TRUE for 400ns and then 
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														|  |       * O_FALSE until the counter reloads. By changing the ARR via DMA we alter
 |  |       * O_FALSE until the counter reloads. By changing the ARR via DMA we alter
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														|  |       * the time between (fixed-width) O_TRUE pulses, mimicking floppy drive 
 |  |       * the time between (fixed-width) O_TRUE pulses, mimicking floppy drive 
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														|  |       * timings. */
 |  |       * timings. */
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														|  | -    tim_wdata->psc = 0;
 |  | 
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														|  | 
 |  | +    tim_wdata->psc = TIM_PSC-1;
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														|  |      tim_wdata->ccmr1 = (TIM_CCMR1_CC1S(TIM_CCS_OUTPUT) |
 |  |      tim_wdata->ccmr1 = (TIM_CCMR1_CC1S(TIM_CCS_OUTPUT) |
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														|  |                          TIM_CCMR1_OC1M(TIM_OCM_PWM1));
 |  |                          TIM_CCMR1_OC1M(TIM_OCM_PWM1));
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														|  |      tim_wdata->ccer = TIM_CCER_CC1E | ((O_TRUE==0) ? TIM_CCER_CC1P : 0);
 |  |      tim_wdata->ccer = TIM_CCER_CC1E | ((O_TRUE==0) ? TIM_CCER_CC1P : 0);
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														|  | -    tim_wdata->ccr1 = sysclk_ns(400);
 |  | 
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														|  | 
 |  | +    tim_wdata->ccr1 = sample_ns(400);
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														|  |      tim_wdata->dier = TIM_DIER_UDE;
 |  |      tim_wdata->dier = TIM_DIER_UDE;
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														|  |      tim_wdata->cr2 = 0;
 |  |      tim_wdata->cr2 = 0;
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														|  |  }
 |  |  }
 |