f7_regs.h 22 KB

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  1. /*
  2. * stm32/f7_regs.h
  3. *
  4. * Core and peripheral register definitions.
  5. *
  6. * Written & released by Keir Fraser <keir.xen@gmail.com>
  7. *
  8. * This is free and unencumbered software released into the public domain.
  9. * See the file COPYING for more details, or visit <http://unlicense.org>.
  10. */
  11. struct dbg {
  12. uint32_t mcu_idcode; /* 00: MCU ID code */
  13. uint32_t mcu_cr; /* 04: Debug MCU configuration */
  14. uint32_t mcu_apb1_fz;/* 08: Debug MCU APB1 freeze */
  15. uint32_t mcu_apb2_fz;/* 0C: Debug MCU APB2 freeze */
  16. };
  17. #define DBG_BASE 0xe0042000
  18. struct cpufeat {
  19. uint32_t clidr; /* 00: Cache level ID */
  20. uint32_t ctr; /* 04: Cache type */
  21. uint32_t ccsidr; /* 08: Cache size ID */
  22. uint32_t csselr; /* 10: Cache size selection */
  23. };
  24. #define CCSIDR_SETS(x) (((x)>>13)&0x7fffu)
  25. #define CCSIDR_WAYS(x) (((x)>> 3)& 0x3ffu)
  26. #define CPUFEAT_BASE 0xe000ed78
  27. struct cache {
  28. uint32_t iciallu; /* 00: ICache invalidate all to PoU */
  29. uint32_t _unused0;
  30. uint32_t icimvau; /* 08: ICache invalidate by address to PoU */
  31. uint32_t dcimvac; /* 0C: DCache invalidate by address to PoC */
  32. uint32_t dcisw; /* 10: DCache invalidate by set/way */
  33. uint32_t dccmvau; /* 14: DCache clean by adress to PoU */
  34. uint32_t dccmvac; /* 18: DCache clean by address to PoC */
  35. uint32_t dccsw; /* 1C: DCache clean by set/way */
  36. uint32_t dccimvac; /* 20: DCache clean & invalidate by address to PoC */
  37. uint32_t dccisw; /* 24: DCache clean & invalidate by set/way */
  38. uint32_t bpiall;
  39. };
  40. #define DCISW_WAY(x) ((x)<<30)
  41. #define DCISW_SET(x) ((x)<< 5)
  42. #define CACHE_BASE 0xe000ef50
  43. /* Flash memory interface */
  44. struct flash {
  45. uint32_t acr; /* 00: Flash access control */
  46. uint32_t keyr; /* 04: Flash key */
  47. uint32_t optkeyr; /* 08: Flash option key */
  48. uint32_t sr; /* 0C: Flash status */
  49. uint32_t cr; /* 10: Flash control */
  50. uint32_t optcr; /* 14: Flash option control */
  51. uint32_t optcr1; /* 18: Flash option control */
  52. uint32_t optcr2; /* 1C: Flash option control */
  53. };
  54. #define FLASH_ACR_ARTRST (1u<<11)
  55. #define FLASH_ACR_ARTEN (1u<< 9)
  56. #define FLASH_ACR_PRFTEN (1u<< 8)
  57. #define FLASH_ACR_LATENCY(w) ((w)<<0) /* wait states */
  58. #define FLASH_SR_BSY (1u<<16)
  59. #define FLASH_SR_RDERR (1u<< 8)
  60. #define FLASH_SR_ERRSERR (1u<< 7)
  61. #define FLASH_SR_PGPERR (1u<< 6)
  62. #define FLASH_SR_PGAERR (1u<< 5)
  63. #define FLASH_SR_WRPERR (1u<< 4)
  64. #define FLASH_SR_OPERR (1u<< 1)
  65. #define FLASH_SR_EOP (1u<< 0)
  66. #define FLASH_CR_LOCK (1u<<31)
  67. #define FLASH_CR_RDERRIE (1u<<26)
  68. #define FLASH_CR_ERRIE (1u<<25)
  69. #define FLASH_CR_EOPIE (1u<<24)
  70. #define FLASH_CR_STRT (1u<<16)
  71. #define FLASH_CR_PSIZE(x) ((x)<<8)
  72. #define FLASH_CR_SNB(x) ((x)<<3)
  73. #define FLASH_CR_MER (1u<< 2)
  74. #define FLASH_CR_SER (1u<< 1)
  75. #define FLASH_CR_PG (1u<< 0)
  76. #define FLASH_BASE 0x40023c00
  77. /* Power control */
  78. struct pwr {
  79. uint32_t cr1; /* 00: Power control #1 */
  80. uint32_t csr1; /* 04: Power control/status #1 */
  81. uint32_t cr2; /* 08: Power control #2 */
  82. uint32_t csr2; /* 0C: Power control/status #2 */
  83. };
  84. #define PWR_CR1_UDEN(x) ((x)<<18)
  85. #define PWR_CR1_ODSWEN (1u<<17)
  86. #define PWR_CR1_ODEN (1u<<16)
  87. #define PWR_CR1_VOS(x) ((x)<<14)
  88. #define PWR_CR1_ADCDC1 (1u<<13)
  89. #define PWR_CR1_MRUDS (1u<<11)
  90. #define PWR_CR1_LPUDS (1u<<10)
  91. #define PWR_CR1_FPDS (1u<< 9)
  92. #define PWR_CR1_DBP (1u<< 8)
  93. #define PWR_CR1_PLS(x) ((x)<<5)
  94. #define PWR_CR1_PVDE (1u<< 4)
  95. #define PWR_CR1_CSBF (1u<< 3)
  96. #define PWR_CR1_PDDS (1u<< 1)
  97. #define PWR_CR1_LPDS (1u<< 0)
  98. #define PWR_CSR1_ODSWRDY (1u<<17)
  99. #define PWR_CSR1_ODRDY (1u<<16)
  100. #define PWR_CSR1_VOSRDY (1u<<14)
  101. #define PWR_CSR1_BRE (1u<< 9)
  102. #define PWR_CSR1_EIWUP (1u<< 8)
  103. #define PWR_CSR1_BRR (1u<< 3)
  104. #define PWR_CSR1_PVDO (1u<< 2)
  105. #define PWR_CSR1_SBF (1u<< 1)
  106. #define PWR_CSR1_WUIF (1u<< 0)
  107. #define PWR_BASE 0x40007000
  108. /* Reset and clock control */
  109. struct rcc {
  110. uint32_t cr; /* 00: Clock control */
  111. uint32_t pllcfgr; /* 04: PLL configuration */
  112. uint32_t cfgr; /* 08: Clock configuration */
  113. uint32_t cir; /* 0C: Clock interrupt */
  114. uint32_t ahb1rstr; /* 10: AHB1 peripheral reset */
  115. uint32_t ahb2rstr; /* 14: AHB2 peripheral reset */
  116. uint32_t ahb3rstr; /* 18: AHB3 peripheral reset */
  117. uint32_t _unused0; /* 1C: - */
  118. uint32_t apb1rstr; /* 20: APB1 peripheral reset */
  119. uint32_t apb2rstr; /* 24: APB2 peripheral reset */
  120. uint32_t _unused1; /* 28: - */
  121. uint32_t _unused2; /* 2C: - */
  122. uint32_t ahb1enr; /* 30: AHB1 peripheral clock enable */
  123. uint32_t ahb2enr; /* 34: AHB2 peripheral clock enable */
  124. uint32_t ahb3enr; /* 38: AHB3 peripheral clock enable */
  125. uint32_t _unused3; /* 3C: - */
  126. uint32_t apb1enr; /* 40: APB1 peripheral clock enable */
  127. uint32_t apb2enr; /* 44: APB1 peripheral clock enable */
  128. uint32_t _unused4; /* 48: - */
  129. uint32_t _unused5; /* 4C: - */
  130. uint32_t ahb1lpenr;/* 50: AHB1 peripheral clock enable (low-power mode) */
  131. uint32_t ahb2lpenr;/* 54: AHB2 peripheral clock enable (low-power mode) */
  132. uint32_t ahb3lpenr;/* 58: AHB3 peripheral clock enable (low-power mode) */
  133. uint32_t _unused6; /* 5C: - */
  134. uint32_t apb1lpenr;/* 60: APB1 peripheral clock enable (low-power mode) */
  135. uint32_t apb2lpenr;/* 64: APB2 peripheral clock enable (low-power mode) */
  136. uint32_t _unused7; /* 68: - */
  137. uint32_t _unused8; /* 6C: - */
  138. uint32_t bdcr; /* 70: Backup domain control */
  139. uint32_t csr; /* 74: Clock control & status */
  140. uint32_t _unused9; /* 78: - */
  141. uint32_t _unusedA; /* 7C: - */
  142. uint32_t sscgr; /* 80: Spread spectrum clock generation */
  143. uint32_t plli2scfgr; /* 84: PLLI2S configuration */
  144. uint32_t pllsaicfgr; /* 88: PLLSAI configuration */
  145. uint32_t dckcfgr1; /* 8C: Dedicated clocks configuration #1 */
  146. uint32_t dckcfgr2; /* 90: Dedicated clocks configuration #2 */
  147. };
  148. #define RCC_CR_SAIRDY (1u<<29)
  149. #define RCC_CR_SAION (1u<<28)
  150. #define RCC_CR_PLLIS2RDY (1u<<27)
  151. #define RCC_CR_PLLI2SON (1u<<26)
  152. #define RCC_CR_PLLRDY (1u<<25)
  153. #define RCC_CR_PLLON (1u<<24)
  154. #define RCC_CR_CSSON (1u<<19)
  155. #define RCC_CR_HSEBYP (1u<<18)
  156. #define RCC_CR_HSERDY (1u<<17)
  157. #define RCC_CR_HSEON (1u<<16)
  158. #define RCC_CR_HSIRDY (1u<<1)
  159. #define RCC_CR_HSION (1u<<0)
  160. #define RCC_PLLCFGR_PLLQ(x) ((x)<<24)
  161. #define RCC_PLLCFGR_PLLSRC_HSE (1<<22)
  162. #define RCC_PLLCFGR_PLLP(x) ((x)<<16)
  163. #define RCC_PLLCFGR_PLLN(x) ((x)<< 6)
  164. #define RCC_PLLCFGR_PLLM(x) ((x)<< 0)
  165. #define RCC_CFGR_MCO2(x) ((x)<<30)
  166. #define RCC_CFGR_MCO2PRE(x) ((x)<<27)
  167. #define RCC_CFGR_MCO1PRE(x) ((x)<<24)
  168. #define RCC_CFGR_I2SSCR (1 <<23)
  169. #define RCC_CFGR_MCO1(x) ((x)<<21)
  170. #define RCC_CFGR_RTCPRE(x) ((x)<<16)
  171. #define RCC_CFGR_PPRE2(x) ((x)<<13)
  172. #define RCC_CFGR_PPRE1(x) ((x)<<10)
  173. #define RCC_CFGR_HPRE(x) ((x)<< 4)
  174. #define RCC_CFGR_SWS(x) ((x)<< 2)
  175. #define RCC_CFGR_SW(x) ((x)<< 0)
  176. #define RCC_AHB1ENR_OTGHSULPIEN (1u<<30)
  177. #define RCC_AHB1ENR_OTGHSEN (1u<<29)
  178. #define RCC_AHB1ENR_DMA2EN (1u<<22)
  179. #define RCC_AHB1ENR_DMA1EN (1u<<21)
  180. #define RCC_AHB1ENR_DTCMRAMEN (1u<<20)
  181. #define RCC_AHB1ENR_BKPSRAMEN (1u<<18)
  182. #define RCC_AHB1ENR_CRCEN (1u<<12)
  183. #define RCC_AHB1ENR_GPIOIEN (1u<< 8)
  184. #define RCC_AHB1ENR_GPIOHEN (1u<< 7)
  185. #define RCC_AHB1ENR_GPIOGEN (1u<< 6)
  186. #define RCC_AHB1ENR_GPIOFEN (1u<< 5)
  187. #define RCC_AHB1ENR_GPIOEEN (1u<< 4)
  188. #define RCC_AHB1ENR_GPIODEN (1u<< 3)
  189. #define RCC_AHB1ENR_GPIOCEN (1u<< 2)
  190. #define RCC_AHB1ENR_GPIOBEN (1u<< 1)
  191. #define RCC_AHB1ENR_GPIOAEN (1u<< 0)
  192. #define RCC_AHB2ENR_OTGFSEN (1u<< 7)
  193. #define RCC_AHB2ENR_RNGEN (1u<< 6)
  194. #define RCC_AHB2ENR_AESEN (1u<< 4)
  195. #define RCC_AHB3ENR_QSPIEN (1u<< 1)
  196. #define RCC_AHB3ENR_FMCEN (1u<< 0)
  197. #define RCC_APB1ENR_USART8EN (1u<<31)
  198. #define RCC_APB1ENR_USART7EN (1u<<30)
  199. #define RCC_APB1ENR_DACEN (1u<<29)
  200. #define RCC_APB1ENR_PWREN (1u<<28)
  201. #define RCC_APB1ENR_CAN1EN (1u<<25)
  202. #define RCC_APB1ENR_I2C3EN (1u<<23)
  203. #define RCC_APB1ENR_I2C2EN (1u<<22)
  204. #define RCC_APB1ENR_I2C1EN (1u<<21)
  205. #define RCC_APB1ENR_USART5EN (1u<<20)
  206. #define RCC_APB1ENR_USART4EN (1u<<19)
  207. #define RCC_APB1ENR_USART3EN (1u<<18)
  208. #define RCC_APB1ENR_USART2EN (1u<<17)
  209. #define RCC_APB1ENR_SPI3EN (1u<<15)
  210. #define RCC_APB1ENR_SPI2EN (1u<<14)
  211. #define RCC_APB1ENR_WWDGEN (1u<<11)
  212. #define RCC_APB1ENR_RTCAPBEN (1u<<10)
  213. #define RCC_APB1ENR_LPTIM1EN (1u<< 9)
  214. #define RCC_APB1ENR_TIM14EN (1u<< 8)
  215. #define RCC_APB1ENR_TIM13EN (1u<< 7)
  216. #define RCC_APB1ENR_TIM12EN (1u<< 6)
  217. #define RCC_APB1ENR_TIM7EN (1u<< 5)
  218. #define RCC_APB1ENR_TIM6EN (1u<< 4)
  219. #define RCC_APB1ENR_TIM5EN (1u<< 3)
  220. #define RCC_APB1ENR_TIM4EN (1u<< 2)
  221. #define RCC_APB1ENR_TIM3EN (1u<< 1)
  222. #define RCC_APB1ENR_TIM2EN (1u<< 0)
  223. #define RCC_APB2ENR_OTGPHYCEN (1u<<31)
  224. #define RCC_APB2ENR_SAI2EN (1u<<23)
  225. #define RCC_APB2ENR_SAI1EN (1u<<22)
  226. #define RCC_APB2ENR_SPI5EN (1u<<20)
  227. #define RCC_APB2ENR_TIM11EN (1u<<18)
  228. #define RCC_APB2ENR_TIM10EN (1u<<17)
  229. #define RCC_APB2ENR_TIM9EN (1u<<16)
  230. #define RCC_APB2ENR_SYSCFGEN (1u<<14)
  231. #define RCC_APB2ENR_SPI4EN (1u<<13)
  232. #define RCC_APB2ENR_SPI1EN (1u<<12)
  233. #define RCC_APB2ENR_SDMMC1EN (1u<<11)
  234. #define RCC_APB2ENR_ADC3EN (1u<<10)
  235. #define RCC_APB2ENR_ADC2EN (1u<< 9)
  236. #define RCC_APB2ENR_ADC1EN (1u<< 8)
  237. #define RCC_APB2ENR_SDMMC2EN (1u<< 7)
  238. #define RCC_APB2ENR_USART6EN (1u<< 5)
  239. #define RCC_APB2ENR_USART1EN (1u<< 4)
  240. #define RCC_APB2ENR_TIM8EN (1u<< 1)
  241. #define RCC_APB2ENR_TIM1EN (1u<< 0)
  242. #define RCC_BDCR_BDRST (1u<<16)
  243. #define RCC_BDCR_RTCEN (1u<<15)
  244. #define RCC_BDCR_RTCSEL(x) ((x)<<8)
  245. #define RCC_BDCR_LSEDRV(x) ((x)<<3)
  246. #define RCC_BDCR_LSEBYP (1u<< 2)
  247. #define RCC_BDCR_LSERDY (1u<< 1)
  248. #define RCC_BDCR_LSEON (1u<< 0)
  249. #define RCC_CSR_LPWRRSTF (1u<<31)
  250. #define RCC_CSR_WWDGRSTF (1u<<30)
  251. #define RCC_CSR_IWDGRSTF (1u<<29)
  252. #define RCC_CSR_SFTRSTF (1u<<28)
  253. #define RCC_CSR_PORRSTF (1u<<27)
  254. #define RCC_CSR_PINRSTF (1u<<26)
  255. #define RCC_CSR_BORRSTF (1u<<25)
  256. #define RCC_CSR_RMVF (1u<<24)
  257. #define RCC_CSR_LSIRDY (1u<< 1)
  258. #define RCC_CSR_LSION (1u<< 0)
  259. #define RCC_DCKCFGR1_TIMPRE (1u<<24)
  260. #define RCC_DCKCFGR1_SAI2SEL(x) ((x)<<22)
  261. #define RCC_DCKCFGR1_SAI1SEL(x) ((x)<<20)
  262. #define RCC_DCKCFGR1_PLLSAIDIVQ(x) ((x)<< 8)
  263. #define RCC_DCKCFGR1_PLLI2SDIVQ(x) ((x)<< 0)
  264. #define RCC_BASE 0x40023800
  265. /* General-purpose I/O */
  266. struct gpio {
  267. uint32_t moder; /* 00: Port mode */
  268. uint32_t otyper; /* 04: Port output type */
  269. uint32_t ospeedr; /* 08: Port output speed */
  270. uint32_t pupdr; /* 0C: Port pull-up/pull-down */
  271. uint32_t idr; /* 10: Port input data */
  272. uint32_t odr; /* 14: Port output data */
  273. uint32_t bsrr; /* 18: Port bit set/reset */
  274. uint32_t lckr; /* 1C: Port configuration lock */
  275. uint32_t afrl; /* 20: Alternate function low */
  276. uint32_t afrh; /* 24: Alternate function high */
  277. };
  278. /* 0-1: MODE, 2: OTYPE, 3-4:OSPEED, 5-6:PUPD, 7:OUTPUT_LEVEL */
  279. #define GPI_analog 0x3u
  280. #define GPI(pupd) (0x0u|((pupd)<<5))
  281. #define PUPD_none 0
  282. #define PUPD_up 1
  283. #define PUPD_down 2
  284. #define GPI_floating GPI(PUPD_none)
  285. #define GPI_pull_down GPI(PUPD_down)
  286. #define GPI_pull_up GPI(PUPD_up)
  287. #define GPO_pushpull(speed,level) (0x1u|((speed)<<3)|((level)<<7))
  288. #define GPO_opendrain(speed,level) (0x5u|((speed)<<3)|((level)<<7))
  289. #define AFI(pupd) (0x2u|((pupd)<<5))
  290. #define AFO_pushpull(speed) (0x2u|((speed)<<3))
  291. #define AFO_opendrain(speed) (0x6u|((speed)<<3))
  292. #define IOSPD_LOW 0 /* 4MHz @ CL=50pF */
  293. #define IOSPD_MED 1 /* 25MHz @ CL=50pF */
  294. #define IOSPD_HIGH 2 /* 50MHz @ CL=40pF */
  295. #define IOSPD_V_HIGH 3 /* 100MHz @ CL=30pF */
  296. #define LOW 0
  297. #define HIGH 1
  298. #define GPIOA_BASE 0x40020000
  299. #define GPIOB_BASE 0x40020400
  300. #define GPIOC_BASE 0x40020800
  301. #define GPIOD_BASE 0x40020C00
  302. #define GPIOE_BASE 0x40021000
  303. #define GPIOF_BASE 0x40021400
  304. #define GPIOG_BASE 0x40021800
  305. #define GPIOH_BASE 0x40021C00
  306. #define GPIOI_BASE 0x40022000
  307. /* System configuration controller */
  308. struct syscfg {
  309. uint32_t memrmp; /* 00: Memory remap */
  310. uint32_t pmc; /* 04: Peripheral mode configuration */
  311. uint32_t exticr1; /* 08: External interrupt configuration #1 */
  312. uint32_t exticr2; /* 0C: External interrupt configuration #2 */
  313. uint32_t exticr3; /* 10: External interrupt configuration #3 */
  314. uint32_t exticr4; /* 14: External interrupt configuration #4 */
  315. uint32_t _pad[2];
  316. uint32_t cmpcr; /* 20: Compensation cell configuration */
  317. };
  318. #define SYSCFG_BASE 0x40013800
  319. #define EXTI_BASE 0x40013c00
  320. /* DMA */
  321. struct dma_str {
  322. uint32_t cr; /* +00: Configuration */
  323. uint32_t ndtr; /* +04: Number of data */
  324. uint32_t par; /* +08: Peripheral address */
  325. union {
  326. uint32_t mar; /* +0C: Memory address */
  327. uint32_t m0ar; /* +0C: Memory 0 address */
  328. };
  329. uint32_t m1ar; /* +10: Memory 1 address */
  330. uint32_t fcr; /* +14: FIFO control */
  331. };
  332. struct dma {
  333. uint32_t lisr; /* 00: Low interrupt status */
  334. uint32_t hisr; /* 00: High interrupt status */
  335. uint32_t lifcr; /* 00: Low interrupt flag clear */
  336. uint32_t hifcr; /* 00: High interrupt flag clear */
  337. struct dma_str str[8]; /* 0x10,0x28,..,0xB8: Stream 0,1,..,7 */
  338. };
  339. #define DMA_ISR_TCIF (1u<<5)
  340. #define DMA_ISR_HTIF (1u<<4)
  341. #define DMA_ISR_TEIF (1u<<3)
  342. #define DMA_ISR_DMEIF (1u<<2)
  343. #define DMA_ISR_FEIF (1u<<0)
  344. #define DMA_IFCR_CTCIF (1u<<5)
  345. #define DMA_IFCR_CHTIF (1u<<4)
  346. #define DMA_IFCR_CTEIF (1u<<3)
  347. #define DMA_IFCR_CDMEIF (1u<<2)
  348. #define DMA_IFCR_CFEIF (1u<<0)
  349. #define DMA_CR_CHSEL(x) ((x)<<25)
  350. #define DMA_CR_CT (1u<<19)
  351. #define DMA_CR_DBM (1u<<18)
  352. #define DMA_CR_PL_LOW (0u<<16)
  353. #define DMA_CR_PL_MEDIUM (1u<<16)
  354. #define DMA_CR_PL_HIGH (2u<<16)
  355. #define DMA_CR_PL_V_HIGH (3u<<16)
  356. #define DMA_CR_PINCOS (1u<<15)
  357. #define DMA_CR_MSIZE_8BIT (0u<<13)
  358. #define DMA_CR_MSIZE_16BIT (1u<<13)
  359. #define DMA_CR_MSIZE_32BIT (2u<<13)
  360. #define DMA_CR_PSIZE_8BIT (0u<<11)
  361. #define DMA_CR_PSIZE_16BIT (1u<<11)
  362. #define DMA_CR_PSIZE_32BIT (2u<<11)
  363. #define DMA_CR_MINC (1u<<10)
  364. #define DMA_CR_PINC (1u<< 9)
  365. #define DMA_CR_CIRC (1u<< 8)
  366. #define DMA_CR_DIR_M2M (2u<< 6)
  367. #define DMA_CR_DIR_M2P (1u<< 6)
  368. #define DMA_CR_DIR_P2M (0u<< 6)
  369. #define DMA_CR_PFCTRL (1u<< 5)
  370. #define DMA_CR_TCIE (1u<< 4)
  371. #define DMA_CR_HTIE (1u<< 3)
  372. #define DMA_CR_TEIE (1u<< 2)
  373. #define DMA_CR_DMEIE (1u<< 1)
  374. #define DMA_CR_EN (1u<< 0)
  375. #define DMA_FCR_DMDIS (1u<< 2)
  376. #define DMA1_BASE 0x40026000
  377. #define DMA2_BASE 0x40026400
  378. #define TIM1_BASE 0x40010000
  379. #define TIM2_BASE 0x40000000
  380. #define TIM3_BASE 0x40000400
  381. #define TIM4_BASE 0x40000800
  382. #define TIM5_BASE 0x40000c00
  383. #define TIM6_BASE 0x40001000
  384. #define TIM7_BASE 0x40001400
  385. #define TIM8_BASE 0x40010400
  386. #define TIM9_BASE 0x40014000
  387. #define TIM10_BASE 0x40014400
  388. #define TIM11_BASE 0x40014800
  389. #define TIM12_BASE 0x40001800
  390. #define TIM13_BASE 0x40001c00
  391. #define TIM14_BASE 0x40002000
  392. #define SPI4_BASE 0x40013400
  393. #define SPI5_BASE 0x40015000
  394. /* I2C */
  395. struct i2c {
  396. uint32_t cr1; /* 00: Control 1 */
  397. uint32_t cr2; /* 04: Control 2 */
  398. uint32_t oar1; /* 08: Own address 1 */
  399. uint32_t oar2; /* 0C: Own address 2 */
  400. uint32_t timingr; /* 10: Timing */
  401. uint32_t timeoutr; /* 14: Timeout */
  402. uint32_t isr; /* 18: Interrupt & status */
  403. uint32_t icr; /* 1C: Interrupt clear */
  404. uint32_t pecr; /* 20: PEC */
  405. uint32_t rxdr; /* 24: Receive data */
  406. uint32_t txdr; /* 28: Transmit data */
  407. };
  408. #define I2C_CR1_PECEN (1u<<23)
  409. #define I2C_CR1_ALERTEN (1u<<22)
  410. #define I2C_CR1_SMBDEN (1u<<21)
  411. #define I2C_CR1_SMBHEN (1u<<20)
  412. #define I2C_CR1_GCEN (1u<<19)
  413. #define I2C_CR1_NOSTRETCH (1u<<17)
  414. #define I2C_CR1_SBC (1u<<16)
  415. #define I2C_CR1_RXDMAEN (1u<<15)
  416. #define I2C_CR1_TXDMAEN (1u<<14)
  417. #define I2C_CR1_ANFOFF (1u<<12)
  418. #define I2C_CR1_DNF(x) ((x)<<8)
  419. #define I2C_CR1_ERRIE (1u<< 7)
  420. #define I2C_CR1_TCIE (1u<< 6)
  421. #define I2C_CR1_STOPIE (1u<< 5)
  422. #define I2C_CR1_NACKIE (1u<< 4)
  423. #define I2C_CR1_ADDRIE (1u<< 3)
  424. #define I2C_CR1_RXIE (1u<< 2)
  425. #define I2C_CR1_TXIE (1u<< 1)
  426. #define I2C_CR1_PE (1u<< 0)
  427. #define I2C_CR2_PECBYTE (1u<<26)
  428. #define I2C_CR2_AUTOEND (1u<<25)
  429. #define I2C_CR2_RELOAD (1u<<24)
  430. #define I2C_CR2_NBYTES(x) ((x)<<16)
  431. #define I2C_CR2_NACK (1u<<15)
  432. #define I2C_CR2_STOP (1u<<14)
  433. #define I2C_CR2_START (1u<<13)
  434. #define I2C_CR2_HEAD10R (1u<<12)
  435. #define I2C_CR2_ADD10 (1u<<11)
  436. #define I2C_CR2_RD_WRN (1u<<10)
  437. #define I2C_CR2_SADD(x) ((x)<<0)
  438. #define I2C_OA1_EN (1u<<15)
  439. #define I2C_OA1_MODE (1u<<10)
  440. #define I2C_ISR_DIR (1<<16)
  441. #define I2C_ISR_BUSY (1<<15)
  442. #define I2C_ISR_ALERT (1<<13)
  443. #define I2C_ISR_TIMEOUT (1<<12)
  444. #define I2C_ISR_PECERR (1<<11)
  445. #define I2C_ISR_OVR (1<<10)
  446. #define I2C_ISR_ARLO (1<< 9)
  447. #define I2C_ISR_BERR (1<< 8)
  448. #define I2C_ISR_TCR (1<< 7)
  449. #define I2C_ISR_TC (1<< 6)
  450. #define I2C_ISR_STOPF (1<< 5)
  451. #define I2C_ISR_NACKF (1<< 4)
  452. #define I2C_ISR_ADDR (1<< 3)
  453. #define I2C_ISR_RXNE (1<< 2)
  454. #define I2C_ISR_TXIS (1<< 1)
  455. #define I2C_ISR_TXE (1<< 0)
  456. #define I2C_ICR_ALERTCF (1<<13)
  457. #define I2C_ICR_TIMOUTCF (1<<12)
  458. #define I2C_ICR_PECCF (1<<11)
  459. #define I2C_ICR_OVRCF (1<<10)
  460. #define I2C_ICR_ARLOCF (1<< 9)
  461. #define I2C_ICR_BERRCF (1<< 8)
  462. #define I2C_ICR_STOPCF (1<< 5)
  463. #define I2C_ICR_NACKCF (1<< 4)
  464. #define I2C_ICR_ADDRCF (1<< 3)
  465. #define I2C1_BASE 0x40005400
  466. #define I2C2_BASE 0x40005800
  467. #define I2C3_BASE 0x40005C00
  468. /* USART */
  469. struct usart {
  470. uint32_t cr1; /* 00: Control #1 */
  471. uint32_t cr2; /* 00: Control #2 */
  472. uint32_t cr3; /* 00: Control #3 */
  473. uint32_t brr; /* 00: Baud rate */
  474. uint32_t gtpr; /* 00: Guard time & prescaler */
  475. uint32_t rtor; /* 00: Receive timeout */
  476. uint32_t rqr; /* 00: Request */
  477. uint32_t isr; /* 00: Interrupt & status */
  478. uint32_t icr; /* 00: Interrupt flag clear */
  479. uint32_t rdr; /* 00: Receive data */
  480. uint32_t tdr; /* 00: Transmit data */
  481. };
  482. #define USART_CR1_M1 (1u<<28)
  483. #define USART_CR1_OVER8 (1u<<15)
  484. #define USART_CR1_CMIE (1u<<14)
  485. #define USART_CR1_MME (1u<<13)
  486. #define USART_CR1_M0 (1u<<12)
  487. #define USART_CR1_WAKE (1u<<11)
  488. #define USART_CR1_PCE (1u<<10)
  489. #define USART_CR1_PS (1u<< 9)
  490. #define USART_CR1_PEIE (1u<< 8)
  491. #define USART_CR1_TXEIE (1u<< 7)
  492. #define USART_CR1_TCIE (1u<< 6)
  493. #define USART_CR1_RXNEIE (1u<< 5)
  494. #define USART_CR1_IDLEIE (1u<< 4)
  495. #define USART_CR1_TE (1u<< 3)
  496. #define USART_CR1_RE (1u<< 2)
  497. #define USART_CR1_UE (1u<< 0)
  498. #define USART_CR3_CTSIE (1u<<10)
  499. #define USART_CR3_CTSE (1u<< 9)
  500. #define USART_CR3_RTSE (1u<< 8)
  501. #define USART_CR3_DMAT (1u<< 7)
  502. #define USART_CR3_DMAR (1u<< 6)
  503. #define USART_CR3_SCEN (1u<< 5)
  504. #define USART_CR3_NACK (1u<< 4)
  505. #define USART_CR3_HDSEL (1u<< 3)
  506. #define USART_CR3_IRLP (1u<< 2)
  507. #define USART_CR3_IREN (1u<< 1)
  508. #define USART_CR3_EIE (1u<< 0)
  509. #define USART_RQR_TXFRQ (1u<< 4)
  510. #define USART_RQR_RXFRQ (1u<< 3)
  511. #define USART_RQR_MMRQ (1u<< 2)
  512. #define USART_RQR_SBKRQ (1u<< 1)
  513. #define USART_RQR_ABRRQ (1u<< 0)
  514. #define USART_ISR_TCBGT (1u<<25)
  515. #define USART_ISR_TEACK (1u<<21)
  516. #define USART_ISR_RWU (1u<<19)
  517. #define USART_ISR_SBKF (1u<<18)
  518. #define USART_ISR_CMF (1u<<17)
  519. #define USART_ISR_BUSY (1u<<16)
  520. #define USART_ISR_ABRF (1u<<15)
  521. #define USART_ISR_ABRE (1u<<14)
  522. #define USART_ISR_EOBF (1u<<12)
  523. #define USART_ISR_RTOF (1u<<11)
  524. #define USART_ISR_CTS (1u<<10)
  525. #define USART_ISR_CTSIF (1u<< 9)
  526. #define USART_ISR_LBDF (1u<< 8)
  527. #define USART_ISR_TXE (1u<< 7)
  528. #define USART_ISR_TC (1u<< 6)
  529. #define USART_ISR_RXNE (1u<< 5)
  530. #define USART_ISR_IDLE (1u<< 4)
  531. #define USART_ISR_ORE (1u<< 3)
  532. #define USART_ISR_NF (1u<< 2)
  533. #define USART_ISR_FE (1u<< 1)
  534. #define USART_ISR_PE (1u<< 0)
  535. #define USART_ICR_CMCF (1u<<17)
  536. #define USART_ICR_EOBCF (1u<<12)
  537. #define USART_ICR_RTOCF (1u<<11)
  538. #define USART_ICR_CTSCF (1u<< 9)
  539. #define USART_ICR_LBDCF (1u<< 8)
  540. #define USART_ICR_TCBGTCF (1u<< 7)
  541. #define USART_ICR_TCCF (1u<< 6)
  542. #define USART_ICR_IDLECF (1u<< 4)
  543. #define USART_ICR_ORECF (1u<< 3)
  544. #define USART_ICR_NCF (1u<< 2)
  545. #define USART_ICR_FECF (1u<< 1)
  546. #define USART_ICR_PECF (1u<< 0)
  547. #define USART1_BASE 0x40011000
  548. #define USART2_BASE 0x40004400
  549. #define USART3_BASE 0x40004800
  550. #define USART4_BASE 0x40004C00
  551. #define USART5_BASE 0x40005000
  552. #define USART6_BASE 0x40011400
  553. #define USB_OTG_FS_BASE 0x50000000
  554. #define USB_OTG_HS_BASE 0x40040000
  555. /* USB High-Speed PHY Controller */
  556. struct hsphyc {
  557. uint32_t pll1; /* +00: PLL1 control */
  558. uint32_t _0[2];
  559. uint32_t tune; /* +0C: Tuning control */
  560. uint32_t _1[2];
  561. uint32_t ldo; /* +18: LDO control and status */
  562. };
  563. #define HSPHYC_PLL1_SEL(x) ((x)<<1)
  564. #define HSPHYC_PLL1_EN (1u<< 0)
  565. #define HSPHYC_TUNE_SQLBYP (1u<<23)
  566. #define HSPHYC_TUNE_SHTCCTCTLPROT (1u<<22)
  567. #define HSPHYC_TUNE_HSRXOFF(x) ((x)<<20)
  568. #define HSPHYC_TUNE_HSFALLPREEM (1u<<19)
  569. #define HSPHYC_TUNE_STAGSEL (1u<<18)
  570. #define HSPHYC_TUNE_HFRXGNEQEN (1u<<17)
  571. #define HSPHYC_TUNE_SQLCHCTL(x) ((x)<<15)
  572. #define HSPHYC_TUNE_HSDRVCHKZTRM(x) ((x)<<13)
  573. #define HSPHYC_TUNE_HSDRVCHKITRIM(x) ((x)<< 9)
  574. #define HSPHYC_TUNE_HSDRVRFRED (1u<< 8)
  575. #define HSPHYC_TUNE_FSDRVRFADJ (1u<< 7)
  576. #define HSPHYC_TUNE_HSDRVCURINGR (1u<< 6)
  577. #define HSPHYC_TUNE_HSDRVDCLEV (1u<< 5)
  578. #define HSPHYC_TUNE_HSDRVDCCUR (1u<< 4)
  579. #define HSPHYC_TUNE_HSDRVSLEW (1u<< 3)
  580. #define HSPHYC_TUNE_LFSCAPEN (1u<< 2)
  581. #define HSPHYC_TUNE_INCURRINT (1u<< 1)
  582. #define HSPHYC_TUNE_INCURREN (1u<< 0)
  583. #define HSPHYC_LDO_ENABLE (1u<< 2)
  584. #define HSPHYC_LDO_STATUS (1u<< 1)
  585. #define HSPHYC_LDO_USED (1u<< 0)
  586. #define HSPHYC_BASE 0x40017C00
  587. /*
  588. * Local variables:
  589. * mode: C
  590. * c-file-style: "Linux"
  591. * c-basic-offset: 4
  592. * tab-width: 4
  593. * indent-tabs-mode: nil
  594. * End:
  595. */