floppy.c 28 KB

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  1. /*
  2. * floppy.c
  3. *
  4. * Floppy interface control.
  5. *
  6. * Written & released by Keir Fraser <keir.xen@gmail.com>
  7. *
  8. * This is free and unencumbered software released into the public domain.
  9. * See the file COPYING for more details, or visit <http://unlicense.org>.
  10. */
  11. #define m(bitnr) (1u<<(bitnr))
  12. #define get_index() gpio_read_pin(gpio_index, pin_index)
  13. #define get_trk0() gpio_read_pin(gpio_trk0, pin_trk0)
  14. #define get_wrprot() gpio_read_pin(gpio_wrprot, pin_wrprot)
  15. #define configure_pin(pin, type) \
  16. gpio_configure_pin(gpio_##pin, pin_##pin, type)
  17. #define SAMPLE_MHZ 72
  18. #define TIM_PSC (SYSCLK_MHZ / SAMPLE_MHZ)
  19. #define sample_ns(x) (((x) * SAMPLE_MHZ) / 1000)
  20. #define sample_us(x) ((x) * SAMPLE_MHZ)
  21. #define time_from_samples(x) ((x) * TIME_MHZ / SAMPLE_MHZ)
  22. #define write_pin(pin, level) \
  23. gpio_write_pin(gpio_##pin, pin_##pin, level ? O_TRUE : O_FALSE)
  24. static int bus_type = -1;
  25. static int unit_nr = -1;
  26. static struct {
  27. int cyl;
  28. bool_t motor;
  29. } unit[3];
  30. static struct gw_delay delay_params;
  31. static const struct gw_delay factory_delay_params = {
  32. .select_delay = 10,
  33. .step_delay = 3000,
  34. .seek_settle = 15,
  35. .motor_delay = 750,
  36. .auto_off = 10000
  37. };
  38. #if STM32F == 1
  39. #include "floppy_f1.c"
  40. #elif STM32F == 7
  41. #include "floppy_f7.c"
  42. #endif
  43. static struct index {
  44. /* Main code can reset this at will. */
  45. volatile unsigned int count;
  46. /* For synchronising index pulse reporting to the RDATA flux stream. */
  47. volatile unsigned int rdata_cnt;
  48. } index;
  49. /* A DMA buffer for running a timer associated with a floppy-data I/O pin. */
  50. static struct dma_ring {
  51. /* Indexes into the buf[] ring buffer. */
  52. uint16_t cons; /* dma_rd: our consumer index for flux samples */
  53. union {
  54. uint16_t prod; /* dma_wr: our producer index for flux samples */
  55. timcnt_t prev_sample; /* dma_rd: previous CCRx sample value */
  56. };
  57. /* DMA ring buffer of timer values (ARR or CCRx). */
  58. timcnt_t buf[512];
  59. } dma;
  60. static struct {
  61. time_t deadline;
  62. bool_t armed;
  63. } auto_off;
  64. static enum {
  65. ST_inactive,
  66. ST_command_wait,
  67. ST_zlp,
  68. ST_read_flux,
  69. ST_read_flux_drain,
  70. ST_write_flux_wait_data,
  71. ST_write_flux_wait_index,
  72. ST_write_flux,
  73. ST_write_flux_drain,
  74. ST_erase_flux,
  75. ST_source_bytes,
  76. ST_sink_bytes,
  77. } floppy_state = ST_inactive;
  78. static uint32_t u_cons, u_prod;
  79. #define U_MASK(x) ((x)&(U_BUF_SZ-1))
  80. static void step_one_out(void)
  81. {
  82. write_pin(dir, FALSE);
  83. delay_us(10);
  84. write_pin(step, TRUE);
  85. delay_us(10);
  86. write_pin(step, FALSE);
  87. delay_us(delay_params.step_delay);
  88. }
  89. static void step_one_in(void)
  90. {
  91. write_pin(dir, TRUE);
  92. delay_us(10);
  93. write_pin(step, TRUE);
  94. delay_us(10);
  95. write_pin(step, FALSE);
  96. delay_us(delay_params.step_delay);
  97. }
  98. static void _set_bus_type(uint8_t type)
  99. {
  100. int i;
  101. bus_type = type;
  102. unit_nr = -1;
  103. for (i = 0; i < ARRAY_SIZE(unit); i++) {
  104. unit[i].cyl = -1;
  105. unit[i].motor = FALSE;
  106. }
  107. reset_bus();
  108. }
  109. static bool_t set_bus_type(uint8_t type)
  110. {
  111. if (type == bus_type)
  112. return TRUE;
  113. if (type > BUS_SHUGART)
  114. return FALSE;
  115. _set_bus_type(type);
  116. return TRUE;
  117. }
  118. static uint8_t floppy_seek(unsigned int cyl)
  119. {
  120. int cur_cyl;
  121. if (unit_nr < 0)
  122. return ACK_NO_UNIT;
  123. cur_cyl = unit[unit_nr].cyl;
  124. if ((cyl == 0) || (cur_cyl < 0)) {
  125. unsigned int i;
  126. for (i = 0; i < 256; i++) {
  127. if (get_trk0() == LOW)
  128. break;
  129. step_one_out();
  130. }
  131. cur_cyl = 0;
  132. if (get_trk0() == HIGH) {
  133. unit[unit_nr].cyl = -1;
  134. return ACK_NO_TRK0;
  135. }
  136. }
  137. if (cur_cyl < 0) {
  138. } else if (cur_cyl <= cyl) {
  139. unsigned int nr = cyl - cur_cyl;
  140. while (nr--)
  141. step_one_in();
  142. } else {
  143. unsigned int nr = cur_cyl - cyl;
  144. while (nr--)
  145. step_one_out();
  146. }
  147. delay_ms(delay_params.seek_settle);
  148. unit[unit_nr].cyl = cyl;
  149. return ACK_OKAY;
  150. }
  151. static void floppy_flux_end(void)
  152. {
  153. /* Turn off write pins. */
  154. write_pin(wgate, FALSE);
  155. configure_pin(wdata, GPO_bus);
  156. /* Turn off timers. */
  157. tim_rdata->ccer = 0;
  158. tim_rdata->cr1 = 0;
  159. tim_rdata->sr = 0; /* dummy, drains any pending DMA */
  160. tim_wdata->ccer = 0;
  161. tim_wdata->cr1 = 0;
  162. tim_wdata->sr = 0; /* dummy, drains any pending DMA */
  163. /* Turn off DMA. */
  164. dma_rdata.cr &= ~DMA_CR_EN;
  165. dma_wdata.cr &= ~DMA_CR_EN;
  166. while ((dma_rdata.cr & DMA_CR_EN) || (dma_wdata.cr & DMA_CR_EN))
  167. continue;
  168. }
  169. static void floppy_reset(void)
  170. {
  171. floppy_state = ST_inactive;
  172. auto_off.armed = FALSE;
  173. floppy_flux_end();
  174. drive_deselect();
  175. act_led(FALSE);
  176. }
  177. void floppy_init(void)
  178. {
  179. floppy_mcu_init();
  180. /* Output pins, unbuffered. */
  181. configure_pin(densel, GPO_bus);
  182. configure_pin(dir, GPO_bus);
  183. configure_pin(step, GPO_bus);
  184. configure_pin(wgate, GPO_bus);
  185. configure_pin(side, GPO_bus);
  186. configure_pin(wdata, GPO_bus);
  187. /* Input pins. */
  188. configure_pin(index, GPI_bus);
  189. configure_pin(trk0, GPI_bus);
  190. configure_pin(wrprot, GPI_bus);
  191. /* Configure INDEX-changed IRQs and timer. */
  192. exti->rtsr = 0;
  193. exti->imr = exti->ftsr = m(pin_index);
  194. IRQx_set_prio(irq_index, INDEX_IRQ_PRI);
  195. IRQx_enable(irq_index);
  196. delay_params = factory_delay_params;
  197. _set_bus_type(BUS_NONE);
  198. }
  199. static struct gw_info gw_info = {
  200. .max_index = 15, .max_cmd = CMD_MAX,
  201. .sample_freq = 72000000u,
  202. .hw_type = STM32F
  203. };
  204. static void auto_off_arm(void)
  205. {
  206. auto_off.armed = TRUE;
  207. auto_off.deadline = time_now() + time_ms(delay_params.auto_off);
  208. }
  209. static void floppy_end_command(void *ack, unsigned int ack_len)
  210. {
  211. auto_off_arm();
  212. usb_write(EP_TX, ack, ack_len);
  213. u_cons = u_prod = 0;
  214. if (floppy_state == ST_command_wait)
  215. act_led(FALSE);
  216. if (ack_len == usb_bulk_mps) {
  217. ASSERT(floppy_state == ST_command_wait);
  218. floppy_state = ST_zlp;
  219. }
  220. }
  221. /*
  222. * READ PATH
  223. */
  224. static struct {
  225. union {
  226. time_t start; /* read, write: Time at which read/write started. */
  227. time_t end; /* erase: Time at which to end the erasure. */
  228. };
  229. uint8_t status;
  230. uint8_t idx, nr_idx;
  231. bool_t packet_ready;
  232. bool_t write_finished;
  233. bool_t terminate_at_index;
  234. bool_t no_flux_area;
  235. unsigned int packet_len;
  236. int ticks_since_index;
  237. uint32_t ticks_since_flux;
  238. uint32_t index_ticks[15];
  239. uint8_t packet[USB_HS_MPS];
  240. } rw;
  241. static void rdata_encode_flux(void)
  242. {
  243. const uint16_t buf_mask = ARRAY_SIZE(dma.buf) - 1;
  244. uint16_t cons = dma.cons, prod;
  245. timcnt_t prev = dma.prev_sample, curr, next;
  246. uint32_t ticks = rw.ticks_since_flux;
  247. int ticks_since_index = rw.ticks_since_index;
  248. ASSERT(rw.idx < rw.nr_idx);
  249. /* We don't want to race the Index IRQ handler. */
  250. IRQ_global_disable();
  251. /* Find out where the DMA engine's producer index has got to. */
  252. prod = ARRAY_SIZE(dma.buf) - dma_rdata.ndtr;
  253. if (rw.idx != index.count) {
  254. /* We have just passed the index mark: Record information about
  255. * the just-completed revolution. */
  256. int partial_flux = ticks + (timcnt_t)(index.rdata_cnt - prev);
  257. rw.index_ticks[rw.idx++] = ticks_since_index + partial_flux;
  258. ticks_since_index = -partial_flux;
  259. }
  260. IRQ_global_enable();
  261. /* Process the flux timings into the raw bitcell buffer. */
  262. for (; cons != prod; cons = (cons+1) & buf_mask) {
  263. next = dma.buf[cons];
  264. curr = next - prev;
  265. prev = next;
  266. ticks += curr;
  267. if (ticks == 0) {
  268. /* 0: Skip. */
  269. } else if (ticks < 250) {
  270. /* 1-249: One byte. */
  271. u_buf[U_MASK(u_prod++)] = ticks;
  272. } else {
  273. unsigned int high = ticks / 250;
  274. if (high <= 5) {
  275. /* 250-1499: Two bytes. */
  276. u_buf[U_MASK(u_prod++)] = 249 + high;
  277. u_buf[U_MASK(u_prod++)] = 1 + (ticks % 250);
  278. } else {
  279. /* 1500-(2^28-1): Five bytes */
  280. u_buf[U_MASK(u_prod++)] = 0xff;
  281. u_buf[U_MASK(u_prod++)] = 1 | (ticks << 1);
  282. u_buf[U_MASK(u_prod++)] = 1 | (ticks >> 6);
  283. u_buf[U_MASK(u_prod++)] = 1 | (ticks >> 13);
  284. u_buf[U_MASK(u_prod++)] = 1 | (ticks >> 20);
  285. }
  286. }
  287. ticks_since_index += ticks;
  288. ticks = 0;
  289. }
  290. /* If it has been a long time since the last flux timing, transfer some of
  291. * the accumulated time from the 16-bit timestamp into the 32-bit
  292. * accumulator. This avoids 16-bit overflow and because, we take care to
  293. * keep the 16-bit timestamp at least 200us behind, we cannot race the next
  294. * flux timestamp. */
  295. if (sizeof(timcnt_t) == sizeof(uint16_t)) {
  296. curr = tim_rdata->cnt - prev;
  297. if (unlikely(curr > sample_us(400))) {
  298. prev += sample_us(200);
  299. ticks += sample_us(200);
  300. }
  301. }
  302. /* Save our progress for next time. */
  303. dma.cons = cons;
  304. dma.prev_sample = prev;
  305. rw.ticks_since_flux = ticks;
  306. rw.ticks_since_index = ticks_since_index;
  307. }
  308. static uint8_t floppy_read_prep(const struct gw_read_flux *rf)
  309. {
  310. if ((rf->nr_idx == 0) || (rf->nr_idx > gw_info.max_index))
  311. return ACK_BAD_COMMAND;
  312. /* Prepare Timer & DMA. */
  313. dma_rdata.mar = (uint32_t)(unsigned long)dma.buf;
  314. dma_rdata.ndtr = ARRAY_SIZE(dma.buf);
  315. rdata_prep();
  316. /* DMA soft state. */
  317. dma.cons = 0;
  318. dma.prev_sample = tim_rdata->cnt;
  319. /* Start Timer. */
  320. tim_rdata->cr1 = TIM_CR1_CEN;
  321. index.count = 0;
  322. floppy_state = ST_read_flux;
  323. memset(&rw, 0, sizeof(rw));
  324. rw.nr_idx = rf->nr_idx;
  325. rw.start = time_now();
  326. rw.status = ACK_OKAY;
  327. return ACK_OKAY;
  328. }
  329. static void make_read_packet(unsigned int n)
  330. {
  331. unsigned int c = U_MASK(u_cons);
  332. unsigned int l = U_BUF_SZ - c;
  333. if (l < n) {
  334. memcpy(rw.packet, &u_buf[c], l);
  335. memcpy(&rw.packet[l], u_buf, n-l);
  336. } else {
  337. memcpy(rw.packet, &u_buf[c], n);
  338. }
  339. u_cons += n;
  340. rw.packet_ready = TRUE;
  341. }
  342. static void floppy_read(void)
  343. {
  344. unsigned int avail = (uint32_t)(u_prod - u_cons);
  345. if (floppy_state == ST_read_flux) {
  346. rdata_encode_flux();
  347. avail = (uint32_t)(u_prod - u_cons);
  348. if (avail > U_BUF_SZ) {
  349. /* Overflow */
  350. printk("OVERFLOW %u %u %u %u\n", u_cons, u_prod,
  351. rw.packet_ready, ep_tx_ready(EP_TX));
  352. floppy_flux_end();
  353. rw.status = ACK_FLUX_OVERFLOW;
  354. floppy_state = ST_read_flux_drain;
  355. u_cons = u_prod = avail = 0;
  356. } else if (rw.idx >= rw.nr_idx) {
  357. /* Read all requested revolutions. */
  358. floppy_flux_end();
  359. floppy_state = ST_read_flux_drain;
  360. } else if ((index.count == 0)
  361. && (time_since(rw.start) > time_ms(2000))) {
  362. /* Timeout */
  363. printk("NO INDEX\n");
  364. floppy_flux_end();
  365. rw.status = ACK_NO_INDEX;
  366. floppy_state = ST_read_flux_drain;
  367. u_cons = u_prod = avail = 0;
  368. }
  369. } else if ((avail < usb_bulk_mps)
  370. && !rw.packet_ready
  371. && ep_tx_ready(EP_TX)) {
  372. /* Final packet, including ACK byte (NUL). */
  373. memset(rw.packet, 0, usb_bulk_mps);
  374. make_read_packet(avail);
  375. floppy_state = ST_command_wait;
  376. floppy_end_command(rw.packet, avail+1);
  377. return; /* FINISHED */
  378. }
  379. if (!rw.packet_ready && (avail >= usb_bulk_mps))
  380. make_read_packet(usb_bulk_mps);
  381. if (rw.packet_ready && ep_tx_ready(EP_TX)) {
  382. usb_write(EP_TX, rw.packet, usb_bulk_mps);
  383. rw.packet_ready = FALSE;
  384. }
  385. }
  386. /*
  387. * WRITE PATH
  388. */
  389. static unsigned int _wdata_decode_flux(timcnt_t *tbuf, unsigned int nr)
  390. {
  391. unsigned int todo = nr;
  392. uint32_t x, ticks = rw.ticks_since_flux;
  393. if (todo == 0)
  394. return 0;
  395. if (rw.no_flux_area) {
  396. unsigned int nfa_pulse = sample_ns(1250);
  397. while (ticks >= nfa_pulse) {
  398. *tbuf++ = nfa_pulse - 1;
  399. ticks -= nfa_pulse;
  400. if (!--todo)
  401. goto out;
  402. }
  403. rw.no_flux_area = FALSE;
  404. }
  405. while (u_cons != u_prod) {
  406. x = u_buf[U_MASK(u_cons)];
  407. if (x == 0) {
  408. /* 0: Terminate */
  409. u_cons++;
  410. rw.write_finished = TRUE;
  411. goto out;
  412. } else if (x < 250) {
  413. /* 1-249: One byte */
  414. u_cons++;
  415. } else if (x < 255) {
  416. /* 250-254: Two bytes */
  417. if ((uint32_t)(u_prod - u_cons) < 2)
  418. goto out;
  419. u_cons++;
  420. x = (x - 249) * 250;
  421. x += u_buf[U_MASK(u_cons++)] - 1;
  422. } else {
  423. /* 255: Five bytes */
  424. if ((uint32_t)(u_prod - u_cons) < 5)
  425. goto out;
  426. u_cons++;
  427. x = (u_buf[U_MASK(u_cons++)] ) >> 1;
  428. x |= (u_buf[U_MASK(u_cons++)] & 0xfe) << 6;
  429. x |= (u_buf[U_MASK(u_cons++)] & 0xfe) << 13;
  430. x |= (u_buf[U_MASK(u_cons++)] & 0xfe) << 20;
  431. }
  432. ticks += x;
  433. if (ticks < sample_ns(800))
  434. continue;
  435. if (ticks > sample_us(150)) {
  436. rw.no_flux_area = TRUE;
  437. goto out;
  438. }
  439. *tbuf++ = ticks - 1;
  440. ticks = 0;
  441. if (!--todo)
  442. goto out;
  443. }
  444. out:
  445. rw.ticks_since_flux = ticks;
  446. return nr - todo;
  447. }
  448. static void wdata_decode_flux(void)
  449. {
  450. const uint16_t buf_mask = ARRAY_SIZE(dma.buf) - 1;
  451. uint16_t nr_to_wrap, nr_to_cons, nr, dmacons;
  452. /* Find out where the DMA engine's consumer index has got to. */
  453. dmacons = ARRAY_SIZE(dma.buf) - dma_wdata.ndtr;
  454. /* Find largest contiguous stretch of ring buffer we can fill. */
  455. nr_to_wrap = ARRAY_SIZE(dma.buf) - dma.prod;
  456. nr_to_cons = (dmacons - dma.prod - 1) & buf_mask;
  457. nr = min(nr_to_wrap, nr_to_cons);
  458. /* Now attempt to fill the contiguous stretch with flux data calculated
  459. * from buffered bitcell data. */
  460. dma.prod += _wdata_decode_flux(&dma.buf[dma.prod], nr);
  461. dma.prod &= buf_mask;
  462. }
  463. static void floppy_process_write_packet(void)
  464. {
  465. int len = ep_rx_ready(EP_RX);
  466. if ((len >= 0) && !rw.packet_ready) {
  467. usb_read(EP_RX, rw.packet, len);
  468. rw.packet_ready = TRUE;
  469. rw.packet_len = len;
  470. }
  471. if (rw.packet_ready) {
  472. unsigned int avail = U_BUF_SZ - (uint32_t)(u_prod - u_cons);
  473. unsigned int n = rw.packet_len;
  474. if (avail >= n) {
  475. unsigned int p = U_MASK(u_prod);
  476. unsigned int l = U_BUF_SZ - p;
  477. if (l < n) {
  478. memcpy(&u_buf[p], rw.packet, l);
  479. memcpy(u_buf, &rw.packet[l], n-l);
  480. } else {
  481. memcpy(&u_buf[p], rw.packet, n);
  482. }
  483. u_prod += n;
  484. rw.packet_ready = FALSE;
  485. }
  486. }
  487. }
  488. static uint8_t floppy_write_prep(const struct gw_write_flux *wf)
  489. {
  490. if (get_wrprot() == LOW)
  491. return ACK_WRPROT;
  492. wdata_prep();
  493. /* WDATA DMA setup: From a circular buffer into the WDATA Timer's ARR. */
  494. dma_wdata.par = (uint32_t)(unsigned long)&tim_wdata->arr;
  495. dma_wdata.mar = (uint32_t)(unsigned long)dma.buf;
  496. /* Initialise DMA ring indexes (consumer index is implicit). */
  497. dma_wdata.ndtr = ARRAY_SIZE(dma.buf);
  498. dma.prod = 0;
  499. floppy_state = ST_write_flux_wait_data;
  500. memset(&rw, 0, sizeof(rw));
  501. rw.status = ACK_OKAY;
  502. rw.terminate_at_index = wf->terminate_at_index;
  503. return ACK_OKAY;
  504. }
  505. static void floppy_write_wait_data(void)
  506. {
  507. bool_t write_finished;
  508. floppy_process_write_packet();
  509. wdata_decode_flux();
  510. /* Wait for DMA and input buffers to fill, or write stream to end. We must
  511. * take care because, since we are not yet draining the DMA buffer, the
  512. * write stream may end without us noticing and setting rw.write_finished.
  513. * Hence we peek for a NUL byte in the input buffer if it's non-empty. */
  514. write_finished = ((u_prod == u_cons)
  515. ? rw.write_finished
  516. : (u_buf[U_MASK(u_prod-1)] == 0));
  517. if (((dma.prod != (ARRAY_SIZE(dma.buf)-1))
  518. || ((uint32_t)(u_prod - u_cons) < (U_BUF_SZ - 512)))
  519. && !write_finished)
  520. return;
  521. floppy_state = ST_write_flux_wait_index;
  522. rw.start = time_now();
  523. /* Enable DMA only after flux values are generated. */
  524. dma_wdata_start();
  525. /* Preload timer with first flux value. */
  526. tim_wdata->egr = TIM_EGR_UG;
  527. tim_wdata->sr = 0; /* dummy write, gives h/w time to process EGR.UG=1 */
  528. barrier(); /* Trigger timer update /then/ wait for next index pulse */
  529. index.count = 0;
  530. }
  531. static void floppy_write_wait_index(void)
  532. {
  533. if (index.count == 0) {
  534. if (time_since(rw.start) > time_ms(2000)) {
  535. /* Timeout */
  536. floppy_flux_end();
  537. rw.status = ACK_NO_INDEX;
  538. floppy_state = ST_write_flux_drain;
  539. }
  540. return;
  541. }
  542. /* Start timer. */
  543. tim_wdata->cr1 = TIM_CR1_CEN;
  544. /* Enable output. */
  545. configure_pin(wdata, AFO_bus);
  546. write_pin(wgate, TRUE);
  547. index.count = 0;
  548. floppy_state = ST_write_flux;
  549. }
  550. static void floppy_write_check_underflow(void)
  551. {
  552. uint32_t avail = u_prod - u_cons;
  553. if (/* We've run the input buffer dry. */
  554. (avail == 0)
  555. /* The input buffer is nearly dry, and doesn't contain EOStream. */
  556. || ((avail < 16) && (u_buf[U_MASK(u_prod-1)] != 0))) {
  557. /* Underflow */
  558. printk("UNDERFLOW %u %u %u %u\n", u_cons, u_prod,
  559. rw.packet_ready, ep_rx_ready(EP_RX));
  560. floppy_flux_end();
  561. rw.status = ACK_FLUX_UNDERFLOW;
  562. floppy_state = ST_write_flux_drain;
  563. }
  564. }
  565. static void floppy_write(void)
  566. {
  567. uint16_t dmacons, todo, prev_todo;
  568. floppy_process_write_packet();
  569. wdata_decode_flux();
  570. /* Early termination on index pulse? */
  571. if (rw.terminate_at_index && (index.count != 0))
  572. goto terminate;
  573. if (!rw.write_finished) {
  574. floppy_write_check_underflow();
  575. return;
  576. }
  577. /* Wait for DMA ring to drain. */
  578. todo = ~0;
  579. do {
  580. /* Check for early termination on index pulse. */
  581. if (rw.terminate_at_index && (index.count != 0))
  582. goto terminate;
  583. /* Check progress of draining the DMA ring. */
  584. prev_todo = todo;
  585. dmacons = ARRAY_SIZE(dma.buf) - dma_wdata.ndtr;
  586. todo = (dma.prod - dmacons) & (ARRAY_SIZE(dma.buf) - 1);
  587. } while ((todo != 0) && (todo <= prev_todo));
  588. terminate:
  589. floppy_flux_end();
  590. floppy_state = ST_write_flux_drain;
  591. }
  592. static void floppy_write_drain(void)
  593. {
  594. /* Drain the write stream. */
  595. if (!rw.write_finished) {
  596. floppy_process_write_packet();
  597. (void)_wdata_decode_flux(dma.buf, ARRAY_SIZE(dma.buf));
  598. return;
  599. }
  600. /* Wait for space to write ACK packet. */
  601. if (!ep_tx_ready(EP_TX))
  602. return;
  603. /* ACK with Status byte. */
  604. u_buf[0] = rw.status;
  605. floppy_state = ST_command_wait;
  606. floppy_end_command(u_buf, 1);
  607. }
  608. /*
  609. * ERASE PATH
  610. */
  611. static uint8_t floppy_erase_prep(const struct gw_erase_flux *ef)
  612. {
  613. if (get_wrprot() == LOW)
  614. return ACK_WRPROT;
  615. write_pin(wgate, TRUE);
  616. floppy_state = ST_erase_flux;
  617. memset(&rw, 0, sizeof(rw));
  618. rw.status = ACK_OKAY;
  619. rw.end = time_now() + time_from_samples(ef->erase_ticks);
  620. return ACK_OKAY;
  621. }
  622. static void floppy_erase(void)
  623. {
  624. if (time_since(rw.end) < 0)
  625. return;
  626. write_pin(wgate, FALSE);
  627. /* ACK with Status byte. */
  628. u_buf[0] = rw.status;
  629. floppy_state = ST_command_wait;
  630. floppy_end_command(u_buf, 1);
  631. }
  632. /*
  633. * SINK/SOURCE
  634. */
  635. static struct {
  636. unsigned int todo;
  637. unsigned int min_delta;
  638. unsigned int max_delta;
  639. } ss;
  640. static void sink_source_prep(const struct gw_sink_source_bytes *ssb)
  641. {
  642. ss.min_delta = INT_MAX;
  643. ss.max_delta = 0;
  644. ss.todo = ssb->nr_bytes;
  645. }
  646. static void ss_update_deltas(int len)
  647. {
  648. uint32_t *u_times = (uint32_t *)u_buf;
  649. time_t delta, now = time_now();
  650. unsigned int p = u_prod;
  651. /* Every four bytes we store a timestamp in a u_buf[]-sized ring buffer.
  652. * We then record min/max time taken to overwrite a previous timestamp. */
  653. while (len--) {
  654. if (p++ & 3)
  655. continue;
  656. delta = time_diff(u_times[U_MASK(p)>>2], now);
  657. u_times[U_MASK(p)>>2] = now;
  658. if ((delta > ss.max_delta) && (p >= U_BUF_SZ))
  659. ss.max_delta = delta;
  660. if ((delta < ss.min_delta) && (p >= U_BUF_SZ))
  661. ss.min_delta = delta;
  662. }
  663. u_prod = p;
  664. }
  665. static void source_bytes(void)
  666. {
  667. if (!ep_tx_ready(EP_TX))
  668. return;
  669. if (ss.todo < usb_bulk_mps) {
  670. floppy_state = ST_command_wait;
  671. floppy_end_command(rw.packet, ss.todo);
  672. return; /* FINISHED */
  673. }
  674. usb_write(EP_TX, rw.packet, usb_bulk_mps);
  675. ss.todo -= usb_bulk_mps;
  676. ss_update_deltas(usb_bulk_mps);
  677. }
  678. static void sink_bytes(void)
  679. {
  680. int len;
  681. if (ss.todo == 0) {
  682. /* We're done: Wait for space to write the ACK byte. */
  683. if (!ep_tx_ready(EP_TX))
  684. return;
  685. u_buf[0] = ACK_OKAY;
  686. floppy_state = ST_command_wait;
  687. floppy_end_command(u_buf, 1);
  688. return; /* FINISHED */
  689. }
  690. /* Packet ready? */
  691. len = ep_rx_ready(EP_RX);
  692. if (len < 0)
  693. return;
  694. /* Read it and adjust byte counter. */
  695. usb_read(EP_RX, rw.packet, len);
  696. ss.todo = (ss.todo <= len) ? 0 : ss.todo - len;
  697. ss_update_deltas(len);
  698. }
  699. static void process_command(void)
  700. {
  701. uint8_t cmd = u_buf[0];
  702. uint8_t len = u_buf[1];
  703. uint8_t resp_sz = 2;
  704. auto_off_arm();
  705. act_led(TRUE);
  706. switch (cmd) {
  707. case CMD_GET_INFO: {
  708. uint8_t idx = u_buf[2];
  709. if (len != 3)
  710. goto bad_command;
  711. memset(&u_buf[2], 0, 32);
  712. switch(idx) {
  713. case GETINFO_FIRMWARE: /* gw_info */
  714. gw_info.fw_major = fw_major;
  715. gw_info.fw_minor = fw_minor;
  716. memcpy(&u_buf[2], &gw_info, sizeof(gw_info));
  717. break;
  718. case GETINFO_BW_STATS: /* gw_bw_stats */ {
  719. struct gw_bw_stats bw;
  720. bw.min_bw.bytes = U_BUF_SZ;
  721. bw.min_bw.usecs = ss.max_delta / time_us(1);
  722. bw.max_bw.bytes = U_BUF_SZ;
  723. bw.max_bw.usecs = ss.min_delta / time_us(1);
  724. memcpy(&u_buf[2], &bw, sizeof(bw));
  725. break;
  726. }
  727. default:
  728. goto bad_command;
  729. }
  730. resp_sz += 32;
  731. break;
  732. }
  733. case CMD_SEEK: {
  734. uint8_t cyl = u_buf[2];
  735. if ((len != 3) || (cyl > 85))
  736. goto bad_command;
  737. u_buf[1] = floppy_seek(cyl);
  738. goto out;
  739. }
  740. case CMD_SIDE: {
  741. uint8_t side = u_buf[2];
  742. if ((len != 3) || (side > 1))
  743. goto bad_command;
  744. write_pin(side, side);
  745. break;
  746. }
  747. case CMD_SET_PARAMS: {
  748. uint8_t idx = u_buf[2];
  749. if ((len < 3) || (idx != PARAMS_DELAYS)
  750. || (len > (3 + sizeof(delay_params))))
  751. goto bad_command;
  752. memcpy(&delay_params, &u_buf[3], len-3);
  753. break;
  754. }
  755. case CMD_GET_PARAMS: {
  756. uint8_t idx = u_buf[2];
  757. uint8_t nr = u_buf[3];
  758. if ((len != 4) || (idx != PARAMS_DELAYS)
  759. || (nr > sizeof(delay_params)))
  760. goto bad_command;
  761. memcpy(&u_buf[2], &delay_params, nr);
  762. resp_sz += nr;
  763. break;
  764. }
  765. case CMD_MOTOR: {
  766. uint8_t unit = u_buf[2], on_off = u_buf[3];
  767. if ((len != 4) || (on_off & ~1))
  768. goto bad_command;
  769. u_buf[1] = drive_motor(unit, on_off & 1);
  770. goto out;
  771. }
  772. case CMD_READ_FLUX: {
  773. struct gw_read_flux rf = { .nr_idx = 2 };
  774. if ((len < 2) || (len > (2 + sizeof(rf))))
  775. goto bad_command;
  776. memcpy(&rf, &u_buf[2], len-2);
  777. u_buf[1] = floppy_read_prep(&rf);
  778. goto out;
  779. }
  780. case CMD_WRITE_FLUX: {
  781. struct gw_write_flux wf = { 0 };
  782. if ((len < 2) || (len > (2 + sizeof(wf))))
  783. goto bad_command;
  784. memcpy(&wf, &u_buf[2], len-2);
  785. u_buf[1] = floppy_write_prep(&wf);
  786. goto out;
  787. }
  788. case CMD_GET_FLUX_STATUS: {
  789. if (len != 2)
  790. goto bad_command;
  791. u_buf[1] = rw.status;
  792. goto out;
  793. }
  794. case CMD_GET_INDEX_TIMES: {
  795. uint8_t f = u_buf[2], n = u_buf[3];
  796. if ((len != 4) || (n > 15) || ((f+n) > gw_info.max_index))
  797. goto bad_command;
  798. memcpy(&u_buf[2], rw.index_ticks+f, n*4);
  799. resp_sz += n*4;
  800. break;
  801. }
  802. case CMD_SELECT: {
  803. uint8_t unit = u_buf[2];
  804. if (len != 3)
  805. goto bad_command;
  806. u_buf[1] = drive_select(unit);
  807. goto out;
  808. }
  809. case CMD_DESELECT: {
  810. if (len != 2)
  811. goto bad_command;
  812. drive_deselect();
  813. break;
  814. }
  815. case CMD_SET_BUS_TYPE: {
  816. uint8_t type = u_buf[2];
  817. if ((len != 3) || !set_bus_type(type))
  818. goto bad_command;
  819. break;
  820. }
  821. case CMD_SET_PIN: {
  822. uint8_t pin = u_buf[2];
  823. uint8_t level = u_buf[3];
  824. if ((len != 4) || (level & ~1))
  825. goto bad_command;
  826. if (pin != 2) {
  827. u_buf[1] = ACK_BAD_PIN;
  828. goto out;
  829. }
  830. gpio_write_pin(gpio_densel, pin_densel, level);
  831. break;
  832. }
  833. case CMD_RESET: {
  834. if (len != 2)
  835. goto bad_command;
  836. delay_params = factory_delay_params;
  837. _set_bus_type(BUS_NONE);
  838. write_pin(densel, FALSE);
  839. break;
  840. }
  841. case CMD_ERASE_FLUX: {
  842. struct gw_erase_flux ef;
  843. if (len != (2 + sizeof(ef)))
  844. goto bad_command;
  845. memcpy(&ef, &u_buf[2], len-2);
  846. u_buf[1] = floppy_erase_prep(&ef);
  847. goto out;
  848. }
  849. case CMD_SOURCE_BYTES:
  850. case CMD_SINK_BYTES: {
  851. struct gw_sink_source_bytes ssb;
  852. if (len != (2 + sizeof(ssb)))
  853. goto bad_command;
  854. memcpy(&ssb, &u_buf[2], len-2);
  855. floppy_state = (cmd == CMD_SOURCE_BYTES)
  856. ? ST_source_bytes : ST_sink_bytes;
  857. sink_source_prep(&ssb);
  858. break;
  859. }
  860. case CMD_SWITCH_FW_MODE: {
  861. uint8_t mode = u_buf[2];
  862. if ((len != 3) || (mode & ~1))
  863. goto bad_command;
  864. if (mode == FW_MODE_BOOTLOADER) {
  865. usb_deinit();
  866. delay_ms(500);
  867. /* Poke a flag in SRAM1, picked up by the bootloader. */
  868. *(volatile uint32_t *)0x20010000 = 0xdeadbeef;
  869. system_reset();
  870. }
  871. break;
  872. }
  873. default:
  874. goto bad_command;
  875. }
  876. u_buf[1] = ACK_OKAY;
  877. out:
  878. floppy_end_command(u_buf, resp_sz);
  879. return;
  880. bad_command:
  881. u_buf[1] = ACK_BAD_COMMAND;
  882. goto out;
  883. }
  884. static void floppy_configure(void)
  885. {
  886. auto_off_arm();
  887. floppy_flux_end();
  888. floppy_state = ST_command_wait;
  889. u_cons = u_prod = 0;
  890. act_led(FALSE);
  891. }
  892. void floppy_process(void)
  893. {
  894. int i, len;
  895. if (auto_off.armed && (time_since(auto_off.deadline) >= 0)) {
  896. floppy_flux_end();
  897. for (i = 0; i < ARRAY_SIZE(unit); i++) {
  898. if (unit[i].motor)
  899. drive_motor(i, FALSE);
  900. }
  901. drive_deselect();
  902. auto_off.armed = FALSE;
  903. }
  904. switch (floppy_state) {
  905. case ST_command_wait:
  906. len = ep_rx_ready(EP_RX);
  907. if ((len >= 0) && (len < (U_BUF_SZ-u_prod))) {
  908. usb_read(EP_RX, &u_buf[u_prod], len);
  909. u_prod += len;
  910. }
  911. if ((u_prod >= 2) && (u_prod >= u_buf[1]) && ep_tx_ready(EP_TX)) {
  912. process_command();
  913. }
  914. break;
  915. case ST_zlp:
  916. if (ep_tx_ready(EP_TX)) {
  917. usb_write(EP_TX, NULL, 0);
  918. floppy_state = ST_command_wait;
  919. }
  920. break;
  921. case ST_read_flux:
  922. case ST_read_flux_drain:
  923. floppy_read();
  924. break;
  925. case ST_write_flux_wait_data:
  926. floppy_write_wait_data();
  927. break;
  928. case ST_write_flux_wait_index:
  929. floppy_write_wait_index();
  930. break;
  931. case ST_write_flux:
  932. floppy_write();
  933. break;
  934. case ST_write_flux_drain:
  935. floppy_write_drain();
  936. break;
  937. case ST_erase_flux:
  938. floppy_erase();
  939. break;
  940. case ST_source_bytes:
  941. source_bytes();
  942. break;
  943. case ST_sink_bytes:
  944. sink_bytes();
  945. break;
  946. default:
  947. break;
  948. }
  949. }
  950. const struct usb_class_ops usb_cdc_acm_ops = {
  951. .reset = floppy_reset,
  952. .configure = floppy_configure
  953. };
  954. /*
  955. * INTERRUPT HANDLERS
  956. */
  957. static void IRQ_INDEX_changed(void)
  958. {
  959. /* Clear INDEX-changed flag. */
  960. exti->pr = m(pin_index);
  961. index.count++;
  962. index.rdata_cnt = tim_rdata->cnt;
  963. }
  964. /*
  965. * Local variables:
  966. * mode: C
  967. * c-file-style: "Linux"
  968. * c-basic-offset: 4
  969. * tab-width: 4
  970. * indent-tabs-mode: nil
  971. * End:
  972. */