Fix data out pins for scsi

sw/src/main.cpp

@@ -83,16 +83,10 @@ static const uint32_t scsiDbInputOutputAnd_PEREG      = 0b0000000000000000001111
 static const uint32_t scsiDbInputOutputPullAnd_PEREG  = 0b00000000000000000101010101010001;
 
 
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-// Put DB and DP in output mode
+// Put DB and DP in output mode and control buffers
 #define SCSI_DB_OUTPUT() { PDREG->MODER = (PDREG->MODER & scsiDbInputOutputAnd_PDREG) | scsiDbOutputRegOr_PDREG; PEREG->MODER = (PEREG->MODER & scsiDbInputOutputAnd_PEREG) | scsiDbOutputRegOr_PEREG; SCSI_BUFFERS_OUT() ;}
 
-// Put DB and DP in input mode
+// Put DB and DP in input mode and control buffers
 #define SCSI_DB_INPUT()  { PDREG->MODER = (PDREG->MODER & scsiDbInputOutputAnd_PDREG); PEREG->MODER = (PEREG->MODER & scsiDbInputOutputAnd_PEREG); SCSI_BUFFERS_IN();}
 #define SCSI_SET_PULL()  { PDREG->PUPDR |= scsiDbInputOutputPullAnd_PDREG; PEREG->PUPDR |= scsiDbInputOutputPullAnd_PEREG; }
 
@@ -137,13 +131,13 @@ static uint32_t genBSRR(uint32_t data) {
   // positions[0] is for data bit 0, position[1] for data bit 1, etc
   // DB0, DB1, DB2, DB4, DB5, DB6, DB7 in order
   uint8_t positions[] = {0UL, 1UL, 2UL, 3UL, 4UL, 5UL, 6UL, 7UL};
-  uint8_t dbpPosition = 0UL;
-  int reqPosition = 6;
+  uint8_t dbpPosition = 8UL;
+  int reqPosition = 13UL;
   uint8_t bitsAsserted = 0;
 
   uint32_t output = 0x00000000;
 
-  //BLACKSASI should be simplied now
+  //BLACKSASI should be able to simplify now
   for (int i = 0; i < 8; i++) {
     if (data & (0x1 << masks[i])) {
       // There's a one in this bit position, BSRR reset
@@ -531,8 +525,10 @@ void onBusReset(void)
  */
 inline void writeHandshake(byte d)
 {
-  GPIOB->regs->BSRR = db_bsrr[d]; // setup DB,DBP (160ns)
-  SCSI_DB_OUTPUT() // (180ns)
+  //BLACKSASI NEED TO BE FIXED IN NEXT PCB!!!!
+  GPIOD->regs->BSRR = (db_bsrr[d] & 0xFF); // setup DB(160ns)
+  GPIOE->regs->BSRR = ((db_bsrr[d] & 0x0100) >> 8); // setup DBP(160ns)
+  SCSI_DB_OUTPUT() // 
   // ACK.Fall to DB output delay 100ns(MAX)  (DTC-510B)
   SCSI_OUT(vREQ,inactive) // setup wait (30ns)
   SCSI_OUT(vREQ,inactive) // setup wait (30ns)
@@ -542,9 +538,11 @@ inline void writeHandshake(byte d)
   while(!m_isBusReset && !SCSI_IN(vACK));
   
   // ACK.Fall to REQ.Raise delay 500ns(typ.) (DTC-510B)
-   //BLACKSASI NEED TO BE FIXED !!!!
-  uint32_t bsrrCall = ((db_bsrr[0xff] & 0xFFBFFFFF) | 0x00000040);
-  GPIOD->regs->BSRR = bsrrCall;  // DB=0xFF , SCSI_OUT(vREQ,inactive)
+  //BLACKSASI need to be fixed in next PCB
+  uint32_t bsrrCallE = ((db_bsrr[0xff] & 0xFFDFFFFF) | 0x00000020);
+  uint32_t bsrrCallD = ((db_bsrr[0xff] & 0xFFFFFFFF) | 0x00000000);
+  GPIOE->regs->BSRR = bsrrCallE;  
+  GPIOD->regs->BSRR = bsrrCallD;  
   
   // REQ.Raise to DB hold time 0ns
   SCSI_DB_INPUT() // (150ns)
@@ -608,7 +606,7 @@ void writeDataPhaseSD(uint32_t adds, uint32_t len)
     /*register*/ byte src_byte;                       // Send data bytes
     register const uint32_t *bsrr_tbl = db_bsrr;  // Table to convert to BSRR
     register uint32_t bsrr_val;                   // BSRR value to output (DB, DBP, REQ = ACTIVE)
-    register volatile uint32 *db_dst = &(GPIOB->regs->BSRR); // DB&DBP Output port
+    register volatile uint32 *db_dst = &(GPIOB->regs->BSRR); // DB&DBP Output port BLACKSASI
 
     // prefetch & 1st out
     FETCH_SRC();