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@@ -1,5 +1,5 @@
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Analysis & Synthesis report for max80
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-Fri Aug 6 18:12:58 2021
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+Fri Aug 6 18:17:26 2021
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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@@ -67,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+---------------------------------------------+
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-; Analysis & Synthesis Status ; Successful - Fri Aug 6 18:12:58 2021 ;
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+; Analysis & Synthesis Status ; Successful - Fri Aug 6 18:17:26 2021 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; max80 ;
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; Top-level Entity Name ; max80 ;
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@@ -197,6 +197,7 @@ https://fpgasoftware.intel.com/eula.
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; ip/hdmitx.v ; yes ; User Wizard-Generated File ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v ; ;
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; ip/pll.v ; yes ; User Wizard-Generated File ; /home/hpa/abc80/max80/blinktest/ip/pll.v ; ;
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; transpose.sv ; yes ; User SystemVerilog HDL File ; /home/hpa/abc80/max80/blinktest/transpose.sv ; ;
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+; tmdsenc.sv ; yes ; User SystemVerilog HDL File ; /home/hpa/abc80/max80/blinktest/tmdsenc.sv ; ;
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; max80.sv ; yes ; User SystemVerilog HDL File ; /home/hpa/abc80/max80/blinktest/max80.sv ; ;
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; altpll.tdf ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/altpll.tdf ; ;
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; aglobal201.inc ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/aglobal201.inc ; ;
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@@ -204,7 +205,6 @@ https://fpgasoftware.intel.com/eula.
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; stratixii_pll.inc ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
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; cycloneii_pll.inc ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
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; db/pll_altpll.v ; yes ; Auto-Generated Megafunction ; /home/hpa/abc80/max80/blinktest/db/pll_altpll.v ; ;
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-; tmdsenc.v ; yes ; Auto-Found Verilog HDL File ; /home/hpa/abc80/max80/blinktest/tmdsenc.v ; ;
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; altlvds_tx.tdf ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/altlvds_tx.tdf ; ;
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; stratix_lvds_transmitter.inc ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc ; ;
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; stratixii_lvds_transmitter.inc ; yes ; Megafunction ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ; ;
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@@ -1093,11 +1093,10 @@ Note: In order to hide this table in the UI and the text report file, please set
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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- Info: Processing started: Fri Aug 6 18:12:53 2021
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+ Info: Processing started: Fri Aug 6 18:17:21 2021
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
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-Warning (12019): Can't analyze file -- file syncho.v is missing
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Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
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Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
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Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
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@@ -1106,6 +1105,12 @@ Info (12021): Found 3 design units, including 3 entities, in source file transpo
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Info (12023): Found entity 1: condreg File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 4
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Info (12023): Found entity 2: transpose File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 35
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Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
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+Warning (12019): Can't analyze file -- file syncho.sv is missing
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+Warning (10229): Verilog HDL Expression warning at tmdsenc.sv(84): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 84
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+Warning (10259): Verilog HDL error at tmdsenc.sv(93): constant value overflow File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 93
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+Warning (10229): Verilog HDL Expression warning at tmdsenc.sv(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 117
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+Info (12021): Found 1 design units, including 1 entities, in source file tmdsenc.sv
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+ Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 73
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Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
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Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
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Warning (10236): Verilog HDL Implicit Net warning at max80.sv(184): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
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@@ -1265,17 +1270,12 @@ Info (12128): Elaborating entity "pll_cntr" for hierarchy "pll:pll|altpll:altpll
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Info (12128): Elaborating entity "pll_cmpr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|pll_cmpr:cmpr12" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 273
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Info (12128): Elaborating entity "pll_cntr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 573
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Info (12128): Elaborating entity "pll_cmpr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|pll_cmpr1:cmpr14" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 421
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-Warning (10229): Verilog HDL Expression warning at tmdsenc.v(84): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 84
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-Warning (10259): Verilog HDL error at tmdsenc.v(93): constant value overflow File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 93
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-Warning (10229): Verilog HDL Expression warning at tmdsenc.v(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 117
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-Warning (12125): Using design file tmdsenc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
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- Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 73
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Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 179
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-Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 92
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-Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 134
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-Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 135
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-Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 140
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-Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 145
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+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 92
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+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 134
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+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 135
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+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 140
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+Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 145
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Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 196
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Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
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Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
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@@ -1341,12 +1341,12 @@ Info (12128): Elaborating entity "hdmitx_shift_reg" for hierarchy "hdmitx:hdmitx
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Info (12128): Elaborating entity "hdmitx_shift_reg1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 819
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Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 89
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-Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
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+Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
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Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
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Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
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@@ -1368,35 +1368,35 @@ Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
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Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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Info (13005): Duplicate registers merged to single register
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[7]" merged to single register "dummydata[0]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[0]" merged to single register "dummydata[1]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[1]" merged to single register "dummydata[2]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[2]" merged to single register "dummydata[3]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[3]" merged to single register "dummydata[4]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[4]" merged to single register "dummydata[5]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[5]" merged to single register "dummydata[6]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[6]" merged to single register "dummydata[7]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[7]" merged to single register "dummydata[8]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[0]" merged to single register "dummydata[9]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[1]" merged to single register "dummydata[10]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[2]" merged to single register "dummydata[11]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[3]" merged to single register "dummydata[12]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[4]" merged to single register "dummydata[13]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[5]" merged to single register "dummydata[14]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[6]" merged to single register "dummydata[15]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[7]" merged to single register "dummydata[16]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[0]" merged to single register "dummydata[17]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[1]" merged to single register "dummydata[18]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[2]" merged to single register "dummydata[19]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[3]" merged to single register "dummydata[20]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[4]" merged to single register "dummydata[21]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[5]" merged to single register "dummydata[22]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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- Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[6]" merged to single register "dummydata[23]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[7]" merged to single register "dummydata[0]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[0]" merged to single register "dummydata[1]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[1]" merged to single register "dummydata[2]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[2]" merged to single register "dummydata[3]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[3]" merged to single register "dummydata[4]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[4]" merged to single register "dummydata[5]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[5]" merged to single register "dummydata[6]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[6]" merged to single register "dummydata[7]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[7]" merged to single register "dummydata[8]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[0]" merged to single register "dummydata[9]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[1]" merged to single register "dummydata[10]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[2]" merged to single register "dummydata[11]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[3]" merged to single register "dummydata[12]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[4]" merged to single register "dummydata[13]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[5]" merged to single register "dummydata[14]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[6]" merged to single register "dummydata[15]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[7]" merged to single register "dummydata[16]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[0]" merged to single register "dummydata[17]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[1]" merged to single register "dummydata[18]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[2]" merged to single register "dummydata[19]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[3]" merged to single register "dummydata[20]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[4]" merged to single register "dummydata[21]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[5]" merged to single register "dummydata[22]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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+ Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[6]" merged to single register "dummydata[23]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 615
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Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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Info (13005): Duplicate registers merged to single register
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
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- Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 88
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 88
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+ Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 88
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Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
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Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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Warning (13039): The following bidirectional pins have no drivers
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@@ -1426,7 +1426,7 @@ Warning (13032): The following tri-state nodes are fed by constants
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Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
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Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
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Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
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-Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
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+Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
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Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
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Warning (13024): Output pins are stuck at VCC or GND
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Warning (13410): Pin "abc_d_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
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@@ -1518,10 +1518,10 @@ Info (21057): Implemented 484 device resources after synthesis - the final resou
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Info (21060): Implemented 51 bidirectional pins
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Info (21061): Implemented 340 logic cells
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Info (21065): Implemented 2 PLLs
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-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 219 warnings
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- Info: Peak virtual memory: 678 megabytes
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- Info: Processing ended: Fri Aug 6 18:12:58 2021
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+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 218 warnings
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+ Info: Peak virtual memory: 676 megabytes
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+ Info: Processing ended: Fri Aug 6 18:17:26 2021
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Info: Elapsed time: 00:00:05
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- Info: Total CPU time (on all processors): 00:00:16
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+ Info: Total CPU time (on all processors): 00:00:15
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H. Peter Anvin