Update configuration assigments, JIC generation

max80.qsf

@@ -284,4 +284,7 @@ set_location_assignment PIN_A3 -to abc_nmi_x
 set_location_assignment PIN_B3 -to abc_int80_x
 set_location_assignment PIN_D3 -to sr_clk
 
+set_global_assignment -name GENERATE_JAM_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

max80jic.cof

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
 <cof>
-	<eprom_name>EPCQ128A</eprom_name>
+	<eprom_name>MT25QL128</eprom_name>
 	<flash_loader_device>EP4CE15</flash_loader_device>
 	<output_filename>output_files/max80.jic</output_filename>
 	<n_pages>1</n_pages>

output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Fri Aug  6 18:02:17 2021
+Fri Aug  6 18:13:07 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -11,9 +11,10 @@ Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
   3. Assembler Settings
   4. Assembler Generated Files
   5. Assembler Device Options: max80.sof
-  6. Assembler Device Options: max80.jbc
-  7. Assembler Device Options: max80.pof
-  8. Assembler Messages
+  6. Assembler Device Options: max80.jam
+  7. Assembler Device Options: max80.jbc
+  8. Assembler Device Options: max80.pof
+  9. Assembler Messages
 
 
 
@@ -40,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Aug  6 18:02:17 2021 ;
+; Assembler Status      ; Successful - Fri Aug  6 18:13:07 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -61,6 +62,7 @@ https://fpgasoftware.intel.com/eula.
 ; File Name                                              ;
 +--------------------------------------------------------+
 ; /home/hpa/abc80/max80/blinktest/output_files/max80.sof ;
+; /home/hpa/abc80/max80/blinktest/output_files/max80.jam ;
 ; /home/hpa/abc80/max80/blinktest/output_files/max80.jbc ;
 ; /home/hpa/abc80/max80/blinktest/output_files/max80.pof ;
 +--------------------------------------------------------+
@@ -76,6 +78,15 @@ https://fpgasoftware.intel.com/eula.
 +----------------+--------------------+
 
 
++-------------------------------------+
+; Assembler Device Options: max80.jam ;
++-------------------------+-----------+
+; Option                  ; Setting   ;
++-------------------------+-----------+
+; JEDEC STAPL ASCII file  ;           ;
++-------------------------+-----------+
+
+
 +-------------------------------------+
 ; Assembler Device Options: max80.jbc ;
 +-----------------------+-------------+
@@ -102,16 +113,18 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:02:15 2021
+    Info: Processing started: Fri Aug  6 18:13:05 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info (210117): Created JAM or JBC file for the specified chain: 
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
+Info (210117): Created JAM or JBC file for the specified chain: 
+Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 570 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:17 2021
+    Info: Peak virtual memory: 569 megabytes
+    Info: Processing ended: Fri Aug  6 18:13:07 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

output_files/max80.done

@@ -1 +1 @@
-Fri Aug  6 18:02:21 2021
+Fri Aug  6 18:13:11 2021

output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Fri Aug  6 18:02:21 2021
+Fri Aug  6 18:13:11 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Fri Aug  6 18:02:21 2021 ;
+; EDA Netlist Writer Status ; Successful - Fri Aug  6 18:13:11 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -84,15 +84,15 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:02:20 2021
+    Info: Processing started: Fri Aug  6 18:13:11 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 815 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:21 2021
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 816 megabytes
+    Info: Processing ended: Fri Aug  6 18:13:11 2021
+    Info: Elapsed time: 00:00:00
     Info: Total CPU time (on all processors): 00:00:00
 
 

output_files/max80.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for max80
-Fri Aug  6 18:02:14 2021
+Fri Aug  6 18:13:04 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -73,7 +73,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Fri Aug  6 18:02:14 2021       ;
+; Fitter Status                      ; Successful - Fri Aug  6 18:13:04 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -1694,8 +1694,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Error detection CRC                                              ; Off           ;
 ; Enable open drain on CRC_ERROR pin                               ; Off           ;
 ; Enable input tri-state on active configuration pins in user mode ; Off           ;
-; Configuration Voltage Level                                      ; Auto          ;
-; Force Configuration Voltage Level                                ; Off           ;
+; Configuration Voltage Level                                      ; 3.3V          ;
+; Force Configuration Voltage Level                                ; On            ;
 ; nCEO                                                             ; Unreserved    ;
 ; Data[0]                                                          ; Unreserved    ;
 ; Data[1]/ASDO                                                     ; Unreserved    ;
@@ -1818,6 +1818,8 @@ Info (12825): Data[1]/ASDO dual-purpose pin not reserved
 Info (12825): nCSO dual-purpose pin not reserved
 Info (12825): DCLK dual-purpose pin not reserved
 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
+Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
 Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
     Warning (176118): Pin "hdmi_d[0]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[0](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 108
     Warning (176118): Pin "hdmi_d[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[1](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 108
@@ -1929,6 +1931,8 @@ Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
+Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
 Warning (169180): Following 1 pins must use external clamping diodes.
     Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
@@ -2078,8 +2082,8 @@ Warning (169064): Following 51 pins have no output enable or a GND or VCC output
     Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 113
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 31 warnings
-    Info: Peak virtual memory: 1488 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:14 2021
+    Info: Peak virtual memory: 1521 megabytes
+    Info: Processing ended: Fri Aug  6 18:13:04 2021
     Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:07
 

output_files/max80.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Fri Aug  6 18:02:14 2021
+Fitter Status : Successful - Fri Aug  6 18:13:04 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Fri Aug  6 18:02:21 2021
+Fri Aug  6 18:13:11 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Fri Aug  6 18:02:21 2021       ;
+; Flow Status                        ; Successful - Fri Aug  6 18:13:11 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 08/06/2021 18:02:03 ;
+; Start date & time ; 08/06/2021 18:12:53 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 160641081344597.162829812334854        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 117270187186385.162829877337083        ; --            ; --          ; --                                ;
 ; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 678 MB              ; 00:00:15                           ;
-; Fitter               ; 00:00:06     ; 1.0                     ; 1488 MB             ; 00:00:07                           ;
-; Assembler            ; 00:00:02     ; 1.0                     ; 570 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:01     ; 1.0                     ; 1029 MB             ; 00:00:01                           ;
+; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 678 MB              ; 00:00:16                           ;
+; Fitter               ; 00:00:06     ; 1.0                     ; 1521 MB             ; 00:00:07                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1020 MB             ; 00:00:01                           ;
 ; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 728 MB              ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 815 MB              ; 00:00:00                           ;
-; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:26                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
+; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:27                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

output_files/max80.jam

@@ -0,0 +1,2286 @@
+'Copyright (C) 2020  Intel Corporation. All rights reserved.
+'Your use of Intel Corporation's design tools, logic functions 
+'and other software and tools, and any partner logic 
+'functions, and any output files from any of the foregoing 
+'(including device programming or simulation files), and any 
+'associated documentation or information are expressly subject 
+'to the terms and conditions of the Intel Program License 
+'Subscription Agreement, the Intel Quartus Prime License Agreement,
+'the Intel FPGA IP License Agreement, or other applicable license
+'agreement, including, without limitation, that your use is for
+'the sole purpose of programming logic devices manufactured by
+'Intel and sold by Intel or its authorized distributors.  Please
+'refer to the applicable agreement for further details, at
+'https://fpgasoftware.intel.com/eula.
+
+'Device #1: EP4CE15 - /home/hpa/abc80/max80/blinktest/output_files/max80.sof Fri Aug  6 18:13:05 2021
+
+
+NOTE "CREATOR" "QUARTUS PRIME JAM COMPOSER 20.1";
+NOTE "DATE" "2021/08/06";
+NOTE "DEVICE" "EP4CE15";
+NOTE "NEED_FREQUENCY_CONTROL" "0";
+NOTE "FILE" "max80.sof";
+NOTE "TARGET" "1";
+NOTE "IDCODE" "020F20DD";
+NOTE "USERCODE" "0010F462";
+NOTE "CHECKSUM" "0010F462";
+NOTE "SAVE_DATA" "DEVICE_DATA";
+NOTE "SAVE_DATA_VARIABLES" "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A105, A109, A111";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "JAM_VERSION" "2.0";
+NOTE "ALG_VERSION" "68";
+ACTION CONFIGURE = L20, DO_READ_USERCODE OPTIONAL, DO_HALT_ON_CHIP_CC OPTIONAL, DO_IGNORE_IDCODE_ERRORS OPTIONAL, DO_IGNORE_INTOSC_BYPASS RECOMMENDED, DO_BYPASS_SECOND_IDCODE_READ OPTIONAL,
+L27;
+ACTION READ_USERCODE = L25, L27;
+ACTION CHECK_IDCODE = L966, L27;
+DATA DEVICE_DATA;
+INTEGER V0 = 1;
+INTEGER V1 = 0;
+BOOLEAN V185 = 0;
+BOOLEAN V193 = 0;
+INTEGER A12[1] = 12;
+INTEGER A105[1] = 0;
+INTEGER A59[1] = 1080;
+INTEGER A60[1] = 409;
+INTEGER A61[2] = 34545885, 1;
+INTEGER A13[1] = 36;
+INTEGER A147[1] = 0;
+INTEGER A25[1] = 10;
+INTEGER A43[1] = 4087056;
+INTEGER A109[1] = 0;
+INTEGER A111[1] = 0;
+INTEGER A125[1] = 0;
+INTEGER A186[1] = 0;
+INTEGER A174[2] = 0, 0;
+INTEGER A92[1] = 0;
+INTEGER A94[1] = 0;
+BOOLEAN A95[1] = $0;
+BOOLEAN A93[1] = $0;
+BOOLEAN A96[1];
+INTEGER A97 = 1;
+BOOLEAN A42[4087056] = @
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+Ku900yVm@3t@@VtaKVXS@ThIqtv000KZW00Go77s@lS000Dj600avMB@F0voxv00
+02000a0Z00WoNii@@n000ntzu9z0Lj00ePu100zFyVxJ@lUr@9VNqz7qA00_lyC_
+FFBX@7i7008AJ10Wnx_Fyl@@Ey@_Fo700eLwDs@Uq@xNy@_5XyU8v20WqKF00000
+1OuR3Q_sWXlDevR66MtWSgPuvQ36_sWQjPeH0Zo88D04hOfVbF00000yAKxNaF00
+000WMPblz@or@dyz@7d@Vw@9aVZ1z@RmxDCS6l4ltOG_z9yUJ2D2OK61i9q21u@W
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+000W0G@@4200eWZ00Got@d_GQz@3900eTM000rzBN@57200kJA00GW@z6GFF00WP
+X200ayz@3t@Vm@@7y@@3t@Vmzv3006OhF66k@@W@@lwLu100T25008u@@BVx@W@@
+Fu@@RU_@al@Fvx@FE@@Yt@Vux4Q_sWXlDevR6W000qyT23VRGpt6Cyj1DVpGZ06b
+HGQ0e3R2_@@W@@Fu@@@Ey@Zp@Fxoy10010WmO9z@4olnW_@Duz66ol9XByJuz63Q
+MEXmCPeH0Zo88DXM80@7yV@3@J0AeLe1W4a4G04GJ8209a8X44WaG20281198W4X
+5a2K4I8G09X981K4aGG0IIB9288aWW02WMI2GG8XH95W4a4G0G2J8A09a9e0KWcG
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+40o_59ayz@JtxwFn5100us600Gnx@FS@@7@dyOtC0002e@@G000uIG00e@VCcFlB
+0100z@FpDJCq@lG000M2@x@XxTT@1d000DGO00OtVIkmjQ00WiQ500AVx@_7_Vu_
+@3_@@al@Fu@@3_@@W@@Vu_@VE_@W@@Fu@@FktU00G000WEX2004y@@BFAnvxdB00
+G1u00mmt9qyj1000W0WW0qyD3G000Q_EXXlDevR36_sWclPeH060402q8WHP4e50
+SjbXx@Fu@@BVxXk@L701400ITmal@lyXs3T@108gf5l@VXoLyU33vtam5_9yUZ1N
+GdGtwCq8WHP4acGB4W@3_l@X@905q8a0G2I2802e941W4IaG22GI8101aWW44GYm
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+2cGR00Gm@@Ny_@3t@VmzFCUkw000Ry300qyiz0000000l2A00uuy@J__@Xx@Fu@@
+3_@@Xx@Fvx@3_@@W@@Fu@@7k@@Y@pN00qCy00WW@@Vu_@3_@@ot_Vu_@3_@@W@@V
+ux4Q_sWXlDevR6W000qyT23VRGpt6Cyj1DVpGZ06bHGQ0e3R2_@@Xx@Fu@@F@YV0
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+5qAq0G2I2802e941W4IaG22GI8101aWW44GYm2I1A2948Wam4a0A2I8809fb4144
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+1CAZWV02080P8b01a06WKGHG21181CW8WYHA220P@Y4I__@Zp@luz@7k@@W@@FwV
+s0080q@V8NBzmM0jq@@9000T0E004y@@3tBN@3aq@VBzFC3008000m@47006k@@z
+7ah@@3500XX5008u@@3_@@W@@Fvx@B9LqK0e86WAw@76DK001@@Vm@@FS@@Z4Nw@
+7NvBK18@4_5Aw0q@m@hVz9020WyRaG000W020WyR4IKf2G5vYM@Z420W0Y1eY_@X
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+WXlDevR6Q4meC2Um010G61ISYX1P4y300e4@100hN5RF@6y@m3z@F300O5x200ra
+9w8Adq@FC000w5A00K_sdzFS500801006c200EVZM04G0dl9400O71300JTUxuT2
+100_dz00G@3@tM33z@RmxDCKki4vtOmC_6yU33D2OK61d4@Z1P4y30aSp@34LG08
+m_rISXb154b0020WB6c10yVT@3ekUP2LKi100eWYCP8qYG0mcG101e0DX40aGI02
+G0D290aWa4IW0I2H08W48aW0a4MGKGH8111a8iW4WYG21289D99WWW422G0Q9H01
+X4CbK0aGI0209C2f0aWiW2W2Q2H08XC15W0q4I0G2P9R4m083f4D2OK61@W4G08Z
+0306GAGH8X01a06W4GHG211ceD0UUEV00006W006_@jKLUe@V@4hY0ayTodu_m4k
+X0W000Ji0Gq39V@xC2UV06SVxq@31ue0mrf@lxlS000Ww@@70004na3pefLuh918
+vxR1O00q@lGaKO0syYXj@LyPi7M9xXi02f@@J8E304y@@v_psm4jSwWAzFa3e67W
+zBKvi4Xw@@d_Bmew@S4GP04y@@TEeuk3Hr@V8Ex00YyXm_@n3xN0m@1@FyFdXO06
+2L1WohoC3anSlh0iO3jr_BK@@6eaA0Owod50W0y_lAu5J0Y_Sxe@3HNe0Gnzo180
+WuL@kARN5ENA0ddz@m@o10WWuuhVkzV3120WXdgYCO7Wnx_@Ut40010iNk1PyQGv
+v6yPk10201EGtWZ0Cu0T3E2eYs4Ju806I_bXLqb00000200W7@DuMT3YJtWw1IOd
+03wOaXC2CudH3wNt0001071O0000Xr0OeiT6_OdX4tDmjy202094100000048W20
+008m004G000941W02G08W8W00028000Cm0K290000002818020038001400GI900
+W0271a0280aZ0I0000nH06i6G200281804S40300I810140802G0000802eZ0Iuj
+V3E2814G000140000G0004eHW40200004Gw8W7_AmWZ0O0283qq09qKl1V5mGSz6
+ebb0eCIOsktWqxD0280m8@XysG202002Yu100000008JjCaZ0UuG23UJzXekV83L
+3_xaXiCb00G0Wpe7WyBU3W010200W1@P8@2C0100aV1C0100plG50000kiH0Mkjk
+v699tnPwQ763wA0zkZt4242vM1u@W@dkz@eV@@vu@RU_@Pv6R_chAyNYvRWHE2zl
+@@@@4088204210YW001;
+
+ENDDATA;
+DATA TEMP_DATA;
+INTEGER A0[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 15, 14, 13, 95, 23, 23, 23, 96, 96, 96, 96, 96, 95, 95, 95, 95, 95, 95, 95, 95, 95, 95, 15, 791, 791, 791, 791, 317, 293, 281, 273, 261, 253, 237, 791;
+INTEGER A1[46] =
+2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 16, 16, 16, 16, 3144, 16, 16, 16,3144,1574, 716, 360, 183,1574, 716, 360, 183,3144, 0,1574, 716, 360, 183, 64, 280, 240, 200, 160, 640, 480, 400, 320, 240, 160, 80,3144;
+INTEGER A2[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 165, 165, 165, 165, 0, 0, 0, 0, 0, 0, 0, 165;
+INTEGER A3[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 96, 80, 64, 0, 0, 0, 0, 0, 0, 0, 112;
+INTEGER A4[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 648, 600, 552, 504, 0, 0, 0, 0, 0, 0, 0, 648;
+INTEGER A5[46] =
+2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 2081, 16, 16, 16, 16, 3144, 18, 18, 18,3144,1574, 716, 360, 183,1574, 716, 360, 183,3144, 0,1574, 716, 360, 183, 64, 56, 48, 40, 32, 128, 96, 80, 64, 48, 32, 16,3144;
+INTEGER A6[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 32, 16, 8, 4, 2, 16, 8, 4, 2, 32, 24, 16, 8, 4, 2, 0, 0, 0, 0, 0, 16, 12, 10, 8, 6, 4, 2, 32;
+INTEGER A7[46] =
+-1, 524288, 262144, 131072, 65536, 32768, 16384, 8192, 2048, 512, 21760, 13056, 6912, 3328, 0, 16, 8, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 0, 0, 0, 0, 0, 0, 0, 7;
+INTEGER A8[46] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 512, 0, 0, 0, 512, 256, 128, 64, 32, 256, 128, 64, 32, 512, 384, 256, 128, 64, 32, 0, 560, 480, 400, 320, 256, 192, 160, 128, 96, 64, 32, 560;
+INTEGER A9[21] =
+12, 3, 131, 8, 3, 131, 0, 0, 0, 6, 3, 131, 0, 0, 0, 3, 1, 118, 1, 3, 126;
+INTEGER A10[14] =
+12, 3, 8, 3, 8, 3, 6, 3, 0, 0, 3, 1, 1, 1;
+INTEGER A51[19] =
+294, 0, 0, 0, 294, 148, 38, 20, 2, 148, 38, 20, 2, 294, 0, 148, 38, 20, 2;
+INTEGER A49[14] =
+12, 114, 8, 114, 8, 114, 6, 114, 0, 0, 3, 109, 1, 109;
+INTEGER A11[6 * 3 * 45] =
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  -1,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  33,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  32,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  25,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  24,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  22,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  21,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  20,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  18,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  16,
+0, 0,  0, 0, 0, 0, 3, 1536,12337, 3, 1280,12337, 0, 0, 0, 1, 0,  13360,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 3, 1280,12337, 1, 256, 13360, 1, 0,  13360,
+0, 0,  0, 0, 0, 0, 3, 1024,12337, 3, 768, 12337, 2, 0, 14128, 1, 0,  13360,
+3, 768, 12337, 3, 512, 12337, 3, 256, 12337, 3, 0, 12337, 2, 0, 14128, 1, 0,  13360,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 0,  98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, (39<<16)+0, 187, 32, (39<<16)+0, 145, 137, (39<<16)+0, 233, 176,
+0, 0,  0, 0, 0, 0, 0, 0, 0, (23<<16)+0, 187, 32, (23<<16)+0, 145, 137, (23<<16)+0, 237, 176,
+0, 0,  0, 0, 0, 0, 0, 0, 0, (15<<16)+0, 187, 32, (15<<16)+0, 145, 137, (7 <<16)+6, 113, 137,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1025, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1025, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1025, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1025, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0,  1025, 4, 0, 1, 1, 0, 1025, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 99, 1, 0,  99,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,  99, 1, 0, 99,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 99, 1, 0, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 99, 1, 0, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 99,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 99,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 98,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 97, 0, 1, 94,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 97, 0, 1, 94,
+0, 0,  0, 0, 0, 0, 1, 0, 98, 2, 1,  96, 1, 0, 97, 0, 2, 96,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 97, 0, 0, 96,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 98,
+0, 0,  0, 129, 10, 98, 1, 0, 98, 2, 1,  96, 1, 0, 97, 0, 0, 96,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  0,
+0, 0,  0, 0, 0, 0, 1, 1, 97, 1, 0,  97, 0, 2, 96, 0, 1,  96,
+0, 0,  0, 0, 0, 0, 0, 0, 0, 1, 31, 97, 4, 31, 98, 1, 0,  98;
+INTEGER A14[64] =
+8600,6400,4800,3600,2800,2000,1540,1140, 860, 640, 480, 360, 280, 200, 154, 116,
+86, 64, 50, 36, 28, 24, 20, 16, 14, 12, 11, 9, 7, 5, 4, 3,
+2000,1600,1300,1000, 900, 800, 720, 660, 600, 560, 520, 480, 440, 400, 380, 360,
+340, 300, 280, 260, 240, 220, 200, 180, 160, 140, 120, 100, 80, 60, 40, 20;
+INTEGER A15[16] =
+60000,28000,10800,4200,1660, 660, 260, 100, 500, 200, 100, 60, 40, 30, 20, 10;
+INTEGER A54[30] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 16, 0, 0, 0, 32, 0, 32, 255, 65, 255, 82, 255, 69, 255, 84, 255, 76, 255, 65;
+INTEGER A55[30] =
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 16, 0, 32, 0, 32, 255, 65, 255, 82, 255, 69, 255, 84, 255, 76, 255, 65;
+INTEGER A56[8] =
+255, 1, 255, 56, 255, 57, 255, 65;
+BOOLEAN V261  = 0;
+BOOLEAN V262  = 0;
+BOOLEAN V263  = 0;
+BOOLEAN V264  = 0;
+BOOLEAN V265[10000];
+BOOLEAN V266[3];
+BOOLEAN V278[15];
+BOOLEAN V279[16];
+INTEGER V267;
+INTEGER V268;
+INTEGER V269;
+BOOLEAN V189[80] = $80000000000000000000;
+BOOLEAN V190[80] = $80010000000000000000;
+BOOLEAN V192[80] = $00FF0000000000000000;
+' VARIABLES
+INTEGER A17[1];
+INTEGER A48[1];
+INTEGER A52[1];
+INTEGER A113[1];
+INTEGER A153[1];
+BOOLEAN A18[21];
+BOOLEAN A32[60];
+BOOLEAN A33[10];
+BOOLEAN A39[10];
+BOOLEAN A26[5];
+BOOLEAN A27[5];
+BOOLEAN A28[1];
+BOOLEAN A31[50];
+BOOLEAN A57[50];
+BOOLEAN A29[1080];
+BOOLEAN A45[1080];
+BOOLEAN A30[1080];
+BOOLEAN A34[50];
+BOOLEAN A35[50];
+BOOLEAN A36[50];
+BOOLEAN A37[50];
+BOOLEAN A38[70];
+INTEGER V2 = 0;
+BOOLEAN V216 = 0;
+INTEGER V3 = 0;
+INTEGER V4 = 0;
+INTEGER V77 = 0;
+INTEGER V78 = 0;
+INTEGER V186;
+INTEGER V187;
+BOOLEAN b;
+BOOLEAN ba[32];
+INTEGER i;
+INTEGER j;
+INTEGER k;
+INTEGER l;
+INTEGER m;
+INTEGER n;
+INTEGER V271;
+INTEGER V270;
+INTEGER V10;
+INTEGER V11;
+INTEGER V12;
+INTEGER V13;
+BOOLEAN A19[20];
+BOOLEAN A20[10];
+INTEGER V14;
+INTEGER V15;
+INTEGER V89;
+INTEGER V16;
+INTEGER V87;
+INTEGER V17;
+INTEGER V181;
+INTEGER V18;
+INTEGER V19;
+INTEGER V20;
+INTEGER V21;
+INTEGER V88;
+INTEGER V94;
+INTEGER V22;
+INTEGER V179;
+INTEGER V211;
+INTEGER V223;
+INTEGER V23;
+INTEGER V24;
+INTEGER V25;
+INTEGER V26;
+INTEGER V27;
+INTEGER V28;
+INTEGER V29 = 1;
+INTEGER A16[15];
+INTEGER V30;
+INTEGER V31;
+INTEGER V32 = 0;
+INTEGER V33 = 0;
+INTEGER V34 = 1;
+INTEGER V35 = 0;
+INTEGER V36 = 0;
+INTEGER V37 = 0;
+INTEGER V38 = 0;
+INTEGER V72 = 0;
+INTEGER V73 = 0;
+BOOLEAN V39 = 0;
+BOOLEAN V40 = 0;
+INTEGER V41 = 0;
+INTEGER V42 = 0;
+BOOLEAN V43 = 0;
+BOOLEAN V44 = 0;
+BOOLEAN V45 = 0;
+INTEGER V46;
+INTEGER V47;
+INTEGER V48;
+BOOLEAN V49 = 0;
+INTEGER V51 = -1;
+INTEGER V52 = -1;
+BOOLEAN V74 = 0;
+BOOLEAN V75 = 0;
+BOOLEAN V56 = 0;
+BOOLEAN V57 = 0;
+BOOLEAN V58 = 1;
+BOOLEAN A40[10];
+BOOLEAN A41[10];
+BOOLEAN A44[10];
+BOOLEAN V76 = 0;
+BOOLEAN V80 = 1;
+BOOLEAN V81 = 0;
+BOOLEAN V82 = 0;
+INTEGER V83 = 5;
+INTEGER V84 = 0;
+INTEGER V86 = 0;
+BOOLEAN V91 = 0;
+INTEGER V68 = 0;
+INTEGER V69 = 0;
+INTEGER V96 = 94;
+BOOLEAN V97 = 1;
+BOOLEAN V398 = 0;
+INTEGER V188 = 0;
+INTEGER V191 = 0;
+BOOLEAN V233 = 0;
+BOOLEAN V102 = 0;
+BOOLEAN V100 = 0;
+BOOLEAN V272 = 0;
+BOOLEAN V392 = 1;
+BOOLEAN V103 = 0;
+BOOLEAN V108 = 0;
+BOOLEAN V104 = 0;
+BOOLEAN V105 = 0;
+BOOLEAN V107 = 0;
+BOOLEAN V106 = 0;
+BOOLEAN V101 = 0;
+BOOLEAN V231 = 0;
+BOOLEAN V259 = 0;
+BOOLEAN V260 = 0;
+BOOLEAN V280 = 0;
+BOOLEAN V293 = 0;
+BOOLEAN V308 = 1;
+BOOLEAN V310 = 0;
+BOOLEAN V336 = 0;
+BOOLEAN V337 = 0;
+BOOLEAN V340 = 0;
+BOOLEAN V370 = 0;
+BOOLEAN V362 = 0;
+BOOLEAN V421 = 0;
+BOOLEAN A175 = 0;
+BOOLEAN USE_EXTEND_IR_DELAY_METHOD = 0;
+BOOLEAN USE_FIXED_ALGORITHM = 0;
+BOOLEAN USE_REV0_PROG_ALG = 0;
+INTEGER V203 = 0;
+BOOLEAN V228 = 0;
+BOOLEAN V344 = 0;
+BOOLEAN V431 = 1;
+BOOLEAN V230 = 0;
+BOOLEAN V232 = 0;
+BOOLEAN V393 = 0;
+ENDDATA;
+PROCEDURE DO_READ_USERCODE USES TEMP_DATA;
+V105 = 1;
+ENDPROC;
+PROCEDURE DO_HALT_ON_CHIP_CC USES TEMP_DATA;
+V230 = 1;
+ENDPROC;
+PROCEDURE DO_IGNORE_IDCODE_ERRORS USES TEMP_DATA;
+V232 = 1;
+ENDPROC;
+PROCEDURE DO_IGNORE_INTOSC_BYPASS USES TEMP_DATA;
+V393 = 1;
+ENDPROC;
+PROCEDURE DO_BYPASS_SECOND_IDCODE_READ USES TEMP_DATA;
+A175 = 1;
+ENDPROC;
+PROCEDURE L20 USES TEMP_DATA;
+V101 = 1;
+ENDPROC;
+PROCEDURE L25 USES TEMP_DATA;
+V105 = 1;
+ENDPROC;
+PROCEDURE L966 USES TEMP_DATA;
+V340 = 1;
+ENDPROC;
+PROCEDURE L27 USES DEVICE_DATA, TEMP_DATA, L39, L101, L107,
+L141, L1190,
+L1223,
+L124, L113, L108, L93;
+CALL L39;
+IF(!(V101 || V103 || V108 || V107 ||
+V100 || V102
+) &&
+V105) THEN GOTO L38;
+IF ((V42 == 0) && V340) THEN CALL L108;
+IF ((V42 == 0) && V340) THEN GOTO L38;
+V3 = 0;
+V4 = 32;
+CALL L101;
+IF (V2 == 0) THEN GOTO L28;
+IF ((V42 == 0) && V101) THEN CALL L1190;
+V3 = 0;
+V4 = 32;
+CALL L101;
+IF ((V42 == 0) && V101) THEN CALL L141;
+L28:
+IF ((V42 == 0) && V104) THEN CALL L124;
+L38:
+CALL L93;
+EXIT V42;
+ENDPROC;
+PROCEDURE L39 USES DEVICE_DATA, TEMP_DATA,
+L106, L458, L108, L107;
+INTEGER V66 = 0;
+INTEGER V90 = 0;
+INTEGER V95 = 0;
+INTEGER V67 = 0;
+INTEGER V180 = 0;
+INTEGER V212 = 0;
+INTEGER V224 = 0;
+INTEGER V199 = 0;
+INTEGER V201 = 0;
+INTEGER V202 = 0;
+IF (V103) THEN V102 = 1;
+IF (V106) THEN V107 = 1;
+IF ((V102 || V100) && !V103 &&
+(V108 || V107)) THEN V42 = 1;
+IF (V42 != 0) THEN GOTO L84;
+V21 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 1) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L40;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+L40:
+V21 = V21 + j;
+V66 = V66 + k;
+NEXT i;
+l = 0;
+FOR i = 4 TO 0 STEP -1;
+FOR j = 0 TO V1;
+IF (((A13[j] & 1) == 0) ||
+((A13[j] & 4) == 0)) THEN GOTO L41;
+V2 = A12[j];
+FOR k = 0 TO (A1[V2] - 1);
+IF ((k % 5) == i) THEN A26[l] = 1;
+l = l + 1;
+NEXT k;
+GOTO L42;
+L41:
+l = l + 1;
+L42:
+NEXT j;
+NEXT i;
+V88 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 256) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L43;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+IF ((V2 >= 23) && (V2 <= 27)) THEN
+V96 = 95;
+L43:
+V88 = V88 + j;
+V90 = V90 + k;
+NEXT i;
+V94 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 512) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L44;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+L44:
+V94 = V94 + j;
+V95 = V95 + k;
+NEXT i;
+V179 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 2048) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L45;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+L45:
+V179 = V179 + j;
+V180 = V180 + k;
+NEXT i;
+V211 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 16384) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L46;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+L46:
+V211 = V211 + j;
+V212 = V212 + k;
+NEXT i;
+V223 = 0
+;
+V224 = 0
+;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 32768) == 0) ||
+((A13[i] & 4) == 0) ||
+((A13[i] & 32) == 0)) THEN GOTO L47;
+V2 = A105[i];
+j = j + A1[V2];
+k = k + A5[V2];
+L47:
+V223 = V223 + j;
+V224 = V224 + k;
+NEXT i;
+V22 = 0;
+FOR i = 0 TO V1;
+j = 1;
+k = 1;
+IF (((A13[i] & 2) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L48;
+V2 = A12[i];
+j = A1[V2];
+k = A5[V2];
+L48:
+V22 = V22 + j;
+V67 = V67 + k;
+NEXT i;
+l = 0;
+FOR i = 4 TO 0 STEP -1;
+FOR j = 0 TO V1;
+IF (((A13[j] & 2) == 0) ||
+((A13[j] & 4) == 0)) THEN GOTO L49;
+V2 = A12[j];
+FOR k = 0 TO (A1[V2] - 1);
+IF ((k % 5) == i) THEN A27[l] = 1;
+l = l + 1;
+NEXT k;
+GOTO L50;
+L49:
+l = l + 1;
+L50:
+NEXT j;
+NEXT i;
+V16 = 0;
+FOR i = 0 TO V1;
+j = 1;
+IF (((A13[i] & 1) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L51;
+V2 = A12[i];
+j = A0[V2];
+L51:
+V16 = V16 + j;
+NEXT i;
+V87 = 0;
+FOR i = 0 TO V1;
+j = 1;
+IF (((A13[i] & 256) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L52;
+V2 = A12[i];
+j = A0[V2];
+L52:
+V87 = V87 + j;
+NEXT i;
+V17 = 0;
+FOR i = 0 TO V1;
+j = 1;
+IF (((A13[i] & 2) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L53;
+V2 = A12[i];
+j = A0[V2];
+L53:
+V17 = V17 + j;
+NEXT i;
+V181 = 0;
+FOR i = 0 TO V1;
+j = 1;
+IF (((A13[i] & 2048) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L54;
+V2 = A12[i];
+j = A0[V2];
+L54:
+V181 = V181 + j;
+NEXT i;
+V18 = V17;
+IF (V16 > V18) THEN V18 = V16;
+IF (V87 > V18) THEN V18 = V87;
+IF (V181 > V18) THEN V18 = V181;
+V20 = 32 + V1;
+IF ((2 * 5 * 5 * V67) > V20) THEN V20 = 2 * 5 * 5 * V67;
+IF ((2 * 5 * V66) > V20) THEN V20 = 2 * 5 * V66;
+IF (V90 > V20) THEN V20 = V90;
+IF (V95 > V20) THEN V20 = V95;
+IF (V180 > V20) THEN V20 = V180;
+IF (V212 > V20) THEN V20 = V212;
+IF (V224 > V20) THEN V20 = V224;
+V19 = V18;
+IF (V21 > V19) THEN V19 = V21;
+IF (V88 > V19) THEN V19 = V88;
+IF (V94 > V19) THEN V19 = V94;
+IF (V179 > V19) THEN V19 = V179;
+IF (V211 > V19) THEN V19 = V211;
+IF (V223 > V19) THEN V19 = V223;
+IF (V20 > V19) THEN V19 = V20;
+FOR i = 0 TO (V19 - 1);
+A29[i] = 0;
+A30[i] = 1;
+NEXT i;
+V33 = 0;
+FOR i = 0 TO V1;
+IF (((A13[i] & 2) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L55;
+V2 = A12[i];
+IF (V33 < A7[V2]) THEN
+V33 = A7[V2];
+L55:
+NEXT i;
+V12 = 0;
+V13 = 0;
+FOR i = 0 TO V1;
+V12 = V12 + A25[i];
+IF (A25[i] > V13) THEN V13 = A25[i];
+NEXT i;
+FOR i = 0 TO (V13 - 1);
+A39[i] = 1;
+NEXT i;
+FOR i = 0 TO 4;
+j = 10 * i;
+A34[(j + 9)..j] = $016;
+A35[(j + 9)..j] = $01A;
+A36[(j + 9)..j] = $022;
+A37[(j + 9)..j] = $026;
+FOR k = 0 TO 2;
+b = 0;
+IF ((i & (1 << k)) != 0) THEN b = 1;
+A34[j + k + 7] = b;
+A35[j + k + 7] = b;
+A36[j + k + 7] = b;
+A37[j + k + 7] = b;
+NEXT k;
+NEXT i;
+FOR i = 0 TO 6;
+j = 10 * i;
+A38[(j + 9)..j] = $02A;
+FOR k = 0 TO 2;
+b = 0;
+IF ((i & (1 << k)) != 0) THEN b = 1;
+A38[j + k + 7] = b;
+NEXT k;
+NEXT i;
+FOR i = 0 TO V1;
+A52[i] = 0;
+IF (((A13[i] & 256) == 0) ||
+((A13[i] & 4) == 0)) THEN GOTO L56;
+V2 = A12[i];
+A52[i] =
+A5[V2] - (80 * A6[V2]);
+L56:
+NEXT i;
+CALL L106;
+IRSTOP IRPAUSE;
+DRSTOP IDLE;
+STATE IDLE;
+IF(!(V101 || V103 || V108 || V107 ||
+V100 || V102
+) &&
+V105) THEN GOTO L84;
+V4 = 0;
+FOR i = 0 TO V1;
+IF (((A17[i] & (32)) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 64) != 0)) THEN
+V4 = 32;
+NEXT i;
+IF (V4 != 32) THEN
+GOTO L57;
+FOR i = 0 TO V1;
+IF (((A17[i] & (32)) != 0) &&
+((A17[i] & 4) != 0) &&
+(((A17[i] & 64) == 0) ||
+(((A147[i] & 1) != 0) && !V231 && !V259))) THEN
+A17[i] = A17[i] | 8;
+NEXT i;
+A18[9..0] = $281;
+CALL L458;
+FOR i = 0 TO 200;
+WAIT IDLE, 512 CYCLES, 512 USEC, IDLE;
+NEXT i;
+FOR i = 0 TO V1;
+IF (((A17[i] & (32)) != 0) &&
+((A17[i] & 4) != 0) &&
+(((A17[i] & 64) == 0) ||
+(((A147[i] & 1) != 0) && !V231 && !V259))) THEN
+A17[i] = A17[i] & ~8;
+NEXT i;
+L57:
+IF (V101 || V231 || V259 || V4 == 131072) THEN CALL L108;
+IF (V42 != 0) THEN GOTO L84;
+FOR i = 0 TO V1;
+IF (((A17[i] & (1 | 2)) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 1 | 2;
+NEXT i;
+IF (V4 != (1 | 2)) THEN
+GOTO L58;
+A18[9..0] = $071;
+CALL L458;
+WAIT 10000 USEC;
+L58:
+FOR i = 0 TO V1;
+IF (((A17[i] & 256) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 256;
+NEXT i;
+IF (V4 != 256) THEN
+GOTO L70;
+A18[9..0] = $332;
+CALL L458;
+WAIT 10000 USEC;
+V203 = 0;
+L70:
+FOR i = 0 TO V1;
+IF (((A17[i] & 512) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 512;
+NEXT i;
+IF (V4 != 512) THEN
+GOTO L71;
+A18[9..0] = $044;
+CALL L458;
+WAIT 10000 USEC;
+L71:
+FOR i = 0 TO V1;
+IF (((A17[i] & 2048) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 2048;
+NEXT i;
+IF (V4 != 2048) THEN
+GOTO L72;
+IF (V103 || V102) THEN V38 = 1;
+V38 = 0;
+WAIT 10000 USEC;
+L72:
+FOR i = 0 TO V1;
+IF (((A17[i] & 16384) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 16384;
+NEXT i;
+IF (V4 != 16384) THEN
+GOTO L1187;
+L1187:
+V203 = 0;
+CALL L107;
+FOR i = 0 TO V1;
+A17[i] = A17[i] & ~8;
+NEXT i;
+V4 = 0;
+FOR i = 0 TO V1;
+IF ((A17[i] & 131072) != 0) THEN V4 = 131072;
+NEXT i;
+IF (V4 != 131072) THEN GOTO L84;
+V203 = 0;
+L84:
+ENDPROC;
+PROCEDURE L85 USES DEVICE_DATA, TEMP_DATA, L88, L458 ;
+IF (V233 || !V76 || (V42 != 0)) THEN GOTO L87;
+A18[9..0] = $003;
+V4 = 32;
+CALL L458;
+WAIT IDLE, 4096 CYCLES, 5 USEC, IDLE;
+V233 = 1;
+FOR i = 0 TO V1;
+IF (A94[i] != 0) THEN
+V191 = 1;
+NEXT i;
+IF(V191 == 1) THEN GOTO L86;
+GOTO L87;
+L86:
+CALL L88;
+L87:
+ENDPROC;
+PROCEDURE L88 USES DEVICE_DATA, TEMP_DATA, L458 ;
+PREIR 0;
+POSTIR 0;
+PREDR 0;
+POSTDR 0;
+FOR i = V1 TO 0 STEP -1;
+IF (((A17[i] & 32) == 0) ||
+((A17[i] & 4) == 0) ||
+(V42 != 0)) THEN
+GOTO L91;
+IF (A94[i] == 0) THEN GOTO L91;
+V77 = 0;
+V78 = 0;
+V30 = 0;
+FOR j = V1 TO 0 STEP -1;
+IF (i == j) THEN GOTO L89;
+IF ((A17[j] & 32) != 0) THEN
+A17[j] = A17[j] & ~4;
+IF (i > j) THEN V77 = V77 + 1;
+IF (i < j) THEN V78 = V78 + 1;
+IF (j < i) THEN V30 = V30 + A94[j];
+L89:
+NEXT j;
+V31 = V30 + A94[i] - 1;
+IF(V31 == V30) THEN GOTO L90;
+PUSH i;
+A18[9..0] = $00A;
+CALL L458;
+POP i;
+PREDR V77;
+POSTDR V78;
+FOR j = 0 TO 100;
+DRSCAN A94[i], A95[V31..V30], CAPTURE A45[79..0];
+IF(A45[79] == 0) THEN j = 100;
+NEXT j;
+if(A45[79] == 0) THEN GOTO L90;
+V42 = 12;
+GOTO L92;
+L90:
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, V192[79..0], CAPTURE A45[79..0];
+L91:
+NEXT i;
+L92:
+PREIR 0;
+POSTIR 0;
+PREDR 0;
+POSTDR 0;
+ENDPROC;
+PROCEDURE L93 USES DEVICE_DATA, TEMP_DATA, L107, L458, L108, L113
+, L85
+;
+IF (V42 == 1) THEN GOTO L100;
+CALL L107;
+CALL L85;
+L94:
+FOR i = 0 TO V1;
+IF (((A17[i] & (1 | 2)) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 1 | 2;
+NEXT i;
+IF (V4 != (1 | 2)) THEN
+GOTO L95;
+A18[9..0] = $079;
+CALL L458;
+WAIT 10000 USEC;
+L95:
+FOR i = 0 TO V1;
+IF (((A17[i] & 256) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 256;
+NEXT i;
+IF (V4 != 256) THEN
+GOTO L96;
+A18[9..0] = $006;
+CALL L458;
+L96:
+FOR i = 0 TO V1;
+IF (((A17[i] & 512) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 512;
+NEXT i;
+IF (V4 != 512) THEN
+GOTO L96a;
+A18[9..0] = $04A;
+CALL L458;
+WAIT 10000 USEC;
+L96a:
+FOR i = 0 TO V1;
+IF (((A17[i] & 2048) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 2048;
+NEXT i;
+IF (V4 != 2048) THEN
+GOTO L97;
+A18[9..0] = $04A;
+WAIT 10000 USEC;
+L97:
+FOR i = 0 TO V1;
+IF (((A17[i] & 16384) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 16384;
+NEXT i;
+IF (V4 != 16384) THEN
+GOTO L98;
+A18[9..0] = $201;
+IF (V228 == 1) THEN A18[9..0] = $166;
+CALL L458;
+WAIT 10000 USEC;
+L98:
+FOR i = 0 TO V1;
+IF (((A17[i] & 131072) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 131072;
+NEXT i;
+IF (V4 != 131072) THEN GOTO L1193;
+L1193:
+IF ((!V76 && !V231 && !V259) || (V42 != 0)) THEN GOTO L99;
+WAIT IDLE, 256 CYCLES, 10 USEC, IDLE;
+V80 = 0;
+IF (!V421 && !A175) THEN CALL L108;
+IF ((V42 != 0) && V76) THEN V42 = 10;
+IF ((V42 != 0) && !V76) THEN V42 = 10;
+IF (V42 != 0) THEN GOTO L100;
+L99:
+A18[9..0] = $3FF;
+CALL L458;
+IF (V105 && (V42 == 0)) THEN CALL L113;
+L100:
+IF (V42 == 0) THEN
+PRINT "DONE";
+IF (V42 == 1) THEN
+PRINT "Invalid option combination specified";
+IF (V42 == 6) THEN
+PRINT "Unrecognized device";
+IF (V42 == 7) THEN
+PRINT "Device revision is not supported";
+IF ((V42 == 10) && (V103)) THEN
+PRINT "Device programming failure";
+IF (V42 == 9) THEN
+PRINT "Device is not blank";
+IF (V42 == 11) THEN
+PRINT "Device verify failure";
+IF ((V42 == 10) && (V101)) THEN
+PRINT "Device configuration failure";
+IF (V42 == 4) THEN
+PRINT "Unable to read USERCODE/UES from device #", V84 + 1;
+IF (V42 == 12) THEN
+PRINT "Failed to configure Excalibur stripe";
+IF (V42 == 14) THEN
+PRINT "Failed to erase or program ASC device";
+IF (V42 == 15) THEN
+PRINT "Unable to erase the protected sector(s) of the ASC device";
+IF (V42 == 18) THEN
+PRINT "Reserved block start address mismatch - operation aborted";
+IF (V42 == 19) THEN
+PRINT "Unexpected problem has occurred during NAND flash bad block management.";
+IF (V42 == 20) THEN
+PRINT "Device is write-protected";
+IF (V42 == 21) THEN
+PRINT "Programming file size is larger than flash density";
+IF (V42 == 22) THEN
+PRINT "Programming file format is not aligned with flash type";
+ENDPROC;
+PROCEDURE L101 USES DEVICE_DATA, TEMP_DATA;
+j = 0;
+FOR i = 0 TO V1;
+IF ((j <= V3) &&
+((A13[i] & V4) != 0) &&
+((A13[i] & 4) != 0)) THEN j = i + 1;
+NEXT i;
+IF (j > V3) THEN GOTO L102;
+V2 = 0;
+V3 = 0;
+GOTO L105;
+L102:
+V2 = A12[j - 1];
+V3 = j;
+IF(!V216) THEN GOTO L103;
+V2 = A105[j - 1];
+L103:
+IF ((V4 == 32) || (V4 == 256) ||
+(V4 == 512) || (V4 == 2048) ||
+(V4 == 16384) || (V4 == 32768) ||
+(V4 == 1024))
+THEN GOTO L105;
+IF (V58) THEN GOTO L104;
+A41[9..0] = $066;
+GOTO L105;
+L104:
+A41[9..0] = $006;
+L105:
+IF (V4 == 1) THEN A40[9..0] = $00E;
+IF (V4 == 1) THEN A44[9..0] = $012;
+IF (V4 == 2) THEN A40[9..0] = $38E;
+IF (V4 == 2) THEN A44[9..0] = $392;
+ENDPROC;
+PROCEDURE L106 USES DEVICE_DATA, TEMP_DATA, L107
+;
+CALL L107;
+V10 = 0;
+V14 = 0;
+V15 = 0;
+V89 = 0;
+V49 = 1;
+V34 = 0;
+V51 = -1;
+V52 = -1;
+V45 = 0;
+V29 = 1;
+IF (V103) THEN V29 = 0;
+IF (V102 && V74) THEN V29 = 2;
+ENDPROC;
+PROCEDURE L107 USES DEVICE_DATA, TEMP_DATA;
+FOR i = 0 TO V1;
+A17[i] = (A13[i] | A48[i]);
+IF (((A17[i] & 4) != 0) &&
+((A17[i] & (1 | 256 | 2 | 512 | 2048 | 16384 | 131072)) != 0) &&
+!V102 && !V100 && !V103 && !V108 &&
+!V107 && !V106 && V101) THEN
+A17[i] = A17[i] & ~4;
+IF (((A17[i] & 4) != 0) &&
+((A17[i] & 32) != 0) && ((A17[i] & 32768) == 0) && ((A17[i] & 1024) == 0) && !V101 &&
+(V102 || V100 || V103 || V108 ||
+V107 || V106)) THEN
+A17[i] = A17[i] & ~4;
+NEXT i;
+ENDPROC;
+PROCEDURE L108 USES DEVICE_DATA, TEMP_DATA, L107;
+INTEGER V79 = 32 * V0;
+BOOLEAN A46[V79];
+INTEGER A47[8];
+INTEGER V145;
+CALL L107;
+STATE IDLE;
+V27 = 0;
+FOR i = 0 TO V1;
+A18[(A25[i] - 1)..0] = A39[(A25[i] - 1)..0];
+IF ((A17[i] & (1 | 2 | 256 | 512 | 2048)) != 0) THEN
+A18[9..0] = $059;
+IF ((A17[i] & (32 | 16384 | 131072 | 262144)) != 0) THEN
+A18[9..0] = $006;
+IF ((A17[i] & 65536) != 0) THEN
+A18[3..0] = $E;
+A32[(V27 + (A25[i] - 1))..V27] = A18[(A25[i] - 1)..0];
+V27 = V27 + A25[i];
+NEXT i;
+IRSCAN V27, A32[(V27 - 1)..0];
+WAIT IRPAUSE, 5 USEC, IDLE;
+WAIT 3 CYCLES;
+DRSCAN V79, A46[(V79 - 1)..0], CAPTURE A46[(V79 - 1)..0];
+V27 = 0;
+FOR i = 0 TO V1;
+IF (A46[V27] == 1) THEN GOTO L109;
+IF (V80) THEN
+PRINT "Device #", V0 - i, " unable to read IDCODE";
+IF (V101 && ((A17[i] & 32) != 0) &&
+((A17[i] & 4) != 0)) THEN V42 = 6;
+GOTO L110;
+L109:
+FOR j = 0 TO 7;
+A47[j] = 0;
+FOR k = 0 TO 3;
+IF (A46[V27 + (4 * j) + k]) THEN
+A47[j] = A47[j] | (1 << k);
+NEXT k;
+A47[j] = A47[j] + 48;
+IF (A47[j] >= 58) THEN A47[j] = A47[j] + 7;
+NEXT j;
+IF (V80) THEN
+PRINT "Device #", V0 - i, " IDCODE is ",
+CHR$(A47[7]), CHR$(A47[6]),
+CHR$(A47[5]), CHR$(A47[4]),
+CHR$(A47[3]), CHR$(A47[2]),
+CHR$(A47[1]), CHR$(A47[0]);
+IF (V101 && ((A17[i] & 32) != 0) &&
+((A17[i] & 4) != 0) && (A47[0] != 68) &&
+(A47[1] != 68)) THEN
+V42 = 6;
+V27 = V27 + 31;
+L110:
+V27 = V27 + 1;
+NEXT i;
+V27 = 0;
+k = 0;
+push l;
+FOR i = 0 TO V1;
+IF (A61[k] != 0) THEN GOTO L111;
+IF (A46[V27] != 0) THEN
+V42 = 6;
+V27 = V27 + 1;
+k = k + 1;
+NEXT i;
+GOTO L112;
+L111:
+V145 = 0;
+FOR j = 0 TO 31;
+IF (A46[(V27 + j)]) THEN
+V145 = V145 + (1 << j);
+NEXT j;
+l = 6;
+FOR j = 0 TO (A61[k] - 1);
+IF (V145 == A61[k+j+1]) THEN l = 0;
+IF (l == 0) THEN j = A61[k];
+NEXT j;
+V27 = V27 + 32;
+k = k + A61[k] + 1;
+IF (l == 6) THEN
+V42 = 6;
+NEXT i;
+L112:
+pop l;
+IF (V232 && (V42 != 0)) THEN
+PRINT "IDCODE failures ignored";
+IF (V232 && (V42 != 0)) THEN
+V42 = 0;
+ENDPROC;
+PROCEDURE L113 USES DEVICE_DATA, TEMP_DATA, L107, L458, L119;
+j = 0;
+k = V1;
+V84 = V84 - 1;
+IF (V84 == -1) THEN GOTO L114;
+IF ((V84 < 0) || (V84 > V1) ||
+(((A17[V1 - V84] & 256) == 0) &&
+((A17[V1 - V84] & 32) == 0) &&
+((A17[V1 - V84] & 512) == 0) &&
+((A17[V1 - V84] & 16384) == 0) &&
+((A17[V1 - V84] & 2048) == 0) &&
+((A17[V1 - V84] & 131072) == 0))) THEN
+V42 = 4;
+IF (V42 != 0) THEN GOTO L118;
+j = V84;
+k = V84;
+L114:
+CALL L107;
+FOR i = 0 TO V1;
+IF (((A17[i] & 256) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 256;
+NEXT i;
+IF (V4 != 256) THEN
+GOTO L115;
+A18[9..0] = $006;
+CALL L458;
+WAIT 10000 USEC;
+L115:
+FOR i = 0 TO V1;
+IF (((A17[i] & (512 | 2048)) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 512 | 2048;
+NEXT i;
+IF (V4 != (512 | 2048)) THEN
+GOTO L116;
+A18[9..0] = $04A;
+CALL L458;
+WAIT 10000 USEC;
+L116:
+FOR i = 0 TO V1;
+IF (((A17[i] & 16384) != 0) &&
+((A17[i] & 4) != 0) &&
+((A17[i] & 8) == 0)) THEN
+V4 = 16384;
+NEXT i;
+IF (V4 != 16384) THEN
+GOTO L117;
+A18[9..0] = $201;
+CALL L458;
+WAIT 10000 USEC;
+L117:
+A18[9..0] = $3FF;
+CALL L458;
+STATE IDLE;
+FOR i = 0 TO (V19 - 1);
+A30[i] = 1;
+NEXT i;
+FOR i = j TO k;
+V84 = i;
+PUSH i; PUSH j; PUSH k;
+CALL L107;
+V4 = 0;
+IF (((A17[V1 - V84] & 256) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 256;
+IF (((A17[V1 - V84] & 16384) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 16384;
+IF (((A17[V1 - V84] & 32) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 32;
+IF (((A17[V1 - V84] & 512) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 512;
+IF (((A17[V1 - V84] & 2048) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 2048;
+IF (((A17[V1 - V84] & 131072) != 0) &&
+((A17[V1 - V84] & 4) != 0)) THEN
+V4 = 131072;
+IF (V4 != 0) THEN CALL L119;
+POP k; POP j; POP i;
+NEXT i;
+L118:
+V84 = 0;
+ENDPROC;
+PROCEDURE L119 USES DEVICE_DATA, TEMP_DATA, L458, L123;
+j = V1 - V84;
+FOR i = 0 TO V1;
+IF (((A17[i] & V4) != 0) &&
+((A17[i] & 4) != 0) && (i != j)) THEN
+A17[i] = A17[i] | 8;
+NEXT i;
+IF (V4 == 256) THEN
+A18[9..0] = $007;
+IF (V4 == 16384) THEN
+A18[9..0] = $007;
+IF ((V4 == 512) || (V4 == 2048)) THEN
+A18[9..0] = $079;
+IF (V4 == 32) THEN
+A18[9..0] = $007;
+IF (V4 == 131072) THEN
+A18[9..0] = $007;
+CALL L458;
+DRSCAN 32 + j, A30[(32 + j - 1)..0], CAPTURE A31[(32 + j - 1)..0];
+V86 = 0;
+FOR i = 0 TO 31;
+IF (A31[i + j]) THEN
+V86 = V86 | (1 << i);
+NEXT i;
+CALL L123;
+ENDPROC;
+PROCEDURE L120 USES DEVICE_DATA, TEMP_DATA, L107, L458;
+CALL L107;
+V4 = 512;
+j = 0;
+FOR i = 0 TO V1;
+A30[j] = 1;
+l = 1;
+IF (((A17[i] & 512) == 0) ||
+((A17[i] & 4) == 0)) THEN
+GOTO L122;
+l = 8 * 3;
+FOR V27 = 0 TO l - 1;
+A30[j + V27] = 1;
+IF ((V27 % 3) == 0) THEN
+A30[j + V27] = 0;
+NEXT V27;
+L122:
+j = j + l;
+NEXT i;
+A18[9..0] = $055;
+CALL L458;
+WAIT IDLE, 10 CYCLES, 1000 USEC, IDLE;
+DRSCAN j, A30[j - 1..0];
+WAIT IDLE, 10 CYCLES, 1000 USEC, IDLE;
+A18[9..0] = $000;
+CALL L458;
+WAIT IDLE, 10 CYCLES, 1000 USEC, IDLE;
+A18[9..0] = $3FF;
+CALL L458;
+WAIT IDLE, 10 CYCLES, 1000 USEC, IDLE;
+FOR i = 0 TO j - 1;
+A30[i] = 1;
+NEXT i;
+ENDPROC;
+PROCEDURE L123 USES DEVICE_DATA, TEMP_DATA;
+INTEGER A58[8];
+EXPORT "DEVICE", V84 + 1;
+EXPORT "USERCODE", V86;
+FOR i = 0 TO 7;
+V27 = 0;
+A58[i] = V86 & 15;
+IF (A58[i] > 9) THEN V27 = 7;
+A58[i] = A58[i] + 48 + V27;
+V86 = V86 >> 4;
+NEXT i;
+PRINT "Device #", V84 + 1, " USERCODE code is ",
+CHR$(A58[7]), CHR$(A58[6]),
+CHR$(A58[5]), CHR$(A58[4]),
+CHR$(A58[3]), CHR$(A58[2]),
+CHR$(A58[1]), CHR$(A58[0]);
+ENDPROC;
+PROCEDURE L124 USES DEVICE_DATA, TEMP_DATA, L107
+;
+j = 0;
+k = V1;
+V34 = 1;
+V29 = 1;
+V84 = V84 - 1;
+IF (V84 == -1) THEN GOTO L126;
+IF ((V84 < 0) || (V84 > V1) ||
+(((A17[V1 - V84] & 1) == 0) &&
+((A17[V1 - V84] & 2) == 0))) THEN
+V42 = 4;
+IF (V42 != 0) THEN GOTO L127;
+L125:
+j = V84;
+k = V84;
+L126:
+FOR i = j TO k;
+V84 = i;
+PUSH i; PUSH j; PUSH k;
+CALL L107;
+V86 = 0;
+POP k; POP j; POP i;
+NEXT i;
+L127:
+V84 = 0;
+ENDPROC;
+PROCEDURE L134 USES DEVICE_DATA, TEMP_DATA;
+INTEGER V85[8];
+EXPORT "DEVICE", V84 + 1;
+EXPORT "UES", V86;
+FOR i = 0 TO 3;
+V27 = 0;
+V85[i] = V86 & 15;
+IF (V85[i] > 9) THEN V27 = 7;
+V85[i] = V85[i] + 48 + V27;
+V86 = V86 >> 4;
+NEXT i;
+PRINT "Device #", V84 + 1, " UES code is ",
+CHR$(V85[3]), CHR$(V85[2]),
+CHR$(V85[1]), CHR$(V85[0]);
+ENDPROC;
+PROCEDURE L135 USES DEVICE_DATA, TEMP_DATA, L458;
+A18[9..0] = $00A;
+CALL L458;
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, V189[79..0], CAPTURE A45[79..0];
+FOR i = 0 TO 100;
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, A29[79..0], CAPTURE A45[79..0];
+IF (A45[79] == 0) THEN i = 100;
+NEXT i;
+IF (A45[79] == 0) THEN GOTO L136;
+V42 = 12;
+GOTO L137;
+L136:
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, V190[79..0], CAPTURE A45[79..0];
+FOR i = 0 TO 100;
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, A29[79..0], CAPTURE A45[79..0];
+IF (A45[79] == 0) THEN i = 100;
+NEXT i;
+IF (A45[79] == 0) THEN GOTO L137;
+V42 = 12;
+L137:
+ENDPROC;
+PROCEDURE L138 USES DEVICE_DATA, TEMP_DATA;
+V188 = (V187 - V186)/80;
+FOR i = 0 TO V188;
+FOR j = 0 TO 100;
+PREDR V77;
+POSTDR V78;
+DRSCAN 80, A93[(V186 + 79)..V186], CAPTURE A45[79..0];
+IF (A45[79] == 0) THEN j = 100;
+NEXT j;
+IF (A45[79] == 0) THEN GOTO L139;
+V42 = 12;
+i = V188;
+GOTO L140;
+L139:
+V186 = V186 + 80;
+L140:
+NEXT i;
+ENDPROC;
+PROCEDURE L1223 USES DEVICE_DATA, TEMP_DATA, L458, L849;
+PUSH j;
+PUSH m;
+PUSH n;
+PUSH i;
+A31[22+V1..0] = A29[22+V1..0];
+IF ((A186[j] & 512) == 0) THEN A31[j+22..j] = $500008;
+IF ((A186[j] & 512) != 0) THEN A31[j+22..j] = $480008;
+A18[9..0] = $203;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+DRSCAN (23 + V1), A31[22+V1..0];
+STATE IDLE;
+A18[9..0] = $205;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+DRSCAN (32 + V1), A29[31+V1..0], CAPTURE A31[31+V1..0];
+WAIT IDLE, 3 CYCLES, IDLE;
+ba[31..0] = A31[j+31..j];
+Call L849;
+IF (i == 0) THEN GOTO L1224;
+i = i >> 23;
+m = 0;
+FOR n = 0 TO 8;
+IF ((i & (1 << n)) != 0) THEN m = m + (1 << (8 - n));
+NEXT n;
+IF (m != 120 && m != 124 && m != 126) THEN V42 = 6;
+IF (V42 != 0) THEN PRINT "Detected invalid Max 10 feature ID for device ", V0 - j;
+IF (V42 != 0) THEN GOTO L1224;
+IF (m > (A186[j] & 511)) THEN V42 = 6;
+IF (V42 != 0) THEN PRINT "Incompatible feature ID for device ", V0 - j, ". Expected feature ID is ", (A186[j] & 511), " but fouL742 ", m;
+L1224:
+POP i;
+POP n;
+POP m;
+POP j;
+ENDPROC;
+PROCEDURE L1190 USES DEVICE_DATA, TEMP_DATA, L458, L850, L1223;
+push V91;
+V91 = 1;
+m = 0;
+n = 0;
+FOR i = 0 to V1;
+IF ((A17[i] & 32) != 0 && (A17[i] & 4) != 0) THEN A17[i] = A17[i] | 8;
+m = m + A25[i];
+NEXT i;
+FOR j = 0 to V1;
+IF ((A17[j] & 32) == 0 ||
+(A17[j] & 4) == 0 ||
+(A17[j] & 524288) == 0) THEN GOTO L1191;
+A17[j] = A17[j] & ~8;
+A31[m-1..0] = A30[m-1..0];
+A31[n+9..n] = $006;
+IRSCAN m, A31[m-1..0], CAPTURE A57[m-1..0];
+STATE IDLE;
+A18[9..0] = $2CC;
+CALL L458;
+WAIT IDLE, 16 CYCLES, 350000 USEC, IDLE;
+call L1223;
+IF (V42 != 0) THEN GOTO L1192;
+IF A57[n+2] == 1 THEN GOTO L1192;
+A18[9..0] = $203;
+CALL L458;
+WAIT IDLE, 3 CYCLES, IDLE;
+DRSCAN 23 + V1, A29[22+V1..0];
+A18[9..0] = $3F2;
+CALL L458;
+WAIT IDLE, 16 CYCLES, 350000 USEC, IDLE;
+A18[9..0] = $307;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+DRSCAN V0, A29[V1..0], CAPTURE A31[V1..0];
+IF (A31[j] == 0) THEN V42 = 10;
+IF (A31[j] == 0) THEN GOTO L1192;
+STATE IDLE;
+FOR m = 0 to 3;
+A18[9..0] = $203;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+i = A174[j * 2];
+IF (m == 0) THEN i = i - ((A174[j * 2 + 1]/32) + 1);
+IF (m == 1) THEN i = 14 * (A174[j * 2 + 1]/64);
+IF (m == 3) THEN i = i + (A174[j * 2 + 1]/32);
+CALL L850;
+k = j;
+FOR i = 22 TO 0 STEP -1;
+A31[k] = ba[i];
+k = k + 1;
+NEXT i;
+k = 23 + V1;
+DRSCAN k, A31[k-1..0];
+STATE IDLE;
+A18[9..0] = $3F4;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+A31[j+31..j] = $6C48A50F; 
+IF (m == 1) THEN A31[j+31..j] = $FFF7FFFF; 
+k = 32 + V1;
+DRSCAN k, A31[k-1..0];
+WAIT IDLE, 3 CYCLES, 320 USEC, IDLE;
+A18[9..0] = $307;
+CALL L458;
+WAIT IDLE, 16 CYCLES, IDLE;
+DRSCAN V0, A29[V1..0], CAPTURE A31[V1..0];
+STATE IDLE;
+IF (A31[j] == 0) THEN V42 = 10;
+IF (V42 != 0) THEN m = 2;
+NEXT m;
+L1192:
+A18[9..0] = $201;
+CALL L458;
+WAIT IDLE, 1 CYCLES, 1000 USEC, IDLE;
+A17[j] = A17[j] | 8;
+L1191:
+IF (V42 != 0) THEN j = V1;
+n = n + A25[j];
+NEXT j;
+FOR i = 0 to V1;
+A17[i] = A17[i] & ~8;
+NEXT i;
+pop V91;
+ENDPROC;
+PROCEDURE L141 USES DEVICE_DATA, TEMP_DATA, L107, L458, L138, L135;
+PRINT "configuring SRAM device(s)...";
+CALL L107;
+PREIR 0;
+POSTIR 0;
+PREDR 0;
+POSTDR 0;
+FOR i = V1 TO 0 STEP -1;
+IF (((A17[i] & 32) == 0) ||
+((A17[i] & 4) == 0) ||
+(V42 != 0)) THEN
+GOTO L146;
+V77 = 0;
+V78 = 0;
+V30 = 0;
+V186 = 0;
+FOR j = V1 TO 0 STEP -1;
+IF (i == j) THEN GOTO L142;
+IF ((A17[j] & 32) != 0) THEN
+A17[j] = A17[j] & ~4;
+IF (i > j) THEN V77 = V77 + 1;
+IF (i < j) THEN V78 = V78 + 1;
+IF (j < i) THEN V30 = V30 + A43[j];
+IF (j < i) THEN V186 = V186 + A92[j];
+L142:
+NEXT j;
+IF(A92[i] == 0) THEN
+GOTO L143;
+PUSH i;
+CALL L135;
+POP i;
+V187 = V186 + A92[i] - 1;
+PUSH i;
+CALL L138;
+POP i;
+L143:
+V31 = V30 + A43[i] - 1;
+POSTDR V78;
+PUSH i;
+IF (((A147[i] & 2) == 0) ||
+V393) THEN
+GOTO L1094;
+A18[9..0] = $2EE;
+CALL L458;
+L1094:
+IF ((A17[i] & 64) == 0) THEN
+GOTO L144;
+A18[9..0] = $281;
+CALL L458;
+FOR i = 0 TO 200;
+WAIT IDLE, 512 CYCLES, 512 USEC, IDLE;
+NEXT i;
+POP i;
+PUSH i;
+L144:
+IF (((A17[i] & 128) == 0) || (V230 == 0)) THEN
+GOTO L145;
+A18[9..0] = $00D;
+CALL L458;
+WAIT 2500 USEC;
+L145:
+A18[9..0] = $002;
+CALL L458;
+FOR i = 0 TO 20;
+WAIT IDLE, 512 CYCLES, 512 USEC, IDLE;
+NEXT i;
+POP i;
+DRSCAN A43[i], A42[V31..V30];
+IF (USE_REV0_PROG_ALG) THEN DRSCAN 32, A30[31..0];
+PUSH i;
+A18[9..0] = $004;
+CALL L458;
+POP i;
+PREDR V77;
+POSTDR V78;
+DRSCAN A59[i], A29[A59[i]-1..0], CAPTURE A45[A59[i]-1..0];
+IF !A45[A60[i]] THEN V42 = 10;
+PUSH i;
+IF (((A147[i] & 2) == 0) ||
+V393) THEN
+GOTO L1095;
+WAIT IDLE, 8192 CYCLES, 2048 USEC, IDLE;
+A18[9..0] = $1EE;
+CALL L458;
+L1095:
+CALL L107;
+POP i;
+L146:
+NEXT i;
+PREIR 0;
+POSTIR 0;
+PREDR 0;
+POSTDR 0;
+IF (V42 != 0) THEN
+GOTO L147;
+V76 = 1;
+L147:
+ENDPROC;
+PROCEDURE L458 USES DEVICE_DATA, TEMP_DATA;
+PUSH i;
+PUSH j;
+PUSH l;
+V41 = 0;
+V27 = 0;
+IF (!V56) THEN GOTO L459;
+V56 = 0;
+V41 = 50;
+IF (!USE_EXTEND_IR_DELAY_METHOD) THEN GOTO L459;
+V27 = 50;
+A32[49..0] = A30[49..0];
+L459:
+FOR i = 0 TO V1;
+IF ((A17[i] & 8) != 0) THEN GOTO L460;
+IF (((A17[i] & V4) != 0) &&
+((A17[i] & 4) != 0)) THEN GOTO L462;
+A33[(A25[i] - 1)..0] = A39[(A25[i] - 1)..0];
+IF (((A17[i] & 1) != 0) &&
+((A17[i] & 4) != 0)) THEN
+A33[(A25[i] - 1)..0] = $03E;
+A32[(V27 + (A25[i] - 1))..V27] = A33[(A25[i] - 1)..0];
+V27 = V27 + A25[i];
+GOTO L465;
+L460:
+IF ((A17[i] & 2) != 0) THEN GOTO L461;
+A32[(V27 + 9)..V27] = $3FF;
+IF ((A17[i] & 1) != 0) THEN
+A32[(V27 + 9)..V27] = $03E;
+V27 = V27 + 10;
+GOTO L465;
+L461:
+IF (!V57) THEN GOTO L462;
+A32[(V27 + 9)..V27] = $02A;
+V27 = V27 + 10;
+GOTO L465;
+L462:
+l = 0;
+IF ((A18[20] == 1) && ((A17[i] & 64) != 0)) THEN
+l = 10;
+A32[(V27 + 9)..V27] = A18[(l + 9)..l];
+V27 = V27 + 10;
+GOTO L465;
+L465:
+NEXT i;
+IF ((V41 == 0) || USE_EXTEND_IR_DELAY_METHOD) THEN
+GOTO L466;
+STATE DRPAUSE;
+WAIT DRPAUSE, 5 USEC, DRPAUSE;
+L466:
+IRSCAN V27, A32[(V27 - 1)..0];
+V57 = 0;
+WAIT IRPAUSE, V83 USEC, IRPAUSE;
+IF (V91) THEN GOTO L467;
+STATE IDLE;
+WAIT 3 CYCLES;
+L467:
+POP l;
+POP j;
+POP i;
+ENDPROC;
+PROCEDURE L682 USES DEVICE_DATA, TEMP_DATA;
+V23 = 0;
+V24 = 0;
+FOR i = 0 TO (V19 - 1);
+A30[i] = 1;
+NEXT i;
+FOR i = 0 TO V1;
+V25 = 1;
+V26 = 1;
+IF(V216) THEN V25 = 0;
+IF(V216) THEN V26 = 0;
+IF (((A17[i] & V4) == 0) ||
+((A17[i] & 4) == 0) ||
+((A17[i] & 8) != 0)) THEN GOTO L683;
+V2 = A12[i];
+IF(V216) THEN V2 = A105[i];
+V25 = A1[V2];
+V26 = A5[V2];
+GOTO L684;
+L683:
+IF (V74 && !V216) THEN A30[V24] = 0;
+L684:
+V23 = V23 + V25;
+V24 = V24 + V26;
+NEXT i;
+V49 = 0;
+ENDPROC;
+PROCEDURE L849 USES TEMP_DATA;
+PUSH j;
+i = 0;
+FOR j = 0 to 31;
+IF (ba[j] == 1) THEN i = i + (1<<j);
+NEXT j;
+POP j;
+ENDPROC;
+PROCEDURE L850 USES TEMP_DATA;
+PUSH j;
+ba[31..0] = $00000000;
+FOR j = 0 to 31;
+IF (i&(1<<j))!=0 THEN ba[j]=1;
+NEXT j;
+POP j;
+ENDPROC;
+' END OF FILE
+CRC 332F;

output_files/max80.map

@@ -0,0 +1,18 @@
+BLOCK		START ADDRESS		END ADDRESS
+
+Page_0		0x00000000		0x0007CB87
+
+
+Configuration device: EP4CE15
+Configuration mode: Active Serial
+Quad-Serial configuration device dummy clock cycle: 8
+
+
+Notes:
+
+- Data checksum for this conversion is 0xF75E94D8
+
+- All the addresses in this file are byte addresses
+
+- The following changes from default values for Advanced Options settings are in effect:
+	Disable EPCS ID check: ON

output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Fri Aug  6 18:02:08 2021
+Fri Aug  6 18:12:58 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -67,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Fri Aug  6 18:02:08 2021       ;
+; Analysis & Synthesis Status        ; Successful - Fri Aug  6 18:12:58 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -1093,7 +1093,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:02:03 2021
+    Info: Processing started: Fri Aug  6 18:12:53 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
@@ -1520,8 +1520,8 @@ Info (21057): Implemented 484 device resources after synthesis - the final resou
     Info (21065): Implemented 2 PLLs
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 219 warnings
     Info: Peak virtual memory: 678 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:08 2021
+    Info: Processing ended: Fri Aug  6 18:12:58 2021
     Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:15
+    Info: Total CPU time (on all processors): 00:00:16
 
 

output_files/max80.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Fri Aug  6 18:02:08 2021
+Analysis & Synthesis Status : Successful - Fri Aug  6 18:12:58 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Fri Aug  6 18:02:18 2021
+Fri Aug  6 18:13:09 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -53,19 +53,19 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 16          ;
 ; Maximum allowed            ; 8           ;
 ;                            ;             ;
-; Average used               ; 1.05        ;
+; Average used               ; 1.04        ;
 ; Maximum used               ; 8           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processors 2-8         ;   0.7%      ;
+;     Processors 2-8         ;   0.6%      ;
 +----------------------------+-------------+
 
 
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Fri Aug  6 18:02:18 2021            ;
+; Power Analyzer Status                  ; Successful - Fri Aug  6 18:13:09 2021            ;
 ; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
@@ -391,7 +391,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:02:17 2021
+    Info: Processing started: Fri Aug  6 18:13:07 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -432,9 +432,9 @@ Info (334004): Delay annotation completed successfully
 Info (215049): Average toggle rate for this design is 10.847 millions of transitions / sec
 Info (215031): Total thermal power estimate for the design is 216.99 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1029 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:18 2021
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 1020 megabytes
+    Info: Processing ended: Fri Aug  6 18:13:09 2021
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
 

output_files/max80.pow.summary

@@ -1,4 +1,4 @@
-Power Analyzer Status : Successful - Fri Aug  6 18:02:18 2021
+Power Analyzer Status : Successful - Fri Aug  6 18:13:09 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for max80
-Fri Aug  6 18:02:20 2021
+Fri Aug  6 18:13:10 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -118,13 +118,13 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 16          ;
 ; Maximum allowed            ; 8           ;
 ;                            ;             ;
-; Average used               ; 1.06        ;
+; Average used               ; 1.05        ;
 ; Maximum used               ; 8           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.3%      ;
-;     Processors 3-8         ;   0.8%      ;
+;     Processor 2            ;   1.1%      ;
+;     Processors 3-8         ;   0.7%      ;
 +----------------------------+-------------+
 
 
@@ -133,7 +133,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; max80.sdc     ; OK     ; Fri Aug  6 18:02:19 2021 ;
+; max80.sdc     ; OK     ; Fri Aug  6 18:13:09 2021 ;
 +---------------+--------+--------------------------+
 
 
@@ -3236,7 +3236,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:02:19 2021
+    Info: Processing started: Fri Aug  6 18:13:09 2021
 Info: Command: quartus_sta max80 -c max80
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -3359,7 +3359,7 @@ Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
     Info: Peak virtual memory: 728 megabytes
-    Info: Processing ended: Fri Aug  6 18:02:20 2021
+    Info: Processing ended: Fri Aug  6 18:13:10 2021
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01