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@@ -1,5 +1,5 @@
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Fitter report for max80
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-Fri Aug 6 17:56:41 2021
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+Fri Aug 6 18:02:14 2021
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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@@ -73,7 +73,7 @@ https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+---------------------------------------------+
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-; Fitter Status ; Successful - Fri Aug 6 17:56:41 2021 ;
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+; Fitter Status ; Successful - Fri Aug 6 18:02:14 2021 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; max80 ;
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; Top-level Entity Name ; max80 ;
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@@ -265,7 +265,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
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; -- I/O registers ; 11 / 758 ( 1 % ) ;
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; ; ;
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-; Total LABs: partially or completely used ; 31 / 963 ( 3 % ) ;
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+; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 142 / 166 ( 86 % ) ;
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; -- Clock pins ; 4 / 3 ( 133 % ) ;
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@@ -283,11 +283,11 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; ASMI blocks ; 0 / 1 ( 0 % ) ;
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; Oscillator blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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-; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.2% ;
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-; Peak interconnect usage (total/H/V) ; 1.6% / 1.4% / 1.8% ;
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+; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.4% ;
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+; Peak interconnect usage (total/H/V) ; 2.8% / 3.0% / 2.5% ;
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; Maximum fan-out ; 90 ;
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; Highest non-global fan-out ; 42 ;
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-; Total fan-out ; 1657 ;
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+; Total fan-out ; 1655 ;
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; Average fan-out ; 1.87 ;
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+---------------------------------------------+----------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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@@ -320,7 +320,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Dedicated logic registers ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % ) ;
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; -- I/O registers ; 6 ; 16 ;
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; ; ; ;
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-; Total LABs: partially or completely used ; 31 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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+; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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; ; ; ;
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; Virtual pins ; 0 ; 0 ;
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; I/O pins ; 134 ; 8 ;
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@@ -338,7 +338,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Registered Output Connections ; 8 ; 0 ;
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; ; ; ;
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; Internal Connections ; ; ;
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-; -- Total Connections ; 1621 ; 291 ;
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+; -- Total Connections ; 1619 ; 291 ;
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; -- Registered Connections ; 779 ; 0 ;
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; ; ; ;
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; External Connections ; ; ;
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@@ -431,7 +431,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; abc_xm_x ; B1 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
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; flash_clk ; H1 ; 1 ; 0 ; 20 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
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; flash_cs_n ; D2 ; 1 ; 0 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
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-; flash_mosi ; K10 ; 4 ; 28 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
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+; flash_mosi ; C1 ; 1 ; 0 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; Default ; Off ; -- ; no ; no ; User ; - ; - ;
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; hdmi_clk ; J15 ; 5 ; 41 ; 13 ; 7 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
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; hdmi_clk(n) ; J16 ; 5 ; 41 ; 13 ; 14 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; Fitter ; - ; - ;
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; hdmi_d[0] ; K15 ; 5 ; 41 ; 13 ; 21 ; yes ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Maximum Current ; Off ; -- ; 1 ; 1 ; User ; - ; - ;
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@@ -537,6 +537,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+----------+------------------------------------------+------------------------+------------------+---------------------------+
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; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
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+----------+------------------------------------------+------------------------+------------------+---------------------------+
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+; C1 ; DIFFIO_L4n, DATA1, ASDO ; Use as regular IO ; flash_mosi ; Dual Purpose Pin ;
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; D2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; Use as regular IO ; flash_cs_n ; Dual Purpose Pin ;
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; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
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; H1 ; DCLK ; Use as regular IO ; flash_clk ; Dual Purpose Pin ;
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@@ -583,20 +584,20 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+----------+------------------------------------------+------------------------+------------------+---------------------------+
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-+------------------------------------------------------------+
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-; I/O Bank Usage ;
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-+----------+------------------+---------------+--------------+
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-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
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-+----------+------------------+---------------+--------------+
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-; 1 ; 13 / 14 ( 93 % ) ; 3.3V ; -- ;
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-; 2 ; 16 / 18 ( 89 % ) ; 3.3V ; -- ;
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-; 3 ; 24 / 25 ( 96 % ) ; 3.3V ; -- ;
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-; 4 ; 21 / 27 ( 78 % ) ; 3.3V ; -- ;
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-; 5 ; 9 / 20 ( 45 % ) ; 2.5V ; -- ;
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-; 6 ; 13 / 14 ( 93 % ) ; 3.3V ; -- ;
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-; 7 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
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-; 8 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
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-+----------+------------------+---------------+--------------+
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++-------------------------------------------------------------+
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+; I/O Bank Usage ;
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++----------+-------------------+---------------+--------------+
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+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
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++----------+-------------------+---------------+--------------+
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+; 1 ; 14 / 14 ( 100 % ) ; 3.3V ; -- ;
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+; 2 ; 16 / 18 ( 89 % ) ; 3.3V ; -- ;
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+; 3 ; 24 / 25 ( 96 % ) ; 3.3V ; -- ;
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+; 4 ; 20 / 27 ( 74 % ) ; 3.3V ; -- ;
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+; 5 ; 9 / 20 ( 45 % ) ; 2.5V ; -- ;
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+; 6 ; 13 / 14 ( 93 % ) ; 3.3V ; -- ;
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+; 7 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
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+; 8 ; 23 / 24 ( 96 % ) ; 3.3V ; -- ;
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++----------+-------------------+---------------+--------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
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@@ -636,7 +637,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; B14 ; 285 ; 7 ; sr_a[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
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; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; B16 ; 241 ; 6 ; rtc_int_n ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
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-; C1 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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+; C1 ; 9 ; 1 ; flash_mosi ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
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; C2 ; 8 ; 1 ; abc_a_oe ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
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; C3 ; 362 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; C4 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
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@@ -758,7 +759,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; K8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; K9 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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-; K10 ; 150 ; 4 ; flash_mosi ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; On ;
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+; K10 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; K12 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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@@ -919,105 +920,104 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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+-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
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-+--------------------------------------------+
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-; I/O Assignment Warnings ;
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-+--------------+-----------------------------+
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-; Pin Name ; Reason ;
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-+--------------+-----------------------------+
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-; abc_d_oe ; Missing drive strength ;
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-; abc_rdy_x ; Missing drive strength ;
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-; abc_resin_x ; Missing drive strength ;
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-; abc_int80_x ; Missing drive strength ;
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-; abc_int800_x ; Missing drive strength ;
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-; abc_nmi_x ; Missing drive strength ;
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-; abc_xm_x ; Missing drive strength ;
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-; abc_master ; Missing drive strength ;
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-; abc_a_oe ; Missing drive strength ;
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-; abc_d_ce_n ; Missing drive strength ;
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-; sr_cke ; Missing drive strength ;
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-; sr_ba[0] ; Missing drive strength ;
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-; sr_ba[1] ; Missing drive strength ;
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-; sr_a[0] ; Missing drive strength ;
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-; sr_a[1] ; Missing drive strength ;
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-; sr_a[2] ; Missing drive strength ;
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-; sr_a[3] ; Missing drive strength ;
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-; sr_a[4] ; Missing drive strength ;
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-; sr_a[5] ; Missing drive strength ;
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-; sr_a[6] ; Missing drive strength ;
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-; sr_a[7] ; Missing drive strength ;
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-; sr_a[8] ; Missing drive strength ;
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-; sr_a[9] ; Missing drive strength ;
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-; sr_a[10] ; Missing drive strength ;
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-; sr_a[11] ; Missing drive strength ;
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-; sr_a[12] ; Missing drive strength ;
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-; sr_dqm[0] ; Missing drive strength ;
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-; sr_dqm[1] ; Missing drive strength ;
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-; sr_cs_n ; Missing drive strength ;
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-; sr_we_n ; Missing drive strength ;
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-; sr_cas_n ; Missing drive strength ;
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-; sr_ras_n ; Missing drive strength ;
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-; sd_clk ; Missing drive strength ;
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-; sd_cmd ; Missing drive strength ;
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-; tty_rxd ; Missing drive strength ;
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-; tty_cts ; Missing drive strength ;
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-; flash_cs_n ; Missing drive strength ;
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-; flash_clk ; Missing drive strength ;
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-; flash_mosi ; Missing drive strength ;
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-; led[2] ; Missing drive strength ;
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-; led[3] ; Missing drive strength ;
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-; abc_d[0] ; Missing drive strength ;
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-; abc_d[1] ; Missing drive strength ;
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-; abc_d[2] ; Missing drive strength ;
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-; abc_d[3] ; Missing drive strength ;
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-; abc_d[4] ; Missing drive strength ;
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-; abc_d[5] ; Missing drive strength ;
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-; abc_d[6] ; Missing drive strength ;
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-; abc_d[7] ; Missing drive strength ;
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-; hdmi_sda ; Missing drive strength ;
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-; exth_ha ; Missing drive strength ;
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-; exth_hb ; Missing drive strength ;
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-; exth_hd ; Missing drive strength ;
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-; exth_he ; Missing drive strength ;
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-; exth_hf ; Missing drive strength ;
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-; exth_hg ; Missing drive strength ;
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-; sr_dq[0] ; Missing drive strength ;
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-; sr_dq[1] ; Missing drive strength ;
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-; sr_dq[2] ; Missing drive strength ;
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-; sr_dq[3] ; Missing drive strength ;
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-; sr_dq[4] ; Missing drive strength ;
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-; sr_dq[5] ; Missing drive strength ;
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-; sr_dq[6] ; Missing drive strength ;
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-; sr_dq[7] ; Missing drive strength ;
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-; sr_dq[8] ; Missing drive strength ;
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-; sr_dq[9] ; Missing drive strength ;
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-; sr_dq[10] ; Missing drive strength ;
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-; sr_dq[11] ; Missing drive strength ;
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-; sr_dq[12] ; Missing drive strength ;
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-; sr_dq[13] ; Missing drive strength ;
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-; sr_dq[14] ; Missing drive strength ;
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-; sr_dq[15] ; Missing drive strength ;
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-; sd_dat[0] ; Missing drive strength ;
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-; sd_dat[1] ; Missing drive strength ;
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-; sd_dat[2] ; Missing drive strength ;
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-; sd_dat[3] ; Missing drive strength ;
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-; spi_clk ; Missing drive strength ;
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-; spi_miso ; Missing drive strength ;
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-; spi_mosi ; Missing drive strength ;
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-; spi_cs_esp_n ; Missing drive strength ;
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-; esp_io0 ; Missing drive strength ;
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-; esp_int ; Missing drive strength ;
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-; i2c_scl ; Missing drive strength ;
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-; i2c_sda ; Missing drive strength ;
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-; gpio[0] ; Missing drive strength ;
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-; gpio[1] ; Missing drive strength ;
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-; gpio[2] ; Missing drive strength ;
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-; gpio[3] ; Missing drive strength ;
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-; gpio[4] ; Missing drive strength ;
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-; gpio[5] ; Missing drive strength ;
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-; hdmi_scl ; Missing drive strength ;
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-; hdmi_hpd ; Missing drive strength ;
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-; flash_mosi ; Missing location assignment ;
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-+--------------+-----------------------------+
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++---------------------------------------+
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+; I/O Assignment Warnings ;
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++--------------+------------------------+
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+; Pin Name ; Reason ;
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++--------------+------------------------+
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+; abc_d_oe ; Missing drive strength ;
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+; abc_rdy_x ; Missing drive strength ;
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+; abc_resin_x ; Missing drive strength ;
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+; abc_int80_x ; Missing drive strength ;
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+; abc_int800_x ; Missing drive strength ;
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+; abc_nmi_x ; Missing drive strength ;
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+; abc_xm_x ; Missing drive strength ;
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+; abc_master ; Missing drive strength ;
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+; abc_a_oe ; Missing drive strength ;
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+; abc_d_ce_n ; Missing drive strength ;
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+; sr_cke ; Missing drive strength ;
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+; sr_ba[0] ; Missing drive strength ;
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+; sr_ba[1] ; Missing drive strength ;
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+; sr_a[0] ; Missing drive strength ;
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+; sr_a[1] ; Missing drive strength ;
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+; sr_a[2] ; Missing drive strength ;
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+; sr_a[3] ; Missing drive strength ;
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+; sr_a[4] ; Missing drive strength ;
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+; sr_a[5] ; Missing drive strength ;
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+; sr_a[6] ; Missing drive strength ;
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+; sr_a[7] ; Missing drive strength ;
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+; sr_a[8] ; Missing drive strength ;
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+; sr_a[9] ; Missing drive strength ;
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+; sr_a[10] ; Missing drive strength ;
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+; sr_a[11] ; Missing drive strength ;
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+; sr_a[12] ; Missing drive strength ;
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+; sr_dqm[0] ; Missing drive strength ;
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+; sr_dqm[1] ; Missing drive strength ;
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+; sr_cs_n ; Missing drive strength ;
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+; sr_we_n ; Missing drive strength ;
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+; sr_cas_n ; Missing drive strength ;
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+; sr_ras_n ; Missing drive strength ;
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+; sd_clk ; Missing drive strength ;
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+; sd_cmd ; Missing drive strength ;
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+; tty_rxd ; Missing drive strength ;
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+; tty_cts ; Missing drive strength ;
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+; flash_cs_n ; Missing drive strength ;
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+; flash_clk ; Missing drive strength ;
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+; flash_mosi ; Missing drive strength ;
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+; led[2] ; Missing drive strength ;
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+; led[3] ; Missing drive strength ;
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+; abc_d[0] ; Missing drive strength ;
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+; abc_d[1] ; Missing drive strength ;
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+; abc_d[2] ; Missing drive strength ;
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+; abc_d[3] ; Missing drive strength ;
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+; abc_d[4] ; Missing drive strength ;
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+; abc_d[5] ; Missing drive strength ;
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+; abc_d[6] ; Missing drive strength ;
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+; abc_d[7] ; Missing drive strength ;
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+; hdmi_sda ; Missing drive strength ;
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+; exth_ha ; Missing drive strength ;
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+; exth_hb ; Missing drive strength ;
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+; exth_hd ; Missing drive strength ;
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+; exth_he ; Missing drive strength ;
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+; exth_hf ; Missing drive strength ;
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+; exth_hg ; Missing drive strength ;
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+; sr_dq[0] ; Missing drive strength ;
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+; sr_dq[1] ; Missing drive strength ;
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+; sr_dq[2] ; Missing drive strength ;
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+; sr_dq[3] ; Missing drive strength ;
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+; sr_dq[4] ; Missing drive strength ;
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+; sr_dq[5] ; Missing drive strength ;
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+; sr_dq[6] ; Missing drive strength ;
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+; sr_dq[7] ; Missing drive strength ;
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+; sr_dq[8] ; Missing drive strength ;
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+; sr_dq[9] ; Missing drive strength ;
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+; sr_dq[10] ; Missing drive strength ;
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+; sr_dq[11] ; Missing drive strength ;
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+; sr_dq[12] ; Missing drive strength ;
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+; sr_dq[13] ; Missing drive strength ;
|
|
|
+; sr_dq[14] ; Missing drive strength ;
|
|
|
+; sr_dq[15] ; Missing drive strength ;
|
|
|
+; sd_dat[0] ; Missing drive strength ;
|
|
|
+; sd_dat[1] ; Missing drive strength ;
|
|
|
+; sd_dat[2] ; Missing drive strength ;
|
|
|
+; sd_dat[3] ; Missing drive strength ;
|
|
|
+; spi_clk ; Missing drive strength ;
|
|
|
+; spi_miso ; Missing drive strength ;
|
|
|
+; spi_mosi ; Missing drive strength ;
|
|
|
+; spi_cs_esp_n ; Missing drive strength ;
|
|
|
+; esp_io0 ; Missing drive strength ;
|
|
|
+; esp_int ; Missing drive strength ;
|
|
|
+; i2c_scl ; Missing drive strength ;
|
|
|
+; i2c_sda ; Missing drive strength ;
|
|
|
+; gpio[0] ; Missing drive strength ;
|
|
|
+; gpio[1] ; Missing drive strength ;
|
|
|
+; gpio[2] ; Missing drive strength ;
|
|
|
+; gpio[3] ; Missing drive strength ;
|
|
|
+; gpio[4] ; Missing drive strength ;
|
|
|
+; gpio[5] ; Missing drive strength ;
|
|
|
+; hdmi_scl ; Missing drive strength ;
|
|
|
+; hdmi_hpd ; Missing drive strength ;
|
|
|
++--------------+------------------------+
|
|
|
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
@@ -1025,7 +1025,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
|
|
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
|
|
|
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
|
|
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
|
|
|
-; |max80 ; 327 (68) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 142 ; 0 ; 109 (2) ; 49 (0) ; 169 (50) ; |max80 ; max80 ; work ;
|
|
|
+; |max80 ; 327 (69) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 142 ; 0 ; 109 (3) ; 49 (0) ; 169 (49) ; |max80 ; max80 ; work ;
|
|
|
; |hdmitx:hdmitx| ; 118 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
|
|
|
; |altlvds_tx:ALTLVDS_TX_component| ; 118 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
|
|
|
; |hdmitx_lvds_tx:auto_generated| ; 118 (59) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 40 (39) ; 69 (20) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
|
|
|
@@ -1047,7 +1047,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
|
|
; |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; pll_altpll_dyn_phase_le12 ; work ;
|
|
|
; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
|
|
|
; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
|
|
|
-; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 3 (3) ; 18 (18) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
|
|
|
+; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 3 (3) ; 19 (19) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
|
|
|
; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
|
|
|
; |tmdsenc:hdmitmds[2].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
|
|
|
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
|
|
|
@@ -1310,14 +1310,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
|
|
|
; clock_48 ; PIN_M15 ; 1 ; Clock ; no ; -- ; -- ; -- ;
|
|
|
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X23_Y14_N19 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X24_Y24_N19 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ;
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; Clock ; yes ; Global Clock ; GCLK9 ; -- ;
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked ; PLL_2 ; 13 ; Async. clear ; no ; -- ; -- ; -- ;
|
|
|
-; rst_n ; FF_X21_Y28_N1 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
-; rst_n ; FF_X21_Y28_N1 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK13 ; -- ;
|
|
|
-; tmdsenc:hdmitmds[0].enc|denreg ; FF_X31_Y14_N11 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
|
|
|
+; rst_n ; FF_X31_Y28_N1 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
+; rst_n ; FF_X31_Y28_N1 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK13 ; -- ;
|
|
|
+; tmdsenc:hdmitmds[0].enc|denreg ; FF_X27_Y22_N7 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
|
|
|
+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
|
|
|
@@ -1331,7 +1331,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
|
|
|
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
|
|
|
-; rst_n ; FF_X21_Y28_N1 ; 75 ; 0 ; Global Clock ; GCLK13 ; -- ;
|
|
|
+; rst_n ; FF_X31_Y28_N1 ; 75 ; 0 ; Global Clock ; GCLK13 ; -- ;
|
|
|
+-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
|
|
|
@@ -1340,37 +1340,37 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+-----------------------+------------------------+
|
|
|
; Routing Resource Type ; Usage ;
|
|
|
+-----------------------+------------------------+
|
|
|
-; Block interconnects ; 256 / 47,787 ( < 1 % ) ;
|
|
|
-; C16 interconnects ; 0 / 1,804 ( 0 % ) ;
|
|
|
-; C4 interconnects ; 77 / 31,272 ( < 1 % ) ;
|
|
|
-; Direct links ; 94 / 47,787 ( < 1 % ) ;
|
|
|
+; Block interconnects ; 257 / 47,787 ( < 1 % ) ;
|
|
|
+; C16 interconnects ; 7 / 1,804 ( < 1 % ) ;
|
|
|
+; C4 interconnects ; 95 / 31,272 ( < 1 % ) ;
|
|
|
+; Direct links ; 75 / 47,787 ( < 1 % ) ;
|
|
|
; Global clocks ; 6 / 20 ( 30 % ) ;
|
|
|
-; Local interconnects ; 184 / 15,408 ( 1 % ) ;
|
|
|
-; R24 interconnects ; 2 / 1,775 ( < 1 % ) ;
|
|
|
-; R4 interconnects ; 119 / 41,310 ( < 1 % ) ;
|
|
|
+; Local interconnects ; 196 / 15,408 ( 1 % ) ;
|
|
|
+; R24 interconnects ; 5 / 1,775 ( < 1 % ) ;
|
|
|
+; R4 interconnects ; 135 / 41,310 ( < 1 % ) ;
|
|
|
+-----------------------+------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Logic Elements ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Logic Elements (Average = 10.55) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Logic Elements (Average = 11.28) ; Number of LABs (Total = 29) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; 1 ; 5 ;
|
|
|
-; 2 ; 3 ;
|
|
|
+; 1 ; 1 ;
|
|
|
+; 2 ; 5 ;
|
|
|
; 3 ; 0 ;
|
|
|
; 4 ; 0 ;
|
|
|
-; 5 ; 0 ;
|
|
|
+; 5 ; 1 ;
|
|
|
; 6 ; 0 ;
|
|
|
; 7 ; 1 ;
|
|
|
-; 8 ; 0 ;
|
|
|
+; 8 ; 1 ;
|
|
|
; 9 ; 1 ;
|
|
|
-; 10 ; 2 ;
|
|
|
-; 11 ; 1 ;
|
|
|
+; 10 ; 0 ;
|
|
|
+; 11 ; 0 ;
|
|
|
; 12 ; 1 ;
|
|
|
-; 13 ; 3 ;
|
|
|
-; 14 ; 2 ;
|
|
|
-; 15 ; 2 ;
|
|
|
+; 13 ; 1 ;
|
|
|
+; 14 ; 3 ;
|
|
|
+; 15 ; 4 ;
|
|
|
; 16 ; 10 ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
|
|
|
@@ -1378,101 +1378,100 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+-------------------------------------------------------------------+
|
|
|
; LAB-wide Signals ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
-; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 31) ;
|
|
|
+; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 29) ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
; 1 Async. clear ; 10 ;
|
|
|
-; 1 Clock ; 21 ;
|
|
|
+; 1 Clock ; 22 ;
|
|
|
; 1 Clock enable ; 3 ;
|
|
|
; 1 Sync. clear ; 3 ;
|
|
|
-; 2 Clocks ; 7 ;
|
|
|
+; 1 Sync. load ; 1 ;
|
|
|
+; 2 Clocks ; 5 ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced (Average = 17.32) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Signals Sourced (Average = 18.45) ; Number of LABs (Total = 29) ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
-; 1 ; 2 ;
|
|
|
-; 2 ; 4 ;
|
|
|
-; 3 ; 1 ;
|
|
|
+; 1 ; 0 ;
|
|
|
+; 2 ; 2 ;
|
|
|
+; 3 ; 3 ;
|
|
|
; 4 ; 1 ;
|
|
|
; 5 ; 0 ;
|
|
|
; 6 ; 0 ;
|
|
|
; 7 ; 1 ;
|
|
|
; 8 ; 0 ;
|
|
|
; 9 ; 0 ;
|
|
|
-; 10 ; 0 ;
|
|
|
+; 10 ; 1 ;
|
|
|
; 11 ; 0 ;
|
|
|
; 12 ; 0 ;
|
|
|
; 13 ; 0 ;
|
|
|
; 14 ; 0 ;
|
|
|
; 15 ; 0 ;
|
|
|
-; 16 ; 0 ;
|
|
|
+; 16 ; 1 ;
|
|
|
; 17 ; 1 ;
|
|
|
-; 18 ; 1 ;
|
|
|
+; 18 ; 0 ;
|
|
|
; 19 ; 3 ;
|
|
|
-; 20 ; 1 ;
|
|
|
+; 20 ; 0 ;
|
|
|
; 21 ; 0 ;
|
|
|
-; 22 ; 1 ;
|
|
|
+; 22 ; 0 ;
|
|
|
; 23 ; 5 ;
|
|
|
; 24 ; 3 ;
|
|
|
; 25 ; 0 ;
|
|
|
-; 26 ; 3 ;
|
|
|
+; 26 ; 2 ;
|
|
|
; 27 ; 1 ;
|
|
|
-; 28 ; 1 ;
|
|
|
+; 28 ; 2 ;
|
|
|
; 29 ; 1 ;
|
|
|
-; 30 ; 1 ;
|
|
|
+; 30 ; 2 ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced Out ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced Out (Average = 4.61) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Signals Sourced Out (Average = 4.93) ; Number of LABs (Total = 29) ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
; 0 ; 1 ;
|
|
|
-; 1 ; 8 ;
|
|
|
-; 2 ; 6 ;
|
|
|
+; 1 ; 3 ;
|
|
|
+; 2 ; 9 ;
|
|
|
; 3 ; 4 ;
|
|
|
; 4 ; 1 ;
|
|
|
-; 5 ; 2 ;
|
|
|
+; 5 ; 3 ;
|
|
|
; 6 ; 0 ;
|
|
|
; 7 ; 1 ;
|
|
|
; 8 ; 0 ;
|
|
|
-; 9 ; 1 ;
|
|
|
+; 9 ; 0 ;
|
|
|
; 10 ; 0 ;
|
|
|
-; 11 ; 4 ;
|
|
|
-; 12 ; 2 ;
|
|
|
-; 13 ; 1 ;
|
|
|
+; 11 ; 0 ;
|
|
|
+; 12 ; 7 ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Distinct Inputs ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Distinct Inputs (Average = 6.39) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Distinct Inputs (Average = 6.76) ; Number of LABs (Total = 29) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
; 1 ; 0 ;
|
|
|
-; 2 ; 8 ;
|
|
|
+; 2 ; 5 ;
|
|
|
; 3 ; 8 ;
|
|
|
-; 4 ; 0 ;
|
|
|
-; 5 ; 0 ;
|
|
|
-; 6 ; 2 ;
|
|
|
-; 7 ; 0 ;
|
|
|
-; 8 ; 3 ;
|
|
|
-; 9 ; 2 ;
|
|
|
-; 10 ; 0 ;
|
|
|
-; 11 ; 2 ;
|
|
|
+; 4 ; 1 ;
|
|
|
+; 5 ; 1 ;
|
|
|
+; 6 ; 0 ;
|
|
|
+; 7 ; 2 ;
|
|
|
+; 8 ; 1 ;
|
|
|
+; 9 ; 1 ;
|
|
|
+; 10 ; 2 ;
|
|
|
+; 11 ; 1 ;
|
|
|
; 12 ; 0 ;
|
|
|
; 13 ; 1 ;
|
|
|
-; 14 ; 0 ;
|
|
|
-; 15 ; 0 ;
|
|
|
-; 16 ; 0 ;
|
|
|
-; 17 ; 3 ;
|
|
|
-; 18 ; 1 ;
|
|
|
+; 14 ; 1 ;
|
|
|
+; 15 ; 1 ;
|
|
|
+; 16 ; 2 ;
|
|
|
+; 17 ; 1 ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
@@ -1533,9 +1532,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
|
|
; Pin/Rules ; IO_000003 ; IO_000002 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000020 ; IO_000011 ; IO_000021 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000009 ; IO_000010 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000022 ; IO_000019 ; IO_000033 ; IO_000034 ; IO_000042 ;
|
|
|
+--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
|
|
-; Total Pass ; 137 ; 7 ; 137 ; 142 ; 0 ; 142 ; 137 ; 0 ; 90 ; 2 ; 4 ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 142 ; 142 ; 0 ; 0 ; 4 ; 90 ; 2 ; 0 ; 0 ; 142 ; 102 ; 0 ;
|
|
|
+; Total Pass ; 138 ; 7 ; 138 ; 142 ; 0 ; 142 ; 138 ; 0 ; 90 ; 2 ; 4 ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 142 ; 142 ; 0 ; 0 ; 4 ; 90 ; 2 ; 0 ; 0 ; 142 ; 102 ; 0 ;
|
|
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
|
-; Total Inapplicable ; 5 ; 135 ; 5 ; 0 ; 142 ; 0 ; 5 ; 142 ; 52 ; 140 ; 138 ; 85 ; 142 ; 142 ; 142 ; 142 ; 142 ; 142 ; 0 ; 0 ; 142 ; 142 ; 138 ; 52 ; 140 ; 142 ; 142 ; 0 ; 40 ; 142 ;
|
|
|
+; Total Inapplicable ; 4 ; 135 ; 4 ; 0 ; 142 ; 0 ; 4 ; 142 ; 52 ; 140 ; 138 ; 85 ; 142 ; 142 ; 142 ; 142 ; 142 ; 142 ; 0 ; 0 ; 142 ; 142 ; 138 ; 52 ; 140 ; 142 ; 142 ; 0 ; 40 ; 142 ;
|
|
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
|
; abc_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
; abc_a[0] ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
@@ -1612,7 +1611,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
; tty_dtr ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
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|
; flash_cs_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
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; flash_clk ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
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-; flash_mosi ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
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+; flash_mosi ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
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; flash_miso ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; rtc_32khz ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; rtc_int_n ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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@@ -1723,7 +1722,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
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; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
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+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
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-; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 14.4 ;
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+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 10.7 ;
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+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
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Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
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This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
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@@ -1734,37 +1733,31 @@ This will disable optimization of problematic paths and expose them for further
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+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
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; Source Register ; Destination Register ; Delay Added in ns ;
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+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4] ; 0.578 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.432 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.274 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.430 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.275 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1] ; 0.263 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.182 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.043 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025 ;
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@@ -1774,7 +1767,7 @@ This will disable optimization of problematic paths and expose them for further
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025 ;
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+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
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-Note: This table only shows the top 39 path(s) that have the largest delay added for hold.
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+Note: This table only shows the top 33 path(s) that have the largest delay added for hold.
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+-----------------+
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@@ -1830,7 +1823,6 @@ Warning (176674): Following 4 pins are differential I/O pins but do not have the
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Warning (176118): Pin "hdmi_d[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[1](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 108
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Warning (176118): Pin "hdmi_d[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[2](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 108
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Warning (176118): Pin "hdmi_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_clk(n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
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-Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 138 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
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Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
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Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
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Warning (15567): Can't achieve requested High bandwidth type; current PLL requires a bandwidth value of greater than 2.000 Mhz -- achieved bandwidth of 1.03 MHz to 1.97 MHz File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
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@@ -1911,19 +1903,6 @@ Info (176221): The fitter is attempting to aggressively pack all registers conne
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Info (176235): Finished register packing
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Extra Info (176218): Packed 3 registers into blocks of type I/O Output Buffer
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Extra Info (176220): Created 3 register duplicates
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-Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
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- Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
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- Info (176212): I/O standards used: 3.3-V LVTTL.
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-Info (176215): I/O bank details before I/O pin placement
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- Info (176214): Statistics of I/O banks
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- Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 13 total pin(s) used -- 1 pins available
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- Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used -- 2 pins available
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- Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 1 pins available
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- Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 6 pins available
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- Info (176213): I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 11 pins available
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- Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 13 total pin(s) used -- 1 pins available
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- Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 23 total pin(s) used -- 0 pins available
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- Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 23 total pin(s) used -- 1 pins available
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Warning (15058): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
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Warning (15064): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "sr_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
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Warning (15055): PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
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@@ -1939,12 +1918,12 @@ Info (170137): Fitter placement was successful
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Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
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Info (170193): Fitter routing operations beginning
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Info (170195): Router estimated average interconnect usage is 0% of the available device resources
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- Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
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+ Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
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Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
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Info (170201): Optimizations that may affect the design's routability were skipped
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Info (170200): Optimizations that may affect the design's timing were skipped
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
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-Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
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+Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
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Info (334003): Started post-fitting delay annotation
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Info (334004): Delay annotation completed successfully
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Info (334003): Started post-fitting delay annotation
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@@ -2098,9 +2077,9 @@ Warning (169064): Following 51 pins have no output enable or a GND or VCC output
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Info (169065): Pin hdmi_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
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Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 113
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Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
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-Info: Quartus Prime Fitter was successful. 0 errors, 32 warnings
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+Info: Quartus Prime Fitter was successful. 0 errors, 31 warnings
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Info: Peak virtual memory: 1488 megabytes
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- Info: Processing ended: Fri Aug 6 17:56:41 2021
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+ Info: Processing ended: Fri Aug 6 18:02:14 2021
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Info: Elapsed time: 00:00:06
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Info: Total CPU time (on all processors): 00:00:07
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H. Peter Anvin