Update pinout to match latest schematic

.gitignore

@@ -11,3 +11,5 @@ greybox_tmp/
 *.inc
 *.ppf
 *.qip
+*.pins.qsf
+*.nopins.qsf

Makefile

@@ -0,0 +1,11 @@
+PERL = perl
+
+all: max80.qsf
+
+# Ugly hack, because Quartus edits max80.qsf directly
+%.qsf: %.pins.qsf
+	grep -v '^set_location_assignment *PIN_' $@ > $*.nopins.qsf
+	cat $*.nopins.qsf $< > $@
+
+%.pins.qsf: %.pins pin2qsf.pl
+	$(PERL) pin2qsf.pl < $< > $@

max80.pins

@@ -1,162 +1,192 @@
-a2	abc_int800_x
-a3	abc_nmi_x
-a4	sr_dq[11]
-a5	sr_dq[8]
-a6	sr_a[9]
-a7	sr_a[7]
-a8	abc_a[0]
-a9	abc_a[2]
-a10	sr_dq[7]
-a11	sr_dq[5]
-a12	sr_dq[0]
-a13	sr_ba[0]
-a14	sr_a[0]
-a15	sr_a[3]
-
+# Bank 1
+# j5	TMS
+# j3	nCE
+# j4	TDO
+# h4	TDI
+e1	abc_a[6]
 b1	abc_xm_x
-b3	abc_int80_x
-b4	abc_rdy_x
-b5	sr_dq[10]
-b6	sr_a[12]
-b7	sr_a[8]
-b8	abc_a[1]
-b10	sr_dq[6]
-b11	sr_dq[4]
-b12	sr_ras_n
-b13	sr_ba[1]
-b14	sr_a[1]
-b16	rtc_int_n
-
-c1	flash_mosi
 c2	abc_a_oe
-c6	sr_dq[14]
-c8	sr_a[11]
-c9	sr_a[4]
-c11	sr_dq[3]
-c14	sr_a[10]
-c15	i2c_sda
-c16	i2c_scl
-
-d1	abc_a[3]
+# c1	ASDO
+f3	abc_a[5]
 d2	flash_cs_n
-d3	sr_clk
-d5	sr_dq[15]
-d6	sr_dq[13]
-d8	sr_dqm[1]
-d9	sr_a[5]
-d11	sr_dq[2]
-d12	sr_cs_n
-d14	sr_a[2]
-d15	tty_cts
-d16	tty_rts
-
-e1	abc_a[6]
-e6	sr_dq[12]
-e7	sr_dq[9]
-e8	sr_a[6]
-e9	sr_cas_n
-e10	sr_dqm[0]
-e11	sr_dq[1]
-e15	rtc_32khz
-e16	tty_txd
-
-f1	abc_a[7]
+d1	abc_a[3]
+# f4	nSTATUS
+g5	abc_a[4]
 f2	abc_cs_n
-f3	abc_a[5]
-f8	sr_cke
-f9	sr_we_n
-f13	tty_rxd
-f14	sd_dat[2]
-f15	sd_dat[0]
-f16	sd_dat[3]
-
-g1	abc_a[8]
+f1	abc_a[7]
 g2	abc_out_n[0]
-g5	abc_a[4]
-g15	sd_clk
-g16	sd_cmd
-
+g1	abc_a[8]
 h1	flash_clk
 h2	flash_miso
-h3	tck
-h4	tdi
+# h5	nCONFIG
+# h3	TCK
 
-j1	abc_a[9]
+# Bank 2
+r1	abc_xmemw80_n
+p2	abc_rst_n
+p1	abc_xmemw800_n
+m2	abc_inp_n[1]
+m1	abc_a[13]
 j2	abc_out_n[1]
-j4	tdo
-j5	tms
-j15	hdmi_clk
-# j16	hdmi_clk(n)
-
+j1	abc_a[9]
+# k6	N/C
+# l6	N/C
+l3	abc_out_n[3]
 k1	abc_a[11]
+l2	abc_inp_n[0]
+l1	abc_a[12]
 k2	abc_out_n[4]
+n2	abc_a[14]
+n1	abc_a[15]
 k5	abc_out_n[2]
-k15	hdmi_d[0]
-# k16	hdmi_d[0](n)
-
-l1	abc_a[12]
-l2	abc_inp_n[0]
-l3	abc_out_n[3]
 l4	abc_a[10]
-l7	gpio[0]
-l8	esp_io0
-l10	abc_xoutpstb_n
 
-m1	abc_a[13]
-m2	abc_inp_n[1]
+# Bank 3
 m6	abc_d[1]
+p6	spi_clk
 m7	spi_miso
+r5	abc_d_ce_n
+t5	abc_d_oe
+r6	abc_resin_x
+t6	gpio[2]
+l7	gpio[0]
+r7	gpio[5]
+t7	gpio[4]
+l8	esp_io0
 m8	spi_mosi
-m10	sd_dat[1]
-m11	hdmi_scl
-m15	clock_48
-
-n1	abc_a[15]
-n2	abc_a[14]
-n3	abc_xmemfl_n
-n5	abc_d[2]
-n6	esp_io1
 n8	spi_cs_esp_n
-n9	xabc_op[2]
-n11	xabc_xm_n
-n12	xabc_xio_n
-n15	hdmi_d[1]
-# n16	hdmi_d[1](n)
-
-p1	abc_xmemw800_n
-p2	abc_rst_n
-p3	abc_d[0]
-p6	spi_clk
 p8	esp_int
-p9	gpio[1]
-p14	tty_dtr
-p16	hdmi_d[2](n)
-
-r1	abc_xmemw80_n
+r8	exth_hh
+t8	abc_clk
+n3	abc_xmemfl_n
+p3	abc_d[0]
 r3	abc_d[4]
-r4	abc_d[6]
-r5	abc_d_ce_n
-r6	abc_resin_x
-r7	gpio[5]
-r8	xabc_op[0]
-r10	gpio[3]
-r11	xabc_nmi_n
-r12	xabc_gpio[1]
-r13	hdmi_sda
-r14	led[2]
-r16	hdmi_d[2]
-
-t2	abc_d[3]
 t3	abc_d[5]
+t2	abc_d[3]
+r4	abc_d[6]
 t4	abc_d[7]
-t5	abc_d_oe
-t6	gpio[2]
-t7	gpio[4]
-t8	abc_clk
-t9	xabc_op[1]
+n5	abc_d[2]
+n6	spi_cs_flash_n
+
+# Bank 4
+# l11	N/C
+# k9	N/C
+m11	hdmi_scl
+# l9	N/C
+t13	led[1]
+# m9	N/C
+# r9	VCC
+n9	exth_hb
+t9	exth_hc
+r10	gpio[3]
 t10	abc_master
-t11	xabc_gpio[0]
+r11	exth_hd
+t11	exth_hf
+r12	exth_he
 t12	abc_xinpstb_n
-t13	led[1]
+# k10	N/C
+l10	abc_xoutpstb_n
+p9	gpio[1]
+n12	exth_ha
+n11	exth_hg
+r13	hdmi_sda
 t14	led[3]
 t15	hdmi_hpd
+m10	sd_dat[1]
+# p11	N/C
+p14	tty_dtr
+r14	led[2]
+
+# Bank 5 (2.5 V)
+# n14	N/C
+# p15	N/C
+# p16	hdmi_d[2](n)
+r16	hdmi_d[2]
+# k17	N/C
+# n16	hdmi_d[1](n)
+n15	hdmi_d[1]
+# l14	N/C
+# l13	N/C
+# l16	N/C
+# l15	N/C
+# k16	hdmi_d[0](n)
+k15	hdmi_d[0]
+# j16	hdmi_clk(n)
+j15	hdmi_clk
+# m16	GND
+# j14	N/C
+m15	clock_48
+# j12	N/C
+# j13	N/C
+
+# Bank 6
+e16	tty_txd
+e15	rtc_32khz
+# h14	CONF_DONE
+# h13	MSEL[0]
+# h12	MSEL[1]
+# g12	MSEL[2]
+g16	sd_cmd
+g15	sd_clk
+f13	tty_rxd
+f16	sd_dat[3]
+f15	sd_dat[0]
+b16	rtc_int_n
+f14	sd_dat[2]
+d16	tty_rts
+d15	tty_cts
+# g11	N/C
+c16	i2c_scl
+c15	i2c_sda
+
+# Bank 7
+d12	sr_cs_n
+c11	sr_dq[3]
+c14	sr_a[10]
+b13	sr_ba[1]
+d14	sr_a[2]
+a14	sr_a[0]
+d11	sr_dq[2]
+b14	sr_a[1]
+e11	sr_dq[1]
+e10	sr_dqm[0]
+a12	sr_dq[0]
+b12	sr_ras_n
+a11	sr_dq[5]
+b11	sr_dq[4]
+a13	sr_ba[0]
+a15	sr_a[3]
+f9	sr_we_n
+a10	sr_dq[7]
+b10	sr_dq[6]
+c9	sr_a[4]
+d9	sr_a[5]
+e9	sr_cas_n
+a9	abc_a[2]
+# a8	abc_a[2]
+
+# Bank 8
+d8	sr_dqm[1]
+e8	sr_a[6]
+a8	abc_a[0]
+f8	sr_cke
+b8	abc_a[1]
+a7	sr_a[7]
+c8	sr_a[11]
+b7	sr_a[8]
+c6	sr_dq[14]
+a6	sr_a[9]
+b6	sr_a[12]
+e7	sr_dq[9]
+e6	sr_dq[12]
+a5	sr_dq[8]
+b5	sr_dq[10]
+d6	sr_dq[13]
+a4	sr_dq[11]
+b4	abc_rdy_x
+a2	abc_int800_x
+d5	sr_dq[15]
+a3	abc_nmi_x
+b3	abc_int80_x
+# c3	N/C
+d3	sr_clk

max80.qsf

@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EP4CE15F17C8
 set_global_assignment -name TOP_LEVEL_ENTITY max80
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:33  FEBRUARY 22, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -126,162 +126,160 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_miso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48
-set_location_assignment PIN_A2 -to abc_int800_x
-set_location_assignment PIN_A3 -to abc_nmi_x
-set_location_assignment PIN_A4 -to sr_dq[11]
-set_location_assignment PIN_A5 -to sr_dq[8]
-set_location_assignment PIN_A6 -to sr_a[9]
-set_location_assignment PIN_A7 -to sr_a[7]
-set_location_assignment PIN_A8 -to abc_a[0]
-set_location_assignment PIN_A9 -to abc_a[2]
-set_location_assignment PIN_A10 -to sr_dq[7]
-set_location_assignment PIN_A11 -to sr_dq[5]
-set_location_assignment PIN_A12 -to sr_dq[0]
-set_location_assignment PIN_A13 -to sr_ba[0]
-set_location_assignment PIN_A14 -to sr_a[0]
-set_location_assignment PIN_A15 -to sr_a[3]
+
+
+set_global_assignment -name VERILOG_FILE syncho.v
+set_global_assignment -name VERILOG_FILE ip/hdmitx.v
+set_global_assignment -name VERILOG_FILE ip/pll.v
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
+set_global_assignment -name SDC_FILE max80.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A
+
+
+
+set_location_assignment PIN_E1 -to abc_a[6]
 set_location_assignment PIN_B1 -to abc_xm_x
-set_location_assignment PIN_B3 -to abc_int80_x
-set_location_assignment PIN_B4 -to abc_rdy_x
-set_location_assignment PIN_B5 -to sr_dq[10]
-set_location_assignment PIN_B6 -to sr_a[12]
-set_location_assignment PIN_B7 -to sr_a[8]
-set_location_assignment PIN_B8 -to abc_a[1]
-set_location_assignment PIN_B10 -to sr_dq[6]
-set_location_assignment PIN_B11 -to sr_dq[4]
-set_location_assignment PIN_B12 -to sr_ras_n
-set_location_assignment PIN_B13 -to sr_ba[1]
-set_location_assignment PIN_B14 -to sr_a[1]
-set_location_assignment PIN_B16 -to rtc_int_n
-set_location_assignment PIN_C1 -to flash_mosi
 set_location_assignment PIN_C2 -to abc_a_oe
-set_location_assignment PIN_C6 -to sr_dq[14]
-set_location_assignment PIN_C8 -to sr_a[11]
-set_location_assignment PIN_C9 -to sr_a[4]
-set_location_assignment PIN_C11 -to sr_dq[3]
-set_location_assignment PIN_C14 -to sr_a[10]
-set_location_assignment PIN_C15 -to i2c_sda
-set_location_assignment PIN_C16 -to i2c_scl
-set_location_assignment PIN_D1 -to abc_a[3]
+set_location_assignment PIN_F3 -to abc_a[5]
 set_location_assignment PIN_D2 -to flash_cs_n
-set_location_assignment PIN_D3 -to sr_clk
-set_location_assignment PIN_D5 -to sr_dq[15]
-set_location_assignment PIN_D6 -to sr_dq[13]
-set_location_assignment PIN_D8 -to sr_dqm[1]
-set_location_assignment PIN_D9 -to sr_a[5]
-set_location_assignment PIN_D11 -to sr_dq[2]
-set_location_assignment PIN_D12 -to sr_cs_n
-set_location_assignment PIN_D14 -to sr_a[2]
-set_location_assignment PIN_D15 -to tty_cts
-set_location_assignment PIN_D16 -to tty_rts
-set_location_assignment PIN_E1 -to abc_a[6]
-set_location_assignment PIN_E6 -to sr_dq[12]
-set_location_assignment PIN_E7 -to sr_dq[9]
-set_location_assignment PIN_E8 -to sr_a[6]
-set_location_assignment PIN_E9 -to sr_cas_n
-set_location_assignment PIN_E10 -to sr_dqm[0]
-set_location_assignment PIN_E11 -to sr_dq[1]
-set_location_assignment PIN_E15 -to rtc_32khz
-set_location_assignment PIN_E16 -to tty_txd
-set_location_assignment PIN_F1 -to abc_a[7]
+set_location_assignment PIN_D1 -to abc_a[3]
+set_location_assignment PIN_G5 -to abc_a[4]
 set_location_assignment PIN_F2 -to abc_cs_n
-set_location_assignment PIN_F3 -to abc_a[5]
-set_location_assignment PIN_F8 -to sr_cke
-set_location_assignment PIN_F9 -to sr_we_n
-set_location_assignment PIN_F13 -to tty_rxd
-set_location_assignment PIN_F14 -to sd_dat[2]
-set_location_assignment PIN_F15 -to sd_dat[0]
-set_location_assignment PIN_F16 -to sd_dat[3]
-set_location_assignment PIN_G1 -to abc_a[8]
+set_location_assignment PIN_F1 -to abc_a[7]
 set_location_assignment PIN_G2 -to abc_out_n[0]
-set_location_assignment PIN_G5 -to abc_a[4]
-set_location_assignment PIN_G15 -to sd_clk
-set_location_assignment PIN_G16 -to sd_cmd
+set_location_assignment PIN_G1 -to abc_a[8]
 set_location_assignment PIN_H1 -to flash_clk
 set_location_assignment PIN_H2 -to flash_miso
-set_location_assignment PIN_H3 -to tck
-set_location_assignment PIN_H4 -to tdi
-set_location_assignment PIN_J1 -to abc_a[9]
+set_location_assignment PIN_R1 -to abc_xmemw80_n
+set_location_assignment PIN_P2 -to abc_rst_n
+set_location_assignment PIN_P1 -to abc_xmemw800_n
+set_location_assignment PIN_M2 -to abc_inp_n[1]
+set_location_assignment PIN_M1 -to abc_a[13]
 set_location_assignment PIN_J2 -to abc_out_n[1]
-set_location_assignment PIN_J4 -to tdo
-set_location_assignment PIN_J5 -to tms
-set_location_assignment PIN_J15 -to hdmi_clk
+set_location_assignment PIN_J1 -to abc_a[9]
+set_location_assignment PIN_L3 -to abc_out_n[3]
 set_location_assignment PIN_K1 -to abc_a[11]
+set_location_assignment PIN_L2 -to abc_inp_n[0]
+set_location_assignment PIN_L1 -to abc_a[12]
 set_location_assignment PIN_K2 -to abc_out_n[4]
+set_location_assignment PIN_N2 -to abc_a[14]
+set_location_assignment PIN_N1 -to abc_a[15]
 set_location_assignment PIN_K5 -to abc_out_n[2]
-set_location_assignment PIN_K15 -to hdmi_d[0]
-set_location_assignment PIN_L1 -to abc_a[12]
-set_location_assignment PIN_L2 -to abc_inp_n[0]
-set_location_assignment PIN_L3 -to abc_out_n[3]
 set_location_assignment PIN_L4 -to abc_a[10]
-set_location_assignment PIN_L7 -to gpio[0]
-set_location_assignment PIN_L8 -to esp_io0
-set_location_assignment PIN_L10 -to abc_xoutpstb_n
-set_location_assignment PIN_M1 -to abc_a[13]
-set_location_assignment PIN_M2 -to abc_inp_n[1]
 set_location_assignment PIN_M6 -to abc_d[1]
+set_location_assignment PIN_P6 -to spi_clk
 set_location_assignment PIN_M7 -to spi_miso
+set_location_assignment PIN_R5 -to abc_d_ce_n
+set_location_assignment PIN_T5 -to abc_d_oe
+set_location_assignment PIN_R6 -to abc_resin_x
+set_location_assignment PIN_T6 -to gpio[2]
+set_location_assignment PIN_L7 -to gpio[0]
+set_location_assignment PIN_R7 -to gpio[5]
+set_location_assignment PIN_T7 -to gpio[4]
+set_location_assignment PIN_L8 -to esp_io0
 set_location_assignment PIN_M8 -to spi_mosi
-set_location_assignment PIN_M10 -to sd_dat[1]
-set_location_assignment PIN_M11 -to hdmi_scl
-set_location_assignment PIN_M15 -to clock_48
-set_location_assignment PIN_N1 -to abc_a[15]
-set_location_assignment PIN_N2 -to abc_a[14]
-set_location_assignment PIN_N3 -to abc_xmemfl_n
-set_location_assignment PIN_N5 -to abc_d[2]
-set_location_assignment PIN_N6 -to esp_io1
 set_location_assignment PIN_N8 -to spi_cs_esp_n
-set_location_assignment PIN_N9 -to xabc_op[2]
-set_location_assignment PIN_N11 -to xabc_xm_n
-set_location_assignment PIN_N12 -to xabc_xio_n
-set_location_assignment PIN_N15 -to hdmi_d[1]
-set_location_assignment PIN_P1 -to abc_xmemw800_n
-set_location_assignment PIN_P2 -to abc_rst_n
-set_location_assignment PIN_P3 -to abc_d[0]
-set_location_assignment PIN_P6 -to spi_clk
 set_location_assignment PIN_P8 -to esp_int
-set_location_assignment PIN_P9 -to gpio[1]
-set_location_assignment PIN_P14 -to tty_dtr
-set_location_assignment PIN_P16 -to "hdmi_d[2](n)"
-set_location_assignment PIN_R1 -to abc_xmemw80_n
+set_location_assignment PIN_R8 -to exth_hh
+set_location_assignment PIN_T8 -to abc_clk
+set_location_assignment PIN_N3 -to abc_xmemfl_n
+set_location_assignment PIN_P3 -to abc_d[0]
 set_location_assignment PIN_R3 -to abc_d[4]
-set_location_assignment PIN_R4 -to abc_d[6]
-set_location_assignment PIN_R5 -to abc_d_ce_n
-set_location_assignment PIN_R6 -to abc_resin_x
-set_location_assignment PIN_R7 -to gpio[5]
-set_location_assignment PIN_R8 -to xabc_op[0]
-set_location_assignment PIN_R10 -to gpio[3]
-set_location_assignment PIN_R11 -to xabc_nmi_n
-set_location_assignment PIN_R12 -to xabc_gpio[1]
-set_location_assignment PIN_R13 -to hdmi_sda
-set_location_assignment PIN_R14 -to led[2]
-set_location_assignment PIN_R16 -to hdmi_d[2]
-set_location_assignment PIN_T2 -to abc_d[3]
 set_location_assignment PIN_T3 -to abc_d[5]
+set_location_assignment PIN_T2 -to abc_d[3]
+set_location_assignment PIN_R4 -to abc_d[6]
 set_location_assignment PIN_T4 -to abc_d[7]
-set_location_assignment PIN_T5 -to abc_d_oe
-set_location_assignment PIN_T6 -to gpio[2]
-set_location_assignment PIN_T7 -to gpio[4]
-set_location_assignment PIN_T8 -to abc_clk
-set_location_assignment PIN_T9 -to xabc_op[1]
+set_location_assignment PIN_N5 -to abc_d[2]
+set_location_assignment PIN_N6 -to spi_cs_flash_n
+set_location_assignment PIN_M11 -to hdmi_scl
+set_location_assignment PIN_T13 -to led[1]
+set_location_assignment PIN_N9 -to exth_hb
+set_location_assignment PIN_T9 -to exth_hc
+set_location_assignment PIN_R10 -to gpio[3]
 set_location_assignment PIN_T10 -to abc_master
-set_location_assignment PIN_T11 -to xabc_gpio[0]
+set_location_assignment PIN_R11 -to exth_hd
+set_location_assignment PIN_T11 -to exth_hf
+set_location_assignment PIN_R12 -to exth_he
 set_location_assignment PIN_T12 -to abc_xinpstb_n
-set_location_assignment PIN_T13 -to led[1]
+set_location_assignment PIN_L10 -to abc_xoutpstb_n
+set_location_assignment PIN_P9 -to gpio[1]
+set_location_assignment PIN_N12 -to exth_ha
+set_location_assignment PIN_N11 -to exth_hg
+set_location_assignment PIN_R13 -to hdmi_sda
 set_location_assignment PIN_T14 -to led[3]
 set_location_assignment PIN_T15 -to hdmi_hpd
+set_location_assignment PIN_M10 -to sd_dat[1]
+set_location_assignment PIN_P14 -to tty_dtr
+set_location_assignment PIN_R14 -to led[2]
+set_location_assignment PIN_R16 -to hdmi_d[2]
+set_location_assignment PIN_N15 -to hdmi_d[1]
+set_location_assignment PIN_K15 -to hdmi_d[0]
+set_location_assignment PIN_J15 -to hdmi_clk
+set_location_assignment PIN_M15 -to clock_48
+set_location_assignment PIN_E16 -to tty_txd
+set_location_assignment PIN_E15 -to rtc_32khz
+set_location_assignment PIN_G16 -to sd_cmd
+set_location_assignment PIN_G15 -to sd_clk
+set_location_assignment PIN_F13 -to tty_rxd
+set_location_assignment PIN_F16 -to sd_dat[3]
+set_location_assignment PIN_F15 -to sd_dat[0]
+set_location_assignment PIN_B16 -to rtc_int_n
+set_location_assignment PIN_F14 -to sd_dat[2]
+set_location_assignment PIN_D16 -to tty_rts
+set_location_assignment PIN_D15 -to tty_cts
+set_location_assignment PIN_C16 -to i2c_scl
+set_location_assignment PIN_C15 -to i2c_sda
+set_location_assignment PIN_D12 -to sr_cs_n
+set_location_assignment PIN_C11 -to sr_dq[3]
+set_location_assignment PIN_C14 -to sr_a[10]
+set_location_assignment PIN_B13 -to sr_ba[1]
+set_location_assignment PIN_D14 -to sr_a[2]
+set_location_assignment PIN_A14 -to sr_a[0]
+set_location_assignment PIN_D11 -to sr_dq[2]
+set_location_assignment PIN_B14 -to sr_a[1]
+set_location_assignment PIN_E11 -to sr_dq[1]
+set_location_assignment PIN_E10 -to sr_dqm[0]
+set_location_assignment PIN_A12 -to sr_dq[0]
+set_location_assignment PIN_B12 -to sr_ras_n
+set_location_assignment PIN_A11 -to sr_dq[5]
+set_location_assignment PIN_B11 -to sr_dq[4]
+set_location_assignment PIN_A13 -to sr_ba[0]
+set_location_assignment PIN_A15 -to sr_a[3]
+set_location_assignment PIN_F9 -to sr_we_n
+set_location_assignment PIN_A10 -to sr_dq[7]
+set_location_assignment PIN_B10 -to sr_dq[6]
+set_location_assignment PIN_C9 -to sr_a[4]
+set_location_assignment PIN_D9 -to sr_a[5]
+set_location_assignment PIN_E9 -to sr_cas_n
+set_location_assignment PIN_A9 -to abc_a[2]
+set_location_assignment PIN_D8 -to sr_dqm[1]
+set_location_assignment PIN_E8 -to sr_a[6]
+set_location_assignment PIN_A8 -to abc_a[0]
+set_location_assignment PIN_F8 -to sr_cke
+set_location_assignment PIN_B8 -to abc_a[1]
+set_location_assignment PIN_A7 -to sr_a[7]
+set_location_assignment PIN_C8 -to sr_a[11]
+set_location_assignment PIN_B7 -to sr_a[8]
+set_location_assignment PIN_C6 -to sr_dq[14]
+set_location_assignment PIN_A6 -to sr_a[9]
+set_location_assignment PIN_B6 -to sr_a[12]
+set_location_assignment PIN_E7 -to sr_dq[9]
+set_location_assignment PIN_E6 -to sr_dq[12]
+set_location_assignment PIN_A5 -to sr_dq[8]
+set_location_assignment PIN_B5 -to sr_dq[10]
+set_location_assignment PIN_D6 -to sr_dq[13]
+set_location_assignment PIN_A4 -to sr_dq[11]
+set_location_assignment PIN_B4 -to abc_rdy_x
+set_location_assignment PIN_A2 -to abc_int800_x
+set_location_assignment PIN_D5 -to sr_dq[15]
+set_location_assignment PIN_A3 -to abc_nmi_x
+set_location_assignment PIN_B3 -to abc_int80_x
+set_location_assignment PIN_D3 -to sr_clk
 
-
-set_global_assignment -name VERILOG_FILE syncho.v
-set_global_assignment -name VERILOG_FILE ip/hdmitx.v
-set_global_assignment -name VERILOG_FILE ip/pll.v
-set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
-set_global_assignment -name SDC_FILE max80.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

max80.sv

@@ -10,94 +10,106 @@
 
 module max80 (
 	      // Clock oscillator
-	      input 	    clock_48, // 48 MHz
+	      input	    clock_48, // 48 MHz
 
 	      // ABC-bus
-	      input 	    abc_clk, // ABC-bus 3 MHz clock
+	      input	    abc_clk, // ABC-bus 3 MHz clock
 	      input [15:0]  abc_a, // ABC address bus
 	      inout [7:0]   abc_d, // ABC data bus
-	      output 	    abc_d_oe, // Data bus output enable
-	      input 	    abc_rst_n, // ABC bus reset strobe
-	      input 	    abc_cs_n, // ABC card select strobe
+	      output	    abc_d_oe, // Data bus output enable
+	      input	    abc_rst_n, // ABC bus reset strobe
+	      input	    abc_cs_n, // ABC card select strobe
 	      input [4:0]   abc_out_n, // OUT, C1-C4 strobe
 	      input [1:0]   abc_inp_n, // INP, STATUS strobe
-	      input 	    abc_xmemfl_n, // Memory read strobe
-	      input 	    abc_xmemw800_n, // Memory write strobe (ABC800)
-	      input 	    abc_xmemw80_n, // Memory write strobe (ABC80)
-	      input 	    abc_xinpstb_n, // I/O read strobe (ABC800)
-	      input 	    abc_xoutpstb_n, // I/O write strobe (ABC80)
+	      input	    abc_xmemfl_n, // Memory read strobe
+	      input	    abc_xmemw800_n, // Memory write strobe (ABC800)
+	      input	    abc_xmemw80_n, // Memory write strobe (ABC80)
+	      input	    abc_xinpstb_n, // I/O read strobe (ABC800)
+	      input	    abc_xoutpstb_n, // I/O write strobe (ABC80)
 	      // The following are inverted versus the bus IF
 	      // the corresponding MOSFETs are installed
-	      output 	    abc_rdy_x, // RDY = WAIT#
-	      output 	    abc_resin_x, // System reset request
-	      output 	    abc_int80_x, // System INT request (ABC80)
-	      output 	    abc_int800_x, // System INT request (ABC800)
-	      output 	    abc_nmi_x, // System NMI request (ABC800)
-	      output 	    abc_xm_x, // System memory override (ABC800)
+	      output	    abc_rdy_x, // RDY = WAIT#
+	      output	    abc_resin_x, // System reset request
+	      output	    abc_int80_x, // System INT request (ABC80)
+	      output	    abc_int800_x, // System INT request (ABC800)
+	      output	    abc_nmi_x, // System NMI request (ABC800)
+	      output	    abc_xm_x, // System memory override (ABC800)
 	      // Master/slave control
-	      output 	    abc_master, // 1 = master, 0 = slave
-	      output 	    abc_a_oe,
+	      output	    abc_master, // 1 = master, 0 = slave
+	      output	    abc_a_oe,
 	      // Bus isolation
-	      output 	    abc_d_ce_n,
+	      output	    abc_d_ce_n,
+
+	      // ABC-bus extension header
+	      // (Note: cannot use an array here because HC and HH are
+	      // input only.)
+	      inout	    exth_ha,
+	      inout	    exth_hb,
+	      input	    exth_hc,
+	      inout	    exth_hd,
+	      inout	    exth_he,
+	      inout	    exth_hf,
+	      inout	    exth_hg,
+	      input	    exth_hh,
 
 	      // SDRAM bus
-	      output 	    sr_clk,
-	      output 	    sr_cke,
+	      output	    sr_clk,
+	      output	    sr_cke,
 	      output [1:0]  sr_ba, // Bank address
 	      output [12:0] sr_a, // Address within bank
 	      inout [15:0]  sr_dq, // Also known as D or IO
 	      output [1:0]  sr_dqm, // DQML and DQMH
-	      output 	    sr_cs_n,
-	      output 	    sr_we_n,
-	      output 	    sr_cas_n,
-	      output 	    sr_ras_n,
+	      output	    sr_cs_n,
+	      output	    sr_we_n,
+	      output	    sr_cas_n,
+	      output	    sr_ras_n,
 
 	      // SD card
-	      output 	    sd_clk,
-	      output 	    sd_cmd,
+	      output	    sd_clk,
+	      output	    sd_cmd,
 	      inout [3:0]   sd_dat,
 
 	      // USB serial (naming is FPGA as DCE)
-	      input 	    tty_txd,
-	      output 	    tty_rxd,
-	      input 	    tty_rts,
-	      output 	    tty_cts,
-	      input 	    tty_dtr,
+	      input	    tty_txd,
+	      output	    tty_rxd,
+	      input	    tty_rts,
+	      output	    tty_cts,
+	      input	    tty_dtr,
 
 	      // SPI flash memory (also configuration)
-	      output 	    flash_cs_n,
-	      output 	    flash_clk,
-	      output 	    flash_mosi,
-	      input 	    flash_miso,
-	      
+	      output	    flash_cs_n,
+	      output	    flash_clk,
+	      output	    flash_mosi,
+	      input	    flash_miso,
+
 	      // SPI bus (connected to ESP32 so can be bidirectional)
-	      inout 	    spi_clk,
-	      inout 	    spi_miso,
-	      inout 	    spi_mosi,
-	      inout 	    spi_cs_esp_n, // ESP32 IO10
+	      inout	    spi_clk,
+	      inout	    spi_miso,
+	      inout	    spi_mosi,
+	      inout	    spi_cs_esp_n, // ESP32 IO10
 
 	      // Other ESP32 connections
-	      inout 	    esp_io0, // ESP32 IO00
-	      inout 	    esp_int, // ESP32 IO09
+	      inout	    esp_io0, // ESP32 IO00
+	      inout	    esp_int, // ESP32 IO09
 
 	      // I2C bus (RTC and external)
-	      inout 	    i2c_scl,
-	      inout 	    i2c_sda,
-	      input 	    rtc_32khz,
-	      input 	    rtc_int_n,
-	      
+	      inout	    i2c_scl,
+	      inout	    i2c_sda,
+	      input	    rtc_32khz,
+	      input	    rtc_int_n,
+
 	      // LED
 	      output [3:1]  led,
-	      
+
 	      // GPIO pins
 	      inout [5:0]   gpio,
 
 	      // HDMI
 	      output [2:0]  hdmi_d,
-	      output 	    hdmi_clk,
-	      inout 	    hdmi_scl,
-	      inout 	    hdmi_sda,
-	      inout 	    hdmi_hpd
+	      output	    hdmi_clk,
+	      inout	    hdmi_scl,
+	      inout	    hdmi_sda,
+	      inout	    hdmi_hpd
 	      );
 
    // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
@@ -107,11 +119,11 @@ module max80 (
    // PLL and reset
    parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
    reg [reset_pow2-1:0]     rst_ctr = 1'b0;
-   reg 			    rst_n   = 1'b0;   // Internal reset
-   wire 		    pll_locked;
-   wire 		    clk; // System clock
-   wire 		    vid_clk;
-   
+   reg			    rst_n   = 1'b0;   // Internal reset
+   wire			    pll_locked;
+   wire			    clk; // System clock
+   wire			    vid_clk;
+
    pll pll (
 	    .areset ( 1'b0 ),
 	    .inclk0 ( clock_48 ),
@@ -136,12 +148,12 @@ module max80 (
        begin
 	  { rst_n, rst_ctr } <= rst_ctr + 1'b1;
        end
-   
+
    // Unused device stubs - remove when used
 
    // HDMI - generate random data to give Quartus something to do
    reg [23:0] dummydata = 30'hc8_fb87;
-   
+
    always @(posedge vid_clk)
      dummydata <= { dummydata[22:0], dummydata[23] };
 
@@ -182,7 +194,7 @@ module max80 (
       .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
       .q ( hdmi_to_tx )
       );
-   
+
    hdmitx hdmitx (
 		  .pll_areset ( 1'b0 ),
 		  .tx_in ( hdmi_to_tx ),
@@ -191,7 +203,7 @@ module max80 (
 		  .tx_out ( hdmi_d ),
 		  .tx_outclock ( hdmi_clk )
 		  );
-   
+
    // ABC bus
 
    // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
@@ -207,7 +219,7 @@ module max80 (
    // I/O read/write strobes
    wire abc_iord = (abc800 & ~abc_xinpstb_n)  | ~(|abc_inp_n);
    wire abc_iowr = (abc800 & ~abc_xoutpstb_n) | ~(|abc_out_n);
-   
+
    // Open drain signals with optional MOSFETs
    wire abc_wait;
    wire abc_resin;
@@ -229,6 +241,53 @@ module max80 (
    assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
    assign abc_xm_x     = opt_mosfet(abc_xm, mosfet_installed[6]);
 
+   // ABC-bus extension header (exth_c and exth_h are input only)
+   // The naming of pins is kind of nonsensical:
+   //
+   //       +3V3 -  1  2 - +3V3
+   //         HA -  3  4 - HE
+   //         HB -  5  6 - HG
+   //         HC -  7  8 - HH
+   //         HD -  9 10 - HF
+   //        GND - 11 12 - GND
+   //
+   // This layout allows the header to be connected on either side
+   // of the board. This logic assigns the following names to the pins;
+   // if the ext_reversed is set to 1 then the left and right sides
+   // are flipped.
+   //
+   //      +3V3  -  1  2 - +3V3
+   //    exth[0] -  3  4 - exth[1]
+   //    exth[2] -  5  6 - exth[3]
+   //    exth[6] -  7  8 - exth[7]
+   //    exth[4] -  9 10 - exth[5]
+   //        GND - 11 12 - GND
+
+   wire exth_reversed = 1'b0;
+   wire [7:0] exth_d;	// Input data
+   wire [5:0] exth_q;	// Output data
+   wire [5:0] exth_oe;	// Output enable
+
+   assign exth_d[0]    = exth_reversed ? exth_he : exth_ha;
+   assign exth_d[1]    = exth_reversed ? exth_ha : exth_he;
+   assign exth_d[2]    = exth_reversed ? exth_hg : exth_hb;
+   assign exth_d[3]    = exth_reversed ? exth_hb : exth_hg;
+   assign exth_d[4]    = exth_reversed ? exth_hf : exth_hd;
+   assign exth_d[5]    = exth_reversed ? exth_hd : exth_hf;
+   assign exth_d[6]    = exth_reversed ? exth_hh : exth_hc;
+   assign exth_d[7]    = exth_reversed ? exth_hc : exth_hh;
+
+   wire [2:0] erx      = { 2'b00, exth_reversed };
+   assign exth_ha      = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
+   assign exth_he      = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
+   assign exth_hb      = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
+   assign exth_hg      = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
+   assign exth_hd      = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
+   assign exth_hf      = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;
+
+   assign exth_q  = 6'b0;
+   assign exth_oe = 6'b0;
+
    // LED blink counter
    reg [28:0] led_ctr;
 
@@ -239,7 +298,7 @@ module max80 (
        led_ctr <= led_ctr + 1'b1;
 
    assign led = led_ctr[28:26];
-   
+
    // SDRAM bus
    assign sr_cke    = 1'b0;
    assign sr_ba     = 2'b0;
@@ -270,7 +329,7 @@ module max80 (
    // ESP32
    assign esp_io0  = 1'bz;
    assign esp_int  = 1'bz;
-   
+
    // I2C
    assign i2c_scl = 1'bz;
    assign i2c_sda = 1'bz;
@@ -279,4 +338,3 @@ module max80 (
    assign gpio    = 6'bzzzzzz;
 
 endmodule
-	      

max80_assignment_defaults.qdf

@@ -0,0 +1,808 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 17:03:47  August 06, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL Enable
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

output_files/max80.asm.rpt

@@ -1,6 +1,6 @@
 Assembler report for max80
-Sun Aug  1 07:28:07 2021
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fri Aug  6 17:56:43 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
 ---------------------
@@ -12,14 +12,15 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
   4. Assembler Generated Files
   5. Assembler Device Options: max80.sof
   6. Assembler Device Options: max80.jbc
-  7. Assembler Messages
+  7. Assembler Device Options: max80.pof
+  8. Assembler Messages
 
 
 
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2020  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@@ -39,7 +40,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Sun Aug  1 07:28:07 2021 ;
+; Assembler Status      ; Successful - Fri Aug  6 17:56:43 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -61,6 +62,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------------------+
 ; /home/hpa/abc80/max80/blinktest/output_files/max80.sof ;
 ; /home/hpa/abc80/max80/blinktest/output_files/max80.jbc ;
+; /home/hpa/abc80/max80/blinktest/output_files/max80.pof ;
 +--------------------------------------------------------+
 
 
@@ -69,8 +71,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------+--------------------+
 ; Option         ; Setting            ;
 +----------------+--------------------+
-; JTAG usercode  ; 0x0010EA95         ;
-; Checksum       ; 0x0010EA95         ;
+; JTAG usercode  ; 0x0010CB6C         ;
+; Checksum       ; 0x0010CB6C         ;
 +----------------+--------------------+
 
 
@@ -83,13 +85,24 @@ https://fpgasoftware.intel.com/eula.
 +-----------------------+-------------+
 
 
++-------------------------------------+
+; Assembler Device Options: max80.pof ;
++--------------------+----------------+
+; Option             ; Setting        ;
++--------------------+----------------+
+; JTAG usercode      ; 0x00000000     ;
+; Checksum           ; 0xFCE38EFD     ;
+; Compression Ratio  ; 3              ;
++--------------------+----------------+
+
+
 +--------------------+
 ; Assembler Messages ;
 +--------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
-    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Sun Aug  1 07:28:06 2021
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Fri Aug  6 17:56:41 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -97,9 +110,9 @@ Info (115030): Assembler is generating device programming files
 Info (210117): Created JAM or JBC file for the specified chain: 
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 905 megabytes
-    Info: Processing ended: Sun Aug  1 07:28:07 2021
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 569 megabytes
+    Info: Processing ended: Fri Aug  6 17:56:43 2021
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 
 

output_files/max80.done

@@ -1 +1 @@
-Sun Aug  1 07:28:14 2021
+Fri Aug  6 17:56:48 2021

output_files/max80.eda.rpt

@@ -1,6 +1,6 @@
 EDA Netlist Writer report for max80
-Sun Aug  1 07:28:13 2021
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fri Aug  6 17:56:47 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
 ---------------------
@@ -17,7 +17,7 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2020  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Sun Aug  1 07:28:13 2021 ;
+; EDA Netlist Writer Status ; Successful - Fri Aug  6 17:56:47 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -83,15 +83,15 @@ https://fpgasoftware.intel.com/eula.
 +-----------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
-    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Sun Aug  1 07:28:13 2021
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Fri Aug  6 17:56:47 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 1125 megabytes
-    Info: Processing ended: Sun Aug  1 07:28:13 2021
+    Info: Peak virtual memory: 816 megabytes
+    Info: Processing ended: Fri Aug  6 17:56:47 2021
     Info: Elapsed time: 00:00:00
     Info: Total CPU time (on all processors): 00:00:00
 

output_files/max80.fit.summary

@@ -1,15 +1,15 @@
-Fitter Status : Successful - Sun Aug  1 07:28:05 2021
-Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fitter Status : Successful - Fri Aug  6 17:56:41 2021
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
 Device : EP4CE15F17C8
 Timing Models : Final
-Total logic elements : 329 / 15,408 ( 2 % )
+Total logic elements : 327 / 15,408 ( 2 % )
     Total combinational functions : 278 / 15,408 ( 2 % )
     Dedicated logic registers : 218 / 15,408 ( 1 % )
 Total registers : 229
-Total pins : 134 / 166 ( 81 % )
+Total pins : 142 / 166 ( 86 % )
 Total virtual pins : 0
 Total memory bits : 0 / 516,096 ( 0 % )
 Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )

output_files/max80.flow.rpt

@@ -1,6 +1,6 @@
 Flow report for max80
-Sun Aug  1 07:28:13 2021
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fri Aug  6 17:56:47 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
 ---------------------
@@ -21,7 +21,7 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2020  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@@ -41,18 +41,18 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Sun Aug  1 07:28:13 2021       ;
-; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Flow Status                        ; Successful - Fri Aug  6 17:56:47 2021       ;
+; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
 ; Family                             ; Cyclone IV E                                ;
 ; Device                             ; EP4CE15F17C8                                ;
 ; Timing Models                      ; Final                                       ;
-; Total logic elements               ; 329 / 15,408 ( 2 % )                        ;
+; Total logic elements               ; 327 / 15,408 ( 2 % )                        ;
 ;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
 ;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
 ; Total registers                    ; 229                                         ;
-; Total pins                         ; 134 / 166 ( 81 % )                          ;
+; Total pins                         ; 142 / 166 ( 86 % )                          ;
 ; Total virtual pins                 ; 0                                           ;
 ; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
 ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 08/01/2021 07:27:43 ;
+; Start date & time ; 08/06/2021 17:56:30 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 180546899331588.162782806355872        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 195769225774250.162829779033027        ; --            ; --          ; --                                ;
 ; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
@@ -129,28 +129,28 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:13     ; 1.0                     ; 1035 MB             ; 00:00:28                           ;
-; Fitter               ; 00:00:09     ; 1.0                     ; 1340 MB             ; 00:00:09                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 905 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1264 MB             ; 00:00:02                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 894 MB              ; 00:00:02                           ;
-; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 1125 MB             ; 00:00:00                           ;
-; Total                ; 00:00:27     ; --                      ; --                  ; 00:00:43                           ;
+; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 677 MB              ; 00:00:15                           ;
+; Fitter               ; 00:00:06     ; 1.0                     ; 1488 MB             ; 00:00:07                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
+; Power Analyzer       ; 00:00:01     ; 1.0                     ; 1022 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 732 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 816 MB              ; 00:00:00                           ;
+; Total                ; 00:00:15     ; --                      ; --                  ; 00:00:26                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
-+---------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                             ;
-+----------------------+-------------------------+-------------+-------------+----------------+
-; Module Name          ; Machine Hostname        ; OS Name     ; OS Version  ; Processor type ;
-+----------------------+-------------------------+-------------+-------------+----------------+
-; Analysis & Synthesis ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-; Fitter               ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-; Assembler            ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-; Power Analyzer       ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-; Timing Analyzer      ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-; EDA Netlist Writer   ; carbon-x1.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
-+----------------------+-------------------------+-------------+-------------+----------------+
++-------------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                           ;
++----------------------+-----------------------+-------------+-------------+----------------+
+; Module Name          ; Machine Hostname      ; OS Name     ; OS Version  ; Processor type ;
++----------------------+-----------------------+-------------+-------------+----------------+
+; Analysis & Synthesis ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Fitter               ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Assembler            ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Power Analyzer       ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; Timing Analyzer      ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+; EDA Netlist Writer   ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
++----------------------+-----------------------+-------------+-------------+----------------+
 
 
 ------------

output_files/max80.map.rpt

@@ -1,6 +1,6 @@
 Analysis & Synthesis report for max80
-Sun Aug  1 07:27:55 2021
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fri Aug  6 17:56:35 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
 ---------------------
@@ -47,7 +47,7 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2020  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Sun Aug  1 07:27:55 2021       ;
-; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Analysis & Synthesis Status        ; Successful - Fri Aug  6 17:56:35 2021       ;
+; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
 ; Family                             ; Cyclone IV E                                ;
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 ;     Total combinational functions  ; 274                                         ;
 ;     Dedicated logic registers      ; 218                                         ;
 ; Total registers                    ; 226                                         ;
-; Total pins                         ; 130                                         ;
+; Total pins                         ; 138                                         ;
 ; Total virtual pins                 ; 0                                           ;
 ; Total memory bits                  ; 0                                           ;
 ; Embedded Multiplier 9-bit elements ; 0                                           ;
@@ -177,15 +177,15 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+
 ; Processors                 ; Number      ;
 +----------------------------+-------------+
-; Number detected on machine ; 4           ;
-; Maximum allowed            ; 2           ;
+; Number detected on machine ; 16          ;
+; Maximum allowed            ; 8           ;
 ;                            ;             ;
 ; Average used               ; 1.00        ;
-; Maximum used               ; 2           ;
+; Maximum used               ; 8           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
+;     Processors 2-8         ;   0.0%      ;
 +----------------------------+-------------+
 
 
@@ -198,20 +198,20 @@ https://fpgasoftware.intel.com/eula.
 ; ip/pll.v                         ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/pll.v                                        ;         ;
 ; transpose.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/transpose.sv                                    ;         ;
 ; max80.sv                         ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/max80.sv                                        ;         ;
-; altpll.tdf                       ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf                     ;         ;
-; aglobal181.inc                   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/aglobal181.inc                 ;         ;
-; stratix_pll.inc                  ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_pll.inc                ;         ;
-; stratixii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_pll.inc              ;         ;
-; cycloneii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc              ;         ;
+; altpll.tdf                       ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altpll.tdf                     ;         ;
+; aglobal201.inc                   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/aglobal201.inc                 ;         ;
+; stratix_pll.inc                  ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratix_pll.inc                ;         ;
+; stratixii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_pll.inc              ;         ;
+; cycloneii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/cycloneii_pll.inc              ;         ;
 ; db/pll_altpll.v                  ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/pll_altpll.v                                 ;         ;
 ; tmdsenc.v                        ; yes             ; Auto-Found Verilog HDL File  ; /home/hpa/abc80/max80/blinktest/tmdsenc.v                                       ;         ;
-; altlvds_tx.tdf                   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf                 ;         ;
-; stratix_lvds_transmitter.inc     ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc   ;         ;
-; stratixii_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ;         ;
-; stratixgx_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_lvds_transmitter.inc ;         ;
-; stratixgx_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixgx_pll.inc              ;         ;
-; stratixii_clkctrl.inc            ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratixii_clkctrl.inc          ;         ;
-; altddio_out.inc                  ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altddio_out.inc                ;         ;
+; altlvds_tx.tdf                   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altlvds_tx.tdf                 ;         ;
+; stratix_lvds_transmitter.inc     ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc   ;         ;
+; stratixii_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ;         ;
+; stratixgx_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixgx_lvds_transmitter.inc ;         ;
+; stratixgx_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixgx_pll.inc              ;         ;
+; stratixii_clkctrl.inc            ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_clkctrl.inc          ;         ;
+; altddio_out.inc                  ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altddio_out.inc                ;         ;
 ; db/hdmitx_lvds_tx.v              ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v                             ;         ;
 +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
 
@@ -237,7 +237,7 @@ https://fpgasoftware.intel.com/eula.
 ;     -- Dedicated logic registers            ; 218                                                                                    ;
 ;     -- I/O registers                        ; 16                                                                                     ;
 ;                                             ;                                                                                        ;
-; I/O pins                                    ; 130                                                                                    ;
+; I/O pins                                    ; 138                                                                                    ;
 ;                                             ;                                                                                        ;
 ; Embedded Multiplier 9-bit elements          ; 0                                                                                      ;
 ;                                             ;                                                                                        ;
@@ -246,8 +246,8 @@ https://fpgasoftware.intel.com/eula.
 ;                                             ;                                                                                        ;
 ; Maximum fan-out node                        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
 ; Maximum fan-out                             ; 114                                                                                    ;
-; Total fan-out                               ; 1566                                                                                   ;
-; Average fan-out                             ; 1.94                                                                                   ;
+; Total fan-out                               ; 1580                                                                                   ;
+; Average fan-out                             ; 1.91                                                                                   ;
 +---------------------------------------------+----------------------------------------------------------------------------------------+
 
 
@@ -256,7 +256,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
 ; Compilation Hierarchy Node                                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
-; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 130  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
+; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 138  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
 ;    |hdmitx:hdmitx|                                           ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
 ;       |altlvds_tx:ALTLVDS_TX_component|                      ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
 ;          |hdmitx_lvds_tx:auto_generated|                     ; 78 (20)             ; 109 (60)                  ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
@@ -409,8 +409,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
 ; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[4] ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[1] ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[6] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[2] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[4] ;
 ; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[5] ;
 ; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[5] ;
 ; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[7] ;
@@ -1051,7 +1051,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 +-----------------------+-----------------------------+
 ; Type                  ; Count                       ;
 +-----------------------+-----------------------------+
-; boundary_port         ; 130                         ;
+; boundary_port         ; 138                         ;
 ; cycloneiii_ddio_out   ; 4                           ;
 ; cycloneiii_ff         ; 218                         ;
 ;     CLR               ; 46                          ;
@@ -1060,7 +1060,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 ;     ENA               ; 27                          ;
 ;     ENA CLR           ; 12                          ;
 ;     plain             ; 106                         ;
-; cycloneiii_io_obuf    ; 51                          ;
+; cycloneiii_io_obuf    ; 57                          ;
 ; cycloneiii_lcell_comb ; 278                         ;
 ;     arith             ; 56                          ;
 ;         2 data inputs ; 39                          ;
@@ -1074,7 +1074,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 ; cycloneiii_pll        ; 2                           ;
 ;                       ;                             ;
 ; Max LUT depth         ; 7.20                        ;
-; Average LUT depth     ; 2.84                        ;
+; Average LUT depth     ; 2.82                        ;
 +-----------------------+-----------------------------+
 
 
@@ -1083,7 +1083,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 +----------------+--------------+
 ; Partition Name ; Elapsed Time ;
 +----------------+--------------+
-; Top            ; 00:00:01     ;
+; Top            ; 00:00:00     ;
 +----------------+--------------+
 
 
@@ -1092,11 +1092,11 @@ Note: In order to hide this table in the UI and the text report file, please set
 +-------------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Sun Aug  1 07:27:42 2021
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Fri Aug  6 17:56:30 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
 Warning (12019): Can't analyze file -- file syncho.v is missing
 Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
     Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
@@ -1108,67 +1108,76 @@ Info (12021): Found 3 design units, including 3 entities, in source file transpo
     Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
 Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
     Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
-Warning (10236): Verilog HDL Implicit Net warning at max80.sv(172): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
-Warning (10236): Verilog HDL Implicit Net warning at max80.sv(268): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
+Warning (10236): Verilog HDL Implicit Net warning at max80.sv(184): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
+Warning (10236): Verilog HDL Implicit Net warning at max80.sv(327): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 327
 Info (12127): Elaborating entity "max80" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(172): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(268): object "spi_cs_flash_n" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(204): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 204
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(205): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 205
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(208): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 208
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(209): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 209
-Warning (10858): Verilog HDL warning at max80.sv(212): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
-Warning (10858): Verilog HDL warning at max80.sv(213): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
-Warning (10858): Verilog HDL warning at max80.sv(214): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
-Warning (10858): Verilog HDL warning at max80.sv(215): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
-Warning (10858): Verilog HDL warning at max80.sv(216): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
-Warning (10230): Verilog HDL assignment warning at max80.sv(143): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 143
-Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(239): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 239
-Warning (10030): Net "abc_wait" at max80.sv(212) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 212
-Warning (10030): Net "abc_resin" at max80.sv(213) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 213
-Warning (10030): Net "abc_int" at max80.sv(214) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 214
-Warning (10030): Net "abc_nmi" at max80.sv(215) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 215
-Warning (10030): Net "abc_xm" at max80.sv(216) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(184): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(327): object "spi_cs_flash_n" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 327
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(216): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(217): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 217
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(220): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 220
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(221): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 221
+Warning (10858): Verilog HDL warning at max80.sv(224): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 224
+Warning (10858): Verilog HDL warning at max80.sv(225): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
+Warning (10858): Verilog HDL warning at max80.sv(226): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
+Warning (10858): Verilog HDL warning at max80.sv(227): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
+Warning (10858): Verilog HDL warning at max80.sv(228): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(267): object "exth_d" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 267
+Warning (10230): Verilog HDL assignment warning at max80.sv(155): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 155
+Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(298): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 298
+Warning (10030): Net "abc_wait" at max80.sv(224) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 224
+Warning (10030): Net "abc_resin" at max80.sv(225) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
+Warning (10030): Net "abc_int" at max80.sv(226) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
+Warning (10030): Net "abc_nmi" at max80.sv(227) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
+Warning (10030): Net "abc_xm" at max80.sv(228) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
 Warning (10034): Output port "abc_d_oe" at max80.sv(19) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
 Warning (10034): Output port "abc_master" at max80.sv(38) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
 Warning (10034): Output port "abc_a_oe" at max80.sv(39) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
 Warning (10034): Output port "abc_d_ce_n" at max80.sv(41) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
-Warning (10034): Output port "flash_cs_n" at max80.sv(68) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
-Warning (10034): Output port "flash_clk" at max80.sv(69) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
-Warning (10034): Output port "flash_mosi" at max80.sv(70) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
+Warning (10034): Output port "flash_cs_n" at max80.sv(80) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
+Warning (10034): Output port "flash_clk" at max80.sv(81) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
+Warning (10034): Output port "flash_mosi" at max80.sv(82) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 82
 Warning (10862): input port "abc_a" at max80.sv(17) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
 Warning (10863): bidir port "abc_d" at max80.sv(18) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
 Warning (10862): bidir port "abc_d" at max80.sv(18) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
 Warning (10862): input port "abc_out_n" at max80.sv(22) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
 Warning (10862): input port "abc_inp_n" at max80.sv(23) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
-Warning (10862): bidir port "sr_dq" at max80.sv(48) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-Warning (10862): bidir port "sd_dat" at max80.sv(58) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
-Warning (10862): bidir port "gpio" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+Warning (10862): bidir port "sr_dq" at max80.sv(60) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+Warning (10862): bidir port "sd_dat" at max80.sv(70) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
+Warning (10862): bidir port "gpio" at max80.sv(105) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 105
 Warning (10862): input port "abc_clk" at max80.sv(16) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
 Warning (10862): input port "abc_rst_n" at max80.sv(20) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
 Warning (10862): input port "abc_cs_n" at max80.sv(21) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
 Warning (10862): input port "abc_xmemfl_n" at max80.sv(24) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
 Warning (10862): input port "abc_xmemw800_n" at max80.sv(25) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
 Warning (10862): input port "abc_xmemw80_n" at max80.sv(26) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
-Warning (10862): input port "tty_txd" at max80.sv(61) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
-Warning (10862): input port "tty_rts" at max80.sv(63) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
-Warning (10862): input port "tty_dtr" at max80.sv(65) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
-Warning (10862): input port "flash_miso" at max80.sv(71) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
-Warning (10862): bidir port "spi_clk" at max80.sv(74) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
-Warning (10862): bidir port "spi_miso" at max80.sv(75) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
-Warning (10862): bidir port "spi_mosi" at max80.sv(76) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
-Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(77) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
-Warning (10862): bidir port "esp_io0" at max80.sv(80) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
-Warning (10862): bidir port "esp_int" at max80.sv(81) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
-Warning (10862): bidir port "i2c_scl" at max80.sv(84) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 84
-Warning (10862): bidir port "i2c_sda" at max80.sv(85) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 85
-Warning (10862): input port "rtc_32khz" at max80.sv(86) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
-Warning (10862): input port "rtc_int_n" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
-Warning (10862): bidir port "hdmi_scl" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
-Warning (10863): bidir port "hdmi_sda" at max80.sv(99) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
-Warning (10862): bidir port "hdmi_sda" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
-Warning (10862): bidir port "hdmi_hpd" at max80.sv(101) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
-Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 127
+Warning (10862): bidir port "exth_ha" at max80.sv(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
+Warning (10862): bidir port "exth_hb" at max80.sv(47) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
+Warning (10862): input port "exth_hc" at max80.sv(48) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+Warning (10862): bidir port "exth_hd" at max80.sv(49) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
+Warning (10862): bidir port "exth_he" at max80.sv(50) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
+Warning (10862): bidir port "exth_hf" at max80.sv(51) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
+Warning (10862): bidir port "exth_hg" at max80.sv(52) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
+Warning (10862): input port "exth_hh" at max80.sv(53) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
+Warning (10862): input port "tty_txd" at max80.sv(73) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
+Warning (10862): input port "tty_rts" at max80.sv(75) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
+Warning (10862): input port "tty_dtr" at max80.sv(77) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
+Warning (10862): input port "flash_miso" at max80.sv(83) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
+Warning (10862): bidir port "spi_clk" at max80.sv(86) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
+Warning (10862): bidir port "spi_miso" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
+Warning (10862): bidir port "spi_mosi" at max80.sv(88) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
+Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
+Warning (10862): bidir port "esp_io0" at max80.sv(92) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 92
+Warning (10862): bidir port "esp_int" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+Warning (10862): bidir port "i2c_scl" at max80.sv(96) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 96
+Warning (10862): bidir port "i2c_sda" at max80.sv(97) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
+Warning (10862): input port "rtc_32khz" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+Warning (10862): input port "rtc_int_n" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Warning (10862): bidir port "hdmi_scl" at max80.sv(110) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
+Warning (10863): bidir port "hdmi_sda" at max80.sv(111) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
+Warning (10862): bidir port "hdmi_sda" at max80.sv(111) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
+Warning (10862): bidir port "hdmi_hpd" at max80.sv(113) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 113
+Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 139
 Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
 Info (12130): Elaborated megafunction instantiation "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
 Info (12133): Instantiated megafunction "pll:pll|altpll:altpll_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
@@ -1245,7 +1254,7 @@ Info (12021): Found 8 design units, including 8 entities, in source file db/pll_
     Info (12023): Found entity 6: pll_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 309
     Info (12023): Found entity 7: pll_cntr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 343
     Info (12023): Found entity 8: pll_altpll File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 446
-Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
+Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated" File: /opt/altera/20.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
 Info (12128): Elaborating entity "pll_altpll_dyn_phase_le" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 509
 Warning (10862): input port "datad" at pll_altpll.v(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 46
 Info (12128): Elaborating entity "pll_altpll_dyn_phase_le1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 516
@@ -1261,13 +1270,13 @@ Warning (10259): Verilog HDL error at tmdsenc.v(93): constant value overflow Fil
 Warning (10229): Verilog HDL Expression warning at tmdsenc.v(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 117
 Warning (12125): Using design file tmdsenc.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
     Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 73
-Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 167
+Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 179
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 92
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 134
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 135
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 140
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.v(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 145
-Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
+Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 196
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(67): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 67
@@ -1275,7 +1284,7 @@ Info (12128): Elaborating entity "condreg" for hierarchy "transpose:hdmitranspos
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(14): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 14
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(15): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 15
 Warning (10862): input port "clk" at transpose.sv(8) has no fan-out File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 8
-Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 193
+Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 205
 Info (12128): Elaborating entity "altlvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
 Info (12130): Elaborated megafunction instantiation "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
 Info (12133): Instantiated megafunction "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
@@ -1321,7 +1330,7 @@ Info (12021): Found 8 design units, including 8 entities, in source file db/hdmi
     Info (12023): Found entity 6: hdmitx_shift_reg File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 477
     Info (12023): Found entity 7: hdmitx_shift_reg1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 527
     Info (12023): Found entity 8: hdmitx_lvds_tx File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 574
-Info (12128): Elaborating entity "hdmitx_lvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated" File: /opt/altera/18.1/quartus/libraries/megafunctions/altlvds_tx.tdf Line: 263
+Info (12128): Elaborating entity "hdmitx_lvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated" File: /opt/altera/20.1/quartus/libraries/megafunctions/altlvds_tx.tdf Line: 263
 Warning (10036): Verilog HDL or VHDL warning at hdmitx_lvds_tx.v(604): object "dffe19a" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 604
 Info (12128): Elaborating entity "hdmitx_ddio_out" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 649
 Info (12128): Elaborating entity "hdmitx_ddio_out1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 656
@@ -1399,24 +1408,24 @@ Warning (13039): The following bidirectional pins have no drivers
     Warning (13040): bidirectional pin "abc_d[5]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
     Warning (13040): bidirectional pin "abc_d[6]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
     Warning (13040): bidirectional pin "abc_d[7]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
-    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
 Warning (13032): The following tri-state nodes are fed by constants
-    Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[2]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[3]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[4]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[5]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[6]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[7]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[8]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[9]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[10]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[11]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[12]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
-    Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[2]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[3]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[4]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[5]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[6]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[7]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[8]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[9]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[10]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[11]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[12]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
+    Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
 Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.v Line: 124
 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
 Warning (13024): Output pins are stuck at VCC or GND
@@ -1424,35 +1433,35 @@ Warning (13024): Output pins are stuck at VCC or GND
     Warning (13410): Pin "abc_master" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
     Warning (13410): Pin "abc_a_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
     Warning (13410): Pin "abc_d_ce_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
-    Warning (13410): Pin "sr_cke" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 45
-    Warning (13410): Pin "sr_ba[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
-    Warning (13410): Pin "sr_ba[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
-    Warning (13410): Pin "sr_a[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[2]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[3]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[4]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[5]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[6]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[7]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[8]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[9]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[10]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[11]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_a[12]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
-    Warning (13410): Pin "sr_dqm[0]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
-    Warning (13410): Pin "sr_dqm[1]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
-    Warning (13410): Pin "sr_cs_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
-    Warning (13410): Pin "sr_we_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
-    Warning (13410): Pin "sr_cas_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
-    Warning (13410): Pin "sr_ras_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
-    Warning (13410): Pin "sd_clk" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 56
-    Warning (13410): Pin "sd_cmd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 57
-    Warning (13410): Pin "tty_rxd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 62
-    Warning (13410): Pin "tty_cts" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 64
-    Warning (13410): Pin "flash_cs_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
-    Warning (13410): Pin "flash_clk" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
-    Warning (13410): Pin "flash_mosi" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
+    Warning (13410): Pin "sr_cke" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 57
+    Warning (13410): Pin "sr_ba[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Warning (13410): Pin "sr_ba[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
+    Warning (13410): Pin "sr_a[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[2]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[3]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[4]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[5]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[6]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[7]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[8]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[9]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[10]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[11]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_a[12]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
+    Warning (13410): Pin "sr_dqm[0]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
+    Warning (13410): Pin "sr_dqm[1]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
+    Warning (13410): Pin "sr_cs_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 62
+    Warning (13410): Pin "sr_we_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
+    Warning (13410): Pin "sr_cas_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 64
+    Warning (13410): Pin "sr_ras_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
+    Warning (13410): Pin "sd_clk" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
+    Warning (13410): Pin "sd_cmd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
+    Warning (13410): Pin "tty_rxd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
+    Warning (13410): Pin "tty_cts" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
+    Warning (13410): Pin "flash_cs_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
+    Warning (13410): Pin "flash_clk" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
+    Warning (13410): Pin "flash_mosi" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 82
 Info (286030): Timing-Driven Synthesis is running
 Info (17016): Found the following redundant logic cells in design
     Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 59
@@ -1463,7 +1472,7 @@ Info (17016): Found the following redundant logic cells in design
     Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 562
 Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
     Info (16011): Adding 20 node(s), including 4 DDIO, 2 PLL, 0 transceiver and 6 LCELL
-Warning (21074): Design contains 37 input pin(s) that do not drive logic
+Warning (21074): Design contains 39 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "abc_clk" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
     Warning (15610): No output dependent on input pin "abc_a[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
     Warning (15610): No output dependent on input pin "abc_a[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
@@ -1495,22 +1504,24 @@ Warning (21074): Design contains 37 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "abc_xmemw80_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
     Warning (15610): No output dependent on input pin "abc_xinpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
     Warning (15610): No output dependent on input pin "abc_xoutpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
-    Warning (15610): No output dependent on input pin "tty_txd" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
-    Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
-    Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
-    Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
-    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
-    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
-Info (21057): Implemented 476 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 38 input pins
+    Warning (15610): No output dependent on input pin "exth_hc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
+    Warning (15610): No output dependent on input pin "exth_hh" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
+    Warning (15610): No output dependent on input pin "tty_txd" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
+    Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
+    Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
+    Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
+    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Info (21057): Implemented 484 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 40 input pins
     Info (21059): Implemented 47 output pins
-    Info (21060): Implemented 45 bidirectional pins
+    Info (21060): Implemented 51 bidirectional pins
     Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
-    Info: Peak virtual memory: 1084 megabytes
-    Info: Processing ended: Sun Aug  1 07:27:55 2021
-    Info: Elapsed time: 00:00:13
-    Info: Total CPU time (on all processors): 00:00:28
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 219 warnings
+    Info: Peak virtual memory: 677 megabytes
+    Info: Processing ended: Fri Aug  6 17:56:35 2021
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:15
 
 

output_files/max80.map.summary

@@ -1,5 +1,5 @@
-Analysis & Synthesis Status : Successful - Sun Aug  1 07:27:55 2021
-Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Analysis & Synthesis Status : Successful - Fri Aug  6 17:56:35 2021
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
@@ -7,7 +7,7 @@ Total logic elements : 337
     Total combinational functions : 274
     Dedicated logic registers : 218
 Total registers : 226
-Total pins : 130
+Total pins : 138
 Total virtual pins : 0
 Total memory bits : 0
 Embedded Multiplier 9-bit elements : 0

output_files/max80.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2019  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2020  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 CHIP  "max80"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
@@ -101,7 +101,7 @@ sr_ba[1]                     : B13       : output : 3.3-V LVTTL       :
 sr_a[1]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
 GND                          : B15       : gnd    :                   :         :           :                
 rtc_int_n                    : B16       : input  : 3.3-V LVTTL       :         : 6         : Y              
-flash_mosi                   : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
 abc_a_oe                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
 VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
@@ -222,7 +222,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : K6        :        :                   :
 VCCINT                       : K7        : power  :                   : 1.2V    :           :                
 GND                          : K8        : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K10       :        :                   :         : 4         :                
+flash_mosi                   : K10       : output : 3.3-V LVTTL       :         : 4         : N              
 VCCINT                       : K11       : power  :                   : 1.2V    :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 5         :                
 GND                          : K13       : gnd    :                   :         :           :                
@@ -269,10 +269,10 @@ abc_d[2]                     : N5        : bidir  : 3.3-V LVTTL       :
 RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
 GND                          : N7        : gnd    :                   :         :           :                
 spi_cs_esp_n                 : N8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 4         :                
+exth_hb                      : N9        : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 GND                          : N10       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N12       :        :                   :         : 4         :                
+exth_hg                      : N11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+exth_ha                      : N12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
 hdmi_d[1]                    : N15       : output : LVDS              :         : 5         : Y              
@@ -292,7 +292,7 @@ GND                          : P12       : gnd    :                   :
 VCCIO4                       : P13       : power  :                   : 3.3V    : 4         :                
 tty_dtr                      : P14       : input  : 3.3-V LVTTL       :         : 4         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : Y              
+hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : N              
 abc_xmemw80_n                : R1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 GND                          : R2        : gnd    :                   :         :           :                
 abc_d[4]                     : R3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
@@ -300,11 +300,11 @@ abc_d[6]                     : R4        : bidir  : 3.3-V LVTTL       :
 abc_d_ce_n                   : R5        : output : 3.3-V LVTTL       :         : 3         : Y              
 abc_resin_x                  : R6        : output : 3.3-V LVTTL       :         : 3         : Y              
 gpio[5]                      : R7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : R8        :        :                   :         : 3         :                
+exth_hh                      : R8        : input  : 3.3-V LVTTL       :         : 3         : Y              
 GND+                         : R9        :        :                   :         : 4         :                
 gpio[3]                      : R10       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 4         :                
+exth_hd                      : R11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+exth_he                      : R12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 hdmi_sda                     : R13       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 led[2]                       : R14       : output : 3.3-V LVTTL       :         : 4         : Y              
 GND                          : R15       : gnd    :                   :         :           :                
@@ -317,9 +317,9 @@ abc_d_oe                     : T5        : output : 3.3-V LVTTL       :
 gpio[2]                      : T6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 gpio[4]                      : T7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 abc_clk                      : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : T9        :        :                   :         : 4         :                
+exth_hc                      : T9        : input  : 3.3-V LVTTL       :         : 4         : Y              
 abc_master                   : T10       : output : 3.3-V LVTTL       :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 4         :                
+exth_hf                      : T11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 abc_xinpstb_n                : T12       : input  : 3.3-V LVTTL       :         : 4         : Y              
 led[1]                       : T13       : output : 3.3-V LVTTL       :         : 4         : Y              
 led[3]                       : T14       : output : 3.3-V LVTTL       :         : 4         : Y              

output_files/max80.pow.rpt

@@ -1,6 +1,6 @@
 Power Analyzer report for max80
-Sun Aug  1 07:28:10 2021
-Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Fri Aug  6 17:56:45 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
 ---------------------
@@ -28,7 +28,7 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 ----------------
 ; Legal Notice ;
 ----------------
-Copyright (C) 2019  Intel Corporation. All rights reserved.
+Copyright (C) 2020  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 
@@ -50,32 +50,32 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+
 ; Processors                 ; Number      ;
 +----------------------------+-------------+
-; Number detected on machine ; 4           ;
-; Maximum allowed            ; 2           ;
+; Number detected on machine ; 16          ;
+; Maximum allowed            ; 8           ;
 ;                            ;             ;
-; Average used               ; 1.01        ;
-; Maximum used               ; 2           ;
+; Average used               ; 1.04        ;
+; Maximum used               ; 8           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.5%      ;
+;     Processors 2-8         ;   0.6%      ;
 +----------------------------+-------------+
 
 
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Sun Aug  1 07:28:10 2021            ;
-; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
+; Power Analyzer Status                  ; Successful - Fri Aug  6 17:56:45 2021            ;
+; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
 ; Family                                 ; Cyclone IV E                                     ;
 ; Device                                 ; EP4CE15F17C8                                     ;
 ; Power Models                           ; Final                                            ;
-; Total Thermal Power Dissipation        ; 213.53 mW                                        ;
-; Core Dynamic Thermal Power Dissipation ; 38.05 mW                                         ;
-; Core Static Thermal Power Dissipation  ; 60.18 mW                                         ;
-; I/O Thermal Power Dissipation          ; 115.30 mW                                        ;
+; Total Thermal Power Dissipation        ; 216.33 mW                                        ;
+; Core Dynamic Thermal Power Dissipation ; 36.37 mW                                         ;
+; Core Static Thermal Power Dissipation  ; 60.19 mW                                         ;
+; I/O Thermal Power Dissipation          ; 119.77 mW                                        ;
 ; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
 +----------------------------------------+--------------------------------------------------+
 
@@ -143,6 +143,8 @@ https://fpgasoftware.intel.com/eula.
 ; abc_xmemw80_n  ; No valid clock domain found ;
 ; abc_xinpstb_n  ; No valid clock domain found ;
 ; abc_xoutpstb_n ; No valid clock domain found ;
+; exth_hc        ; No valid clock domain found ;
+; exth_hh        ; No valid clock domain found ;
 ; tty_txd        ; No valid clock domain found ;
 ; tty_rts        ; No valid clock domain found ;
 ; tty_dtr        ; No valid clock domain found ;
@@ -157,6 +159,12 @@ https://fpgasoftware.intel.com/eula.
 ; abc_d[6]       ; No valid clock domain found ;
 ; abc_d[7]       ; No valid clock domain found ;
 ; hdmi_sda       ; No valid clock domain found ;
+; exth_ha        ; No valid clock domain found ;
+; exth_hb        ; No valid clock domain found ;
+; exth_hd        ; No valid clock domain found ;
+; exth_he        ; No valid clock domain found ;
+; exth_hf        ; No valid clock domain found ;
+; exth_hg        ; No valid clock domain found ;
 ; sr_dq[0]       ; No valid clock domain found ;
 ; sr_dq[1]       ; No valid clock domain found ;
 ; sr_dq[2]       ; No valid clock domain found ;
@@ -211,7 +219,7 @@ https://fpgasoftware.intel.com/eula.
 ;     2.5 V I/O Standard                  ; 2.5 V                      ;
 ;     LVDS I/O Standard                   ; 2.5 V                      ;
 ;                                         ;                            ;
-; Auto computed junction temperature      ; 31.3 degrees Celsius       ;
+; Auto computed junction temperature      ; 31.4 degrees Celsius       ;
 ;     Ambient temperature                 ; 25.0 degrees Celsius       ;
 ;     Junction-to-Case thermal resistance ; 7.30 degrees Celsius/Watt  ;
 ;     Case-to-Ambient thermal resistance  ; 22.30 degrees Celsius/Watt ;
@@ -234,12 +242,12 @@ https://fpgasoftware.intel.com/eula.
 ; Block Type                            ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
 +---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
 ; PLL                                   ; 22.56 mW                          ; 22.56 mW                    ; --                             ; 0.00 mW                       ;  111.003                                                  ;
-; Combinational cell                    ; 0.42 mW                           ; 0.35 mW                     ; --                             ; 0.07 mW                       ;    8.056                                                  ;
-; Clock control block                   ; 12.52 mW                          ; 0.00 mW                     ; --                             ; 12.52 mW                      ;  180.003                                                  ;
-; Register cell                         ; 2.56 mW                           ; 1.99 mW                     ; --                             ; 0.57 mW                       ;   13.191                                                  ;
+; Combinational cell                    ; 0.42 mW                           ; 0.35 mW                     ; --                             ; 0.07 mW                       ;    8.079                                                  ;
+; Clock control block                   ; 11.03 mW                          ; 0.00 mW                     ; --                             ; 11.03 mW                      ;  180.003                                                  ;
+; Register cell                         ; 2.36 mW                           ; 1.92 mW                     ; --                             ; 0.44 mW                       ;   13.191                                                  ;
 ; Double Data Rate I/O Output Circuitry ; 0.49 mW                           ; 0.49 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
 ; I/O register                          ; 0.21 mW                           ; 0.21 mW                     ; --                             ; 0.00 mW                       ;   12.000                                                  ;
-; I/O                                   ; 88.23 mW                          ; 3.58 mW                     ; 84.65 mW                       ; 0.00 mW                       ;    2.418                                                  ;
+; I/O                                   ; 92.71 mW                          ; 3.58 mW                     ; 89.13 mW                       ; 0.00 mW                       ;    2.282                                                  ;
 +---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
 (1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
 
@@ -249,30 +257,30 @@ https://fpgasoftware.intel.com/eula.
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
 ; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
-; |max80                                                          ; 126.98 mW (91.35 mW)                 ; 29.17 mW (4.25 mW)              ; 84.65 mW (84.65 mW)               ; 13.16 mW (2.45 mW)                ; |max80                                                                                                             ;
+; |max80                                                          ; 129.77 mW (95.97 mW)                 ; 29.10 mW (4.27 mW)              ; 89.13 mW (89.13 mW)               ; 11.54 mW (2.58 mW)                ; |max80                                                                                                             ;
 ;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
-;     |tmdsenc:hdmitmds[0].enc                                    ; 0.17 mW (0.17 mW)                    ; 0.14 mW (0.14 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
+;     |tmdsenc:hdmitmds[0].enc                                    ; 0.15 mW (0.15 mW)                    ; 0.13 mW (0.13 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
 ;     |tmdsenc:hdmitmds[1].enc                                    ; 0.15 mW (0.15 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
 ;     |tmdsenc:hdmitmds[2].enc                                    ; 0.14 mW (0.14 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ;
 ;     |transpose:hdmitranspose                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|transpose:hdmitranspose                                                                                     ;
-;     |hdmitx:hdmitx                                              ; 19.77 mW (0.00 mW)                   ; 13.33 mW (0.00 mW)              ; --                                ; 6.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
-;         |altlvds_tx:ALTLVDS_TX_component                        ; 19.77 mW (0.00 mW)                   ; 13.33 mW (0.00 mW)              ; --                                ; 6.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
-;             |hdmitx_lvds_tx:auto_generated                      ; 19.77 mW (18.14 mW)                  ; 13.33 mW (12.00 mW)             ; --                                ; 6.43 mW (6.14 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
-;                 |hdmitx_cntr:cntr2                              ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
-;                 |hdmitx_cntr:cntr13                             ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
+;     |hdmitx:hdmitx                                              ; 17.71 mW (0.00 mW)                   ; 13.27 mW (0.00 mW)              ; --                                ; 4.44 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
+;         |altlvds_tx:ALTLVDS_TX_component                        ; 17.71 mW (0.00 mW)                   ; 13.27 mW (0.00 mW)              ; --                                ; 4.44 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
+;             |hdmitx_lvds_tx:auto_generated                      ; 17.71 mW (16.18 mW)                  ; 13.27 mW (11.93 mW)             ; --                                ; 4.44 mW (4.25 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
+;                 |hdmitx_cntr:cntr2                              ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
+;                 |hdmitx_cntr:cntr13                             ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
 ;                 |hdmitx_ddio_out:ddio_out                       ; 0.37 mW (0.37 mW)                    ; 0.37 mW (0.37 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ;
 ;                 |hdmitx_shift_reg:outclk_shift_h                ; 0.10 mW (0.10 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ;
 ;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.09 mW (0.09 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
 ;                 |hdmitx_ddio_out1:outclock_ddio                 ; 0.12 mW (0.12 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ;
-;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.12 mW (0.12 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
-;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
-;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
-;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
-;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.14 mW (0.14 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
-;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.13 mW (0.13 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
-;     |pll:pll                                                    ; 15.40 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.19 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
-;         |altpll:altpll_component                                ; 15.40 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.19 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
-;             |pll_altpll:auto_generated                          ; 15.40 mW (15.40 mW)                  ; 11.21 mW (11.21 mW)             ; --                                ; 4.19 mW (4.19 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
+;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
+;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
+;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
+;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
+;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.12 mW (0.12 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
+;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.12 mW (0.12 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
+;     |pll:pll                                                    ; 15.65 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.44 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
+;         |altpll:altpll_component                                ; 15.65 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.44 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
+;             |pll_altpll:auto_generated                          ; 15.65 mW (15.65 mW)                  ; 11.21 mW (11.21 mW)             ; --                                ; 4.44 mW (4.44 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
 ;                 |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2   ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ;
 ;                 |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ;
 ;                 |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ;
@@ -290,12 +298,12 @@ https://fpgasoftware.intel.com/eula.
 ; Clock Domain                                                                                        ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
 +-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; 96.00                 ; 12.46                    ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; 96.00                 ; 2.66                     ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; 36.00                 ; 1.43                     ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; 96.00                 ; 2.67                     ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; 36.00                 ; 1.66                     ;
 ; clock_48                                                                                            ; 48.00                 ; 0.00                     ;
-; rst_n                                                                                               ; 96.00                 ; 2.43                     ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; 180.02                ; 18.81                    ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; 36.00                 ; 0.95                     ;
+; rst_n                                                                                               ; 96.00                 ; 2.57                     ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; 180.02                ; 16.68                    ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; 36.00                 ; 1.02                     ;
 ; rtc_32khz                                                                                           ; 0.03                  ; 0.00                     ;
 +-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
 
@@ -305,8 +313,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 ; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
-; VCCINT         ; 53.80 mA                ; 13.77 mA                  ; 40.03 mA                 ; 53.80 mA                         ;
-; VCCIO          ; 28.12 mA                ; 1.01 mA                   ; 27.11 mA                 ; 28.12 mA                         ;
+; VCCINT         ; 55.74 mA                ; 12.37 mA                  ; 43.38 mA                 ; 55.74 mA                         ;
+; VCCIO          ; 28.25 mA                ; 1.01 mA                   ; 27.25 mA                 ; 28.25 mA                         ;
 ; VCCA           ; 21.83 mA                ; 3.55 mA                   ; 18.28 mA                 ; 21.83 mA                         ;
 ; VCCD           ; 19.19 mA                ; 11.40 mA                  ; 7.78 mA                  ; 19.19 mA                         ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
@@ -319,10 +327,10 @@ https://fpgasoftware.intel.com/eula.
 +----------+---------------+---------------------+-----------------------+----------------------+
 ; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
 +----------+---------------+---------------------+-----------------------+----------------------+
-; 1        ; 3.3V          ; 1.27 mA             ; 0.00 mA               ; 1.27 mA              ;
+; 1        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
 ; 2        ; 3.3V          ; 1.31 mA             ; 0.00 mA               ; 1.31 mA              ;
-; 3        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
-; 4        ; 3.3V          ; 1.41 mA             ; 0.15 mA               ; 1.25 mA              ;
+; 3        ; 3.3V          ; 1.44 mA             ; 0.00 mA               ; 1.44 mA              ;
+; 4        ; 3.3V          ; 1.55 mA             ; 0.15 mA               ; 1.39 mA              ;
 ; 5        ; 2.5V          ; 17.77 mA            ; 0.03 mA               ; 17.74 mA             ;
 ; 6        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
 ; 7        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
@@ -336,37 +344,37 @@ https://fpgasoftware.intel.com/eula.
 ; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
 +---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 ; 2.5V          ; 17.77 mA                ; 0.03 mA                   ; 17.74 mA                 ; 17.77 mA                         ;
-; 3.3V          ; 10.35 mA                ; 0.98 mA                   ; 9.37 mA                  ; 10.35 mA                         ;
+; 3.3V          ; 10.49 mA                ; 0.98 mA                   ; 9.51 mA                  ; 10.49 mA                         ;
 +---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 (1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
 (2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
 
 
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Confidence Metric Details                                                                                                                       ;
-+----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+
-; Data Source                                                                            ; Total       ; Pin        ; Registered  ; Combinational ;
-+----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+
-; Simulation (from file)                                                                 ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate from Simulation                              ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)    ; 0 (0.0%)      ;
-;     -- Number of signals with Static Probability from Simulation                       ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)    ; 0 (0.0%)      ;
-;                                                                                        ;             ;            ;             ;               ;
-; Node, entity or clock assignment                                                       ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate from Node, entity or clock assignment        ; 8 (0.9%)    ; 2 (1.1%)   ; 1 (0.5%)    ; 5 (1.0%)      ;
-;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 8 (0.9%)    ; 2 (1.1%)   ; 1 (0.5%)    ; 5 (1.0%)      ;
-;                                                                                        ;             ;            ;             ;               ;
-; Vectorless estimation                                                                  ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 798 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 482 (99.0%)   ;
-;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 200 (22.5%) ; 92 (51.4%) ; 1 (0.5%)    ; 107 (22.0%)   ;
-;     -- Number of signals with Static Probability from Vectorless estimation            ; 798 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 482 (99.0%)   ;
-;                                                                                        ;             ;            ;             ;               ;
-; Default assignment                                                                     ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)    ; 0 (0.0%)      ;
-;     -- Number of signals with Static Probability from Default assignment               ; 81 (9.1%)   ; 81 (45.3%) ; 0 (0.0%)    ; 0 (0.0%)      ;
-;                                                                                        ;             ;            ;             ;               ;
-; Assumed 0                                                                              ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate assumed 0                                    ; 81 (9.1%)   ; 81 (45.3%) ; 0 (0.0%)    ; 0 (0.0%)      ;
-+----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Confidence Metric Details                                                                                                                        ;
++----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
+; Data Source                                                                            ; Total       ; Pin         ; Registered  ; Combinational ;
++----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
+; Simulation (from file)                                                                 ;             ;             ;             ;               ;
+;     -- Number of signals with Toggle Rate from Simulation                              ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Simulation                       ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
+;                                                                                        ;             ;             ;             ;               ;
+; Node, entity or clock assignment                                                       ;             ;             ;             ;               ;
+;     -- Number of signals with Toggle Rate from Node, entity or clock assignment        ; 8 (0.9%)    ; 2 (1.0%)    ; 1 (0.5%)    ; 5 (1.0%)      ;
+;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 8 (0.9%)    ; 2 (1.0%)    ; 1 (0.5%)    ; 5 (1.0%)      ;
+;                                                                                        ;             ;             ;             ;               ;
+; Vectorless estimation                                                                  ;             ;             ;             ;               ;
+;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 813 (89.3%) ; 102 (52.8%) ; 220 (99.5%) ; 491 (99.0%)   ;
+;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 212 (23.3%) ; 98 (50.8%)  ; 1 (0.5%)    ; 113 (22.8%)   ;
+;     -- Number of signals with Static Probability from Vectorless estimation            ; 813 (89.3%) ; 102 (52.8%) ; 220 (99.5%) ; 491 (99.0%)   ;
+;                                                                                        ;             ;             ;             ;               ;
+; Default assignment                                                                     ;             ;             ;             ;               ;
+;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Default assignment               ; 89 (9.8%)   ; 89 (46.1%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
+;                                                                                        ;             ;             ;             ;               ;
+; Assumed 0                                                                              ;             ;             ;             ;               ;
+;     -- Number of signals with Toggle Rate assumed 0                                    ; 89 (9.8%)   ; 89 (46.1%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
++----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
 
 
 +---------------------------------------------------------------------------------------------------------------------------------------------+
@@ -382,8 +390,8 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------+
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
-    Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Sun Aug  1 07:28:08 2021
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Fri Aug  6 17:56:44 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -421,12 +429,12 @@ Info (223001): Completed Vectorless Power Activity Estimation
 Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
-Info (215049): Average toggle rate for this design is 11.008 millions of transitions / sec
-Info (215031): Total thermal power estimate for the design is 213.53 mW
+Info (215049): Average toggle rate for this design is 10.891 millions of transitions / sec
+Info (215031): Total thermal power estimate for the design is 216.33 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1264 megabytes
-    Info: Processing ended: Sun Aug  1 07:28:10 2021
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
+    Info: Peak virtual memory: 1022 megabytes
+    Info: Processing ended: Fri Aug  6 17:56:45 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
 
 

output_files/max80.pow.summary

@@ -1,12 +1,12 @@
-Power Analyzer Status : Successful - Sun Aug  1 07:28:10 2021
-Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+Power Analyzer Status : Successful - Fri Aug  6 17:56:45 2021
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
 Device : EP4CE15F17C8
 Power Models : Final
-Total Thermal Power Dissipation : 213.53 mW
-Core Dynamic Thermal Power Dissipation : 38.05 mW
-Core Static Thermal Power Dissipation : 60.18 mW
-I/O Thermal Power Dissipation : 115.30 mW
+Total Thermal Power Dissipation : 216.33 mW
+Core Dynamic Thermal Power Dissipation : 36.37 mW
+Core Static Thermal Power Dissipation : 60.19 mW
+I/O Thermal Power Dissipation : 119.77 mW
 Power Estimation Confidence : Low: user provided insufficient toggle rate data

output_files/max80.sta.summary

@@ -3,7 +3,7 @@ Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 1.779
+Slack : 2.007
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -11,31 +11,31 @@ Slack : 4.943
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 18.707
+Slack : 18.089
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 22.634
+Slack : 22.689
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.466
+Slack : 0.465
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 0.504
+Slack : 0.503
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.519
+Slack : 0.674
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 2.160
+Slack : 2.471
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.477
+Slack : 2.480
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -51,7 +51,7 @@ Slack : 13.587
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 13.589
+Slack : 13.590
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'rtc_32khz'
@@ -59,7 +59,7 @@ Slack : 30513.579
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.014
+Slack : 2.216
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -67,11 +67,11 @@ Slack : 5.426
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 19.293
+Slack : 18.575
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 22.934
+Slack : 22.983
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -79,19 +79,19 @@ Slack : 0.417
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 0.472
+Slack : 0.471
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.480
+Slack : 0.626
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 2.012
+Slack : 2.322
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.476
+Slack : 2.479
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -103,11 +103,11 @@ Slack : 10.354
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 13.587
+Slack : 13.586
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 13.589
+Slack : 13.587
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'rtc_32khz'
@@ -115,7 +115,7 @@ Slack : 30513.579
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 3.799
+Slack : 3.952
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -123,11 +123,11 @@ Slack : 8.053
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 23.683
+Slack : 23.427
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 24.617
+Slack : 24.647
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
@@ -139,15 +139,15 @@ Slack : 0.194
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.211
+Slack : 0.277
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 0.891
+Slack : 1.023
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.564
+Slack : 2.565
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
@@ -159,11 +159,11 @@ Slack : 10.004
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 13.673
+Slack : 13.674
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 13.674
+Slack : 13.675
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'rtc_32khz'

pin2qsf.pl

@@ -1 +0,0 @@
-/home/hpa/hwhacks/fpga/pinlist/pin2qsf.pl

pin2qsf.pl

@@ -0,0 +1,12 @@
+#!/usr/bin/perl
+
+while ( defined($line = <STDIN>) ) {
+    chomp $line;
+    $line =~ s/^\#.*$//;	# Remove comments
+
+    if ( $line =~ /^\s*(\S+)\s+(\S+)/ ) {
+	$pin    = $1;
+	$signal = $2;
+	print "set_location_assignment PIN_\U${pin}\E -to \"${signal}\"\n";
+    }
+}