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@@ -145,7 +145,7 @@ module max80
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// sdram_clk, sys_clk - 2:1 ratio
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// vid_hdmiclk, vid_clk - 5:1 ratio
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//
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- wire reset_plls;
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+ wire reset_plls = 1'b0;
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wire master_clk; // 336 MHz internal master clock
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pll2 pll2 (
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.areset ( reset_plls ),
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@@ -195,7 +195,7 @@ module max80
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//
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// XXX: reuse this counter for the CPU cycle counter.
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//
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- parameter reset_pow2 = 12;
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+ localparam reset_pow2 = 12;
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reg [31:0] sys_clk_ctr;
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reg [31:0] sys_clk_ctr_q;
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@@ -239,9 +239,6 @@ module max80
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end
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end
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- // Unused device stubs - remove when used
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- assign gpio = 6'bz; // Unless assigned elsewhere
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-
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// Reset in the video clock domain
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reg vid_rst_n;
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always @(negedge all_plls_locked or posedge vid_clk)
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@@ -437,7 +434,7 @@ module max80
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);
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// Embedded RISC-V CPU
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- parameter cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
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+ localparam cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
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// Edge-triggered IRQs. picorv32 latches interrupts
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// but doesn't edge detect for a slow signal, so do it
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@@ -695,8 +692,6 @@ module max80
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// Serial port. Direct to the CP2102N for v1 boards
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// boards or to GPIO for v2 boards.
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//
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- // The GPIO numbering matches the order of pins for FT[2]232H.
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- //
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wire tty_data_out; // Output data
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wire tty_data_in; // Input data
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wire tty_cts_out; // Assert CTS# externally
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