Browse Source

More cleanups of multi-version... still broken?!

H. Peter Anvin 3 years ago
parent
commit
08d8d7d2c8
9 changed files with 19 additions and 15 deletions
  1. 2 2
      fpga/max80.qpf
  2. 2 1
      fpga/max80.qsf
  3. 3 8
      fpga/max80.sv
  4. BIN
      fpga/output/v1.jic
  5. BIN
      fpga/output/v1.sof
  6. BIN
      fpga/output/v2.sof
  7. 0 2
      fpga/sdram.sv
  8. 5 0
      fpga/v1.qsf
  9. 7 2
      fpga/v2.qsf

+ 2 - 2
fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 #
 # Quartus Prime
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 01:49:44  December 23, 2021
+# Date created = 03:11:29  December 23, 2021
 #
 #
 # -------------------------------------------------------------------------- #
 # -------------------------------------------------------------------------- #
 
 
 QUARTUS_VERSION = "21.1"
 QUARTUS_VERSION = "21.1"
-DATE = "01:49:44  December 23, 2021"
+DATE = "03:11:29  December 23, 2021"
 
 
 # Revisions
 # Revisions
 
 

+ 2 - 1
fpga/max80.qsf

@@ -1,4 +1,4 @@
-# -------------------------------------------------------------------------- #
+# -*- tcl -*- -------------------------------------------------------------- #
 #
 #
 # Copyright (C) 2019  Intel Corporation. All rights reserved.
 # Copyright (C) 2019  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions
 # Your use of Intel Corporation's design tools, logic functions
@@ -282,6 +282,7 @@ set_global_assignment -name VERILOG_FILE ip/hdmitx.v
 set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
+set_global_assignment -name SYSTEMVERILOG_FILE video.sv
 set_global_assignment -name SDC_FILE max80.sdc
 set_global_assignment -name SDC_FILE max80.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 set_global_assignment -name SYSTEMVERILOG_FILE v1.sv
 set_global_assignment -name SYSTEMVERILOG_FILE v1.sv

+ 3 - 8
fpga/max80.sv

@@ -145,7 +145,7 @@ module max80
    //  sdram_clk, sys_clk    - 2:1 ratio
    //  sdram_clk, sys_clk    - 2:1 ratio
    //  vid_hdmiclk, vid_clk  - 5:1 ratio
    //  vid_hdmiclk, vid_clk  - 5:1 ratio
    //
    //
-   wire     reset_plls;
+   wire     reset_plls = 1'b0;
    wire     master_clk;		// 336 MHz internal master clock
    wire     master_clk;		// 336 MHz internal master clock
    pll2 pll2 (
    pll2 pll2 (
 	      .areset ( reset_plls ),
 	      .areset ( reset_plls ),
@@ -195,7 +195,7 @@ module max80
    //
    //
    // XXX: reuse this counter for the CPU cycle counter.
    // XXX: reuse this counter for the CPU cycle counter.
    //
    //
-   parameter reset_pow2 = 12;
+   localparam reset_pow2 = 12;
 
 
    reg [31:0] sys_clk_ctr;
    reg [31:0] sys_clk_ctr;
    reg [31:0] sys_clk_ctr_q;
    reg [31:0] sys_clk_ctr_q;
@@ -239,9 +239,6 @@ module max80
 	    end
 	    end
        end
        end
 
 
-   // Unused device stubs - remove when used
-   assign gpio = 6'bz;		// Unless assigned elsewhere
-
    // Reset in the video clock domain
    // Reset in the video clock domain
    reg vid_rst_n;
    reg vid_rst_n;
    always @(negedge all_plls_locked or posedge vid_clk)
    always @(negedge all_plls_locked or posedge vid_clk)
@@ -437,7 +434,7 @@ module max80
 	   );
 	   );
 
 
    // Embedded RISC-V CPU
    // Embedded RISC-V CPU
-   parameter cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
+   localparam cpu_fast_mem_bits = SRAM_BITS-2; /* 2^[this] * 4 bytes */
 
 
    // Edge-triggered IRQs. picorv32 latches interrupts
    // Edge-triggered IRQs. picorv32 latches interrupts
    // but doesn't edge detect for a slow signal, so do it
    // but doesn't edge detect for a slow signal, so do it
@@ -695,8 +692,6 @@ module max80
    // Serial port. Direct to the CP2102N for v1 boards
    // Serial port. Direct to the CP2102N for v1 boards
    // boards or to GPIO for v2 boards.
    // boards or to GPIO for v2 boards.
    //
    //
-   // The GPIO numbering matches the order of pins for FT[2]232H.
-   //
    wire        tty_data_out;	// Output data
    wire        tty_data_out;	// Output data
    wire        tty_data_in;	// Input data
    wire        tty_data_in;	// Input data
    wire        tty_cts_out;	// Assert CTS# externally
    wire        tty_cts_out;	// Assert CTS# externally

BIN
fpga/output/v1.jic


BIN
fpga/output/v1.sof


BIN
fpga/output/v2.sof


+ 0 - 2
fpga/sdram.sv

@@ -308,8 +308,6 @@ module sdram
    assign	sr_cas_n = dram_cmd[1];
    assign	sr_cas_n = dram_cmd[1];
    assign	sr_we_n  = dram_cmd[0];
    assign	sr_we_n  = dram_cmd[0];
 
 
-   assign       sr_cke   = 1'b1;
-
    // SDRAM output signal registers
    // SDRAM output signal registers
    reg [12:0]		    dram_a;
    reg [12:0]		    dram_a;
    assign		    sr_a = dram_a;
    assign		    sr_a = dram_a;

+ 5 - 0
fpga/v1.qsf

@@ -1,5 +1,10 @@
+# -*- tcl -*-
+
 set_global_assignment -name TOP_LEVEL_ENTITY v1
 set_global_assignment -name TOP_LEVEL_ENTITY v1
 set_global_assignment -name SOURCE_FILE v1.pins
 set_global_assignment -name SOURCE_FILE v1.pins
 set_global_assignment -name SOURCE_FILE "max80-v1.cof"
 set_global_assignment -name SOURCE_FILE "max80-v1.cof"
 
 
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
+
+# Quartus insists on this line...
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

+ 7 - 2
fpga/v2.qsf

@@ -1,10 +1,12 @@
+# -*- tcl -*-
+
 set_global_assignment -name TOP_LEVEL_ENTITY v2
 set_global_assignment -name TOP_LEVEL_ENTITY v2
 set_global_assignment -name SOURCE_FILE v2.pins
 set_global_assignment -name SOURCE_FILE v2.pins
 set_global_assignment -name SOURCE_FILE "max80-v2.cof"
 set_global_assignment -name SOURCE_FILE "max80-v2.cof"
 
 
-set_instance_assignment -name IO_STANDARD "LVDS" -to usb_rx
+set_instance_assignment -name IO_STANDARD LVDS -to usb_rx
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_rx
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_rx
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_rx(n)
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "usb_rx(n)"
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to usb_dp
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to usb_dp
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to usb_dn
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to usb_dn
 
 
@@ -12,3 +14,6 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to sd_cd_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd_n
 
 
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
+
+# Quartus insists on this line...
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top