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@@ -33,24 +33,23 @@ module spirom (
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parameter [23:0] romstart = 24'h10_0000; // 1 MB
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parameter [23:0] datalen = 24'h08_0000; // 512K
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+ //
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+ // FIFO and input latches
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+ //
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reg [1:0] spi_in_q;
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reg spi_in_req;
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+ reg spi_in_req_q;
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wire [11:0] wrusedw;
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- (* syn_preserve = 1 *) wire [8:0] rdusedw;
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-
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- //
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- // FIFO
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- //
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+ wire [8:0] rdusedw;
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wire [15:0] fifo_out;
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-
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- (* syn_preserve = 1 *) wire rdempty;
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+ wire rdempty;
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ddufifo spirom_fifo (
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.aclr ( ~rst_n ),
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.wrclk ( rom_clk ),
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.data ( spi_in_q ),
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- .wrreq ( spi_in_req ),
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+ .wrreq ( spi_in_req_q ),
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.wrfull ( ),
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.wrusedw ( wrusedw ),
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@@ -128,12 +127,15 @@ module spirom (
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spi_clk_en <= 1'b0;
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spi_data_ctr <= datalen << 2;
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spi_cs_n <= 1'b1;
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+ spi_in_req <= 1'b0;
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+ spi_in_req_q <= 1'b0;
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end
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else
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begin
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- spi_in_q <= spi_io;
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- spi_in_req <= 1'b0;
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- spi_clk_en <= 1'b0;
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+ spi_in_q <= spi_io;
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+ spi_in_req <= 1'b0;
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+ spi_in_req_q <= spi_in_req;
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+ spi_clk_en <= 1'b0;
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if ( ~|spi_data_ctr )
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begin
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@@ -149,7 +151,7 @@ module spirom (
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spi_clk_en <= (~wrusedw) >= 12'd128;
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if ( spi_clk_en )
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begin
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- if ( spi_cmd_ctr[5] & spi_cmd_ctr[3] & spi_cmd_ctr[0] )
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+ if ( spi_cmd_ctr[5] & spi_cmd_ctr[3] )
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begin
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spi_in_req <= 1'b1;
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spi_data_ctr <= spi_data_ctr - 1'b1;
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