max80.sdc: multicycle path between sdram_clk and sr_clk (why?)

fpga/max80.sdc

@@ -23,9 +23,11 @@ set_clock_groups -asynchronous \
     -group $main_clocks \
     -group [get_clocks rst_n]
 
-set sdram_clk [get_clocks pll|*|clk\[0\]]
-set cpu_clk   [get_clocks pll|*|clk\[1\]]
-set vid_clk   [get_clocks pll|*|clk\[2\]]
+set sdram_out_clk [get_clocks pll|*|clk\[0\]]
+set sdram_clk     [get_clocks pll|*|clk\[4\]]
+set cpu_clk       [get_clocks pll|*|clk\[1\]]
+set vid_clk       [get_clocks pll|*|clk\[2\]]
+set flash_clk     [get_clocks pll|*|clk\[3\]]
 
 # SDRAM I/O constraints
 # set_max_skew -to [get_ports sr_*] 0.500ns
@@ -44,6 +46,10 @@ set_multicycle_path -from [all_clocks] -to $synchro_inputs \
     -start -setup 2
 set_multicycle_path -from [all_clocks] -to $synchro_inputs \
     -start -hold 1
+set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
+    -start -setup 2
+set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
+    -start -hold 0
 
 # Don't report signaltap clock problems...
 set_false_path -to [get_registers sld_signaltap:*]