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Change N/C pins to output driving GND

Improve noise immunity by driving unused pins to GND
H. Peter Anvin 3 years ago
parent
commit
0cc1a65b5e

+ 1 - 0
max80.qsf

@@ -289,4 +289,5 @@ set_global_assignment -name GENERATE_JAM_FILE ON
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
 set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
 
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

+ 59 - 58
max80.sv

@@ -10,93 +10,94 @@
 
 module max80 (
 	      // Clock oscillator
-	      input	    clock_48, // 48 MHz
+	      input 	    clock_48, // 48 MHz
 
 	      // ABC-bus
-	      input	    abc_clk, // ABC-bus 3 MHz clock
+	      input 	    abc_clk, // ABC-bus 3 MHz clock
 	      input [15:0]  abc_a, // ABC address bus
 	      inout [7:0]   abc_d, // ABC data bus
-	      output	    abc_d_oe, // Data bus output enable
-	      input	    abc_rst_n, // ABC bus reset strobe
-	      input	    abc_cs_n, // ABC card select strobe
+	      output 	    abc_d_oe, // Data bus output enable
+	      input 	    abc_rst_n, // ABC bus reset strobe
+	      input 	    abc_cs_n, // ABC card select strobe
 	      input [4:0]   abc_out_n, // OUT, C1-C4 strobe
 	      input [1:0]   abc_inp_n, // INP, STATUS strobe
-	      input	    abc_xmemfl_n, // Memory read strobe
-	      input	    abc_xmemw800_n, // Memory write strobe (ABC800)
-	      input	    abc_xmemw80_n, // Memory write strobe (ABC80)
-	      input	    abc_xinpstb_n, // I/O read strobe (ABC800)
-	      input	    abc_xoutpstb_n, // I/O write strobe (ABC80)
+	      input 	    abc_xmemfl_n, // Memory read strobe
+	      input 	    abc_xmemw800_n, // Memory write strobe (ABC800)
+	      input 	    abc_xmemw80_n, // Memory write strobe (ABC80)
+	      input 	    abc_xinpstb_n, // I/O read strobe (ABC800)
+	      input 	    abc_xoutpstb_n, // I/O write strobe (ABC80)
 	      // The following are inverted versus the bus IF
 	      // the corresponding MOSFETs are installed
-	      output	    abc_rdy_x, // RDY = WAIT#
-	      output	    abc_resin_x, // System reset request
-	      output	    abc_int80_x, // System INT request (ABC80)
-	      output	    abc_int800_x, // System INT request (ABC800)
-	      output	    abc_nmi_x, // System NMI request (ABC800)
-	      output	    abc_xm_x, // System memory override (ABC800)
+	      output 	    abc_rdy_x, // RDY = WAIT#
+	      output 	    abc_resin_x, // System reset request
+	      output 	    abc_int80_x, // System INT request (ABC80)
+	      output 	    abc_int800_x, // System INT request (ABC800)
+	      output 	    abc_nmi_x, // System NMI request (ABC800)
+	      output 	    abc_xm_x, // System memory override (ABC800)
 	      // Master/slave control
-	      output	    abc_master, // 1 = master, 0 = slave
-	      output	    abc_a_oe,
+	      output 	    abc_master, // 1 = master, 0 = slave
+	      output 	    abc_a_oe,
 	      // Bus isolation
-	      output	    abc_d_ce_n,
+	      output 	    abc_d_ce_n,
 
 	      // ABC-bus extension header
 	      // (Note: cannot use an array here because HC and HH are
 	      // input only.)
-	      inout	    exth_ha,
-	      inout	    exth_hb,
-	      input	    exth_hc,
-	      inout	    exth_hd,
-	      inout	    exth_he,
-	      inout	    exth_hf,
-	      inout	    exth_hg,
-	      input	    exth_hh,
+	      inout 	    exth_ha,
+	      inout 	    exth_hb,
+	      input 	    exth_hc,
+	      inout 	    exth_hd,
+	      inout 	    exth_he,
+	      inout 	    exth_hf,
+	      inout 	    exth_hg,
+	      input 	    exth_hh,
 
 	      // SDRAM bus
-	      output	    sr_clk,
-	      output	    sr_cke,
+	      output 	    sr_clk,
+	      output 	    sr_cke,
 	      output [1:0]  sr_ba, // Bank address
 	      output [12:0] sr_a, // Address within bank
 	      inout [15:0]  sr_dq, // Also known as D or IO
 	      output [1:0]  sr_dqm, // DQML and DQMH
-	      output	    sr_cs_n,
-	      output	    sr_we_n,
-	      output	    sr_cas_n,
-	      output	    sr_ras_n,
+	      output 	    sr_cs_n,
+	      output 	    sr_we_n,
+	      output 	    sr_cas_n,
+	      output 	    sr_ras_n,
 
 	      // SD card
-	      output	    sd_clk,
-	      output	    sd_cmd,
+	      output 	    sd_clk,
+	      output 	    sd_cmd,
 	      inout [3:0]   sd_dat,
 
 	      // USB serial (naming is FPGA as DCE)
-	      input	    tty_txd,
-	      output	    tty_rxd,
-	      input	    tty_rts,
-	      output	    tty_cts,
-	      input	    tty_dtr,
+	      input 	    tty_txd,
+	      output 	    tty_rxd,
+	      input 	    tty_rts,
+	      output 	    tty_cts,
+	      input 	    tty_dtr,
 
 	      // SPI flash memory (also configuration)
-	      output	    flash_cs_n,
-	      output	    flash_clk,
-	      output	    flash_mosi,
-	      input	    flash_miso,
+	      output 	    flash_cs_n,
+	      output 	    flash_clk,
+	      output 	    flash_mosi,
+	      input 	    flash_miso,
 
 	      // SPI bus (connected to ESP32 so can be bidirectional)
-	      inout	    spi_clk,
-	      inout	    spi_miso,
-	      inout	    spi_mosi,
-	      inout	    spi_cs_esp_n, // ESP32 IO10
+	      inout 	    spi_clk,
+	      inout 	    spi_miso,
+	      inout 	    spi_mosi,
+	      inout 	    spi_cs_esp_n,	// ESP32 IO10
+	      inout         spi_cs_flash_n,	// ESP32 IO01
 
 	      // Other ESP32 connections
-	      inout	    esp_io0, // ESP32 IO00
-	      inout	    esp_int, // ESP32 IO09
+	      inout 	    esp_io0,		// ESP32 IO00
+	      inout 	    esp_int,		// ESP32 IO09
 
 	      // I2C bus (RTC and external)
-	      inout	    i2c_scl,
-	      inout	    i2c_sda,
-	      input	    rtc_32khz,
-	      input	    rtc_int_n,
+	      inout 	    i2c_scl,
+	      inout 	    i2c_sda,
+	      input 	    rtc_32khz,
+	      input 	    rtc_int_n,
 
 	      // LED
 	      output [3:1]  led,
@@ -106,10 +107,10 @@ module max80 (
 
 	      // HDMI
 	      output [2:0]  hdmi_d,
-	      output	    hdmi_clk,
-	      inout	    hdmi_scl,
-	      inout	    hdmi_sda,
-	      inout	    hdmi_hpd
+	      output 	    hdmi_clk,
+	      inout 	    hdmi_scl,
+	      inout 	    hdmi_sda,
+	      inout 	    hdmi_hpd
 	      );
 
    // Set if MOSFETs Q1-Q6 are installed rather than the corresponding

+ 7 - 7
output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Fri Aug  6 18:17:35 2021
+Fri Aug  6 18:26:22 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Aug  6 18:17:35 2021 ;
+; Assembler Status      ; Successful - Fri Aug  6 18:26:22 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -73,8 +73,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------+--------------------+
 ; Option         ; Setting            ;
 +----------------+--------------------+
-; JTAG usercode  ; 0x0010F462         ;
-; Checksum       ; 0x0010F462         ;
+; JTAG usercode  ; 0x00111E47         ;
+; Checksum       ; 0x00111E47         ;
 +----------------+--------------------+
 
 
@@ -102,7 +102,7 @@ https://fpgasoftware.intel.com/eula.
 ; Option             ; Setting        ;
 +--------------------+----------------+
 ; JTAG usercode      ; 0x00000000     ;
-; Checksum           ; 0xFCE24D45     ;
+; Checksum           ; 0xFCE26A8B     ;
 ; Compression Ratio  ; 3              ;
 +--------------------+----------------+
 
@@ -113,7 +113,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:17:33 2021
+    Info: Processing started: Fri Aug  6 18:26:20 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -124,7 +124,7 @@ Info (210117): Created JAM or JBC file for the specified chain:
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 569 megabytes
-    Info: Processing ended: Fri Aug  6 18:17:35 2021
+    Info: Processing ended: Fri Aug  6 18:26:22 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

+ 1 - 1
output_files/max80.done

@@ -1 +1 @@
-Fri Aug  6 18:17:39 2021
+Fri Aug  6 18:26:27 2021

+ 6 - 6
output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Fri Aug  6 18:17:39 2021
+Fri Aug  6 18:26:27 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Fri Aug  6 18:17:39 2021 ;
+; EDA Netlist Writer Status ; Successful - Fri Aug  6 18:26:27 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -84,15 +84,15 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:17:39 2021
+    Info: Processing started: Fri Aug  6 18:26:26 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 816 megabytes
-    Info: Processing ended: Fri Aug  6 18:17:39 2021
-    Info: Elapsed time: 00:00:00
+    Info: Peak virtual memory: 815 megabytes
+    Info: Processing ended: Fri Aug  6 18:26:27 2021
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:00
 
 

File diff suppressed because it is too large
+ 449 - 448
output_files/max80.fit.rpt


+ 2 - 2
output_files/max80.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Fri Aug  6 18:17:32 2021
+Fitter Status : Successful - Fri Aug  6 18:26:19 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
@@ -9,7 +9,7 @@ Total logic elements : 327 / 15,408 ( 2 % )
     Total combinational functions : 278 / 15,408 ( 2 % )
     Dedicated logic registers : 218 / 15,408 ( 1 % )
 Total registers : 229
-Total pins : 142 / 166 ( 86 % )
+Total pins : 143 / 166 ( 86 % )
 Total virtual pins : 0
 Total memory bits : 0 / 516,096 ( 0 % )
 Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )

+ 11 - 11
output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Fri Aug  6 18:17:39 2021
+Fri Aug  6 18:26:27 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Fri Aug  6 18:17:39 2021       ;
+; Flow Status                        ; Successful - Fri Aug  6 18:26:27 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -52,7 +52,7 @@ https://fpgasoftware.intel.com/eula.
 ;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
 ;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
 ; Total registers                    ; 229                                         ;
-; Total pins                         ; 142 / 166 ( 86 % )                          ;
+; Total pins                         ; 143 / 166 ( 86 % )                          ;
 ; Total virtual pins                 ; 0                                           ;
 ; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
 ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 08/06/2021 18:17:21 ;
+; Start date & time ; 08/06/2021 18:26:08 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 117270187186385.162829904138700        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 187498021571645.162829956841996        ; --            ; --          ; --                                ;
 ; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
@@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 676 MB              ; 00:00:15                           ;
-; Fitter               ; 00:00:06     ; 1.0                     ; 1488 MB             ; 00:00:07                           ;
+; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 678 MB              ; 00:00:15                           ;
+; Fitter               ; 00:00:05     ; 1.0                     ; 1526 MB             ; 00:00:07                           ;
 ; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1021 MB             ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 736 MB              ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
-; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:26                           ;
+; Power Analyzer       ; 00:00:01     ; 1.0                     ; 1020 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 727 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 815 MB              ; 00:00:00                           ;
+; Total                ; 00:00:15     ; --                      ; --                  ; 00:00:26                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

File diff suppressed because it is too large
+ 610 - 609
output_files/max80.jam


BIN
output_files/max80.jbc


+ 55 - 56
output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Fri Aug  6 18:17:26 2021
+Fri Aug  6 18:26:14 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -67,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Fri Aug  6 18:17:26 2021       ;
+; Analysis & Synthesis Status        ; Successful - Fri Aug  6 18:26:14 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 ;     Total combinational functions  ; 274                                         ;
 ;     Dedicated logic registers      ; 218                                         ;
 ; Total registers                    ; 226                                         ;
-; Total pins                         ; 138                                         ;
+; Total pins                         ; 139                                         ;
 ; Total virtual pins                 ; 0                                           ;
 ; Total memory bits                  ; 0                                           ;
 ; Embedded Multiplier 9-bit elements ; 0                                           ;
@@ -237,7 +237,7 @@ https://fpgasoftware.intel.com/eula.
 ;     -- Dedicated logic registers            ; 218                                                                                    ;
 ;     -- I/O registers                        ; 16                                                                                     ;
 ;                                             ;                                                                                        ;
-; I/O pins                                    ; 138                                                                                    ;
+; I/O pins                                    ; 139                                                                                    ;
 ;                                             ;                                                                                        ;
 ; Embedded Multiplier 9-bit elements          ; 0                                                                                      ;
 ;                                             ;                                                                                        ;
@@ -246,8 +246,8 @@ https://fpgasoftware.intel.com/eula.
 ;                                             ;                                                                                        ;
 ; Maximum fan-out node                        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
 ; Maximum fan-out                             ; 114                                                                                    ;
-; Total fan-out                               ; 1580                                                                                   ;
-; Average fan-out                             ; 1.91                                                                                   ;
+; Total fan-out                               ; 1582                                                                                   ;
+; Average fan-out                             ; 1.90                                                                                   ;
 +---------------------------------------------+----------------------------------------------------------------------------------------+
 
 
@@ -256,7 +256,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
 ; Compilation Hierarchy Node                                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
-; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 138  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
+; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 139  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
 ;    |hdmitx:hdmitx|                                           ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
 ;       |altlvds_tx:ALTLVDS_TX_component|                      ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
 ;          |hdmitx_lvds_tx:auto_generated|                     ; 78 (20)             ; 109 (60)                  ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
@@ -1051,7 +1051,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 +-----------------------+-----------------------------+
 ; Type                  ; Count                       ;
 +-----------------------+-----------------------------+
-; boundary_port         ; 138                         ;
+; boundary_port         ; 139                         ;
 ; cycloneiii_ddio_out   ; 4                           ;
 ; cycloneiii_ff         ; 218                         ;
 ;     CLR               ; 46                          ;
@@ -1060,7 +1060,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 ;     ENA               ; 27                          ;
 ;     ENA CLR           ; 12                          ;
 ;     plain             ; 106                         ;
-; cycloneiii_io_obuf    ; 57                          ;
+; cycloneiii_io_obuf    ; 58                          ;
 ; cycloneiii_lcell_comb ; 278                         ;
 ;     arith             ; 56                          ;
 ;         2 data inputs ; 39                          ;
@@ -1074,7 +1074,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 ; cycloneiii_pll        ; 2                           ;
 ;                       ;                             ;
 ; Max LUT depth         ; 7.20                        ;
-; Average LUT depth     ; 2.82                        ;
+; Average LUT depth     ; 2.81                        ;
 +-----------------------+-----------------------------+
 
 
@@ -1093,7 +1093,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:17:21 2021
+    Info: Processing started: Fri Aug  6 18:26:08 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
@@ -1113,28 +1113,26 @@ Info (12021): Found 1 design units, including 1 entities, in source file tmdsenc
     Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 73
 Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
     Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
-Warning (10236): Verilog HDL Implicit Net warning at max80.sv(184): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
-Warning (10236): Verilog HDL Implicit Net warning at max80.sv(327): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 327
+Warning (10236): Verilog HDL Implicit Net warning at max80.sv(185): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 185
 Info (12127): Elaborating entity "max80" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(184): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 184
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(327): object "spi_cs_flash_n" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 327
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(216): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 216
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(217): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 217
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(220): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 220
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(221): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 221
-Warning (10858): Verilog HDL warning at max80.sv(224): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 224
-Warning (10858): Verilog HDL warning at max80.sv(225): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
-Warning (10858): Verilog HDL warning at max80.sv(226): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
-Warning (10858): Verilog HDL warning at max80.sv(227): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
-Warning (10858): Verilog HDL warning at max80.sv(228): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
-Warning (10036): Verilog HDL or VHDL warning at max80.sv(267): object "exth_d" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 267
-Warning (10230): Verilog HDL assignment warning at max80.sv(155): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 155
-Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(298): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 298
-Warning (10030): Net "abc_wait" at max80.sv(224) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 224
-Warning (10030): Net "abc_resin" at max80.sv(225) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
-Warning (10030): Net "abc_int" at max80.sv(226) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
-Warning (10030): Net "abc_nmi" at max80.sv(227) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
-Warning (10030): Net "abc_xm" at max80.sv(228) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(185): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 185
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(217): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 217
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(218): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 218
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(221): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 221
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(222): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 222
+Warning (10858): Verilog HDL warning at max80.sv(225): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
+Warning (10858): Verilog HDL warning at max80.sv(226): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
+Warning (10858): Verilog HDL warning at max80.sv(227): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
+Warning (10858): Verilog HDL warning at max80.sv(228): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
+Warning (10858): Verilog HDL warning at max80.sv(229): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 229
+Warning (10036): Verilog HDL or VHDL warning at max80.sv(268): object "exth_d" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
+Warning (10230): Verilog HDL assignment warning at max80.sv(156): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 156
+Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(299): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 299
+Warning (10030): Net "abc_wait" at max80.sv(225) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
+Warning (10030): Net "abc_resin" at max80.sv(226) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
+Warning (10030): Net "abc_int" at max80.sv(227) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
+Warning (10030): Net "abc_nmi" at max80.sv(228) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
+Warning (10030): Net "abc_xm" at max80.sv(229) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 229
 Warning (10034): Output port "abc_d_oe" at max80.sv(19) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
 Warning (10034): Output port "abc_master" at max80.sv(38) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
 Warning (10034): Output port "abc_a_oe" at max80.sv(39) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
@@ -1149,7 +1147,7 @@ Warning (10862): input port "abc_out_n" at max80.sv(22) has no fan-out File: /ho
 Warning (10862): input port "abc_inp_n" at max80.sv(23) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
 Warning (10862): bidir port "sr_dq" at max80.sv(60) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
 Warning (10862): bidir port "sd_dat" at max80.sv(70) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
-Warning (10862): bidir port "gpio" at max80.sv(105) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 105
+Warning (10862): bidir port "gpio" at max80.sv(106) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
 Warning (10862): input port "abc_clk" at max80.sv(16) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
 Warning (10862): input port "abc_rst_n" at max80.sv(20) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
 Warning (10862): input port "abc_cs_n" at max80.sv(21) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
@@ -1172,17 +1170,18 @@ Warning (10862): bidir port "spi_clk" at max80.sv(86) has no fan-out File: /home
 Warning (10862): bidir port "spi_miso" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
 Warning (10862): bidir port "spi_mosi" at max80.sv(88) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
 Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
-Warning (10862): bidir port "esp_io0" at max80.sv(92) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 92
-Warning (10862): bidir port "esp_int" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
-Warning (10862): bidir port "i2c_scl" at max80.sv(96) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 96
-Warning (10862): bidir port "i2c_sda" at max80.sv(97) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
-Warning (10862): input port "rtc_32khz" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
-Warning (10862): input port "rtc_int_n" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
-Warning (10862): bidir port "hdmi_scl" at max80.sv(110) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
-Warning (10863): bidir port "hdmi_sda" at max80.sv(111) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
-Warning (10862): bidir port "hdmi_sda" at max80.sv(111) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
-Warning (10862): bidir port "hdmi_hpd" at max80.sv(113) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 113
-Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 139
+Warning (10862): bidir port "spi_cs_flash_n" at max80.sv(90) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
+Warning (10862): bidir port "esp_io0" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
+Warning (10862): bidir port "esp_int" at max80.sv(94) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
+Warning (10862): bidir port "i2c_scl" at max80.sv(97) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
+Warning (10862): bidir port "i2c_sda" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
+Warning (10862): input port "rtc_32khz" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+Warning (10862): input port "rtc_int_n" at max80.sv(100) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
+Warning (10862): bidir port "hdmi_scl" at max80.sv(111) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
+Warning (10863): bidir port "hdmi_sda" at max80.sv(112) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
+Warning (10862): bidir port "hdmi_sda" at max80.sv(112) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
+Warning (10862): bidir port "hdmi_hpd" at max80.sv(114) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
+Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 140
 Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
 Info (12130): Elaborated megafunction instantiation "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
 Info (12133): Instantiated megafunction "pll:pll|altpll:altpll_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
@@ -1270,13 +1269,13 @@ Info (12128): Elaborating entity "pll_cntr" for hierarchy "pll:pll|altpll:altpll
 Info (12128): Elaborating entity "pll_cmpr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|pll_cmpr:cmpr12" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 273
 Info (12128): Elaborating entity "pll_cntr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 573
 Info (12128): Elaborating entity "pll_cmpr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|pll_cmpr1:cmpr14" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 421
-Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 179
+Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 180
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 92
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 134
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 135
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 140
 Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 145
-Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 196
+Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 197
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(67): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 67
@@ -1284,7 +1283,7 @@ Info (12128): Elaborating entity "condreg" for hierarchy "transpose:hdmitranspos
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(14): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 14
 Warning (10269): Verilog HDL conditional expression warning at transpose.sv(15): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 15
 Warning (10862): input port "clk" at transpose.sv(8) has no fan-out File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 8
-Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 205
+Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 206
 Info (12128): Elaborating entity "altlvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
 Info (12130): Elaborated megafunction instantiation "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
 Info (12133): Instantiated megafunction "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
@@ -1408,7 +1407,7 @@ Warning (13039): The following bidirectional pins have no drivers
     Warning (13040): bidirectional pin "abc_d[5]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
     Warning (13040): bidirectional pin "abc_d[6]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
     Warning (13040): bidirectional pin "abc_d[7]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
-    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
+    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
 Warning (13032): The following tri-state nodes are fed by constants
     Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
     Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
@@ -1510,18 +1509,18 @@ Warning (21074): Design contains 39 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
     Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
     Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
-    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
-    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
-Info (21057): Implemented 484 device resources after synthesis - the final resource count might be different
+    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
+    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
+Info (21057): Implemented 485 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 40 input pins
     Info (21059): Implemented 47 output pins
-    Info (21060): Implemented 51 bidirectional pins
+    Info (21060): Implemented 52 bidirectional pins
     Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 218 warnings
-    Info: Peak virtual memory: 676 megabytes
-    Info: Processing ended: Fri Aug  6 18:17:26 2021
-    Info: Elapsed time: 00:00:05
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 217 warnings
+    Info: Peak virtual memory: 678 megabytes
+    Info: Processing ended: Fri Aug  6 18:26:14 2021
+    Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:15
 
 

+ 2 - 2
output_files/max80.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Fri Aug  6 18:17:26 2021
+Analysis & Synthesis Status : Successful - Fri Aug  6 18:26:14 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
@@ -7,7 +7,7 @@ Total logic elements : 337
     Total combinational functions : 274
     Dedicated logic registers : 218
 Total registers : 226
-Total pins : 138
+Total pins : 139
 Total virtual pins : 0
 Total memory bits : 0
 Embedded Multiplier 9-bit elements : 0

+ 21 - 21
output_files/max80.pin

@@ -103,7 +103,7 @@ GND                          : B15       : gnd    :                   :
 rtc_int_n                    : B16       : input  : 3.3-V LVTTL       :         : 6         : Y              
 flash_mosi                   : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
 abc_a_oe                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+GND*                         : C3        :        :                   :         : 8         :                
 VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
 GND                          : C5        : gnd    :                   :         :           :                
 sr_dq[14]                    : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
@@ -175,7 +175,7 @@ VCCINT                       : G7        : power  :                   : 1.2V
 VCCINT                       : G8        : power  :                   : 1.2V    :           :                
 VCCINT                       : G9        : power  :                   : 1.2V    :           :                
 VCCINT                       : G10       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 6         :                
+GND*                         : G11       :        :                   :         : 6         :                
 MSEL2                        : G12       :        :                   :         : 6         :                
 GND                          : G13       : gnd    :                   :         :           :                
 VCCIO6                       : G14       : power  :                   : 3.3V    : 6         :                
@@ -208,9 +208,9 @@ GND                          : J8        : gnd    :                   :
 GND                          : J9        : gnd    :                   :         :           :                
 GND                          : J10       : gnd    :                   :         :           :                
 GND                          : J11       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 5         :                
+GND*                         : J12       :        :                   :         : 5         :                
+GND*                         : J13       :        :                   :         : 5         :                
+GND*                         : J14       :        :                   :         : 5         :                
 hdmi_clk                     : J15       : output : LVDS              :         : 5         : Y              
 hdmi_clk(n)                  : J16       : output : LVDS              :         : 5         : N              
 abc_a[11]                    : K1        : input  : 3.3-V LVTTL       :         : 2         : Y              
@@ -218,13 +218,13 @@ abc_out_n[4]                 : K2        : input  : 3.3-V LVTTL       :
 VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
 GND                          : K4        : gnd    :                   :         :           :                
 abc_out_n[2]                 : K5        : input  : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : K6        :        :                   :         : 2         :                
+GND*                         : K6        :        :                   :         : 2         :                
 VCCINT                       : K7        : power  :                   : 1.2V    :           :                
 GND                          : K8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K10       :        :                   :         : 4         :                
+GND*                         : K9        :        :                   :         : 4         :                
+GND*                         : K10       :        :                   :         : 4         :                
 VCCINT                       : K11       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 5         :                
+GND*                         : K12       :        :                   :         : 5         :                
 GND                          : K13       : gnd    :                   :         :           :                
 VCCIO5                       : K14       : power  :                   : 2.5V    : 5         :                
 hdmi_d[0]                    : K15       : output : LVDS              :         : 5         : Y              
@@ -234,17 +234,17 @@ abc_inp_n[0]                 : L2        : input  : 3.3-V LVTTL       :
 abc_out_n[3]                 : L3        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_a[10]                    : L4        : input  : 3.3-V LVTTL       :         : 2         : Y              
 VCCA1                        : L5        : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+GND*                         : L6        :        :                   :         : 2         :                
 gpio[0]                      : L7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 esp_io0                      : L8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L9        :        :                   :         : 4         :                
+GND*                         : L9        :        :                   :         : 4         :                
 abc_xoutpstb_n               : L10       : input  : 3.3-V LVTTL       :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : L11       :        :                   :         : 4         :                
+GND*                         : L11       :        :                   :         : 4         :                
 VCCA4                        : L12       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L13       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L14       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 5         :                
+GND*                         : L13       :        :                   :         : 5         :                
+GND*                         : L14       :        :                   :         : 5         :                
+GND*                         : L15       :        :                   :         : 5         :                
+GND*                         : L16       :        :                   :         : 5         :                
 abc_a[13]                    : M1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_inp_n[1]                 : M2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 VCCIO2                       : M3        : power  :                   : 3.3V    : 2         :                
@@ -253,7 +253,7 @@ GNDA1                        : M5        : gnd    :                   :
 abc_d[1]                     : M6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 spi_miso                     : M7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 spi_mosi                     : M8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 4         :                
+GND*                         : M9        :        :                   :         : 4         :                
 sd_dat[1]                    : M10       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 hdmi_scl                     : M11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 GNDA4                        : M12       : gnd    :                   :         :           :                
@@ -266,7 +266,7 @@ abc_a[14]                    : N2        : input  : 3.3-V LVTTL       :
 abc_xmemfl_n                 : N3        : input  : 3.3-V LVTTL       :         : 3         : Y              
 VCCD_PLL1                    : N4        : power  :                   : 1.2V    :           :                
 abc_d[2]                     : N5        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+spi_cs_flash_n               : N6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 GND                          : N7        : gnd    :                   :         :           :                
 spi_cs_esp_n                 : N8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 exth_hb                      : N9        : bidir  : 3.3-V LVTTL       :         : 4         : Y              
@@ -274,7 +274,7 @@ GND                          : N10       : gnd    :                   :
 exth_hg                      : N11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 exth_ha                      : N12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+GND*                         : N14       :        :                   :         : 5         :                
 hdmi_d[1]                    : N15       : output : LVDS              :         : 5         : Y              
 hdmi_d[1](n)                 : N16       : output : LVDS              :         : 5         : N              
 abc_xmemw800_n               : P1        : input  : 3.3-V LVTTL       :         : 2         : Y              
@@ -287,11 +287,11 @@ VCCIO3                       : P7        : power  :                   : 3.3V
 esp_int                      : P8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 gpio[1]                      : P9        : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 VCCIO4                       : P10       : power  :                   : 3.3V    : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P11       :        :                   :         : 4         :                
+GND*                         : P11       :        :                   :         : 4         :                
 GND                          : P12       : gnd    :                   :         :           :                
 VCCIO4                       : P13       : power  :                   : 3.3V    : 4         :                
 tty_dtr                      : P14       : input  : 3.3-V LVTTL       :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+GND*                         : P15       :        :                   :         : 5         :                
 hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : N              
 abc_xmemw80_n                : R1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 GND                          : R2        : gnd    :                   :         :           :                

BIN
output_files/max80.pof


+ 22 - 21
output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Fri Aug  6 18:17:37 2021
+Fri Aug  6 18:26:24 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -65,17 +65,17 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Fri Aug  6 18:17:37 2021            ;
+; Power Analyzer Status                  ; Successful - Fri Aug  6 18:26:24 2021            ;
 ; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
 ; Family                                 ; Cyclone IV E                                     ;
 ; Device                                 ; EP4CE15F17C8                                     ;
 ; Power Models                           ; Final                                            ;
-; Total Thermal Power Dissipation        ; 216.99 mW                                        ;
+; Total Thermal Power Dissipation        ; 217.59 mW                                        ;
 ; Core Dynamic Thermal Power Dissipation ; 37.20 mW                                         ;
 ; Core Static Thermal Power Dissipation  ; 60.20 mW                                         ;
-; I/O Thermal Power Dissipation          ; 119.59 mW                                        ;
+; I/O Thermal Power Dissipation          ; 120.19 mW                                        ;
 ; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
 +----------------------------------------+--------------------------------------------------+
 
@@ -189,6 +189,7 @@ https://fpgasoftware.intel.com/eula.
 ; spi_miso       ; No valid clock domain found ;
 ; spi_mosi       ; No valid clock domain found ;
 ; spi_cs_esp_n   ; No valid clock domain found ;
+; spi_cs_flash_n ; No valid clock domain found ;
 ; esp_io0        ; No valid clock domain found ;
 ; esp_int        ; No valid clock domain found ;
 ; i2c_scl        ; No valid clock domain found ;
@@ -247,7 +248,7 @@ https://fpgasoftware.intel.com/eula.
 ; Register cell                         ; 2.48 mW                           ; 1.87 mW                     ; --                             ; 0.61 mW                       ;   13.191                                                  ;
 ; Double Data Rate I/O Output Circuitry ; 0.49 mW                           ; 0.49 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
 ; I/O register                          ; 0.21 mW                           ; 0.21 mW                     ; --                             ; 0.00 mW                       ;   12.000                                                  ;
-; I/O                                   ; 92.53 mW                          ; 3.58 mW                     ; 88.95 mW                       ; 0.00 mW                       ;    2.282                                                  ;
+; I/O                                   ; 93.12 mW                          ; 3.58 mW                     ; 89.55 mW                       ; 0.00 mW                       ;    2.266                                                  ;
 +---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
 (1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
 
@@ -257,7 +258,7 @@ https://fpgasoftware.intel.com/eula.
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
 ; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
-; |max80                                                          ; 130.42 mW (95.72 mW)                 ; 29.05 mW (4.25 mW)              ; 88.95 mW (88.95 mW)               ; 12.43 mW (2.52 mW)                ; |max80                                                                                                             ;
+; |max80                                                          ; 131.02 mW (96.32 mW)                 ; 29.05 mW (4.25 mW)              ; 89.55 mW (89.55 mW)               ; 12.43 mW (2.52 mW)                ; |max80                                                                                                             ;
 ;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
 ;     |tmdsenc:hdmitmds[0].enc                                    ; 0.16 mW (0.16 mW)                    ; 0.13 mW (0.13 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
 ;     |tmdsenc:hdmitmds[1].enc                                    ; 0.14 mW (0.14 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
@@ -313,8 +314,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 ; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
-; VCCINT         ; 56.29 mA                ; 13.06 mA                  ; 43.24 mA                 ; 56.29 mA                         ;
-; VCCIO          ; 28.25 mA                ; 1.01 mA                   ; 27.25 mA                 ; 28.25 mA                         ;
+; VCCINT         ; 56.74 mA                ; 13.06 mA                  ; 43.69 mA                 ; 56.74 mA                         ;
+; VCCIO          ; 28.27 mA                ; 1.01 mA                   ; 27.26 mA                 ; 28.27 mA                         ;
 ; VCCA           ; 21.83 mA                ; 3.55 mA                   ; 18.28 mA                 ; 21.83 mA                         ;
 ; VCCD           ; 19.19 mA                ; 11.40 mA                  ; 7.78 mA                  ; 19.19 mA                         ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
@@ -329,7 +330,7 @@ https://fpgasoftware.intel.com/eula.
 +----------+---------------+---------------------+-----------------------+----------------------+
 ; 1        ; 3.3V          ; 1.27 mA             ; 0.00 mA               ; 1.27 mA              ;
 ; 2        ; 3.3V          ; 1.31 mA             ; 0.00 mA               ; 1.31 mA              ;
-; 3        ; 3.3V          ; 1.44 mA             ; 0.00 mA               ; 1.44 mA              ;
+; 3        ; 3.3V          ; 1.46 mA             ; 0.00 mA               ; 1.46 mA              ;
 ; 4        ; 3.3V          ; 1.53 mA             ; 0.15 mA               ; 1.38 mA              ;
 ; 5        ; 2.5V          ; 17.77 mA            ; 0.03 mA               ; 17.74 mA             ;
 ; 6        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
@@ -344,7 +345,7 @@ https://fpgasoftware.intel.com/eula.
 ; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
 +---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 ; 2.5V          ; 17.77 mA                ; 0.03 mA                   ; 17.74 mA                 ; 17.77 mA                         ;
-; 3.3V          ; 10.49 mA                ; 0.98 mA                   ; 9.51 mA                  ; 10.49 mA                         ;
+; 3.3V          ; 10.50 mA                ; 0.98 mA                   ; 9.53 mA                  ; 10.50 mA                         ;
 +---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 (1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
 (2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
@@ -364,16 +365,16 @@ https://fpgasoftware.intel.com/eula.
 ;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 8 (0.9%)    ; 2 (1.0%)    ; 1 (0.5%)    ; 5 (1.0%)      ;
 ;                                                                                        ;             ;             ;             ;               ;
 ; Vectorless estimation                                                                  ;             ;             ;             ;               ;
-;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 811 (89.3%) ; 102 (52.8%) ; 220 (99.5%) ; 489 (99.0%)   ;
-;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 212 (23.3%) ; 98 (50.8%)  ; 1 (0.5%)    ; 113 (22.9%)   ;
-;     -- Number of signals with Static Probability from Vectorless estimation            ; 811 (89.3%) ; 102 (52.8%) ; 220 (99.5%) ; 489 (99.0%)   ;
+;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 813 (89.2%) ; 103 (52.8%) ; 220 (99.5%) ; 490 (99.0%)   ;
+;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 214 (23.5%) ; 99 (50.8%)  ; 1 (0.5%)    ; 114 (23.0%)   ;
+;     -- Number of signals with Static Probability from Vectorless estimation            ; 813 (89.2%) ; 103 (52.8%) ; 220 (99.5%) ; 490 (99.0%)   ;
 ;                                                                                        ;             ;             ;             ;               ;
 ; Default assignment                                                                     ;             ;             ;             ;               ;
 ;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
-;     -- Number of signals with Static Probability from Default assignment               ; 89 (9.8%)   ; 89 (46.1%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
+;     -- Number of signals with Static Probability from Default assignment               ; 90 (9.9%)   ; 90 (46.2%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
 ;                                                                                        ;             ;             ;             ;               ;
 ; Assumed 0                                                                              ;             ;             ;             ;               ;
-;     -- Number of signals with Toggle Rate assumed 0                                    ; 89 (9.8%)   ; 89 (46.1%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
+;     -- Number of signals with Toggle Rate assumed 0                                    ; 90 (9.9%)   ; 90 (46.2%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
 +----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
 
 
@@ -391,7 +392,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 18:17:35 2021
+    Info: Processing started: Fri Aug  6 18:26:23 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -429,12 +430,12 @@ Info (223001): Completed Vectorless Power Activity Estimation
 Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
-Info (215049): Average toggle rate for this design is 10.847 millions of transitions / sec
-Info (215031): Total thermal power estimate for the design is 216.99 mW
+Info (215049): Average toggle rate for this design is 10.833 millions of transitions / sec
+Info (215031): Total thermal power estimate for the design is 217.59 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1021 megabytes
-    Info: Processing ended: Fri Aug  6 18:17:37 2021
-    Info: Elapsed time: 00:00:02
+    Info: Peak virtual memory: 1020 megabytes
+    Info: Processing ended: Fri Aug  6 18:26:24 2021
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
 
 

+ 3 - 3
output_files/max80.pow.summary

@@ -1,12 +1,12 @@
-Power Analyzer Status : Successful - Fri Aug  6 18:17:37 2021
+Power Analyzer Status : Successful - Fri Aug  6 18:26:24 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
 Device : EP4CE15F17C8
 Power Models : Final
-Total Thermal Power Dissipation : 216.99 mW
+Total Thermal Power Dissipation : 217.59 mW
 Core Dynamic Thermal Power Dissipation : 37.20 mW
 Core Static Thermal Power Dissipation : 60.20 mW
-I/O Thermal Power Dissipation : 119.59 mW
+I/O Thermal Power Dissipation : 120.19 mW
 Power Estimation Confidence : Low: user provided insufficient toggle rate data

BIN
output_files/max80.sof


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+ 469 - 464
output_files/max80.sta.rpt


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